67246 lines
4.4 MiB
67246 lines
4.4 MiB
; --------------------------------------------------------------------------------
|
|
; @Title: STM32F7x On-Chip Peripherals
|
|
; @Props: Released
|
|
; @Author: GAJ, AMM, AST, WWE, MRD, MTR, KWI, KRZ, JMI, DPR, MIC, JUS, STY
|
|
; @Changelog: 2016-09-08 AST
|
|
; 2015-11-23 GAJ
|
|
; 2017-03-03 WWE
|
|
; 2017-05-23 MTR
|
|
; 2018-05-29 KWI
|
|
; 2020-02-07 KRZ
|
|
; @Manufacturer: STM - ST Microelectronics N.V.
|
|
; @Doc: RM_DM00124865.pdf (Rev.1 2015-05)
|
|
; DS_DM00166114.pdf (Rev.1 2015-05)
|
|
; DM00166116.pdf (Rev.4 2016-02)
|
|
; RM_DM00224583_f76x_f77x.pdf (Rev.2 2016-04)
|
|
; DS_DM00225424_f777_778a_779.pdf (Rev.3 2016-05)
|
|
; DS_DM00273119_f765_767_768a_769 (Rev.3 2016-05)
|
|
; DM00224583_f76x_77x.pdf (Rev.2 24-04-2016)
|
|
; DM00305990_f72x_73x.pdf (Rev.1 25-01-2017)
|
|
; en.DM00330506.pdf (Rev.3 06-2017)
|
|
; en.DM00330507.pdf (Rev.3 06-2017)
|
|
; en.DM00124865.pdf (Rev.8 25-06-2018)
|
|
; en.DM00305990.pdf (Rev.3 26-06-2018)
|
|
; ds_stm32f730i8.pdf (Rev.1 27-06-2018)
|
|
; ds_stm32f750n8.pdf (Rev.1 27-06-2018)
|
|
; @Core: Cortex-M7F
|
|
; @Chip: STM32F745VE, STM32F745VG, STM32F745ZE, STM32F745ZG, STM32F745IE
|
|
; STM32F745IG, STM32F746VG, STM32F746VG, STM32F746BG, STM32F756BG
|
|
; STM32F765II, STM32F767VI, STM32F767BI, STM32F769VG, STM32F769BG
|
|
; STM32F745BE, STM32F745BG, STM32F745NE, STM32F745NG, STM32F746VE
|
|
; STM32F746ZE, STM32F746ZG, STM32F746IE, STM32F746IG, STM32F746BE
|
|
; STM32F746NE, STM32F746NG, STM32F756VG, STM32F756ZG, STM32F756IG
|
|
; STM32F756NG, STM32F765VI, STM32F765VG, STM32F765ZI, STM32F765ZG
|
|
; STM32F765IG, STM32F765BI, STM32F765BG, STM32F765NI, STM32F765NG
|
|
; STM32F767VG, STM32F767ZI, STM32F767ZG, STM32F767II, STM32F767IG
|
|
; STM32F767BG, STM32F767NI, STM32F767NG, STM32F768AI, STM32F769VI
|
|
; STM32F769BI, STM32F769ZI, STM32F769ZG, STM32F769II, STM32F769IG
|
|
; STM32F777ZI, STM32F769NI, STM32F769NG, STM32F769AI, STM32F777VI
|
|
; STM32F777BI, STM32F777NI, STM32F778AI, STM32F779ZI, STM32F779II
|
|
; STM32F779NI, STM32F779AI, STM32F777II, STM32F779BI, STM32F722IC
|
|
; STM32F722IE, STM32F722RC, STM32F722RE, STM32F722VC, STM32F722VE
|
|
; STM32F722ZC, STM32F722ZE, STM32F723IC, STM32F723IE, STM32F723VE
|
|
; STM32F723ZC, STM32F723ZE, STM32F732IE, STM32F732RE, STM32F732VE
|
|
; STM32F732ZE, STM32F733IE, STM32F733VE, STM32F733ZE, STM32F730I8
|
|
; STM32F730R8, STM32F730V8, STM32F730Z8, STM32F750N8, STM32F750V8
|
|
; STM32F750Z8
|
|
; @Copyright: (C) 1989-2020 Lauterbach GmbH, licensed for use with TRACE32(R) only
|
|
; --------------------------------------------------------------------------------
|
|
; $Id: perstm32f7x.per 17736 2024-04-08 09:26:07Z kwisniewski $
|
|
|
|
tree.close "Core Registers (Cortex-M7F)"
|
|
AUTOINDENT.PUSH
|
|
AUTOINDENT.OFF
|
|
tree "System Control"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 12.
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ACTLR,Auxiliary Control Register"
|
|
bitfld.long 0x00 28. " DISFPUISSOPT ,DISFPUISSOPT" "No,Yes"
|
|
bitfld.long 0x00 27. " DISCRITAXIRUW ,Disables critical AXI read-under-write" "No,Yes"
|
|
bitfld.long 0x00 26. " DISDYNADD ,Disables dynamic allocation of ADD and SUB instructions" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 21.--25. " DISISSCH1 ,DISISSCH1" "Normal,Not issued in ch1,,,,,,,,,,,,,,,,,,,,Direct branches,Indirect branches,Loaded to PC,Integer MAC and MUL,VFP,?..."
|
|
bitfld.long 0x00 16.--20. " DISDI ,DISDI" "Normal,ch1,,,,,,,,,,,,,,,Direct branches,Indirect branches,Loaded to PC,Integer MAC and MUL,VFP,?..."
|
|
bitfld.long 0x00 15. " DISCRITAXIRUR ,Disables critical AXI read-under-read" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DISBTACALLOC ,DISBTACALLOC" "No,Yes"
|
|
bitfld.long 0x00 13. " DISBTACREAD ,DISBTACREAD" "No,Yes"
|
|
bitfld.long 0x00 12. " DISITMATBFLUSH ,Disables ITM and DWT ATB flush" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DISRAMODE ,Disables dynamic read allocate mode for Write-Back Write-Allocate memory regions" "No,Yes"
|
|
bitfld.long 0x00 10. " FPEXCODIS ,Disables FPU exception outputs" "No,Yes"
|
|
bitfld.long 0x00 2. " DISFOLD ,Disables dual-issue functionality" "No,Yes"
|
|
textline ""
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
|
|
rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
|
|
bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
|
|
bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "SYST_RVR,SysTick Reload Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
|
|
line.long 0x04 "SYST_CVR,SysTick Current Value Register"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "SYST_CALIB,SysTick Calibration value Register"
|
|
bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
|
|
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
|
|
rgroup.long 0xD00++0x03
|
|
line.long 0x00 "CPUID,CPUID Base Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Indicates implementer"
|
|
bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,Revision 1,?..."
|
|
bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
|
|
bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "Patch 0,Patch 1,Patch 2,?..."
|
|
group.long 0xD04++0x23
|
|
line.long 0x00 "ICSR,Interrupt Control and State Register"
|
|
bitfld.long 0x00 31. " NMIPENDSET ,On writes, makes the NMI exception active. On reads, indicates the state of the exception" "Inactive,Active"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x00 27. " PENDSVSET ,On writes, sets the PendSV exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x00 25. " PENDSTSET ,On writes, sets the SysTick exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 23. " ISRPREEMPT ,Indicates whether a pending exception will be serviced on exit from debug halt state" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt, generated by the NVIC, is pending" "Not pending,Pending"
|
|
hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,The exception number of the highest priority pending and enabled interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " RETTOBASE ,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "Present,Absent"
|
|
hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
|
|
line.long 0x04 "VTOR,Vector Table Offset Register"
|
|
hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Bits[31:7] of the vector table address"
|
|
line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " VECTKEYSTAT ,Vector Key"
|
|
rbitfld.long 0x08 15. " ENDIANNESS ,Indicates the memory system endianness" "Little endian,Big endian"
|
|
bitfld.long 0x08 8.--10. " PRIGROUP ,Priority grouping. Group priority field bits/Subpriority field bits" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
|
|
bitfld.long 0x08 1. " VECTCLRACTIVE ,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "No effect,Clear"
|
|
bitfld.long 0x08 0. " VECTRESET ,Writing 1 to this bit causes a local system reset" "No effect,Reset"
|
|
line.long 0x0C "SCR,System Control Register"
|
|
bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
|
|
bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
|
|
bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
|
|
line.long 0x10 "CCR,Configuration and Control Register"
|
|
bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 9. " STKALIGN ,Determines whether the exception entry sequence guarantees 8-byte stack frame alignment, adjusting the SP if necessary before saving state" "4-byte/no adjustment,8-byte/adjustment"
|
|
bitfld.long 0x10 8. " BFHFNMIGN ,Determines the effect of precise data access faults on handlers running at priority -1 or priority -2" "Lockup,Ignored"
|
|
bitfld.long 0x10 4. " DIV_0_TRP ,Controls the trap on divide by 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " UNALIGN_TRP ,Controls the trapping of unaligned word or halfword accesses" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " NONBASETHRDENA ,Controls whether the processor can enter Thread mode at an execution priority level other than base level" "Disabled,Enabled"
|
|
line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
|
|
textline " "
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
|
|
line.long 0x18 "SHPR2,System Handler Priority Register 2"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
|
|
textline " "
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
|
|
line.long 0x1C "SHPR3,System Handler Priority Register 3"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
|
|
textline " "
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
|
|
line.long 0x20 "SHCSR,System Handler Control and State Register"
|
|
bitfld.long 0x20 18. " USGFAULTENA ,UsageFault" "Disabled,Enabled"
|
|
bitfld.long 0x20 17. " BUSFAULTENA ,BusFault" "Disabled,Enabled"
|
|
bitfld.long 0x20 16. " MEMFAULTENA ,MemManage" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 15. " SVCALLPENDED ,SVCall status" "Not pending,Pending"
|
|
bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault status" "Not pending,Pending"
|
|
bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault status" "Not pending,Pending"
|
|
bitfld.long 0x20 11. " SYSTICKACT ,SysTick status" "Not active,Active"
|
|
bitfld.long 0x20 10. " PENDSVACT ,PendSV status" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x20 8. " MONITORACT ,Monitor status" "Not active,Active"
|
|
bitfld.long 0x20 7. " SVCALLACT ,SVCall status" "Not active,Active"
|
|
bitfld.long 0x20 3. " USGFAULTACT ,UsageFault status" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x20 1. " BUSFAULTACT ,BusFault status" "Not active,Active"
|
|
bitfld.long 0x20 0. " MEMFAULTACT ,MemManage status" "Not active,Active"
|
|
group.byte 0xD28++0x1
|
|
line.byte 0x00 "MMFSR,MemManage Status Register"
|
|
bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
|
|
bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
|
|
line.byte 0x01 "BFSR,Bus Fault Status Register"
|
|
bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
|
|
bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
|
|
bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred"
|
|
bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
|
|
bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
|
|
group.word 0xD2A++0x1
|
|
line.word 0x00 "USAFAULT,Usage Fault Status Register"
|
|
bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
|
|
bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
|
|
bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
|
|
bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error"
|
|
bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
|
|
group.long 0xD2C++0x13
|
|
line.long 0x00 "HFSR,HardFault Status Register"
|
|
eventfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
|
|
eventfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority has been escalated to a HardFault exception" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
|
|
line.long 0x04 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not occurred,Occurred"
|
|
eventfld.long 0x04 3. " VCATCH ,Indicates triggering of a Vector catch" "Not occurred,Occurred"
|
|
eventfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x04 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not occurred,Occurred"
|
|
eventfld.long 0x04 0. " HALTED ,Indicates a debug event generated by a C_HALT or C_STEP request or a step request triggered by setting DEMCR.MON_STEP to 1" "Not occurred,Occurred"
|
|
line.long 0x08 "MMFAR,MemManage Fault Address Register"
|
|
line.long 0x0C "BFAR,BusFault Address Register"
|
|
line.long 0x10 "AFSR,Auxiliary Fault Status Register"
|
|
group.long 0xD88++0x03
|
|
line.long 0x00 "CPACR,Coprocessor Access Control Register"
|
|
bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Denied,Privileged,,Full"
|
|
bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Denied,Privileged,,Full"
|
|
bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Denied,Privileged,,Full"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Denied,Privileged,,Full"
|
|
bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Denied,Privileged,,Full"
|
|
bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Denied,Privileged,,Full"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Denied,Privileged,,Full"
|
|
bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Denied,Privileged,,Full"
|
|
bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Denied,Privileged,,Full"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Denied,Privileged,,Full"
|
|
wgroup.long 0xF00++0x03
|
|
line.long 0x00 "STIR,Software Triggered Interrupt Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
|
|
tree "Memory System"
|
|
width 10.
|
|
rgroup.long 0xD78++0x0B
|
|
line.long 0x00 "CLIDR,Cache Level ID Register"
|
|
bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "Level 1,level 2,?..."
|
|
bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,level 2,?..."
|
|
bitfld.long 0x00 18.--20. " CL7 ,Cache type field level 7" "No cache,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " CL6 ,Cache type field level 6" "No cache,?..."
|
|
bitfld.long 0x00 12.--14. " CL5 ,Cache type field level 5" "No cache,?..."
|
|
bitfld.long 0x00 9.--11. " CL4 ,Cache type field level 4" "No cache,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " CL3 ,Cache type field level 3" "No cache,?..."
|
|
bitfld.long 0x00 3.--5. " CL2 ,Cache type field level 2" "No cache,?..."
|
|
bitfld.long 0x00 0.--2. " CL1 ,Cache type field level 1" "No cache,Instr. only,Data only,Data and Instr.,?..."
|
|
line.long 0x04 "CTR,Cache Type Register"
|
|
bitfld.long 0x04 29.--31. " FORMAT ,Indicates the implemented CTR format" ",,,,ARMv7,?..."
|
|
bitfld.long 0x04 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x04 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " DMINLINE ,Log 2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. " IMINLINE ,Log 2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "CCSIDR,Cache Size ID Register"
|
|
bitfld.long 0x08 31. " WT ,Indicates support available for Write-Through" "Not supported,Supported"
|
|
bitfld.long 0x08 30. " WB ,Indicates support available for Write-Back" "Not supported,Supported"
|
|
bitfld.long 0x08 29. " RA ,Indicates support available for read allocation" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x08 28. " WA ,Indicates support available for write allocation" "Not supported,Supported"
|
|
hexmask.long.word 0x08 13.--27. 1. " NUMSETS ,Indicates the number of sets as (number of sets) - 1"
|
|
hexmask.long.word 0x08 3.--12. 1. " ASSOCIATIVITY ,Indicates the number of ways as (number of ways) - 1"
|
|
textline " "
|
|
bitfld.long 0x08 0.--2. " LINESIZE ,Indicates the number of words in each cache line" "4,8,16,32,64,128,256,512"
|
|
group.long 0xD84++0x03
|
|
line.long 0x00 "CSSELR,Cache Size Selection Register"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Identifies which cache level to select" "Level 1,?..."
|
|
bitfld.long 0x00 0. " IND ,Identifies instruction or data cache to use" "Data,Instruction"
|
|
wgroup.long 0xF50++0x03
|
|
line.long 0x00 "ICIALLU,Instruction cache invalidate all to Point of Unification"
|
|
wgroup.long 0xF58++0x1F
|
|
line.long 0x00 "ICIMVAU,Instruction cache invalidate by address to PoU"
|
|
line.long 0x04 "DCIMVAC,Data cache invalidate by address to Point of Coherency (PoC)"
|
|
line.long 0x08 "DCISW,Data cache invalidate by set/way"
|
|
line.long 0x0C "DCCMVAU,Data cache by address to PoU"
|
|
line.long 0x10 "DCCMVAC,Data cache clean by address to PoC"
|
|
line.long 0x14 "DCCSW,Data cache clean by set/way"
|
|
line.long 0x18 "DCCIMVAC,Data cache clean and invalidate by address to PoC"
|
|
line.long 0x1C "DCCISW,Data cache clean and invalidate by set/way"
|
|
group.long 0xF90++0x13
|
|
line.long 0x00 "ITCMCR,Instruction Tightly-Coupled Memory Control Register"
|
|
bitfld.long 0x00 3.--6. " SZ ,TCM size" "Not implemented,,,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB"
|
|
bitfld.long 0x00 2. " RETEN ,Retry phase enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RMW ,Read-Modify-Write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,TCM enable" "Disabled,Enabled"
|
|
line.long 0x04 "DTCMCR,Data Tightly-Coupled Memory Control Register"
|
|
bitfld.long 0x04 3.--6. " SZ ,TCM size" "Not implemented,,,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB"
|
|
bitfld.long 0x04 2. " RETEN ,Retry phase enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " RMW ,Read-Modify-Write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " EN ,TCM enable" "Disabled,Enabled"
|
|
line.long 0x08 "AHBPCR,AHBP control register"
|
|
bitfld.long 0x08 1.--3. " SZ ,AHBP size" "AHBP disabled,64 MB,128 MB,256 MB,512 MB,?..."
|
|
bitfld.long 0x08 0. " EN ,AHBP enable" "Disabled,Enabled"
|
|
line.long 0x0C "CACR,L1 Cache Control Register"
|
|
bitfld.long 0x0C 2. " FORCEWT ,Enables Force Write-through in the data cache" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " ECCDIS ,Disables ECC in the instruction and data cache" "No,Yes"
|
|
bitfld.long 0x0C 0. " SIWT ,Enables limited cache coherency usage" "Disabled,Enabled"
|
|
line.long 0x10 "AHBSCR,AHB Slave Control Register"
|
|
bitfld.long 0x10 11.--15. " INITCOUNT ,Fairness counter initialization value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x10 2.--10. 1. " TPRI ,Threshold execution priority for AHBS traffic demotion"
|
|
bitfld.long 0x10 0.--1. " CTL ,AHBS prioritization control" "AHBS,Software,AHBSCR.INITCOUNT,AHBSPRI"
|
|
group.long 0xFA8++0x03
|
|
line.long 0x00 "ABFSR,Auxiliary Bus Fault Status Register"
|
|
bitfld.long 0x00 8.--9. " AXIMTYPE ,Indicates the type of fault on the AXIM interface" "OKAY,EXOKAY,SLVERR,DECERR"
|
|
bitfld.long 0x00 4. " EPPB ,Asynchronous fault on EPPB interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " AXIM ,Asynchronous fault on AXIM interface" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AHBP ,Asynchronous fault on AHBP interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " DTCM ,Asynchronous fault on DTCM interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " ITCM ,Asynchronous fault on ITCM interface" "Not occurred,Occurred"
|
|
group.long 0xFB0++0x03
|
|
line.long 0x00 "IEBR0,Instruction Error bank Register 0"
|
|
bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3"
|
|
bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable"
|
|
bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data"
|
|
textline " "
|
|
hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM"
|
|
bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid"
|
|
group.long 0xFB4++0x03
|
|
line.long 0x00 "IEBR1,Instruction Error bank Register 1"
|
|
bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3"
|
|
bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable"
|
|
bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data"
|
|
textline " "
|
|
hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM"
|
|
bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid"
|
|
group.long 0xFB8++0x03
|
|
line.long 0x00 "DEBR0,Data Error bank Register 0"
|
|
bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3"
|
|
bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable"
|
|
bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data"
|
|
textline " "
|
|
hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM"
|
|
bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid"
|
|
group.long 0xFBC++0x03
|
|
line.long 0x00 "DEBR1,Data Error bank Register 1"
|
|
bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3"
|
|
bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable"
|
|
bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data"
|
|
textline " "
|
|
hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM"
|
|
bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid"
|
|
tree.end
|
|
tree "Feature Registers"
|
|
width 10.
|
|
rgroup.long 0xD40++0x0B
|
|
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
|
|
line.long 0x04 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
|
|
line.long 0x08 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
|
|
hgroup.long 0xD4C++0x03
|
|
hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
|
|
rgroup.long 0xD50++0x03
|
|
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
|
|
bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
|
|
bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
|
|
bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
|
|
hgroup.long 0xD54++0x03
|
|
hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
|
|
rgroup.long 0xD58++0x03
|
|
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
|
|
bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
|
|
rgroup.long 0xD60++0x13
|
|
line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
|
|
bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
|
|
bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
|
|
bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
|
|
bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
|
|
bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
|
|
line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
|
|
bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
|
|
bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
|
|
bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
|
|
line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
|
|
bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
|
|
bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
|
|
bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
|
|
bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
|
|
bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
|
|
line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
|
|
bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
|
|
bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
|
|
bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
|
|
bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
|
|
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
|
|
bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
|
|
tree.end
|
|
tree "CoreSight Identification Registers"
|
|
width 6.
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit (MPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif CORENAME()=="CORTEXM7F"
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
newline
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
newline
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
newline
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x0B
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
newline
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
|
|
line.long 0x08 "MVFR2,Media and FP Feature Register 2"
|
|
bitfld.long 0x08 4.--7. " VFP_MISC ,Indicates the hardware support for FP miscellaneous features" "Not supported,,,,Supported,?..."
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Specifies the access type for the transfer" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register, special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
newline
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported"
|
|
newline
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
newline
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
newline
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x30)++0x07
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x40)++0x07
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x50)++0x07
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
config 16. 8.
|
|
tree "FLASH (Embedded Flash Memory)"
|
|
base ad:0x40023C00
|
|
width 9.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ACR,Flash Access Control Register"
|
|
bitfld.long 0x00 11. " ARTRST ,ART accelerator reset" "No reset,Reset"
|
|
bitfld.long 0x00 9. " ARTEN ,ART accelerator enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PRFTEN ,Prefetch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " LATENCY ,Latency (number of wait states)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.long 0x04++0x07
|
|
line.long 0x00 "KEYR,Flash Key Register"
|
|
line.long 0x04 "OPTKEYR,Flash Option Key Register"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SR,Flash Status Register"
|
|
rbitfld.long 0x00 16. " BSY ,Busy" "Not busy,Busy"
|
|
newline
|
|
sif (cpuis("STM32F72*"))||(cpuis("STM32F73*"))
|
|
eventfld.long 0x00 8. " RDERR ,PCROP protection error" "No error,Error"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 7. " ERSERR ,Erase sequence error" "No error,Error"
|
|
eventfld.long 0x00 6. " PGPERR ,Programming parallelism error" "No error,Error"
|
|
eventfld.long 0x00 5. " PGAERR ,Programming alignment error" "No error,Error"
|
|
eventfld.long 0x00 4. " WRPERR ,Write protection error" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 1. " OPERR ,Operation error" "No error,Error"
|
|
eventfld.long 0x00 0. " EOP ,End of operation" "No,Yes"
|
|
sif cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F74*")||cpuis("STM32F75*")
|
|
if (((per.l(ad:0x40023C00+0x10))&0x80000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CR,Flash Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Locks FLASH_CR register" "Not locked,Locked"
|
|
newline
|
|
sif cpuis("STM32F72*")||cpuis("STM32F73*")
|
|
bitfld.long 0x00 26. " RDERRIE ,PCROP error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 25. " ERRIE ,Error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " EOPIE ,End of operation interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " STRT ,Triggers an erase operation" "Not erased,Erased"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Program size" "x8,x16,x32,x64"
|
|
newline
|
|
sif cpuis("STM32F72*")||cpuis("STM32F732*")||cpuis("STM32F733*")||cpuis("STM32F74*")||cpuis("STM32F756*")
|
|
bitfld.long 0x00 3.--6. " SNB ,Sector number" "0,1,2,3,4,5,6,7,?..."
|
|
newline
|
|
elif cpuis("STM32F730*")
|
|
bitfld.long 0x00 3.--6. " SNB ,Sector number" "0,1,2,3,?..."
|
|
newline
|
|
elif cpuis("STM32F750*")
|
|
bitfld.long 0x00 3.--6. " SNB ,Sector number" "0,1,?..."
|
|
newline
|
|
else
|
|
bitfld.long 0x00 3.--6. " SNB ,Sector number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 2. " MER ,Mass erase" "Not activated,Activated"
|
|
newline
|
|
bitfld.long 0x00 1. " SER ,Sector erase" "Not activated,Activated"
|
|
bitfld.long 0x00 0. " PG ,Flash programming" "Not activated,Activated"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "CR,Flash Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Locks FLASH_CR register" "Not locked,Locked"
|
|
newline
|
|
sif cpuis("STM32F72*")||cpuis("STM32F73*")
|
|
bitfld.long 0x00 26. " RDERRIE ,PCROP error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 25. " ERRIE ,Error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " EOPIE ,End of operation interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " STRT ,Triggers an erase operation" "Not erased,Erased"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Program size" "x8,x16,x32,x64"
|
|
newline
|
|
sif cpuis("STM32F72*")||cpuis("STM32F732*")||cpuis("STM32F733*")||cpuis("STM32F74*")||cpuis("STM32F756*")
|
|
bitfld.long 0x00 3.--6. " SNB ,Sector number" "0,1,2,3,4,5,6,7,?..."
|
|
newline
|
|
elif cpuis("STM32F730*")
|
|
bitfld.long 0x00 3.--6. " SNB ,Sector number" "0,1,2,3,?..."
|
|
newline
|
|
elif cpuis("STM32F750*")
|
|
bitfld.long 0x00 3.--6. " SNB ,Sector number" "0,1,?..."
|
|
newline
|
|
else
|
|
bitfld.long 0x00 3.--6. " SNB ,Sector number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 2. " MER ,Mass erase" "Not activated,Activated"
|
|
newline
|
|
bitfld.long 0x00 1. " SER ,Sector erase" "Not activated,Activated"
|
|
bitfld.long 0x00 0. " PG ,Flash programming" "Not activated,Activated"
|
|
endif
|
|
if (((per.l(ad:0x40023C00+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "OPTCR,FLash Option Control Register"
|
|
bitfld.long 0x00 31. " IWDG_STOP ,Independent watchdog counter freeze in stop mode" "Freezed,Not freezed"
|
|
bitfld.long 0x00 30. " IWDG_STDBY ,Independent watchdog counter freeze in standby mode" "Freezed,Not freezed"
|
|
newline
|
|
sif cpuis("STM32F72*")||cpuis("STM32F732*")||cpuis("STM32F733*")||cpuis("STM32F74*")||cpuis("STM32F756*")
|
|
bitfld.long 0x00 23. " NWRP[7] ,Not write protect sector 7" "No,Yes"
|
|
bitfld.long 0x00 22. " [6] ,Not write protect sector 6" "No,Yes"
|
|
bitfld.long 0x00 21. " [5] ,Not write protect sector 5" "No,Yes"
|
|
bitfld.long 0x00 20. " [4] ,Not write protect sector 4" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 19. " [3] ,Not write protect sector 3" "No,Yes"
|
|
bitfld.long 0x00 18. " [2] ,Not write protect sector 2" "No,Yes"
|
|
bitfld.long 0x00 17. " [1] ,Not write protect sector 1" "No,Yes"
|
|
bitfld.long 0x00 16. " [0] ,Not write protect sector 0" "No,Yes"
|
|
newline
|
|
elif cpuis("STM32F730*")
|
|
bitfld.long 0x00 19. " NWRP[3] ,Not write protect sector 3" "No,Yes"
|
|
bitfld.long 0x00 18. " [2] ,Not write protect sector 2" "No,Yes"
|
|
bitfld.long 0x00 17. " [1] ,Not write protect sector 1" "No,Yes"
|
|
bitfld.long 0x00 16. " [0] ,Not write protect sector 0" "No,Yes"
|
|
newline
|
|
elif cpuis("STM32F750*")
|
|
bitfld.long 0x00 17. " NWRP[1] ,Not write protect sector 1" "No,Yes"
|
|
bitfld.long 0x00 16. " [0] ,Not write protect sector 0" "No,Yes"
|
|
newline
|
|
endif
|
|
hexmask.long.byte 0x00 8.--15. 1. " RDP ,Read protect"
|
|
bitfld.long 0x00 7. " NRST_STDBY ,Reset generated when entering the standby mode" "Reset,No reset"
|
|
bitfld.long 0x00 6. " NRST_STOP ,Reset generated when entering the stop mode" "Reset,No reset"
|
|
bitfld.long 0x00 5. " IWDG_SW ,Independent watchdog selection" "Hardware,Software"
|
|
newline
|
|
bitfld.long 0x00 4. " WWDG_SW ,Window watchdog selection" "Hardware,Software"
|
|
bitfld.long 0x00 2.--3. " BOR_LEV ,BOR reset level" "VBOR3,VBOR2,VBOR1,BOR off"
|
|
bitfld.long 0x00 1. " OPTSTRT ,Option start" "Not started,Started"
|
|
bitfld.long 0x00 0. " OPTLOCK ,Option lock" "Not locked,Locked"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "OPTCR,FLash Option Control Register"
|
|
bitfld.long 0x00 31. " IWDG_STOP ,Independent watchdog counter freeze in stop mode" "Freezed,Not freezed"
|
|
bitfld.long 0x00 30. " IWDG_STDBY ,Independent watchdog counter freeze in standby mode" "Freezed,Not freezed"
|
|
newline
|
|
sif cpuis("STM32F72*")||cpuis("STM32F732*")||cpuis("STM32F733*")||cpuis("STM32F74*")||cpuis("STM32F756*")
|
|
bitfld.long 0x00 23. " NWRP[7] ,Not write protect sector 7" "No,Yes"
|
|
bitfld.long 0x00 22. " [6] ,Not write protect sector 6" "No,Yes"
|
|
bitfld.long 0x00 21. " [5] ,Not write protect sector 5" "No,Yes"
|
|
bitfld.long 0x00 20. " [4] ,Not write protect sector 4" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 19. " [3] ,Not write protect sector 3" "No,Yes"
|
|
bitfld.long 0x00 18. " [2] ,Not write protect sector 2" "No,Yes"
|
|
bitfld.long 0x00 17. " [1] ,Not write protect sector 1" "No,Yes"
|
|
bitfld.long 0x00 16. " [0] ,Not write protect sector 0" "No,Yes"
|
|
newline
|
|
elif cpuis("STM32F730*")
|
|
bitfld.long 0x00 19. " NWRP[3] ,Not write protect sector 3" "No,Yes"
|
|
bitfld.long 0x00 18. " [2] ,Not write protect sector 2" "No,Yes"
|
|
bitfld.long 0x00 17. " [1] ,Not write protect sector 1" "No,Yes"
|
|
bitfld.long 0x00 16. " [0] ,Not write protect sector 0" "No,Yes"
|
|
newline
|
|
elif cpuis("STM32F750*")
|
|
bitfld.long 0x00 17. " NWRP[1] ,Not write protect sector 1" "No,Yes"
|
|
bitfld.long 0x00 16. " [0] ,Not write protect sector 0" "No,Yes"
|
|
newline
|
|
endif
|
|
hexmask.long.byte 0x00 8.--15. 1. " RDP ,Read protect"
|
|
bitfld.long 0x00 7. " NRST_STDBY ,Reset generated when entering the standby mode" "Reset,No reset"
|
|
bitfld.long 0x00 6. " NRST_STOP ,Reset generated when entering the stop mode" "Reset,No reset"
|
|
bitfld.long 0x00 5. " IWDG_SW ,Independent watchdog selection" "Hardware,Software"
|
|
newline
|
|
bitfld.long 0x00 4. " WWDG_SW ,Window watchdog selection" "Hardware,Software"
|
|
bitfld.long 0x00 2.--3. " BOR_LEV ,BOR reset level" "VBOR3,VBOR2,VBOR1,BOR off"
|
|
bitfld.long 0x00 1. " OPTSTRT ,Option start" "Not started,Started"
|
|
bitfld.long 0x00 0. " OPTLOCK ,Option lock" "Not locked,Locked"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40023C00+0x14)&0x20000000)==0x00)
|
|
if (((per.l(ad:0x40023C00+0x10))&0x80000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CR,Flash Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Locks FLASH_CR register" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 25. " ERRIE ,Error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " EOPIE ,End of operation interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " STRT ,Triggers an erase operation" "Not erased,Erased"
|
|
newline
|
|
bitfld.long 0x00 15. " MER2 ,Bank 2 mass erase" "Not activated,Activated"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Program size" "x8,x16,x32,x64"
|
|
bitfld.long 0x00 7. " BNK ,Bank number" "Bank 1,Bank 2"
|
|
newline
|
|
bitfld.long 0x00 3.--6. " SNB ,Sector number" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
newline
|
|
bitfld.long 0x00 2. " MER1 ,Bank 1 mass erase" "Not activated,Activated"
|
|
newline
|
|
bitfld.long 0x00 1. " SER ,Sector erase" "Not activated,Activated"
|
|
bitfld.long 0x00 0. " PG ,Flash programming" "Not activated,Activated"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "CR,Flash Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Locks FLASH_CR register" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 25. " ERRIE ,Error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " EOPIE ,End of operation interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " STRT ,Triggers an erase operation" "Not erased,Erased"
|
|
newline
|
|
bitfld.long 0x00 15. " MER2 ,Bank 2 mass erase" "Not activated,Activated"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Program size" "x8,x16,x32,x64"
|
|
bitfld.long 0x00 7. " BNK ,Bank number" "Bank 1,Bank 2"
|
|
newline
|
|
bitfld.long 0x00 3.--6. " SNB ,Sector number" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
newline
|
|
bitfld.long 0x00 2. " MER1 ,Bank 1 mass erase" "Not activated,Activated"
|
|
newline
|
|
bitfld.long 0x00 1. " SER ,Sector erase" "Not activated,Activated"
|
|
bitfld.long 0x00 0. " PG ,Flash programming" "Not activated,Activated"
|
|
endif
|
|
if (((per.l(ad:0x40023C00+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "OPTCR,FLash Option Control Register"
|
|
bitfld.long 0x00 31. " IWDG_STOP ,Independent watchdog counter freeze in stop mode" "Freezed,Not freezed"
|
|
bitfld.long 0x00 30. " IWDG_STDBY ,Independent watchdog counter freeze in standby mode" "Freezed,Not freezed"
|
|
newline
|
|
bitfld.long 0x00 29. " NDBANK ,Not dual bank mode" "Dual bank,Single bank"
|
|
bitfld.long 0x00 28. " NDBOOT ,Dual boot mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " NWRP[11] ,Not write protect for bank 2 sector 10 and sector 11" "No,Yes"
|
|
bitfld.long 0x00 26. " [10] ,Not write protect for bank 2 sector 8 and sector 9" "No,Yes"
|
|
bitfld.long 0x00 25. " [9] ,Not write protect for bank 2 sector 6 and sector 7" "No,Yes"
|
|
bitfld.long 0x00 24. " [8] ,Not write protect for bank 2 sector 4 and sector 5" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 23. " [7] ,Not write protect for bank 2 sector 2 and sector 3" "No,Yes"
|
|
bitfld.long 0x00 22. " [6] ,Not write protect for bank 2 sector 0 and sector 1" "No,Yes"
|
|
bitfld.long 0x00 21. " [5] ,Not write protect for bank 1 sector 10 and sector 11" "No,Yes"
|
|
bitfld.long 0x00 20. " [4] ,Not write protect for bank 1 sector 8 and sector 9" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 19. " [3] ,Not write protect for bank 1 sector 6 and sector 7" "No,Yes"
|
|
bitfld.long 0x00 18. " [2] ,Not write protect for bank 1 sector 4 and sector 5" "No,Yes"
|
|
bitfld.long 0x00 17. " [1] ,Not write protect for bank 1 sector 2 and sector 3" "No,Yes"
|
|
bitfld.long 0x00 16. " [0] ,Not write protect for bank 1 sector 0 and sector 1" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " RDP ,Read protect"
|
|
bitfld.long 0x00 7. " NRST_STDBY ,Reset generated when entering the standby mode" "Reset,No reset"
|
|
bitfld.long 0x00 6. " NRST_STOP ,Reset generated when entering the stop mode" "Reset,No reset"
|
|
bitfld.long 0x00 5. " IWDG_SW ,Independent watchdog selection" "Hardware,Software"
|
|
newline
|
|
bitfld.long 0x00 4. " WWDG_SW ,Window watchdog selection" "Hardware,Software"
|
|
bitfld.long 0x00 2.--3. " BOR_LEV ,BOR reset level" "VBOR3,VBOR2,VBOR1,BOR off"
|
|
bitfld.long 0x00 1. " OPTSTRT ,Option start" "Not started,Started"
|
|
bitfld.long 0x00 0. " OPTLOCK ,Option lock" "Not locked,Locked"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "OPTCR,FLash Option Control Register"
|
|
bitfld.long 0x00 31. " IWDG_STOP ,Independent watchdog counter freeze in stop mode" "Freezed,Not freezed"
|
|
bitfld.long 0x00 30. " IWDG_STDBY ,Independent watchdog counter freeze in standby mode" "Freezed,Not freezed"
|
|
newline
|
|
bitfld.long 0x00 29. " NDBANK ,Not dual bank mode" "Dual bank,Single bank"
|
|
bitfld.long 0x00 28. " NDBOOT ,Dual boot mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " NWRP[11] ,Not write protect for bank 2 sector 10 and sector 11" "No,Yes"
|
|
bitfld.long 0x00 26. " [10] ,Not write protect for bank 2 sector 8 and sector 9" "No,Yes"
|
|
bitfld.long 0x00 25. " [9] ,Not write protect for bank 2 sector 6 and sector 7" "No,Yes"
|
|
bitfld.long 0x00 24. " [8] ,Not write protect for bank 2 sector 4 and sector 5" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 23. " [7] ,Not write protect for bank 2 sector 2 and sector 3" "No,Yes"
|
|
bitfld.long 0x00 22. " [6] ,Not write protect for bank 2 sector 0 and sector 1" "No,Yes"
|
|
bitfld.long 0x00 21. " [5] ,Not write protect for bank 1 sector 10 and sector 11" "No,Yes"
|
|
bitfld.long 0x00 20. " [4] ,Not write protect for bank 1 sector 8 and sector 9" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 19. " [3] ,Not write protect for bank 1 sector 6 and sector 7" "No,Yes"
|
|
bitfld.long 0x00 18. " [2] ,Not write protect for bank 1 sector 4 and sector 5" "No,Yes"
|
|
bitfld.long 0x00 17. " [1] ,Not write protect for bank 1 sector 2 and sector 3" "No,Yes"
|
|
bitfld.long 0x00 16. " [0] ,Not write protect for bank 1 sector 0 and sector 1" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " RDP ,Read protect"
|
|
bitfld.long 0x00 7. " NRST_STDBY ,Reset generated when entering the standby mode" "Reset,No reset"
|
|
bitfld.long 0x00 6. " NRST_STOP ,Reset generated when entering the stop mode" "Reset,No reset"
|
|
bitfld.long 0x00 5. " IWDG_SW ,Independent watchdog selection" "Hardware,Software"
|
|
newline
|
|
bitfld.long 0x00 4. " WWDG_SW ,Window watchdog selection" "Hardware,Software"
|
|
bitfld.long 0x00 2.--3. " BOR_LEV ,BOR reset level" "VBOR3,VBOR2,VBOR1,BOR off"
|
|
bitfld.long 0x00 1. " OPTSTRT ,Option start" "Not started,Started"
|
|
bitfld.long 0x00 0. " OPTLOCK ,Option lock" "Not locked,Locked"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40023C00+0x10))&0x80000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CR,Flash Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Locks FLASH_CR register" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 25. " ERRIE ,Error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " EOPIE ,End of operation interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " STRT ,Triggers an erase operation" "Not erased,Erased"
|
|
newline
|
|
bitfld.long 0x00 15. " MER2 ,Bank 2 mass erase" "Not activated,Activated"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Program size" "x8,x16,x32,x64"
|
|
newline
|
|
bitfld.long 0x00 3.--7. " SNB ,Sector number" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
newline
|
|
bitfld.long 0x00 2. " MER ,Mass erase" "Not activated,Activated"
|
|
newline
|
|
bitfld.long 0x00 1. " SER ,Sector erase" "Not activated,Activated"
|
|
bitfld.long 0x00 0. " PG ,Flash programming" "Not activated,Activated"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "CR,Flash Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,Locks FLASH_CR register" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 25. " ERRIE ,Error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " EOPIE ,End of operation interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " STRT ,Triggers an erase operation" "Not erased,Erased"
|
|
newline
|
|
bitfld.long 0x00 15. " MER2 ,Bank 2 mass erase" "Not activated,Activated"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Program size" "x8,x16,x32,x64"
|
|
newline
|
|
bitfld.long 0x00 3.--7. " SNB ,Sector number" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
newline
|
|
bitfld.long 0x00 2. " MER ,Mass erase" "Not activated,Activated"
|
|
newline
|
|
bitfld.long 0x00 1. " SER ,Sector erase" "Not activated,Activated"
|
|
bitfld.long 0x00 0. " PG ,Flash programming" "Not activated,Activated"
|
|
endif
|
|
if (((per.l(ad:0x40023C00+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "OPTCR,Flash Option Control Register"
|
|
bitfld.long 0x00 31. " IWDG_STOP ,Independent watchdog counter freeze in stop mode" "Freezed,Not freezed"
|
|
bitfld.long 0x00 30. " IWDG_STDBY ,Independent watchdog counter freeze in standby mode" "Freezed,Not freezed"
|
|
newline
|
|
bitfld.long 0x00 29. " NDBANK ,Not dual bank mode" "Dual bank,Single bank"
|
|
newline
|
|
bitfld.long 0x00 27. " NWRP[11] ,Not write protect sector 11" "No,Yes"
|
|
bitfld.long 0x00 26. " [10] ,Not write protect sector 10" "No,Yes"
|
|
bitfld.long 0x00 25. " [9] ,Not write protect sector 9" "No,Yes"
|
|
bitfld.long 0x00 24. " [8] ,Not write protect sector 8" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 23. " [7] ,Not write protect sector 7" "No,Yes"
|
|
bitfld.long 0x00 22. " [6] ,Not write protect sector 6" "No,Yes"
|
|
bitfld.long 0x00 21. " [5] ,Not write protect sector 5" "No,Yes"
|
|
bitfld.long 0x00 20. " [4] ,Not write protect sector 4" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 19. " [3] ,Not write protect sector 3" "No,Yes"
|
|
bitfld.long 0x00 18. " [2] ,Not write protect sector 2" "No,Yes"
|
|
bitfld.long 0x00 17. " [1] ,Not write protect sector 1" "No,Yes"
|
|
bitfld.long 0x00 16. " [0] ,Not write protect sector 0" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " RDP ,Read protect"
|
|
bitfld.long 0x00 7. " NRST_STDBY ,Reset generated when entering the standby mode" "Reset,No reset"
|
|
bitfld.long 0x00 6. " NRST_STOP ,Reset generated when entering the stop mode" "Reset,No reset"
|
|
bitfld.long 0x00 5. " IWDG_SW ,Independent watchdog selection" "Hardware,Software"
|
|
newline
|
|
bitfld.long 0x00 4. " WWDG_SW ,Window watchdog selection" "Hardware,Software"
|
|
bitfld.long 0x00 2.--3. " BOR_LEV ,BOR reset level" "VBOR3,VBOR2,VBOR1,BOR off"
|
|
bitfld.long 0x00 1. " OPTSTRT ,Option start" "Not started,Started"
|
|
bitfld.long 0x00 0. " OPTLOCK ,Option lock" "Not locked,Locked"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "OPTCR,Flash Option Control Register"
|
|
bitfld.long 0x00 31. " IWDG_STOP ,Independent watchdog counter freeze in stop mode" "Freezed,Not freezed"
|
|
bitfld.long 0x00 30. " IWDG_STDBY ,Independent watchdog counter freeze in standby mode" "Freezed,Not freezed"
|
|
newline
|
|
bitfld.long 0x00 29. " NDBANK ,Not dual bank mode" "Dual bank,Single bank"
|
|
newline
|
|
bitfld.long 0x00 27. " NWRP[11] ,Not write protect sector 11" "No,Yes"
|
|
bitfld.long 0x00 26. " [10] ,Not write protect sector 10" "No,Yes"
|
|
bitfld.long 0x00 25. " [9] ,Not write protect sector 9" "No,Yes"
|
|
bitfld.long 0x00 24. " [8] ,Not write protect sector 8" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 23. " [7] ,Not write protect sector 7" "No,Yes"
|
|
bitfld.long 0x00 22. " [6] ,Not write protect sector 6" "No,Yes"
|
|
bitfld.long 0x00 21. " [5] ,Not write protect sector 5" "No,Yes"
|
|
bitfld.long 0x00 20. " [4] ,Not write protect sector 4" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 19. " [3] ,Not write protect sector 3" "No,Yes"
|
|
bitfld.long 0x00 18. " [2] ,Not write protect sector 2" "No,Yes"
|
|
bitfld.long 0x00 17. " [1] ,Not write protect sector 1" "No,Yes"
|
|
bitfld.long 0x00 16. " [0] ,Not write protect sector 0" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " RDP ,Read protect"
|
|
bitfld.long 0x00 7. " NRST_STDBY ,Reset generated when entering the standby mode" "Reset,No reset"
|
|
bitfld.long 0x00 6. " NRST_STOP ,Reset generated when entering the stop mode" "Reset,No reset"
|
|
bitfld.long 0x00 5. " IWDG_SW ,Independent watchdog selection" "Hardware,Software"
|
|
newline
|
|
bitfld.long 0x00 4. " WWDG_SW ,Window watchdog selection" "Hardware,Software"
|
|
bitfld.long 0x00 2.--3. " BOR_LEV ,BOR reset level" "VBOR3,VBOR2,VBOR1,BOR off"
|
|
bitfld.long 0x00 1. " OPTSTRT ,Option start" "Not started,Started"
|
|
bitfld.long 0x00 0. " OPTLOCK ,Option lock" "Not locked,Locked"
|
|
endif
|
|
endif
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "OPTCR1,Flash Option Control Register 1"
|
|
hexmask.long.word 0x00 16.--31. 0x01 " BOOT_ADD1 ,Boot base address when boot pin = 1"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " BOOT_ADD0 ,Boot base address when boot pin = 0"
|
|
sif cpuis("STM32F72*")||cpuis("STM32F732*")||cpuis("STM32F733*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "OPTCR2,Flash Option Control Register 2"
|
|
bitfld.long 0x00 31. " PCROP_RDP ,PCROP zone preserved when RDP level decreased" "Kept,Erased"
|
|
newline
|
|
bitfld.long 0x00 7. " PCROP[7] ,PCROP option byte" "Not active,Active"
|
|
bitfld.long 0x00 6. " [6] ,PCROP option byte" "Not active,Active"
|
|
bitfld.long 0x00 5. " [5] ,PCROP option byte" "Not active,Active"
|
|
bitfld.long 0x00 4. " [4] ,PCROP option byte" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,PCROP option byte" "Not active,Active"
|
|
bitfld.long 0x00 2. " [2] ,PCROP option byte" "Not active,Active"
|
|
bitfld.long 0x00 1. " [1] ,PCROP option byte" "Not active,Active"
|
|
bitfld.long 0x00 0. " [0] ,PCROP option byte" "Not active,Active"
|
|
elif cpuis("STM32F730*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "OPTCR2,Flash Option Control Register 2"
|
|
bitfld.long 0x00 31. " PCROP_RDP ,PCROP zone preserved when RDP level decreased" "Kept,Erased"
|
|
newline
|
|
bitfld.long 0x00 3. " PCROP[3] ,PCROP option byte" "Not active,Active"
|
|
bitfld.long 0x00 2. " [2] ,PCROP option byte" "Not active,Active"
|
|
bitfld.long 0x00 1. " [1] ,PCROP option byte" "Not active,Active"
|
|
bitfld.long 0x00 0. " [0] ,PCROP option byte" "Not active,Active"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "PWR (Power Controller)"
|
|
base ad:0x40007000
|
|
width 6.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "CR1,PWR Power Control Register"
|
|
bitfld.long 0x00 18.--19. " UDEN ,Under-drive enable in stop mode" "Disabled,,,Enabled"
|
|
bitfld.long 0x00 17. " ODSWEN ,Over-drive switching enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ODEN ,Over-drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " VOS ,Regulator voltage scaling output selection" ",Scale 3,Scale 2,Scale 1"
|
|
newline
|
|
bitfld.long 0x00 13. " ADCDC1 ,ADC accuracy" "No effect,Activated"
|
|
bitfld.long 0x00 11. " MRUDS ,Main regulator in deepsleep under-drive mode" "Enabled,Under-driven"
|
|
bitfld.long 0x00 10. " LPUDS ,Low-power regulator in deepsleep under-drive mode" "Enabled,Under-driven"
|
|
bitfld.long 0x00 9. " FPDS ,Flash power-down in stop mode" "Off,On"
|
|
newline
|
|
bitfld.long 0x00 8. " DBP ,Disable backup domain write protection" "No,Yes"
|
|
bitfld.long 0x00 5.--7. " PLS ,PVD level selection" "2.0 V,2.1 V,2.3 V,2.5 V,2.6 V,2.7 V,2.8 V,2.9 V"
|
|
bitfld.long 0x00 4. " PVDE ,Power voltage detector enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " CSBF ,Clear STANDBY flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 1. " PDDS ,Power down deepsleep" "Stop,Standby"
|
|
bitfld.long 0x00 0. " LPDS ,Low-power deepsleep in stop mode" "Main regulator,Low-power regulator"
|
|
line.long 0x04 "CSR1,Power Control/Status Register"
|
|
bitfld.long 0x04 18.--19. " UDRDY ,Under-drive ready flag" "Disabled,,,Activated"
|
|
rbitfld.long 0x04 17. " ODSWRDY ,Over-drive mode switching ready" "Not ready,Ready"
|
|
rbitfld.long 0x04 16. " ODRDY ,Over-drive mode ready" "Not ready,Ready"
|
|
rbitfld.long 0x04 14. " VOSRDY ,Regulator voltage scaling output selection ready bit" "Not ready,Ready"
|
|
newline
|
|
bitfld.long 0x04 9. " BRE ,Backup regulator enable" "Disabled,Enabled"
|
|
sif cpuis("STM32F74*")||cpuis("STM32F75*")||cpuis("STM32F72*")||cpuis("STM32F73*")
|
|
bitfld.long 0x04 8. " EIWUP ,Enable internal wakeup" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
rbitfld.long 0x04 3. " BRR ,Backup regulator ready" "Not ready,Ready"
|
|
rbitfld.long 0x04 2. " PVDO ,PVD output" "VDD > PVD,VDD < PVD"
|
|
rbitfld.long 0x04 1. " SBF ,STANDBY flag" "No standby,Standby"
|
|
rbitfld.long 0x04 0. " WUIF ,Wakeup internal flag" "No wakeup,Wakeup"
|
|
line.long 0x08 "CR2,PWR Power Control/Status Register 2"
|
|
sif cpuis("STM32F72?I*")||cpuis("STM32F73?I*")||cpuis("STM32F750N8")
|
|
bitfld.long 0x08 13. " WUPP6 ,Wakeup pin polarity bit for PI11" "Rising edge,Falling edge"
|
|
bitfld.long 0x08 12. " WUPP5 ,Wakeup pin polarity bit for PI8" "Rising edge,Falling edge"
|
|
newline
|
|
endif
|
|
bitfld.long 0x08 11. " WUPP4 ,Wakeup pin polarity bit for PC13" "Rising edge,Falling edge"
|
|
bitfld.long 0x08 10. " WUPP3 ,Wakeup pin polarity bit for PC1" "Rising edge,Falling edge"
|
|
newline
|
|
bitfld.long 0x08 9. " WUPP2 ,Wakeup pin polarity bit for PA2" "Rising edge,Falling edge"
|
|
bitfld.long 0x08 8. " WUPP1 ,Wakeup pin polarity bit for PA0" "Rising edge,Falling edge"
|
|
newline
|
|
sif cpuis("STM32F72?I*")||cpuis("STM32F73?I*")||cpuis("STM32F750N8")
|
|
bitfld.long 0x08 5. " CWUPF6 ,Clear wakeup pin flag for PI11" "No effect,Clear"
|
|
bitfld.long 0x08 4. " CWUPF5 ,Clear wakeup pin flag for PI8" "No effect,Clear"
|
|
newline
|
|
endif
|
|
bitfld.long 0x08 3. " CWUPF4 ,Clear wakeup pin flag for PC13" "No effect,Clear"
|
|
bitfld.long 0x08 2. " CWUPF3 ,Clear wakeup pin flag for PC1" "No effect,Clear"
|
|
bitfld.long 0x08 1. " CWUPF2 ,Clear wakeup pin flag for PA2" "No effect,Clear"
|
|
bitfld.long 0x08 0. " CWUPF1 ,Clear wakeup pin flag for PA0" "No effect,Clear"
|
|
line.long 0x0C "CSR2,PWR Power Control Register 2"
|
|
sif cpuis("STM32F72?I*")||cpuis("STM32F73?I*")||cpuis("STM32F750N8")
|
|
bitfld.long 0x0C 13. " EWUP6 ,Enable wakeup pin for PI11" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " EWUP5 ,Enable wakeup pin for PI8" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0C 11. " EWUP4 ,Enable wakeup pin for PC13" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " EWUP3 ,Enable wakeup pin for PC1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 9. " EWUP2 ,Enable wakeup pin for PA2" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " EWUP1 ,Enable wakeup pin for PA0" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("STM32F72?I*")||cpuis("STM32F73?I*")||cpuis("STM32F750N8")
|
|
rbitfld.long 0x0C 5. " WUPF6 ,Wakeup pin flag for PI11" "No wakeup,Wakeup"
|
|
rbitfld.long 0x0C 4. " WUPF5 ,Wakeup pin flag for PI8" "No wakeup,Wakeup"
|
|
newline
|
|
endif
|
|
rbitfld.long 0x0C 3. " WUPF4 ,Wakeup pin flag for PC13" "No wakeup,Wakeup"
|
|
rbitfld.long 0x0C 2. " WUPF3 ,Wakeup pin flag for PC1" "No wakeup,Wakeup"
|
|
rbitfld.long 0x0C 1. " WUPF2 ,Wakeup pin flag for PA2" "No wakeup,Wakeup"
|
|
rbitfld.long 0x0C 0. " WUPF1 ,Wakeup pin flag for PA0" "No wakeup,Wakeup"
|
|
width 0x0B
|
|
tree.end
|
|
tree "RCC (Reset And Clock Control)"
|
|
base ad:0x40023800
|
|
width 12.
|
|
if (((per.l(ad:0x40023800))&0x10000)==0x10000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,RCC Clock Control Register"
|
|
sif cpuis("STM32F446*")||cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
rbitfld.long 0x00 29. " PLLSAIRDY ,PLLSAI clock ready flag" "Unlocked,Locked"
|
|
bitfld.long 0x00 28. " PLLSAION ,PLLSAI enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
rbitfld.long 0x00 27. " PLLI2SRDY ,PLLI2S clock ready flag" "Unlocked,Locked"
|
|
bitfld.long 0x00 26. " PLLI2SON ,PLLI2S enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " PLLRDY ,PLL clock ready flag" "Unlocked,Locked"
|
|
bitfld.long 0x00 24. " PLLON ,PLL enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " CSSON ,Clock security system enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 18. " HSEBYP ,HSE clock bypass" "Not bypassed,Bypassed"
|
|
rbitfld.long 0x00 17. " HSERDY ,HSE clock ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 16. " HSEON ,HSE clock enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " HSICAL ,Internal high speed clock calibration"
|
|
bitfld.long 0x00 3.--7. " HSITRIM ,Internal high speed clock trimming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 1. " HSIRDY ,Internal high speed clock ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " HSION ,Internal high speed clock enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,RCC Clock Control Register"
|
|
sif cpuis("STM32F446*")||cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
rbitfld.long 0x00 29. " PLLSAIRDY ,PLLSAI clock ready flag" "Unlocked,Locked"
|
|
bitfld.long 0x00 28. " PLLSAION ,PLLSAI enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
rbitfld.long 0x00 27. " PLLI2SRDY ,PLLI2S clock ready flag" "Unlocked,Locked"
|
|
bitfld.long 0x00 26. " PLLI2SON ,PLLI2S enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25. " PLLRDY ,PLL clock ready flag" "Unlocked,Locked"
|
|
bitfld.long 0x00 24. " PLLON ,PLL enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " CSSON ,Clock security system enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " HSEBYP ,HSE clock bypass" "Not bypassed,Bypassed"
|
|
rbitfld.long 0x00 17. " HSERDY ,HSE clock ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 16. " HSEON ,HSE clock enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " HSICAL ,Internal high speed clock calibration"
|
|
bitfld.long 0x00 3.--7. " HSITRIM ,Internal high speed clock trimming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 1. " HSIRDY ,Internal high speed clock ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " HSION ,Internal high speed clock enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40023800))&0x5000000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PLLCFGR,RCC PLL Configuration Register"
|
|
sif cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
bitfld.long 0x00 28.--30. " PLLR ,PLL division factor (I2S/SAI/SYSTEM/SPDIF)" ",,/2,/3,/4,/5,/6,/7"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 24.--27. " PLLQ ,PLL division factor (USB OTG FS / SDIO / RNG)" ",,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15"
|
|
bitfld.long 0x00 22. " PLLSRC ,PLL and PLLI2S entry clock source" "HSI,HSE"
|
|
bitfld.long 0x00 16.--17. " PLLP ,PLL division factor for main system clock" "/2,/4,/6,/8"
|
|
hexmask.long.word 0x00 6.--14. 1. " PLLN ,PLL multiplication factor for VCO"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " PLLM ,PLL and PLLI2S division factor for input clock" ",,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63"
|
|
elif (((per.l(ad:0x40023800))&0x1000000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PLLCFGR,RCC PLL Configuration Register"
|
|
sif cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
bitfld.long 0x00 28.--30. " PLLR ,PLL division factor (I2S/SAI/SYSTEM/SPDIF)" ",,/2,/3,/4,/5,/6,/7"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 24.--27. " PLLQ ,PLL division factor (USB OTG FS / SDIO / RNG)" ",,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15"
|
|
rbitfld.long 0x00 22. " PLLSRC ,PLL and PLLI2S entry clock source" "HSI,HSE"
|
|
bitfld.long 0x00 16.--17. " PLLP ,PLL division factor for main system clock" "/2,/4,/6,/8"
|
|
hexmask.long.word 0x00 6.--14. 1. " PLLN ,PLL multiplication factor for VCO"
|
|
newline
|
|
rbitfld.long 0x00 0.--5. " PLLM ,PLL and PLLI2S division factor for input clock" ",,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PLLCFGR,RCC PLL Configuration Register"
|
|
sif cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
bitfld.long 0x00 28.--30. " PLLR ,PLL division factor (I2S/SAI/SYSTEM/SPDIF)" ",,/2,/3,/4,/5,/6,/7"
|
|
newline
|
|
endif
|
|
rbitfld.long 0x00 24.--27. " PLLQ ,PLL division factor (USB OTG FS / SDIO / RNG)" ",,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15"
|
|
rbitfld.long 0x00 22. " PLLSRC ,PLL and PLLI2S entry clock source" "HSI,HSE"
|
|
rbitfld.long 0x00 16.--17. " PLLP ,PLL division factor for main system clock" "/2,/4,/6,/8"
|
|
hexmask.long.word 0x00 6.--14. 1. " PLLN ,PLL multiplication factor for VCO"
|
|
newline
|
|
rbitfld.long 0x00 0.--5. " PLLM ,PLL and PLLI2S division factor for input clock" ",,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63"
|
|
endif
|
|
group.long 0x08++0x0F
|
|
line.long 0x00 "CFGR,RCC Clock Configuration Register"
|
|
bitfld.long 0x00 30.--31. " MCO2 ,Clock output 2" "SYSCLK,PLLI2S,HSE,PLL"
|
|
bitfld.long 0x00 27.--29. " MCO2PRE ,MCO2 prescaler" "/1,/1,/1,/1,/2,/3,/4,/5"
|
|
bitfld.long 0x00 24.--26. " MCO1PRE ,MCO1 prescaler" "/1,/1,/1,/1,/2,/3,/4,/5"
|
|
sif !cpuis("STM32F446*")
|
|
bitfld.long 0x00 23. " I2SSRC ,I2S clock select" "PLLI2S,I2S_CKIN pin"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 21.--22. " MCO1 ,Clock output 1" "HSI,LSE,HSE,PLL"
|
|
bitfld.long 0x00 16.--20. " RTCPRE ,HSE division factor (RTC clock)" "/1,/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31"
|
|
bitfld.long 0x00 13.--15. " PPRE2 ,APB high-speed prescaler (APB2)" "/1,/1,/1,/1,/2,/4,/8,/16"
|
|
bitfld.long 0x00 10.--12. " PPRE1 ,APB low speed prescaler (APB1)" "/1,/1,/1,/1,/2,/4,/8,/16"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " HPRE ,AHB prescaler" "/1,/1,/1,/1,/1,/1,/1,/1,/2,/4,/8,/16,/64,/128,/256,/512"
|
|
rbitfld.long 0x00 2.--3. " SWS ,System clock switch status" "HSI,HSE,PLL,?..."
|
|
bitfld.long 0x00 0.--1. " SW ,System clock switch" "HSI,HSE,PLL,?..."
|
|
line.long 0x04 "CIR,RCC Clock Interrupt Register"
|
|
bitfld.long 0x04 23. " CSSC ,Clock security system interrupt clear" "No effect,Clear"
|
|
sif cpuis("STM32F446*")||cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F7*")
|
|
bitfld.long 0x04 22. " PLLSAIRDYC ,PLLSAI ready interrupt clear" "No effect,Clear"
|
|
endif
|
|
newline
|
|
bitfld.long 0x04 21. " PLLI2SRDYC ,PLLI2S ready interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x04 20. " PLLRDYC ,Main PLL (PLL) ready interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x04 19. " HSERDYC ,HSE ready interrupt clear" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 18. " HSIRDYC ,HSI ready interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x04 17. " LSERDYC ,LSE ready interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x04 16. " LSIRDYC ,LSI ready interrupt clear" "No effect,Clear"
|
|
newline
|
|
sif cpuis("STM32F446*")||cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F7*")
|
|
bitfld.long 0x04 14. " PLLSAIRDYIE ,PLLSAI ready interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 13. " PLLI2SRDYIE ,PLLI2S ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " PLLRDYIE ,Main PLL (PLL) ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " HSERDYIE ,HSE ready interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 10. " HSIRDYIE ,HSI ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " LSERDYIE ,LSE ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " LSIRDYIE ,LSI ready interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x04 7. " CSSF ,Clock security system interrupt flag" "No interrupt,Interrupt"
|
|
sif cpuis("STM32F446*")||cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F7*")
|
|
rbitfld.long 0x04 6. " PLLSAIRDYF ,PLLSAI ready interrupt flag" "No interrupt,Interrupt"
|
|
endif
|
|
newline
|
|
rbitfld.long 0x04 5. " PLLI2SRDYF ,PLLI2S ready interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x04 4. " PLLRDYF ,Main PLL (PLL) ready interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x04 3. " HSERDYF ,HSE ready interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
rbitfld.long 0x04 2. " HSIRDYF ,HSI ready interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x04 1. " LSERDYF ,LSE ready interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x04 0. " LSIRDYF ,LSI ready interrupt flag" "No interrupt,Interrupt"
|
|
line.long 0x08 "AHB1RSTR,RCC AHB1 Peripheral Reset Register"
|
|
sif !cpuis("STM32F411*")&&!cpuis("STM32F401*")
|
|
bitfld.long 0x08 29. " OTGHSRST ,USB OTG HS module reset" "No reset,Reset"
|
|
newline
|
|
endif
|
|
sif cpuis("STM32F407*")||cpuis("STM32F417*")||cpuis("STM32F427*")||cpuis("STM32F437*")||cpuis("STM32F429*")||cpuis("STM32F439*")||cpuis("STM32F7*")||cpuis("STM32F469I*")||cpuis("STM32F469B*")||cpuis("STM32F469N*")&&!cpuis("STM32F769A*")&&!cpuis("STM32F778A*")&&!cpuis("STM32F779A*")
|
|
sif !cpuis("STM32F72*")&&!cpuis("STM32F73*")
|
|
bitfld.long 0x08 25. " ETHMACRST ,Ethernet MAC reset" "No reset,Reset"
|
|
newline
|
|
endif
|
|
endif
|
|
sif cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
sif !cpuis("STM32F72*")&&!cpuis("STM32F73*")
|
|
bitfld.long 0x08 23. " DMA2DRST ,DMA2D reset" "No reset,Reset"
|
|
newline
|
|
endif
|
|
endif
|
|
bitfld.long 0x08 22. " DMA2RST ,DMA2 reset" "No reset,Reset"
|
|
bitfld.long 0x08 21. " DMA1RST ,DMA1 reset" "No reset,Reset"
|
|
bitfld.long 0x08 12. " CRCRST ,CRC reset" "No reset,Reset"
|
|
sif cpuis("STM32F429B*")||cpuis("STM32F429N*")||cpuis("STM32F439B*")||cpuis("STM32F439N*")||cpuis("STM32F439B*")||cpuis("STM32F439N*")||cpuis("STM32F439B*")||cpuis("STM32F439N*")||cpuis("STM32F745B*")||cpuis("STM32F745N*")||cpuis("STM32F746B*")||cpuis("STM32F746N*")||cpuis("STM32F756B*")||cpuis("STM32F756N*")||cpuis("STM32F765B*")||cpuis("STM32F765N*")||cpuis("STM32F767B*")||cpuis("STM32F767N*")||cpuis("STM32F769B*")||cpuis("STM32F769N*")||cpuis("STM32F777B*")||cpuis("STM32F777N*")||cpuis("STM32F779B*")||cpuis("STM32F779N*")||cpuis("STM32F750N8")
|
|
newline
|
|
bitfld.long 0x08 10. " GPIOKRST ,IO port K reset" "No reset,Reset"
|
|
bitfld.long 0x08 9. " GPIOJRST ,IO port J reset" "No reset,Reset"
|
|
endif
|
|
sif (cpuis("STM32F429B*")||cpuis("STM32F429N*")||cpuis("STM32F439B*")||cpuis("STM32F439N*")||cpuis("STM32F439B*")||cpuis("STM32F439N*")||cpuis("STM32F439B*")||cpuis("STM32F439N*")||cpuis("STM32F405O*")||cpuis("STM32F415O*")||cpuis("STM32F427A*")||cpuis("STM32F429A*")||cpuis("STM32F437A*")||cpuis("STM32F439A*")||cpuis("STM32F469A*")||cpuis("STM32F479A*")||cpuis("STM32F407I*")||cpuis("STM32F417I*")||cpuis("STM32F427I*")||cpuis("STM32F429I*")||cpuis("STM32F437I*")||cpuis("STM32F439I*")||cpuis("STM32F469I*")||cpuis("STM32F479I*")||cpuis("STM32F7*"))&&(!cpuis("STM32F745V*")&&!cpuis("STM32F745Z*")&&!cpuis("STM32F746V*")&&!cpuis("STM32F746Z*")&&!cpuis("STM32F756V*")&&!cpuis("STM32F756Z*")&&!cpuis("STM32F765V*")&&!cpuis("STM32F765Z*")&&!cpuis("STM32F767V*")&&!cpuis("STM32F767Z*")&&!cpuis("STM32F769V*")&&!cpuis("STM32F769Z*")&&!cpuis("STM32F777V*")&&!cpuis("STM32F777Z*")&&!cpuis("STM32F730R8")&&!cpuis("STM32F730V8")&&!cpuis("STM32F730Z8")&&!cpuis("STM32F750V8")&&!cpuis("STM32F750Z8"))
|
|
newline
|
|
bitfld.long 0x08 8. " GPIOIRST ,IO port I reset" "No reset,Reset"
|
|
endif
|
|
newline
|
|
bitfld.long 0x08 7. " GPIOHRST ,IO port H reset" "No reset,Reset"
|
|
newline
|
|
sif (cpuis("STM32F429B*")||cpuis("STM32F429N*")||cpuis("STM32F439B*")||cpuis("STM32F439N*")||cpuis("STM32F439B*")||cpuis("STM32F439N*")||cpuis("STM32F439B*")||cpuis("STM32F439N*")||cpuis("STM32F446Z*")||cpuis("STM32F405Z*")||cpuis("STM32F407Z*")||cpuis("STM32F415Z*")||cpuis("STM32F417Z*")||cpuis("STM32F427Z*")||cpuis("STM32F429Z*")||cpuis("STM32F437Z*")||cpuis("STM32F439Z*")||cpuis("STM32F469Z*")||cpuis("STM32F479Z*")||cpuis("STM32F427A*")||cpuis("STM32F429A*")||cpuis("STM32F437A*")||cpuis("STM32F439A*")||cpuis("STM32F469A*")||cpuis("STM32F479A*")||cpuis("STM32F407I*")||cpuis("STM32F417I*")||cpuis("STM32F427I*")||cpuis("STM32F429I*")||cpuis("STM32F437I*")||cpuis("STM32F439I*")||cpuis("STM32F469I*")||cpuis("STM32F479I*")||cpuis("STM32F7*"))&&(!cpuis("STM32F745V*")&&!cpuis("STM32F746V*")&&!cpuis("STM32F756V*")&&!cpuis("STM32F765V*")&&!cpuis("STM32F767V*")&&!cpuis("STM32F769V*")&&!cpuis("STM32F777V*")&&!cpuis("STM32F730R8")&&!cpuis("STM32F730V8")&&!cpuis("STM32F750V8"))
|
|
bitfld.long 0x08 6. " GPIOGRST ,IO port G reset" "No reset,Reset"
|
|
bitfld.long 0x08 5. " GPIOFRST ,IO port F reset" "No reset,Reset"
|
|
newline
|
|
endif
|
|
sif (!cpuis("STM32F401C*")&&!cpuis("STM32F411C*")&&!cpuis("STM32F401R*")&&!cpuis("STM32F411R*")&&!cpuis("STM32F446R*")&&!cpuis("STM32F405R*")&&!cpuis("STM32F415R*")&&!cpuis("STM32F730R8"))
|
|
bitfld.long 0x08 4. " GPIOERST ,IO port E reset" "No reset,Reset"
|
|
newline
|
|
endif
|
|
sif (!cpuis("STM32F401C*")&&!cpuis("STM32F411C*"))
|
|
bitfld.long 0x08 3. " GPIODRST ,IO port D reset" "No reset,Reset"
|
|
newline
|
|
endif
|
|
bitfld.long 0x08 2. " GPIOCRST ,IO port C reset" "No reset,Reset"
|
|
bitfld.long 0x08 1. " GPIOBRST ,IO port B reset" "No reset,Reset"
|
|
bitfld.long 0x08 0. " GPIOARST ,IO port A reset" "No reset,Reset"
|
|
line.long 0x0C "AHB2RSTR,RCC AHB2 Peripheral Reset Register"
|
|
bitfld.long 0x0C 7. " OTGFSRST ,USB OTG FS module reset" "No reset,Reset"
|
|
sif !(cpuis("STM32F411*")&&!cpuis("STM32F401*"))
|
|
newline
|
|
bitfld.long 0x0C 6. " RNGRST ,RNG module reset" "No reset,Reset"
|
|
sif (cpuis("STM32F41*")||cpuis("STM32F405*")||cpuis("STM32F427*")||cpuis("STM32F429*")||cpuis("STM32F437*")||cpuis("STM32F439*")||cpuis("STM32F756*")||cpuis("STM32F407*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F75*")||cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
newline
|
|
bitfld.long 0x0C 5. " HASHRST ,Hash module reset" "No reset,Reset"
|
|
bitfld.long 0x0C 4. " CRYPRST ,Cryptographic module reset" "No reset,Reset"
|
|
elif (cpuis("STM32F73*"))
|
|
newline
|
|
bitfld.long 0x0C 4. " AESRST ,AES module reset" "No reset,Reset"
|
|
endif
|
|
sif (cpuis("STM32F767*")||cpuis("STM32F768*")||cpuis("STM32F769*")||cpuis("STM32F77*"))
|
|
newline
|
|
bitfld.long 0x0C 1. " JPEGRST ,JPEG module reset" "No reset,Reset"
|
|
endif
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F407*")||cpuis("STM32F417*")||cpuis("STM32F427*")||cpuis("STM32F437*")||cpuis("STM32F429*")||cpuis("STM32F439*")||cpuis("STM32F7*"))
|
|
sif (!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
newline
|
|
bitfld.long 0x0C 0. " DCMIRST ,Camera interface reset" "No reset,Reset"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (!cpuis("STM32F4?5RG")&&!cpuis("STM32F401*")&&!cpuis("STM32F411*"))
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "AHB3RSTR,RCC AHB3 Peripheral Reset Register"
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*"))
|
|
sif (!cpuis("STM32F72*")&&!cpuis("STM32F73*")&&!cpuis("STM32F76*")&&!cpuis("STM32F77*")&&!cpuis("STM32F750*"))
|
|
bitfld.long 0x00 1. " QSPIRST ,QUADSPI module reset" "No reset,Reset"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 1. " QSPIRST ,Quad SPI memory controller reset" "No reset,Reset"
|
|
newline
|
|
endif
|
|
endif
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F7*"))
|
|
bitfld.long 0x00 0. " FMCRST ,Flexible memory controller module reset" "No reset,Reset"
|
|
else
|
|
bitfld.long 0x00 0. " FSMCRST ,Flexible static memory controller module reset" "No reset,Reset"
|
|
endif
|
|
else
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "AHB3RSTR,RCC AHB3 Peripheral Reset Register"
|
|
endif
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "APB1RSTR,RCC APB1 Peripheral Reset Register"
|
|
sif (cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*"))
|
|
sif (!cpuis("STM32F73?R*")&&!cpuis("STM32F72?R*"))
|
|
bitfld.long 0x00 31. " UART8RST ,UART 8 reset" "No reset,Reset"
|
|
bitfld.long 0x00 30. " UART7RST ,UART 7 reset" "No reset,Reset"
|
|
newline
|
|
endif
|
|
endif
|
|
sif (!cpuis("STM32F401*")&&!cpuis("STM32F411*"))
|
|
bitfld.long 0x00 29. " DACRST ,DAC interface reset" "No reset,Reset"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 28. " PWRRST ,Power interface reset" "No reset,Reset"
|
|
newline
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F7*")&&!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
bitfld.long 0x00 27. " CECRST ,CEC reset" "No reset,Reset"
|
|
newline
|
|
endif
|
|
sif (!cpuis("STM32F401*")&&!cpuis("STM32F411*"))
|
|
sif (!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
bitfld.long 0x00 26. " CAN2RST ,CAN2 reset" "No reset,Reset"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 25. " CAN1RST ,CAN1 reset" "No reset,Reset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32F446*"))
|
|
bitfld.long 0x00 24. " IFMPI2C1RST ,FMPI2C1 reset" "No reset,Reset"
|
|
newline
|
|
elif (cpuis("STM32F7*")&&!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
bitfld.long 0x00 24. " I2C4RST ,I2C4 reset" "No reset,Reset"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 23. " I2C3RST ,I2C3 reset" "No reset,Reset"
|
|
bitfld.long 0x00 22. " I2C2RST ,I2C 2 reset" "No reset,Reset"
|
|
bitfld.long 0x00 21. " I2C1RST ,I2C 1 reset" "No reset,Reset"
|
|
newline
|
|
sif cpuis("STM32F411*")||cpuis("STM32F401*")
|
|
bitfld.long 0x00 17. " USART2RST ,USART 2 reset" "No reset,Reset"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 20. " UART5RST ,USART 5 reset" "No reset,Reset"
|
|
bitfld.long 0x00 19. " UART4RST ,USART 4 reset" "No reset,Reset"
|
|
bitfld.long 0x00 18. " USART3RST ,USART 3 reset" "No reset,Reset"
|
|
bitfld.long 0x00 17. " USART2RST ,USART 2 reset" "No reset,Reset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F7*"))
|
|
sif (!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
bitfld.long 0x00 16. " SPDIFRXRST ,SPDIF-Rx reset" "No reset,Reset"
|
|
newline
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 15. " SPI3RST ,SPI 3 reset" "No reset,Reset"
|
|
bitfld.long 0x00 14. " SPI2RST ,SPI 2 reset" "No reset,Reset"
|
|
newline
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 13. " CAN3RST ,CAN 3 reset" "No reset,Reset"
|
|
newline
|
|
endif
|
|
sif cpuis("STM32F411*")||cpuis("STM32F401*")
|
|
bitfld.long 0x00 11. " WWDGRST ,Window watchdog reset" "No reset,Reset"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 11. " WWDGRST ,Window watchdog reset" "No reset,Reset"
|
|
newline
|
|
sif cpuis("STM32F7*")
|
|
sif !cpuis("STM32F73?R*")&&!cpuis("STM32F72?R*")
|
|
bitfld.long 0x00 9. " LPTIM1RST ,Low power timer 1 reset" "No reset,Reset"
|
|
newline
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 8. " TIM14RST ,TIM14 reset" "No reset,Reset"
|
|
bitfld.long 0x00 7. " TIM13RST ,TIM13 reset" "No reset,Reset"
|
|
newline
|
|
sif (!cpuis("STM32F723R*")&&!cpuis("STM32F733R*")&&!cpuis("STM32F723V*")&&!cpuis("STM32F733V*")&&!cpuis("STM32F723Z*")&&!cpuis("STM32F733Z*")&&!cpuis("STM32F730R*")&&!cpuis("STM32F730V*")&&!cpuis("STM32F730Z*"))
|
|
bitfld.long 0x00 6. " TIM12RST ,TIM12 reset" "No reset,Reset"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " TIM7RST ,TIM7 reset" "No reset,Reset"
|
|
bitfld.long 0x00 4. " TIM6RST ,TIM6 reset" "No reset,Reset"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 3. " TIM5RST ,TIM5 reset" "No reset,Reset"
|
|
bitfld.long 0x00 2. " TIM4RST ,TIM4 reset" "No reset,Reset"
|
|
bitfld.long 0x00 1. " TIM3RST ,TIM3 reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " TIM2RST ,TIM2 reset" "No reset,Reset"
|
|
line.long 0x04 "APB2RSTR,RCC APB2 Peripheral Reset Register"
|
|
sif (cpuis("STM32F723*")||cpuis("STM32F733*")||cpuis("STM32F730Z*")||cpuis("STM32F730I*"))
|
|
bitfld.long 0x04 31. " OTGPHYCRST ,USB OTG HS PHY controller reset" "No reset,Reset"
|
|
newline
|
|
elif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x04 30. " MDIORST ,MDIO module reset" "No reset,Reset"
|
|
bitfld.long 0x04 29. " DFSDM1RST ,DFSDM1 module reset" "No reset,Reset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F769A*")||cpuis("STM32F767I*")||cpuis("STM32F769I*")||cpuis("STM32F767B*")||cpuis("STM32F769B*")||cpuis("STM32F767N*")||cpuis("STM32F769N*")||cpuis("STM32F778A*")||cpuis("STM32F779A*")||cpuis("STM32F777I*")||cpuis("STM32F779I*")||cpuis("STM32F777B*")||cpuis("STM32F779B*")||cpuis("STM32F777N*")||cpuis("STM32F779N*"))
|
|
bitfld.long 0x04 27. " DSIRST ,DSI host reset" "No reset,Reset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32F429*")||cpuis("STM32F439*")||cpuis("STM32F746*")||cpuis("STM32F750*")||cpuis("STM32F756*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F746*")||cpuis("STM32F75*")||cpuis("STM32F767*")||cpuis("STM32F768*")||cpuis("STM32F769*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x04 26. " LTDCRST ,LTDC reset" "No reset,Reset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F469*")||cpuis("STM32F479*"))
|
|
bitfld.long 0x04 22. " SAI1RST ,SAI1 reset" "No reset,Reset"
|
|
newline
|
|
sif (!cpuis("STM32F427V*")&&!cpuis("STM32F429V*")&&!cpuis("STM32F437V*")&&!cpuis("STM32F439V*")&&!cpuis("STM32F469V*")&&!cpuis("STM32F479V*")&&!cpuis("STM32F469Z*")&&!cpuis("STM32F479Z*")&&!cpuis("STM32F745V*")&&!cpuis("STM32F746V*")&&!cpuis("STM32F756V*")&&!cpuis("STM32F765V*")&&!cpuis("STM32F767V*")&&!cpuis("STM32F769V*")&&!cpuis("STM32F777V*"))
|
|
bitfld.long 0x04 21. " SPI6RST ,SPI 6 reset" "No reset,Reset"
|
|
bitfld.long 0x04 20. " SPI5RST ,SPI 5 reset" "No reset,Reset"
|
|
newline
|
|
endif
|
|
elif (cpuis("STM32F446*")||cpuis("STM32F7*"))
|
|
bitfld.long 0x04 23. " SAI2RST ,SAI2 reset" "No reset,Reset"
|
|
bitfld.long 0x04 22. " SAI1RST ,SAI1 reset" "No reset,Reset"
|
|
newline
|
|
sif (cpuis("STM32F7*"))
|
|
sif (!cpuis("STM32F72*")&&!cpuis("STM32F73*")&&!cpuis("STM32F750V*"))
|
|
bitfld.long 0x04 21. " SPI6RST ,SPI 6 reset" "No reset,Reset"
|
|
newline
|
|
endif
|
|
sif (!cpuis("STM32F72?R*")&&!cpuis("STM32F73?R*")&&!cpuis("STM32F72?V*")&&!cpuis("STM32F73?V*")&&!cpuis("STM32F750V*"))
|
|
bitfld.long 0x04 20. " SPI5RST ,SPI 5 reset" "No reset,Reset"
|
|
newline
|
|
endif
|
|
endif
|
|
elif cpuis("STM32F411*")
|
|
bitfld.long 0x04 20. " SPI5RST ,SPI 5 reset" "No reset,Reset"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 18. " TIM11RST ,TIM11 reset" "No reset,Reset"
|
|
bitfld.long 0x04 17. " TIM10RST ,TIM10 reset" "No reset,Reset"
|
|
bitfld.long 0x04 16. " TIM9RST ,TIM9 reset" "No reset,Reset"
|
|
bitfld.long 0x04 14. " SYSCFGRST ,System configuration controller reset" "No reset,Reset"
|
|
newline
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F411*")||cpuis("STM32F401V*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*"))
|
|
sif (!cpuis("STM32F72?R*")&&!cpuis("STM32F73?R*"))
|
|
bitfld.long 0x04 13. " SPI4RST ,SPI 4 reset" "No reset,Reset"
|
|
newline
|
|
endif
|
|
endif
|
|
bitfld.long 0x04 12. " SPI1RST ,SPI 1 reset" "No reset,Reset"
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F750*")||cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x04 11. " SDMMC1RST ,SDMMC1 reset" "No reset,Reset"
|
|
else
|
|
bitfld.long 0x04 11. " SDIORST ,SDIO reset" "No reset,Reset"
|
|
endif
|
|
newline
|
|
bitfld.long 0x04 8. " ADCRST ,ADC reset" "No reset,Reset"
|
|
newline
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
sif (!cpuis("STM32F72?R*")&&!cpuis("STM32F73?R*")&&!cpuis("STM32F723V*")&&!cpuis("STM32F730V*")&&!cpuis("STM32F733V*"))
|
|
bitfld.long 0x04 7. " SDMMC2RST ,SDMMC2 reset" "No reset,Reset"
|
|
newline
|
|
endif
|
|
endif
|
|
bitfld.long 0x04 5. " USART6RST ,USART6 reset" "No reset,Reset"
|
|
bitfld.long 0x04 4. " USART1RST ,USART1 reset" "No reset,Reset"
|
|
newline
|
|
sif (!cpuis("STM32F411*")&&!cpuis("STM32F401*"))
|
|
bitfld.long 0x04 1. " TIM8RST ,TIM8 reset" "No reset,Reset"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 0. " TIM1RST ,TIM1 reset" "No reset,Reset"
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "AHB1ENR,RCC AHB1 Peripheral Clock Enable Register"
|
|
sif (!cpuis("STM32F401*")&&!cpuis("STM32F411*"))
|
|
sif (!cpuis("STM32F723*")&&!cpuis("STM32F733*"))
|
|
bitfld.long 0x00 30. " OTGHSULPIEN ,USB OTG HSULPI clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 29. " OTGHSEN ,USB OTG HS clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif (!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
sif (cpuis("STM32F407*")||cpuis("STM32F417*")||cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F7*")||cpuis("STM32F469I*")||cpuis("STM32F469B*")||cpuis("STM32F469N*")||cpuis("STM32F479I*")||cpuis("STM32F479B*")||cpuis("STM32F479N*"))&&(!cpuis("STM32F769A*")&&!cpuis("STM32F778A*")&&!cpuis("STM32F779A*"))
|
|
bitfld.long 0x00 28. " ETHMACPTPEN ,Ethernet PTP clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ETHMACRXEN ,Ethernet reception clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " ETHMACTXEN ,Ethernet transmission clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " ETHMACEN ,Ethernet MAC clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*"))
|
|
sif (!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
bitfld.long 0x00 23. " DMA2DEN ,DMA2D clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 22. " DMA2EN ,DMA2 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " DMA1EN ,DMA1 clock enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F750*")||cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 20. " DTCMRAMEN ,DTCM data RAM clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " BKPSRAMEN ,Backup SRAM interface clock enable" "Disabled,Enabled"
|
|
newline
|
|
elif (cpuis("STM32F446*"))
|
|
bitfld.long 0x00 18. " BKPSRAMEN ,Backup SRAM interface clock enable" "Disabled,Enabled"
|
|
newline
|
|
elif (!cpuis("STM32F411*")&&!cpuis("STM32F401*"))
|
|
bitfld.long 0x00 20. " CCMDATARAMEN ,CCM data RAM clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " BKPSRAMEN ,Backup SRAM interface clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 12. " CRCEN ,CRC clock enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("STM32F429B*")||cpuis("STM32F429N*")||cpuis("STM32F439B*")||cpuis("STM32F439N*")||cpuis("STM32F469B*")||cpuis("STM32F469N*")||cpuis("STM32F479B*")||cpuis("STM32F479N*")||cpuis("STM32F7??B?")||cpuis("STM32F7??N?")||cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32F745B*")||cpuis("STM32F745N*")||cpuis("STM32F746B*")||cpuis("STM32F746N*")||cpuis("STM32F756B*")||cpuis("STM32F756N*")||cpuis("STM32F765B*")||cpuis("STM32F765N*")||cpuis("STM32F767B*")||cpuis("STM32F767N*")||cpuis("STM32F769B*")||cpuis("STM32F769N*")||cpuis("STM32F777B*")||cpuis("STM32F777N*")||cpuis("STM32F779B*")||cpuis("STM32F779N*")&&!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
bitfld.long 0x00 10. " GPIOKEN ,IO port K clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " GPIOJEN ,IO port J clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif ((cpuis("STM32F405OE")||cpuis("STM32F405OG")||cpuis("STM32F415OG")||cpuis("STM32F429B*")||cpuis("STM32F429N*")||cpuis("STM32F439B*")||cpuis("STM32F439N*")||cpuis("STM32F469B*")||cpuis("STM32F469N*")||cpuis("STM32F479B*")||cpuis("STM32F479N*")||cpuis("STM32F7??B?")||cpuis("STM32F7??N?")||cpuis("STM32F7??I?")||cpuis("STM32F405O*")||cpuis("STM32F415O*")||cpuis("STM32F427A*")||cpuis("STM32F429A*")||cpuis("STM32F437A*")||cpuis("STM32F439A*")||cpuis("STM32F469A*")||cpuis("STM32F479A*")||cpuis("STM32F407I*")||cpuis("STM32F417I*")||cpuis("STM32F427I*")||cpuis("STM32F429I*")||cpuis("STM32F437I*")||cpuis("STM32F439I*")||cpuis("STM32F469I*")||cpuis("STM32F479I*")||cpuis("STM32F76*")||cpuis("STM32F77*"))&&(!cpuis("STM32F745V*")&&!cpuis("STM32F745Z*")&&!cpuis("STM32F746V*")&&!cpuis("STM32F746Z*")&&!cpuis("STM32F756V*")&&!cpuis("STM32F756Z*")&&!cpuis("STM32F765V*")&&!cpuis("STM32F765Z*")&&!cpuis("STM32F767V*")&&!cpuis("STM32F767Z*")&&!cpuis("STM32F769V*")&&!cpuis("STM32F769Z*")&&!cpuis("STM32F777V*")&&!cpuis("STM32F777Z*")))
|
|
bitfld.long 0x00 8. " GPIOIEN ,IO port I clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 7. " GPIOHEN ,IO port H clock enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("STM32F429B*")||cpuis("STM32F429N*")||cpuis("STM32F439B*")||cpuis("STM32F439N*")||cpuis("STM32F469B*")||cpuis("STM32F469N*")||cpuis("STM32F479B*")||cpuis("STM32F479N*")||cpuis("STM32F7??B?")||cpuis("STM32F7??N?")||cpuis("STM32F7??Z?")||cpuis("STM32F7??I?")||cpuis("STM32F405O*")||cpuis("STM32F415O*")||cpuis("STM32F427A*")||cpuis("STM32F429A*")||cpuis("STM32F437A*")||cpuis("STM32F439A*")||cpuis("STM32F469A*")||cpuis("STM32F479A*")||cpuis("STM32F407I*")||cpuis("STM32F417I*")||cpuis("STM32F427I*")||cpuis("STM32F429I*")||cpuis("STM32F437I*")||cpuis("STM32F439I*")||cpuis("STM32F469I*")||cpuis("STM32F479I*")||cpuis("STM32F446Z*")||cpuis("STM32F405Z*")||cpuis("STM32F407Z*")||cpuis("STM32F415Z*")||cpuis("STM32F417Z*")||cpuis("STM32F427Z*")||cpuis("STM32F429Z*")||cpuis("STM32F437Z*")||cpuis("STM32F439Z*")||cpuis("STM32F469Z*")||cpuis("STM32F479Z*"))&&(!cpuis("STM32F745V*")&&!cpuis("STM32F746V*")&&!cpuis("STM32F756V*")&&!cpuis("STM32F765V*")&&!cpuis("STM32F767V*")&&!cpuis("STM32F769V*")&&!cpuis("STM32F777V*"))
|
|
bitfld.long 0x00 6. " GPIOGEN ,IO port G clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " GPIOFEN ,IO port F clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif !cpuis("STM32F401C*")&&!cpuis("STM32F411C*")&&!cpuis("STM32F411R*")&&!cpuis("STM32F446R*")&&!cpuis("STM32F405R*")&&!cpuis("STM32F415R*")&&!cpuis("STM32F730R*")
|
|
sif cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32F750*")||cpuis("STM32F72*")||cpuis("STM32F73*")
|
|
bitfld.long 0x00 4. " GPIOEEN ,IO port E clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
endif
|
|
sif !cpuis("STM32F401C*")&&!cpuis("STM32F411C*")
|
|
sif cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F750*")
|
|
bitfld.long 0x00 3. " GPIODEN ,IO port D clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 2. " GPIOCEN ,IO port C clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " GPIOBEN ,IO port B clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " GPIOAEN ,IO port A clock enable" "Disabled,Enabled"
|
|
line.long 0x04 "AHB2ENR,RCC AHB2 Peripheral Clock Enable Register"
|
|
bitfld.long 0x04 7. " OTGFSEN ,USB OTG FS clock enable" "Disabled,Enabled"
|
|
newline
|
|
sif (!cpuis("STM32F446*")&&!cpuis("STM32F411*")&&!cpuis("STM32F401*"))
|
|
bitfld.long 0x04 6. " RNGEN ,Random number generator clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32F405*")||cpuis("STM32F41*")||cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F756*")||cpuis("STM32F407*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F75*")||cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x04 5. " HASHEN ,Hash modules clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " CRYPEN ,Cryptography modules clock enable" "Disabled,Enabled"
|
|
newline
|
|
elif (cpuis("STM32F73*"))
|
|
bitfld.long 0x04 4. " AESEN ,AES module clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32F767*")||cpuis("STM32F768*")||cpuis("STM32F769*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x04 1. " JPEGEN ,JPEG module clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif (!cpuis("STM32F4?5*")&&!cpuis("STM32F401*")&&!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
bitfld.long 0x04 0. " DCMIEN ,Camera interface enable" "Disabled,Enabled"
|
|
endif
|
|
sif (!cpuis("STM32F4?5RG")&&!cpuis("STM32F401*")&&!cpuis("STM32F411*"))
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "AHB3ENR,RCC AHB3 Peripheral Clock Enable Register"
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F7*"))
|
|
bitfld.long 0x00 1. " QSPIEN ,QUADSPI memory controller module clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*"))
|
|
sif !cpuis("STM32F730R*")
|
|
bitfld.long 0x00 0. " FMCEN ,Flexible memory controller module clock enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
bitfld.long 0x00 0. " FSMCEN ,Flexible static memory controller module clock enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "APB1ENR,RCC APB1 Peripheral Clock Enable Register"
|
|
sif (cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F7*")||cpuis("STM32F407*")||cpuis("STM32F469*")||cpuis("STM32F479*"))
|
|
sif (!cpuis("STM32F73?R*")&&!cpuis("STM32F72?R*"))
|
|
bitfld.long 0x00 31. " UART8EN ,UART 8 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " UART7EN ,UART 7 enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
endif
|
|
sif (!cpuis("STM32F401*")&&!cpuis("STM32F411*"))
|
|
bitfld.long 0x00 29. " DACEN ,DAC interface clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 28. " PWREN ,Power interface clock enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F7*"))
|
|
sif (!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
bitfld.long 0x00 27. " CECEN ,CEC interface clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
endif
|
|
sif (!cpuis("STM32F401*")&&!cpuis("STM32F411*"))
|
|
sif (!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
bitfld.long 0x00 26. " CAN2EN ,CAN2 clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 25. " CAN1EN ,CAN1 clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32F446*"))
|
|
bitfld.long 0x00 24. " FMPI2C1EN ,FMPI2C1 clock enable" "Disabled,Enabled"
|
|
newline
|
|
elif (cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32F750*"))
|
|
bitfld.long 0x00 24. " I2C4 ,I2C4 clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 23. " I2C3EN ,I2C 3 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " I2C2EN ,I2C 2 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " I2C1EN ,I2C 1 clock enable" "Disabled,Enabled"
|
|
newline
|
|
sif (!cpuis("STM32F401*")&&!cpuis("STM32F411*"))
|
|
bitfld.long 0x00 20. " UART5EN ,UART 5 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " UART4EN ,UART 4 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " USART3EN ,USART 3 clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 17. " USART2EN ,USART 2 clock enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F7*"))&&(!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
bitfld.long 0x00 16. " SPDIFRXEN ,SPDIF-Rx clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15. " SPI3EN ,SPI 3 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SPI2EN ,SPI 2 clock enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))&&(!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
bitfld.long 0x00 13. " CAN3EN ,CAN 3 clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif cpuis("STM32F411*")||cpuis("STM32F401*")
|
|
bitfld.long 0x00 11. " WWDGEN ,Window watchdog clock enable" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 11. " WWDGEN ,Window watchdog clock enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("STM32F7*")
|
|
sif !cpuis("STM32F74*")&&!cpuis("STM32F75*")
|
|
bitfld.long 0x00 10. " RTCAPBEN ,RTC register interface clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif !cpuis("STM32F73?R*")&&!cpuis("STM32F72?R*")
|
|
bitfld.long 0x00 9. " LPTIM1EN ,Low power timer 1 clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 8. " TIM14EN ,TIM14 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TIM13EN ,TIM13 clock enable" "Disabled,Enabled"
|
|
newline
|
|
sif (!cpuis("STM32F723R*")&&!cpuis("STM32F733R*")&&!cpuis("STM32F723V*")&&!cpuis("STM32F733V*")&&!cpuis("STM32F723Z*")&&!cpuis("STM32F733Z*")&&!cpuis("STM32F730R*")&&!cpuis("STM32F730V*")&&!cpuis("STM32F730Z*"))
|
|
bitfld.long 0x00 6. " TIM12EN ,TIM12 clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " TIM7EN ,TIM7 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TIM6EN ,TIM6 clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 3. " TIM5EN ,TIM5 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TIM4EN ,TIM4 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIM3EN ,TIM3 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TIM2EN ,TIM2 clock enable" "Disabled,Enabled"
|
|
line.long 0x04 "APB2ENR,RCC APB2 Peripheral Clock Enable Register"
|
|
sif (cpuis("STM32F723*")||cpuis("STM32F733*")||cpuis("STM32F730Z*")||cpuis("STM32F730I*"))
|
|
bitfld.long 0x04 31. " OTGPHYCEN ,USB OTG HS PHY controller clock enable""Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x04 30. " MDIOEN ,MDIO clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " DFSDM1EN ,DFSDM1 module reset" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x04 27. " DSIEN ,DSI clocks enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32F429*")||cpuis("STM32F439*")||cpuis("STM32F746*")||cpuis("STM32F756*")||cpuis("STM32F756*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x04 26. " LTDCEN ,LTDC clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F469*")||cpuis("STM32F479*"))
|
|
bitfld.long 0x04 22. " SAI1EN ,SAI1 clock enable" "Disabled,Enabled"
|
|
newline
|
|
sif (!cpuis("STM32F427V*")&&!cpuis("STM32F429V*")&&!cpuis("STM32F437V*")&&!cpuis("STM32F439V*")&&!cpuis("STM32F469V*")&&!cpuis("STM32F479V*")&&!cpuis("STM32F469Z*")&&!cpuis("STM32F479Z*"))
|
|
bitfld.long 0x04 21. " SPI6EN ,SPI 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " SPI5EN ,SPI 5 enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
elif (cpuis("STM32F446*")||cpuis("STM32F7*"))
|
|
bitfld.long 0x04 23. " SAI2EN ,SAI2 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " SAI1EN ,SAI1 clock enable" "Disabled,Enabled"
|
|
newline
|
|
sif (!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
sif (cpuis("STM32F7??Z?")||cpuis("STM32F7??I?")||cpuis("STM32F7??B?")||cpuis("STM32F7??N?"))
|
|
bitfld.long 0x04 21. " SPI6EN ,SPI 6 enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
endif
|
|
sif (!cpuis("STM32F72?R*")&&!cpuis("STM32F73?R*")&&!cpuis("STM32F72?V*")&&!cpuis("STM32F73?V*")&&!cpuis("STM32F750V*"))
|
|
bitfld.long 0x04 20. " SPI5EN ,SPI 5 enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
elif cpuis("STM32F411*")
|
|
bitfld.long 0x04 20. " SPI5EN ,SPI 5 enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 18. " TIM11EN ,TIM11 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " TIM10EN ,TIM10 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " TIM9EN ,TIM9 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " SYSCFGEN ,System configuration controller clock enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F411*")||cpuis("STM32F401V*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*"))
|
|
sif (!cpuis("STM32F72?R*")&&!cpuis("STM32F73?R*"))
|
|
bitfld.long 0x04 13. " SPI4EN ,SPI 4 clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
endif
|
|
bitfld.long 0x04 12. " SPI1EN ,SPI 1 clock enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("STM32F7*")
|
|
bitfld.long 0x04 11. " SDMMC1EN ,SDMMC1 clock enable" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x04 11. " SDIOEN ,SDIO clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif (!cpuis("STM32F411*")&&!cpuis("STM32F401*"))
|
|
bitfld.long 0x04 10. " ADC3EN ,ADC3 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " ADC2EN ,ADC2 clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 8. " ADC1EN ,ADC1 clock enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
sif (!cpuis("STM32F72?R*")&&!cpuis("STM32F73?R*")&&!cpuis("STM32F723V*")&&!cpuis("STM32F733V*"))
|
|
bitfld.long 0x04 7. " SDMMC2EN ,SDMMC2 clock enable""Disabled,Enabled"
|
|
newline
|
|
endif
|
|
endif
|
|
bitfld.long 0x04 5. " USART6EN ,USART6 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " USART1EN ,USART1 clock enable" "Disabled,Enabled"
|
|
newline
|
|
sif (!cpuis("STM32F411*")&&!cpuis("STM32F401*"))
|
|
bitfld.long 0x04 1. " TIM8EN ,TIM8 clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 0. " TIM1EN ,TIM1 clock enable" "Disabled,Enabled"
|
|
group.long 0x50++0x07
|
|
line.long 0x00 "AHB1LPENR,RCC AHB1 Peripheral Clock Enable In Low Power Mode Register"
|
|
sif (!cpuis("STM32F401*")&&!cpuis("STM32F411*"))
|
|
sif (cpuis("STM32F7?2*")||cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32F750*"))
|
|
bitfld.long 0x00 30. " OTGHSULPILPEN ,USB OTG HS ULPI clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 29. " OTGHSLPEN ,USB OTG HS clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32F407*")||cpuis("STM32F417*")||cpuis("STM32F427*")||cpuis("STM32F429*")||cpuis("STM32F437*")||cpuis("STM32F439*")||cpuis("STM32F469I*")||cpuis("STM32F469B*")||cpuis("STM32F469N*")||cpuis("STM32F479I*")||cpuis("STM32F479B*")||cpuis("STM32F479N*")||cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32F750*"))&&(!cpuis("STM32F769A*")&&!cpuis("STM32F778A*")&&!cpuis("STM32F779A*"))
|
|
bitfld.long 0x00 28. " ETHMACPTPLPEN ,Ethernet PTP clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ETHMACRXLPEN ,Ethernet reception clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " ETHMACTXLPEN ,Ethernet transmission clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " ETHMACLPEN ,Ethernet MAC clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32F750*"))
|
|
bitfld.long 0x00 23. " DMA2DLPEN ,DMA2D clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 22. " DMA2LPEN ,DMA2 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " DMA1LPEN ,DMA1 clock enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("STM32F7*"))
|
|
bitfld.long 0x00 20. " DTCMLPEN ,DTCM RAM interface clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32F42*")||cpuis("STM32F443*"))
|
|
bitfld.long 0x00 19. " SRAM3LPEN ,SRAM 3 interface clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif cpuis("STM32F411*")||cpuis("STM32F401*")
|
|
bitfld.long 0x00 16. " SRAM1LPEN ,SRAM 1interface clock enable" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 18. " BKPSRAMLPEN ,Backup SRAM interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SRAM2LPEN ,SRAM 2 interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " SRAM1LPEN ,SRAM 1interface clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15. " FLITFLPEN ,Flash interface clock enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("STM32F7*"))
|
|
bitfld.long 0x00 13. " AXILPEN ,AXI to AHB bridge clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 12. " CRCLPEN ,CRC clock enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("STM32F429B*")||cpuis("STM32F429N*")||cpuis("STM32F439B*")||cpuis("STM32F439N*")||cpuis("STM32F469B*")||cpuis("STM32F469N*")||cpuis("STM32F479B*")||cpuis("STM32F479N*")||cpuis("STM32F7??B?")||cpuis("STM32F7??N?")||cpuis("STM32F7??I?")||cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32F745B*")||cpuis("STM32F745N*")||cpuis("STM32F746B*")||cpuis("STM32F746N*")||cpuis("STM32F756B*")||cpuis("STM32F756N*")||cpuis("STM32F765B*")||cpuis("STM32F765N*")||cpuis("STM32F767B*")||cpuis("STM32F767N*")||cpuis("STM32F769B*")||cpuis("STM32F769N*")||cpuis("STM32F777B*")||cpuis("STM32F777N*")||cpuis("STM32F779B*")||cpuis("STM32F779N*"))&&(!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
bitfld.long 0x00 10. " GPIOKLPEN ,IO port K clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " GPIOJLPEN ,IO port J clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32F405OE")||cpuis("STM32F405OG")||cpuis("STM32F415OG")||cpuis("STM32F429B*")||cpuis("STM32F429N*")||cpuis("STM32F439B*")||cpuis("STM32F439N*")||cpuis("STM32F469B*")||cpuis("STM32F469N*")||cpuis("STM32F479B*")||cpuis("STM32F479N*")||cpuis("STM32F7??B?")||cpuis("STM32F7??N?")||cpuis("STM32F7??I?")||cpuis("STM32F405O*")||cpuis("STM32F415O*")||cpuis("STM32F427A*")||cpuis("STM32F429A*")||cpuis("STM32F437A*")||cpuis("STM32F439A*")||cpuis("STM32F469A*")||cpuis("STM32F479A*")||cpuis("STM32F407I*")||cpuis("STM32F417I*")||cpuis("STM32F427I*")||cpuis("STM32F429I*")||cpuis("STM32F437I*")||cpuis("STM32F439I*")||cpuis("STM32F469I*")||cpuis("STM32F479I*")||cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32F72*")&&!cpuis("STM32F745V*")&&!cpuis("STM32F745Z*")&&!cpuis("STM32F746V*")&&!cpuis("STM32F746Z*")&&!cpuis("STM32F756V*")&&!cpuis("STM32F756Z*")&&!cpuis("STM32F765V*")&&!cpuis("STM32F765Z*")&&!cpuis("STM32F767V*")&&!cpuis("STM32F767Z*")&&!cpuis("STM32F769V*")&&!cpuis("STM32F769Z*")&&!cpuis("STM32F777V*")&&!cpuis("STM32F777Z*"))
|
|
bitfld.long 0x00 8. " GPIOILPEN ,IO port I clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 7. " GPIOHLPEN ,IO port H clock enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("STM32F429B*")||cpuis("STM32F429N*")||cpuis("STM32F439B*")||cpuis("STM32F439N*")||cpuis("STM32F469B*")||cpuis("STM32F469N*")||cpuis("STM32F479B*")||cpuis("STM32F479N*")||cpuis("STM32F7??B?")||cpuis("STM32F7??N?")||cpuis("STM32F7??I?")||cpuis("STM32F7??Z?")||cpuis("STM32F446Z*")||cpuis("STM32F405Z*")||cpuis("STM32F407Z*")||cpuis("STM32F415Z*")||cpuis("STM32F417Z*")||cpuis("STM32F427Z*")||cpuis("STM32F437Z*")||cpuis("STM32F429Z*")||cpuis("STM32F439Z*")||cpuis("STM32F469Z*")||cpuis("STM32F479Z*")||cpuis("STM32F427A*")||cpuis("STM32F429A*")||cpuis("STM32F437A*")||cpuis("STM32F439A*")||cpuis("STM32F469A*")||cpuis("STM32F479A*")||cpuis("STM32F407I*")||cpuis("STM32F417I*")||cpuis("STM32F427I*")||cpuis("STM32F429I*")||cpuis("STM32F437I*")||cpuis("STM32F439I*")||cpuis("STM32F469I*")||cpuis("STM32F479I*")||cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32F72*")&&!cpuis("STM32F745V*")&&!cpuis("STM32F746V*")&&!cpuis("STM32F756V*")&&!cpuis("STM32F765V*")&&!cpuis("STM32F767V*")&&!cpuis("STM32F769V*")&&!cpuis("STM32F777V*"))
|
|
bitfld.long 0x00 6. " GPIOGLPEN ,IO port G clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " GPIOFLPEN ,IO port F clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif (!cpuis("STM32F401C*")&&!cpuis("STM32F411C*")&&!cpuis("STM32F411R*")&&!cpuis("STM32F446R*")&&!cpuis("STM32F405R*")&&!cpuis("STM32F415R*")&&!cpuis("STM32F730R8"))
|
|
bitfld.long 0x00 4. " GPIOELPEN ,IO port E clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif (!cpuis("STM32F401C*")&&!cpuis("STM32F411C*"))
|
|
bitfld.long 0x00 3. " GPIODLPEN ,IO port D clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 2. " GPIOCLPEN ,IO port C clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " GPIOBLPEN ,IO port B clock enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " GPIOALPEN ,IO port A clock enable" "Disabled,Enabled"
|
|
line.long 0x04 "AHB2LPENR,RCC AHB2 Peripheral Clock Enable In Low Power Mode Register"
|
|
bitfld.long 0x04 7. " OTGFSLPEN ,USB OTG FS clock enable" "Disabled,Enabled"
|
|
newline
|
|
sif (!cpuis("STM32F411*")&&!cpuis("STM32F401*"))
|
|
sif (!cpuis("STM32F446*"))
|
|
bitfld.long 0x04 6. " RNGLPEN ,Random number generator clock enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("STM32F405*")||cpuis("STM32F41*")||cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F750*")||cpuis("STM32F756*")||cpuis("STM32F407*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x04 5. " HASHLPEN ,Hash modules clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " CRYPLPEN ,Cryptography modules clock enable" "Disabled,Enabled"
|
|
newline
|
|
elif (cpuis("STM32F72*")||cpuis("STM32F73*"))
|
|
bitfld.long 0x04 4. " AESLPEN ,AES module clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
endif
|
|
sif (cpuis("STM32F767*")||cpuis("STM32F768*")||cpuis("STM32F769*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x04 1. " JPEGLPEN ,JPEG module enabled" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif (!cpuis("STM32F4?5*")&&!cpuis("STM32F401*")&&!cpuis("STM32F730*"))
|
|
bitfld.long 0x04 0. " DCMILPEN ,Camera interface enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
sif (!cpuis("STM32F411*")&&!cpuis("STM32F401*"))
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "AHB3LPENR,RCC AHB3 Peripheral Clock Enable In Low Power Mode Register"
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*"))
|
|
bitfld.long 0x00 1. " QSPILPEN ,QUADSPI memory controller module clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*"))
|
|
sif !cpuis("STM32F730R*")
|
|
bitfld.long 0x00 0. " FMCLPEN ,Flexible memory controller module clock enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
bitfld.long 0x00 0. " FSMCLPEN ,Flexible static memory controller module clock enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "APB1LPENR,RCC APB1 Peripheral Clock Enable In Low Power Mode Register"
|
|
sif (cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F7*")||cpuis("STM32F407*")||cpuis("STM32F469*")||cpuis("STM32F479*"))
|
|
sif (!cpuis("STM32F73?R*")&&!cpuis("STM32F72?R*"))
|
|
bitfld.long 0x00 31. " UART8LPEN ,UART 8 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " UART7LPEN ,UART 7 clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
endif
|
|
sif (!cpuis("STM32F41*")&&!cpuis("STM32F401*"))
|
|
bitfld.long 0x00 29. " DACLPEN ,DAC interface clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 28. " PWRLPEN ,Power interface clock enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F7*"))&&(!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
bitfld.long 0x00 27. " CECLPEN ,CEC clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif (!cpuis("STM32F41*")&&!cpuis("STM32F401*"))
|
|
sif (!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
bitfld.long 0x00 26. " CAN2LPEN ,CAN 2 clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 25. " CAN1LPEN ,CAN 1 clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32F446*"))
|
|
bitfld.long 0x00 24. " FMPI2C1LPEN ,FMPI2C1 clock enable" "Disabled,Enabled"
|
|
newline
|
|
elif (cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32F750*"))
|
|
bitfld.long 0x00 24. " I2C4LPEN ,I2C4 clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 23. " I2C3LPEN ,I2C3 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " I2C2LPEN ,I2C2 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " I2C1LPEN ,I2C1 clock enable" "Disabled,Enabled"
|
|
newline
|
|
sif (!cpuis("STM32F411*")&&!cpuis("STM32F401*"))
|
|
bitfld.long 0x00 20. " UART5LPEN ,UART5 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " UART4LPEN ,UART4 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " USART3LPEN ,USART3 clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 17. " USART2LPEN ,USART 2 enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F7*"))&&(!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
bitfld.long 0x00 16. " SPDIFRXLPEN ,SPDIFRX clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15. " SPI3LPEN ,SPI 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SPI2LPEN ,SPI 2 enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 13. " CAN3LPEN ,CAN 3 clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif cpuis("STM32F411*")||cpuis("STM32F401*")
|
|
bitfld.long 0x00 11. " WWDGLPEN ,Window watchdog enable" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 11. " WWDGLPEN ,Window watchdog enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("STM32F7*")
|
|
sif !cpuis("STM32F74*")&&!cpuis("STM32F75*")
|
|
bitfld.long 0x00 10. " RTCAPBLPEN ,RTC register interface clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif !cpuis("STM32F730R*")
|
|
bitfld.long 0x00 9. " LPTIM1LPEN ,Low power timer 1 clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 8. " TIM14LPEN ,TIM14 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TIM13LPEN ,TIM13 enable" "Disabled,Enabled"
|
|
newline
|
|
sif (!cpuis("STM32F723R*")&&!cpuis("STM32F733R*")&&!cpuis("STM32F723V*")&&!cpuis("STM32F733V*")&&!cpuis("STM32F723Z*")&&!cpuis("STM32F733Z*")&&!cpuis("STM32F730R*")&&!cpuis("STM32F730V*")&&!cpuis("STM32F730Z*"))
|
|
bitfld.long 0x00 6. " TIM12LPEN ,TIM12 enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " TIM7LPEN ,TIM7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TIM6LPEN ,TIM6 enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 3. " TIM5LPEN ,TIM5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TIM4LPEN ,TIM4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIM3LPEN ,TIM3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TIM2LPEN ,TIM2 enable" "Disabled,Enabled"
|
|
line.long 0x04 "APB2LPENR,RCC APB2 Peripheral Clock Enable In Low Power Mode Register"
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x04 30. " MDIOLPEN ,MDIO clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " DFSDM1LPEN ,DFSDM1 clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F769A*")||cpuis("STM32F767I*")||cpuis("STM32F769I*")||cpuis("STM32F767B*")||cpuis("STM32F769B*")||cpuis("STM32F767N*")||cpuis("STM32F769N*")||cpuis("STM32F778A*")||cpuis("STM32F779A*")||cpuis("STM32F777I*")||cpuis("STM32F779I*")||cpuis("STM32F777B*")||cpuis("STM32F779B*")||cpuis("STM32F777N*")||cpuis("STM32F779N*"))&&(!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
bitfld.long 0x04 27. " DSILPEN ,DSI clocks enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32F429*")||cpuis("STM32F439*")||cpuis("STM32F746*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F75*")||cpuis("STM32F767*")||cpuis("STM32F768*")||cpuis("STM32F769*")||cpuis("STM32F77*"))&&(!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
bitfld.long 0x04 26. " LTDCLPEN ,LTDC enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F469*")||cpuis("STM32F479*"))
|
|
bitfld.long 0x04 22. " SAI1LPEN ,SAI 1 enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("STM32F7??Z?")||cpuis("STM32F7??I?")||cpuis("STM32F7??B?")||cpuis("STM32F7??N?"))
|
|
sif (!cpuis("STM32F745V*")&&!cpuis("STM32F746V*")&&!cpuis("STM32F756V*")&&!cpuis("STM32F765V*")&&!cpuis("STM32F767V*")&&!cpuis("STM32F769V*")&&!cpuis("STM32F777V*"))
|
|
bitfld.long 0x04 21. " SPI6LPEN ,SPI 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " SPI5LPEN ,SPI 5 enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
endif
|
|
elif (cpuis("STM32F446*"))
|
|
bitfld.long 0x04 23. " SAI2LPEN ,SAI 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " SAI1LPEN ,SAI 1 enable" "Disabled,Enabled"
|
|
newline
|
|
elif (cpuis("STM32F411*"))
|
|
bitfld.long 0x04 20. " SPI5LPEN ,SPI 5 enable" "Disabled,Enabled"
|
|
newline
|
|
elif (cpuis("STM32F7*"))
|
|
bitfld.long 0x04 23. " SAI2LPEN ,SAI 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " SAI1LPEN ,SAI 1 enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("STM32F72*")&&!cpuis("STM32F73*")&&!cpuis("STM32F750V*")
|
|
bitfld.long 0x04 21. " SPI6LPEN ,SPI 6 enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif !cpuis("STM32F72?R*")&&!cpuis("STM32F73?R*")&&!cpuis("STM32F72?V*")&&!cpuis("STM32F73?V*")&&!cpuis("STM32F750V*")
|
|
bitfld.long 0x04 20. " SPI5LPEN ,SPI 5 enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
endif
|
|
bitfld.long 0x04 18. " TIM11LPEN ,TIM11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " TIM10LPEN ,TIM10 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " TIM9LPEN ,TIM9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " SYSCFGLPEN ,System configuration controller enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F411*")||cpuis("STM32F401V*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*"))
|
|
sif (!cpuis("STM32F72?R*")&&!cpuis("STM32F73?R*"))
|
|
bitfld.long 0x04 13. " SPI4LPEN ,SPI 4 enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
endif
|
|
bitfld.long 0x04 12. " SPI1LPEN ,SPI 1 enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F750*")||cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x04 11. " SDMMC1LPEN ,SPI1 clock enable" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x04 11. " SDIOLPEN ,SDIO enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif (!cpuis("STM32F411*")&&!cpuis("STM32F401*"))
|
|
bitfld.long 0x04 10. " ADC3LPEN ,ADC enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " ADC2LPEN ,ADC enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 8. " ADC1LPEN ,ADC enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
sif (!cpuis("STM32F72?R*")&&!cpuis("STM32F723V*")&&!cpuis("STM32F730R*")&&!cpuis("STM32F730V*")&&!cpuis("STM32F733V*"))
|
|
bitfld.long 0x04 7. " SDMMC2LPEN ,SDMMC2 clock enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
endif
|
|
bitfld.long 0x04 5. " USART6LPEN ,USART6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " USART1LPEN ,USART1 enable" "Disabled,Enabled"
|
|
newline
|
|
sif (!cpuis("STM32F401*")&&!cpuis("STM32F411*"))
|
|
bitfld.long 0x04 1. " TIM8LPEN ,TIM8 enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 0. " TIM1LPEN ,TIM1 enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40023800+0x70))&0x01)==0x00)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "BDCR,RCC Backup Domain Control Register"
|
|
bitfld.long 0x00 16. " BDRST ,Backup domain software reset" "No reset,Reset"
|
|
bitfld.long 0x00 15. " RTCEN ,RTC clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " RTCSEL ,RTC clock source selection" "No clock,LSE,LSI,HSE"
|
|
newline
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F411*")||cpuis("STM32F469*")||cpuis("STM32F479*"))
|
|
bitfld.long 0x00 3. " LSEMOD ,External low-speed oscillator bypass mode" "Low power,High drive"
|
|
newline
|
|
elif (cpuis("STM32F7*"))
|
|
bitfld.long 0x00 3.--4. " LSEDRV ,LSE oscillator drive capability" "Low,Medium high,Medium low,High"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 2. " LSEBYP ,External low-speed oscillator bypass" "Not bypassed,Bypassed"
|
|
rbitfld.long 0x00 1. " LSERDY ,External low-speed oscillator ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " LSEON ,External low-speed oscillator enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "BDCR,RCC Backup Domain Control Register"
|
|
bitfld.long 0x00 16. " BDRST ,Backup domain software reset" "No reset,Reset"
|
|
bitfld.long 0x00 15. " RTCEN ,RTC clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " RTCSEL ,RTC clock source selection" "No clock,LSE,LSI,HSE"
|
|
newline
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F411*")||cpuis("STM32F469*")||cpuis("STM32F479*"))
|
|
bitfld.long 0x00 3. " LSEMOD ,External low-speed oscillator bypass mode" "Low power,High drive"
|
|
newline
|
|
elif (cpuis("STM32F7*"))
|
|
bitfld.long 0x00 3.--4. " LSEDRV ,LSE oscillator drive capability" "Low,Medium high,Medium low,High"
|
|
newline
|
|
endif
|
|
rbitfld.long 0x00 2. " LSEBYP ,External low-speed oscillator bypass" "Not bypassed,Bypassed"
|
|
rbitfld.long 0x00 1. " LSERDY ,External low-speed oscillator ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " LSEON ,External low-speed oscillator enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "CSR,RCC Clock Control And Status Register"
|
|
rbitfld.long 0x00 31. " LPWRRSTF ,Low-power reset flag" "No reset,Reset"
|
|
rbitfld.long 0x00 30. " WWDGRSTF ,Window watchdog reset flag" "No reset,Reset"
|
|
rbitfld.long 0x00 29. " IWDGRSTF ,Independent watchdog reset flag" "No reset,Reset"
|
|
newline
|
|
rbitfld.long 0x00 28. " SFTRSTF ,Software reset flag" "No reset,Reset"
|
|
rbitfld.long 0x00 27. " PORRSTF ,POR/PDR reset flag" "No reset,Reset"
|
|
rbitfld.long 0x00 26. " PINRSTF ,PIN reset flag" "No reset,Reset"
|
|
newline
|
|
rbitfld.long 0x00 25. " BORRSTF ,POR/PDR or BOR reset flag" "No reset,Reset"
|
|
bitfld.long 0x00 24. " RMVF ,Remove reset flag" "Not removed,Removed"
|
|
rbitfld.long 0x00 1. " LSIRDY ,Internal low-speed oscillator ready" "Not ready,Ready"
|
|
newline
|
|
bitfld.long 0x00 0. " LSION ,Internal low-speed oscillator enable" "Disabled,Enabled"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SSCGR,RCC Spread Spectrum Clock Generation Register"
|
|
bitfld.long 0x00 31. " SSCGEN ,Spread spectrum modulation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SPREADSEL ,Spread select" "Center spread,Down spread"
|
|
hexmask.long.word 0x00 13.--27. 1. " INCSTEP ,Incrementation step"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. " MODPER ,Modulation period"
|
|
sif cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F74*")||cpuis("STM32F75*")||cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
if (((per.l(ad:0x40023800))&0x4000000)==0x00)
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "PLLI2SCFGR,RCC PLLI2S Configuration Register"
|
|
bitfld.long 0x00 28.--30. " PLLI2SR ,PLLI2S division factor for I2S clocks" ",,/2,/3,/4,/5,/6,/7"
|
|
bitfld.long 0x00 24.--27. " PLLI2SQ ,PLLI2S division factor for SAI1 clock" ",,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15"
|
|
sif (!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
bitfld.long 0x00 16.--17. " PLLI2SP ,PLLI2S division factor for SPDIFRX clock" "/2,/4,/6,/8"
|
|
endif
|
|
newline
|
|
hexmask.long.word 0x00 6.--14. 1. " PLLI2SN ,PLLI2S multiplication factor for VCO"
|
|
else
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "PLLI2SCFGR,RCC PLLI2S Configuration Register"
|
|
bitfld.long 0x00 28.--30. " PLLI2SR ,PLLI2S division factor for I2S clocks" ",,/2,/3,/4,/5,/6,/7"
|
|
bitfld.long 0x00 24.--27. " PLLI2SQ ,PLLI2S division factor for SAI1 clock" ",,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15"
|
|
sif (!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
bitfld.long 0x00 16.--17. " PLLI2SP ,PLLI2S division factor for SPDIFRX clock" "/2,/4,/6,/8"
|
|
endif
|
|
newline
|
|
hexmask.long.word 0x00 6.--14. 1. " PLLI2SN ,PLLI2S multiplication factor for VCO"
|
|
endif
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "PLLI2SCFGR,RCC PLLI2S Configuration Register"
|
|
bitfld.long 0x00 28.--30. " PLLI2SR ,PLLI2S division factor for I2S clocks" ",,/2,/3,/4,/5,/6,/7"
|
|
newline
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*"))
|
|
bitfld.long 0x00 24.--27. " PLLI2SQ ,PLLI2S division factor for SAI1 clock" ",,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32F446*"))
|
|
bitfld.long 0x00 16.--17. " PLLI2SP ,PLLI2S division factor for SPDIFRX clock" "/2,/4,/6,/8"
|
|
newline
|
|
endif
|
|
hexmask.long.word 0x00 6.--14. 1. " PLLI2SN ,PLLI2S multiplication factor for VCO"
|
|
newline
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F411*"))
|
|
bitfld.long 0x00 0.--5. " PLLI2SM ,Division factor for PLL and PLLI2S input clock" "/0,/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63"
|
|
endif
|
|
endif
|
|
sif cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F750*")||cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
if (((per.l(ad:0x40023800))&0x10000000)==0x00)
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "PLLSAICFGR,RCC PLLSAI Configuration Register"
|
|
sif (!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
bitfld.long 0x00 28.--30. " PLLSAIR ,PLLSAI division factor for LCD clock" ",,/2,/3,/4,/5,/6,/7"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 24.--27. " PLLSAIQ ,PLLSAI division factor for SAI1 clock" ",,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15"
|
|
bitfld.long 0x00 16.--17. " PLLSAIP ,PLLSAI division factor for 48 MHz clock" "/2,/4,/6,/8"
|
|
hexmask.long.word 0x00 6.--14. 1. " PLLSAIN ,PLLSAI division factor for VCO"
|
|
else
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "PLLSAICFGR,RCC PLLSAI Configuration Register"
|
|
sif (!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
bitfld.long 0x00 28.--30. " PLLSAIR ,PLLSAI division factor for LCD clock" ",,/2,/3,/4,/5,/6,/7"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 24.--27. " PLLSAIQ ,PLLSAI division factor for SAI1 clock" ",,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15"
|
|
bitfld.long 0x00 16.--17. " PLLSAIP ,PLLSAI division factor for 48 MHz clock" "/2,/4,/6,/8"
|
|
hexmask.long.word 0x00 6.--14. 1. " PLLSAIN ,PLLSAI division factor for VCO"
|
|
endif
|
|
else
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "PLLSAICFGR,RCC PLLSAI Configuration Register"
|
|
sif (cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F469*")||cpuis("STM32F479*"))
|
|
bitfld.long 0x00 28.--30. " PLLSAIR ,PLLSAI division factor for LCD clock" ",,/2,/3,/4,/5,/6,/7"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 24.--27. " PLLSAIQ ,PLLSAI division factor for SAI1 clock" ",,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15"
|
|
newline
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*"))
|
|
bitfld.long 0x00 16.--17. " PLLSAIP ,PLLSAI division factor for 48 MHz clock" "/2,/4,/6,/8"
|
|
newline
|
|
endif
|
|
hexmask.long.word 0x00 6.--14. 1. " PLLSAIN ,PLLSAI division factor for VCO"
|
|
sif (cpuis("STM32F446*"))
|
|
bitfld.long 0x00 0.--5. " PLLSAIM ,Division factor for audio PLLSAI input clock" ",,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63"
|
|
endif
|
|
endif
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F469*")||cpuis("STM32F479*"))
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "DCKCFGR,RCC Dedicated Clocks Configuration Register"
|
|
sif (cpuis("STM32F469*")||cpuis("SMT32F479*"))
|
|
bitfld.long 0x00 29. " DSISEL ,DSI clock source selection" "DSI-PHY,PLLR"
|
|
bitfld.long 0x00 28. " SDIOSEL ,SDIO clock source selection" "48 MHz clock,System clock"
|
|
bitfld.long 0x00 27. " 48MSEL ,48 MHz clock source selection" "PLL,PLLSAI"
|
|
newline
|
|
elif (cpuis("STM32F446*"))
|
|
bitfld.long 0x00 27.--28. " I2S2SRC ,I2S APB2 clock source selection" "PLLI2S_R,I2S_CKIN,PLL_R,HSI/HSE"
|
|
bitfld.long 0x00 25.--26. " I2S1SRC ,I2S APB1 clock source selection" "PLLI2S_R,I2S_CKIN,PLL_R,HSI/HSE"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 24. " TIMPRE ,Timers clocks prescalers selection" "PCLK/2xPCLK,HCLK/4xPCLK"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " SAI1BSRC ,SAI1-B clock source selection" "f(PLLSAI_Q) / PLLSAIDIVQ,f(PLLI2S_Q) / PLLI2SDIVQ,Alternate function pin,?..."
|
|
bitfld.long 0x00 20.--21. " SAI1ASRC ,SAI1-A clock source selection" "f(PLLSAI_Q) / PLLSAIDIVQ,f(PLLI2S_Q) / PLLI2SDIVQ,Alternate function pin,?..."
|
|
newline
|
|
sif (cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F469*")||cpuis("STM32F479*"))
|
|
bitfld.long 0x00 16.--17. " PLLSAIDIVR ,Division factor for LCD_CLK" "/2,/4,/8,/16"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 8.--12. " PLLSAIDIVQ ,PLLSAI division factor for SAI1 clock" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,?..."
|
|
bitfld.long 0x00 0.--4. " PLLI2SDIVQ ,PLLI2S division factor for SAI1 clock" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,?..."
|
|
elif (cpuis("STM32F7*"))
|
|
if (((per.l(ad:0x40023800))&0x14000000)==0x00)
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "DCKFGR1,RCC Dedicated Clocks Configuration Register"
|
|
sif cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
bitfld.long 0x00 26. " ADFSDM1SEL ,DFSDM1 AUDIO clock source selection" "SAI1,SAI2"
|
|
bitfld.long 0x00 25. " DFSDM1SEL ,DFSDM1 clock source selection" "APB2,System clock"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 24. " TIMPRE ,Timers clocks prescalers selection" "2x,4x"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " SAI2SEL ,SAI2 clock source selection" "f(PLLSAI_Q)/PLLSAIDIVQ,f(PLLI2S_Q)/PLLI2SDIVQ,Alternate function,HSI or HSE"
|
|
bitfld.long 0x00 20.--21. " SAI1SEL ,SAI1 clock source selection" "f(PLLSAI_Q)/PLLSAIDIVQ,f(PLLI2S_Q)/PLLI2SDIVQ,Alternate function,HSI or HSE"
|
|
newline
|
|
sif cpuis("STM32F750*")||cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
bitfld.long 0x00 16.--17. " PLLSAIDIVR ,Division factor for LCD_CLK" "/2,/4,/8,/16"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 8.--12. " PLLSAIDIVQ ,PLLSAI division factor for SAI1 clock" "/0,/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31"
|
|
bitfld.long 0x00 0.--4. " PLLI2SDIV ,PLLSAI division factor for SAI2 clock" "/0,/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31"
|
|
elif (((per.l(ad:0x40023800))&0x14000000)==0x10000000)
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "DCKFGR1,RCC Dedicated Clocks Configuration Register"
|
|
sif cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
bitfld.long 0x00 26. " ADFSDM1SEL ,DFSDM1 AUDIO clock source selection" "SAI1,SAI2"
|
|
bitfld.long 0x00 25. " DFSDM1SEL ,DFSDM1 clock source selection" "APB2,System clock"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 24. " TIMPRE ,Timers clocks prescalers selection" "2x,4x"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. " SAI2SEL ,SAI2 clock source selection" "f(PLLSAI_Q)/PLLSAIDIVQ,f(PLLI2S_Q)/PLLI2SDIVQ,Alternate function,HSI or HSE"
|
|
rbitfld.long 0x00 20.--21. " SAI1SEL ,SAI1 clock source selection" "f(PLLSAI_Q)/PLLSAIDIVQ,f(PLLI2S_Q)/PLLI2SDIVQ,Alternate function,HSI or HSE"
|
|
newline
|
|
sif cpuis("STM32F750*")||cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
rbitfld.long 0x00 16.--17. " PLLSAIDIVR ,Division factor for LCD_CLK" "/2,/4,/8,/16"
|
|
newline
|
|
endif
|
|
rbitfld.long 0x00 8.--12. " PLLSAIDIVQ ,PLLSAI division factor for SAI1 clock" "/0,/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31"
|
|
bitfld.long 0x00 0.--4. " PLLI2SDIV ,PLLSAI division factor for SAI2 clock" "/0,/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31"
|
|
elif (((per.l(ad:0x40023800))&0x14000000)==0x04000000)
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "DCKFGR1,RCC Dedicated Clocks Configuration Register"
|
|
sif cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
bitfld.long 0x00 26. " ADFSDM1SEL ,DFSDM1 AUDIO clock source selection" "SAI1,SAI2"
|
|
bitfld.long 0x00 25. " DFSDM1SEL ,DFSDM1 clock source selection" "APB2,System clock"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 24. " TIMPRE ,Timers clocks prescalers selection" "2x,4x"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. " SAI2SEL ,SAI2 clock source selection" "f(PLLSAI_Q)/PLLSAIDIVQ,f(PLLI2S_Q)/PLLI2SDIVQ,Alternate function,HSI or HSE"
|
|
rbitfld.long 0x00 20.--21. " SAI1SEL ,SAI1 clock source selection" "f(PLLSAI_Q)/PLLSAIDIVQ,f(PLLI2S_Q)/PLLI2SDIVQ,Alternate function,HSI or HSE"
|
|
sif cpuis("STM32F750*")||cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
bitfld.long 0x00 16.--17. " PLLSAIDIVR ,Division factor for LCD_CLK" "/2,/4,/8,/16"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 8.--12. " PLLSAIDIVQ ,PLLSAI division factor for SAI1 clock" "/0,/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31"
|
|
rbitfld.long 0x00 0.--4. " PLLI2SDIV ,PLLSAI division factor for SAI2 clock" "/0,/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31"
|
|
else
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "DCKFGR1,RCC Dedicated Clocks Configuration Register"
|
|
sif cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
bitfld.long 0x00 26. " ADFSDM1SEL ,DFSDM1 AUDIO clock source selection" "SAI1,SAI2"
|
|
bitfld.long 0x00 25. " DFSDM1SEL ,DFSDM1 clock source selection" "APB2,System clock"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 24. " TIMPRE ,Timers clocks prescalers selection" "2x,4x"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. " SAI2SEL ,SAI2 clock source selection" "f(PLLSAI_Q)/PLLSAIDIVQ,f(PLLI2S_Q)/PLLI2SDIVQ,Alternate function,HSI or HSE"
|
|
rbitfld.long 0x00 20.--21. " SAI1SEL ,SAI1 clock source selection" "f(PLLSAI_Q)/PLLSAIDIVQ,f(PLLI2S_Q)/PLLI2SDIVQ,Alternate function,HSI or HSE"
|
|
sif cpuis("STM32F750*")||cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
rbitfld.long 0x00 16.--17. " PLLSAIDIVR ,Division factor for LCD_CLK" "/2,/4,/8,/16"
|
|
newline
|
|
endif
|
|
rbitfld.long 0x00 8.--12. " PLLSAIDIVQ ,PLLSAI division factor for SAI1 clock" "/0,/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31"
|
|
rbitfld.long 0x00 0.--4. " PLLI2SDIV ,PLLSAI division factor for SAI2 clock" "/0,/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31"
|
|
endif
|
|
elif (cpuis("STM32F411*")||cpuis("STM32F401*"))
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "DCKCFGR,RCC Dedicated Clocks Configuration Register"
|
|
bitfld.long 0x00 24. " TIMPRE ,Timers clocks prescalers selection" "HCLK/2xPCLKx,HCLK/4xPCLKx"
|
|
endif
|
|
sif cpuis("STM32F446*")
|
|
group.long 0x90++0x07
|
|
line.long 0x00 "CKGATENR,RCC Clocks Gated Enable Register"
|
|
bitfld.long 0x00 6. " CKEN ,RCC clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " FLITF_CKEN ,Flash interface clock enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " SRAM_CKEN ,SRQAM controller clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SPARE_CKEN ,Spare clock enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CM4DBG_CKEN ,Cortex M4 ETM clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AHB2APB2_CKEN ,AHB to APB2 bridge clock enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " AHB2APB1_CKEN ,AHB to APB1 bridge clock enable" "Disabled,Enabled"
|
|
line.long 0x04 "DCKCFGR2,RCC Dedicated Clocks Configuration Register 2"
|
|
bitfld.long 0x04 29. " SPDIFRXSEL ,SPDIF-Rx clock selection" "PLL_R,PLLI2S_P"
|
|
bitfld.long 0x04 28. " SDIOSEL ,SDIO clock selection" "48 MHz,System"
|
|
newline
|
|
bitfld.long 0x04 27. " CK48MSEL ,SDIO/USBFS/HS clock selection" "PLL_Q,PLLSAI_P"
|
|
bitfld.long 0x04 26. " CECSEL ,HDMI CEC clock source selection" "HSI/488,LSE"
|
|
newline
|
|
bitfld.long 0x04 22.--23. " FMPI2C1SEL ,I2C4 kernel clock source selection" "APB,System clock,HSI,APB"
|
|
elif (cpuis("STM32F7*"))
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DCKCFGR2,RCC Dedicated Clocks Configuration Register 2"
|
|
sif cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
bitfld.long 0x00 30. " DSISEL ,DSI clock source selection" "DSI-PHY,PLLR"
|
|
bitfld.long 0x00 29. " SDMMC2SEL ,SDMMC2 clock source selection" "48 MHz,System clock"
|
|
newline
|
|
elif cpuis("STM32F72*")||cpuis("STM32F73*")
|
|
sif (!cpuis("STM32F72?R*")&&!cpuis("STM32F73?R*")&&!cpuis("STM32F723V*")&&!cpuis("STM32F733V*"))
|
|
bitfld.long 0x00 29. " SDMMC2SEL ,SDMMC2 clock source selection" "48 MHz,System clock"
|
|
newline
|
|
endif
|
|
endif
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F750*")||cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 28. " SDMMC1SEL ,SDMMC1 clock source selection" "48 MHz,System clock"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 28. " SDMMCSEL ,SDMMC clock source selection" "48 MHz,System clock"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 27. " CK48MSEL ,SDIO/USBFS/HS clock selection" "PLL,PLLSAI"
|
|
newline
|
|
sif (!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
bitfld.long 0x00 26. " CECSEL ,HDMI CEC clock source selection" "LSE,HSI/488"
|
|
newline
|
|
endif
|
|
sif (!cpuis("STM32F72?R*")&&!cpuis("STM32F73?R*"))
|
|
bitfld.long 0x00 24.--25. " LPTIM1SEL ,Low power timer 1 clock source selection" "APB1,LSI,HSI,LSE"
|
|
newline
|
|
endif
|
|
sif (!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
bitfld.long 0x00 22.--23. " I2C4SEL ,I2C4 clock source selection" "APB1,System clock,HSI,?..."
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 20.--21. " I2C3SEL ,I2C3 clock source selection" "APB,System clock,HSI,?..."
|
|
bitfld.long 0x00 18.--19. " I2C2SEL ,I2C2 clock source selection" "APB1,System clock,HSI,?..."
|
|
bitfld.long 0x00 16.--17. " I2C1SEL ,I2C1 clock source selection" "APB,System clock,HSI,?..."
|
|
newline
|
|
sif (!cpuis("STM32F72?R*")&&!cpuis("STM32F73?R*"))
|
|
bitfld.long 0x00 14.--15. " UART8SEL ,UART 8 clock source selection" "APB1,System clock,HSI,LSE"
|
|
bitfld.long 0x00 12.--13. " UART7SEL ,UART 7 clock source selection" "APB1,System clock,HSI,LSE"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 10.--11. " USART6SEL ,USART 6 clock source selection" "APB2,System clock,HSI,LSE"
|
|
bitfld.long 0x00 8.--9. " UART5SEL ,UART 5 clock source selection" "APB1,System clock,HSI,LSE"
|
|
bitfld.long 0x00 6.--7. " UART4SEL ,UART 4 clock source selection" "APB1,System clock,HSI,LSE"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " USART3SEL ,USART 3 clock source selection" "APB1,System clock,HSI,LSE"
|
|
bitfld.long 0x00 2.--3. " USART2SEL ,USART 2 clock source selection" "APB1,System clock,HSI,LSE"
|
|
bitfld.long 0x00 0.--1. " USART1SEL ,USART 1 clock source selection" "APB2,System clock,HSI,LSE"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "GPIO (General Purpose I/O's)"
|
|
tree "GPIO A"
|
|
base ad:0x40020000
|
|
width 13.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "MODER,GPIO Port A Mode Register"
|
|
bitfld.long 0x00 30.--31. " MODER[15] ,Port A pin 15 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " [14] ,Port A pin 14 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " [13] ,Port A pin 13 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 24.--25. " [12] ,Port A pin 12 mode" "Input,Output,Alternate function,Analog"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " [11] ,Port A pin 11 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " [10] ,Port A pin 10 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " [9] ,Port A pin 9 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " [8] ,Port A pin 8 mode" "Input,Output,Alternate function,Analog"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " [7] ,Port A pin 7 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " [6] ,Port A pin 6 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " [5] ,Port A pin 5 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " [4] ,Port A pin 4 mode" "Input,Output,Alternate function,Analog"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " [3] ,Port A pin 3 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " [2] ,Port A pin 2 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " [1] ,Port A pin 1 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " [0] ,Port A pin 0 mode" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "OTYPER,GPIO Port A Output Type Register"
|
|
bitfld.long 0x04 15. " OT[15] ,Port A pin 15 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " [14] ,Port A pin 14 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " [13] ,Port A pin 13 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 12. " [12] ,Port A pin 12 output type" "Push-pull,Open-drain"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Port A pin 11 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " [10] ,Port A pin 10 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 9. " [9] ,Port A pin 9 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " [8] ,Port A pin 8 output type" "Push-pull,Open-drain"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Port A pin 7 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " [6] ,Port A pin 6 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " [5] ,Port A pin 5 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " [4] ,Port A pin 4 output type" "Push-pull,Open-drain"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,Port A pin 3 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " [2] ,Port A pin 2 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " [1] ,Port A pin 1 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " [0] ,Port A pin 0 output type" "Push-pull,Open-drain"
|
|
line.long 0x08 "OSPEEDR,GPIO Port A Output Speed Register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR[15] ,Port A pin 15 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 28.--29. " [14] ,Port A pin 14 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 26.--27. " [13] ,Port A pin 13 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 24.--25. " [12] ,Port A pin 12 output speed" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x08 22.--23. " [11] ,Port A pin 11 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 20.--21. " [10] ,Port A pin 10 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 18.--19. " [9] ,Port A pin 9 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 16.--17. " [8] ,Port A pin 8 output speed" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x08 14.--15. " [7] ,Port A pin 7 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 12.--13. " [6] ,Port A pin 6 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 10.--11. " [5] ,Port A pin 5 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 8.--9. " [4] ,Port A pin 4 output speed" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x08 6.--7. " [3] ,Port A pin 3 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 4.--5. " [2] ,Port A pin 2 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 2.--3. " [1] ,Port A pin 1 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 0.--1. " [0] ,Port A pin 0 output speed" "Low,Medium,High,Very high"
|
|
line.long 0x0C "PUPDR,GPIO Port A Pull-up/Pull-down Register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR[15] ,Port A pin 15 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " [14] ,Port A pin 14 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " [13] ,Port A pin 13 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 24.--25. " [12] ,Port A pin 12 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
newline
|
|
bitfld.long 0x0C 22.--23. " [11] ,Port A pin 11 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " [10] ,Port A pin 10 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 18.--19. " [9] ,Port A pin 9 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " [8] ,Port A pin 8 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
newline
|
|
bitfld.long 0x0C 14.--15. " [7] ,Port A pin 7 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 12.--13. " [6] ,Port A pin 6 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " [5] ,Port A pin 5 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " [4] ,Port A pin 4 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
newline
|
|
bitfld.long 0x0C 6.--7. " [3] ,Port A pin 3 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " [2] ,Port A pin 2 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " [1] ,Port A pin 1 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " [0] ,Port A pin 0 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "IDR,GPIO Port A Input Data Register"
|
|
bitfld.long 0x00 15. " IDR[15] ,Port A pin 15 input data" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Port A pin 14 input data" "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Port A pin 13 input data" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Port A pin 12 input data" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Port A pin 11 input data" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Port A pin 10 input data" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,Port A pin 9 input data" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Port A pin 8 input data" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Port A pin 7 input data" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Port A pin 6 input data" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Port A pin 5 input data" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Port A pin 4 input data" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Port A pin 3 input data" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Port A pin 2 input data" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Port A pin 1 input data" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Port A pin 0 input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ODR_SET/CLR,GPIO Port A Output Data Set/Clear Register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR[15] ,Port A pin 15 output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " [14] ,Port A pin 14 output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " [13] ,Port A pin 13 output data" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " [12] ,Port A pin 12 output data" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " [11] ,Port A pin 11 output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " [10] ,Port A pin 10 output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " [9] ,Port A pin 9 output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " [8] ,Port A pin 8 output data" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " [7] ,Port A pin 7 output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " [6] ,Port A pin 6 output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " [5] ,Port A pin 5 output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " [4] ,Port A pin 4 output data" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " [3] ,Port A pin 3 output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " [2] ,Port A pin 2 output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " [1] ,Port A pin 1 output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " [0] ,Port A pin 0 output data" "Low,High"
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F750*")||cpuis("STM32F767BI"))
|
|
if ((per.l(ad:0x40020000+0x1C)&0x10000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO Port A Configuration Lock Register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
newline
|
|
bitfld.long 0x00 15. " LCK[15] ,Port A pin 15 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " [14] ,Port A pin 14 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " [13] ,Port A pin 13 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " [12] ,Port A pin 12 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Port A pin 11 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " [10] ,Port A pin 10 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " [9] ,Port A pin 9 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " [8] ,Port A pin 8 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Port A pin 7 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " [6] ,Port A pin 6 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " [5] ,Port A pin 5 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " [4] ,Port A pin 4 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Port A pin 3 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " [2] ,Port A pin 2 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " [1] ,Port A pin 1 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " [0] ,Port A pin 0 configuration lock" "Not locked,Locked"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO Port A Configuration Lock Register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
newline
|
|
rbitfld.long 0x00 15. " LCK[15] ,Port A pin 15 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 14. " [14] ,Port A pin 14 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 13. " [13] ,Port A pin 13 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 12. " [12] ,Port A pin 12 configuration lock" "Not locked,Locked"
|
|
newline
|
|
rbitfld.long 0x00 11. " [11] ,Port A pin 11 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 10. " [10] ,Port A pin 10 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 9. " [9] ,Port A pin 9 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 8. " [8] ,Port A pin 8 configuration lock" "Not locked,Locked"
|
|
newline
|
|
rbitfld.long 0x00 7. " [7] ,Port A pin 7 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 6. " [6] ,Port A pin 6 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 5. " [5] ,Port A pin 5 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 4. " [4] ,Port A pin 4 configuration lock" "Not locked,Locked"
|
|
newline
|
|
rbitfld.long 0x00 3. " [3] ,Port A pin 3 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 2. " [2] ,Port A pin 2 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 1. " [1] ,Port A pin 1 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 0. " [0] ,Port A pin 0 configuration lock" "Not locked,Locked"
|
|
endif
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO Port A Configuration Lock Register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
newline
|
|
bitfld.long 0x00 15. " LCK[15] ,Port A pin 15 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " [14] ,Port A pin 14 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " [13] ,Port A pin 13 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " [12] ,Port A pin 12 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Port A pin 11 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " [10] ,Port A pin 10 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " [9] ,Port A pin 9 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " [8] ,Port A pin 8 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Port A pin 7 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " [6] ,Port A pin 6 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " [5] ,Port A pin 5 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " [4] ,Port A pin 4 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Port A pin 3 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " [2] ,Port A pin 2 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " [1] ,Port A pin 1 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " [0] ,Port A pin 0 configuration lock" "Not locked,Locked"
|
|
endif
|
|
newline
|
|
sif (cpuis("STM32F722*")||cpuis("STM32F723*")||cpuis("STM32F732*")||cpuis("STM32F733*"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port A Alternate Function Low Register"
|
|
sif (cpuis("STM32F722R*")||cpuis("STM32F723R*")||cpuis("STM32F730R*")||cpuis("STM32F732R*")||cpuis("STM32F733R*"))
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port A pin 7" ",TIM1_CH1N,TIM3_CH2,TIM8_CH1N,,SPI1_MOSI/I2S1_SD,,,,TIM14_CH1,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port A pin 6" ",TIM1_BKIN,TIM3_CH1,TIM8_BKIN,,SPI1_MISO,,,,TIM13_CH1,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port A pin 5" ",TIM2_CH1/TIM2_ETR,,TIM8_CH1N,,SPI1_SCK/I2S1_CK,,,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port A pin 4" ",,,,,SPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,USART2_CK,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port A pin 3" ",TIM2_CH4,TIM5_CH4,TIM9_CH2,,,,USART2_RX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port A pin 2" ",TIM2_CH3,TIM5_CH3,TIM9_CH1,,,,USART2_TX,SAI2_SCK_B,,,,,,,EVENTOUT"
|
|
else
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port A pin 7" ",TIM1_CH1N,TIM3_CH2,TIM8_CH1N,,SPI1_MOSI/I2S1_SD,,,,TIM14_CH1,,,FMC_SDNWE,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port A pin 6" ",TIM1_BKIN,TIM3_CH1,TIM8_BKIN,,SPI1_MISO,,,,TIM13_CH1,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port A pin 5" ",TIM2_CH1/TIM2_ETR,,TIM8_CH1N,,SPI1_SCK/I2S1_CK,,,,,OTG_HS_ULPI_CK,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port A pin 4" ",,,,,SPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,USART2_CK,,,,,OTG_HS_SOF,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port A pin 3" ",TIM2_CH4,TIM5_CH4,TIM9_CH2,,,,USART2_RX,,,OTG_HS_ULPI_D0,,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port A pin 2" ",TIM2_CH3,TIM5_CH3,TIM9_CH1,,,,USART2_TX,SAI2_SCK_B,,,,,,,EVENTOUT"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port A pin 1" ",TIM2_CH2,TIM5_CH2,,,,,USART2_RTS,UART4_RX,QUADSPI_BK1_IO3,SAI2_MCK_B,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port A pin 0" ",TIM2_CH1/TIM2_ETR,TIM5_CH1,TIM8_ETR,,,,USART2_CTS,UART4_TX,,SAI2_SD_B,,,,,EVENTOUT"
|
|
newline
|
|
line.long 0x04 "AFRH,GPIO Port A Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port A pin 15" "JTDI,TIM2_CH1/TIM2_ETR,,,,SPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,,UART4_RTS,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port A pin 14" "JTCK-SWCLK,,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port A pin 13" "JTMS-SWDIO,,,,,,,,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port A pin 12" ",TIM1_ETR,,,,,,USART1_RTS,SAI2_FS_B,CAN1_TX,OTG_FS_DP,,,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port A pin 11" ",TIM1_CH4,,,,,,USART1_CTS,,CAN1_RX,OTG_FS_DM,,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port A pin 10" ",TIM1_CH3,,,,,,USART1_RX,,,OTG_FS_ID,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port A pin 9" ",TIM1_CH2,,,I2C3_SMBA,SPI2_SCK/I2S2_CK,,USART1_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port A pin 8" "MCO1,TIM1_CH1,,TIM8_BKIN2,I2C3_SCL,,,USART1_CK,,,OTG_FS_SOF,,,,,EVENTOUT"
|
|
newline
|
|
elif cpuis("STM32F730*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port A Alternate Function Low Register"
|
|
sif cpuis("STM32F730R*")||cpuis("STM32F730V*")
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port A pin 7" ",TIM1_CH1N,TIM3_CH2,TIM8_CH1N,,SPI1_MOSI/I2S1_SD,,,,TIM14_CH1,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port A pin 6" ",TIM1_BKIN,TIM3_CH1,TIM8_BKIN,,SPI1_MISO,,,,TIM13_CH1,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port A pin 5" ",TIM2_CH1/TIM2_ETR,,TIM8_CH1N,,SPI1_SCK/I2S1_CK,,,,,OTG_HS_ULPI_CK,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port A pin 4" ",,,,,SPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,USART2_CK,,,,,OTG_HS_SOF,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port A pin 3" ",TIM2_CH4,TIM5_CH4,TIM9_CH2,,,,USART2_RX,,,OTG_HS_ULPI_D0,,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port A pin 2" ",TIM2_CH3,TIM5_CH3,TIM9_CH1,,,,USART2_TX,SAI2_SCK_B,,,,,,,EVENTOUT"
|
|
else
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port A pin 7" ",TIM1_CH1N,TIM3_CH2,TIM8_CH1N,,SPI1_MOSI/I2S1_SD,,,,TIM14_CH1,,,FMC_SDNWE,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port A pin 6" ",TIM1_BKIN,TIM3_CH1,TIM8_BKIN,,SPI1_MISO,,,,TIM13_CH1,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port A pin 5" ",TIM2_CH1/TIM2_ETR,,TIM8_CH1N,,SPI1_SCK/I2S1_CK,,,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port A pin 4" ",,,,,SPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,USART2_CK,,,,,OTG_HS_SOF,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port A pin 3" ",TIM2_CH4,TIM5_CH4,TIM9_CH2,,,,USART2_RX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port A pin 2" ",TIM2_CH3,TIM5_CH3,TIM9_CH1,,,,USART2_TX,SAI2_SCK_B,,,,,,,EVENTOUT"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port A pin 1" ",TIM2_CH2,TIM5_CH2,,,,,USART2_RTS,UART4_RX,QUADSPI_BK1_IO3,SAI2_MCK_B,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port A pin 0" ",TIM2_CH1/TIM2_ETR,TIM5_CH1,TIM8_ETR,,,,USART2_CTS,UART4_TX,,SAI2_SD_B,,,,,EVENTOUT"
|
|
newline
|
|
line.long 0x04 "AFRH,GPIO Port A Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port A pin 15" "JTDI,TIM2_CH1/TIM2_ETR,,,,SPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,,UART4_RTS,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port A pin 14" "JTCK-SWCLK,,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port A pin 13" "JTMS-SWDIO,,,,,,,,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port A pin 12" ",TIM1_ETR,,,,,,USART1_RTS,SAI2_FS_B,CAN1_TX,OTG_FS_DP,,,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port A pin 11" ",TIM1_CH4,,,,,,USART1_CTS,,CAN1_RX,OTG_FS_DM,,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port A pin 10" ",TIM1_CH3,,,,,,USART1_RX,,,OTG_FS_ID,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port A pin 9" ",TIM1_CH2,,,I2C3_SMBA,SPI2_SCK/I2S2_CK,,USART1_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port A pin 8" "MCO1,TIM1_CH1,,TIM8_BKIN2,I2C3_SCL,,,USART1_CK,,,OTG_FS_SOF,,,,,EVENTOUT"
|
|
newline
|
|
elif cpuis("STM32F745V*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port A Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port A pin 7" ",TIM1_CH1N,TIM3_CH2,TIM8_CH1N,,SPI1_MOSI/I2S1_SD,,,,TIM14_CH1,,ETH_MII_RX_DV/ETH_RMII_CRS_DV,FMC_SDNWE,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port A pin 6" ",TIM1_BKIN,TIM3_CH1,TIM8_BKIN,,SPI1_MISO,,,,TIM13_CH1,,,,DCMI_PIXCLK,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port A pin 5" ",TIM2_CH1/TIM2_ETR,,TIM8_CH1N,,SPI1_SCK/I2S1_CK,,,,,OTG_HS_ULPI_CK,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port A pin 4" ",,,,,SPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,USART2_CK,,,,,OTG_HS_SOF,DCMI_HSYNC,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port A pin 3" ",TIM2_CH4,TIM5_CH4,TIM9_CH2,,,,USART2_RX,,,OTG_HS_ULPI_D0,ETH_MII_COL,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port A pin 2" ",TIM2_CH3,TIM5_CH3,TIM9_CH1,,,,USART2_TX,SAI2_SCK_B,,,ETH_MDIO,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port A pin 1" ",TIM2_CH2,TIM5_CH2,,,,,USART2_RTS,UART4_RX,QUADSPI_BK1_IO3,SAI2_MCK_B,ETH_MII_RX_CLK/ETH_RMII_REF_CLK,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port A pin 0" ",TIM2_CH1/TIM2_ETR,TIM_5_CH1,TIM8_ETR,,,,USART2_CTS,UART4_TX,,SAI2_SD_B,ETH_MII_CRS,,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port A Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port A pin 15" "JTDI,TIM2_CH1/TIM2_ETR,,,HDMI_CEC,SPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,,UART4_RTS,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port A pin 14" "JTCK-SWCLK,,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port A pin 13" "JTMS-SWDIO,,,,,,,,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port A pin 12" ",TIM1_ETR,,,,,,USART1_RTS,SAI2_FS_B,CAN1_TX,OTG_FS_DP,,,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port A pin 11" ",TIM1_CH4,,,,,,USART1_CTS,,CAN1_RX,OTG_FS_DM,,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port A pin 10" ",TIM1_CH3,,,,,,USART1_RX,,,OTG_FS_ID,,,DCMI_D1,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port A pin 9" ",TIM1_CH2,,,I2C3_SMBA,SPI2_SCK/I2S2_CK,,USART1_TX,,,,,,DCMI_D0,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port A pin 8" "MCO1,TIM1_CH1,,TIM8_BKIN2,I2C3_SCL,,,USART1_CK,,,OTG_FS_SOF,,,,,EVENTOUT"
|
|
elif (cpuis("STM32F746*"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port A Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port A pin 7" ",TIM1_CH1N,TIM3_CH2,TIM8_CH1N,,SPI1_MOSI/I2S1_SD,,,,TIM14_CH1,,ETH_MII_RX_DV/ETH_RMII_CRS_DV,FMC_SDNWE,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port A pin 6" ",TIM1_BKIN,TIM3_CH1,TIM8_BKIN,,SPI1_MISO,,,,TIM13_CH1,,,,DCMI_PIXCLK,LCD_G2,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port A pin 5" ",TIM2_CH1/TIM2_ETR,,TIM8_CH1N,,SPI1_SCK/I2S1_CK,,,,,OTG_HS_ULPI_CK,,,,LCD_R4,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port A pin 4" ",,,,,SPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,USART2_CK,,,,,OTG_HS_SOF,DCMI_HSYNC,LCD_VSYNC,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port A pin 3" ",TIM2_CH4,TIM5_CH4,TIM9_CH2,,,,USART2_RX,,,OTG_HS_ULPI_D0,ETH_MII_COL,,,LCD_B5,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port A pin 2" ",TIM2_CH3,TIM5_CH3,TIM9_CH1,,,,USART2_TX,SAI2_SCK_B,,,ETH_MDIO,,,LCD_R1,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port A pin 1" ",TIM2_CH2,TIM5_CH2,,,,,USART2_RTS,UART4_RX,QUADSPI_BK1_IO3,SAI2_MCK_B,ETH_MII_RX_CLK/ETH_RMII_REF_CLK,,,LCD_R2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port A pin 0" ",TIM2_CH1/TIM2_ETR,TIM_5_CH1,TIM8_ETR,,,,USART2_CTS,UART4_TX,,SAI2_SD_B,ETH_MII_CRS,,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port A Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port A pin 15" "JTDI,TIM2_CH1/TIM2_ETR,,,HDMI_CEC,SPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,,UART4_RTS,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port A pin 14" "JTCK-SWCLK,,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port A pin 13" "JTMS-SWDIO,,,,,,,,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port A pin 12" ",TIM1_ETR,,,,,,USART1_RTS,SAI2_FS_B,CAN1_TX,OTG_FS_DP,,,,LCD_R5,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port A pin 11" ",TIM1_CH4,,,,,,USART1_CTS,,CAN1_RX,OTG_FS_DM,,,,LCD_R4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port A pin 10" ",TIM1_CH3,,,,,,USART1_RX,,,OTG_FS_ID,,,DCMI_D1,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port A pin 9" ",TIM1_CH2,,,I2C3_SMBA,SPI2_SCK/I2S2_CK,,USART1_TX,,,,,,DCMI_D0,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port A pin 8" "MCO1,TIM1_CH1,,TIM8_BKIN2,I2C3_SCL,,,USART1_CK,,,OTG_FS_SOF,,,,LCD_R6,EVENTOUT"
|
|
elif (cpuis("STM32F750*")||cpuis("STM32F756*"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port A Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port A pin 7" ",TIM1_CH1N,TIM3_CH2,TIM8_CH1N,,SPI1_MOSI/I2S1_SD,,,,TIM14_CH1,,ETH_MII_RX_DV/ETH_RMII_CRS_DV,FMC_SDNWE,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port A pin 6" ",TIM1_BKIN,TIM3_CH1,TIM8_BKIN,,SPI1_MISO,,,,TIM13_CH1,,,,DCMI_PIXCLK,LCD_G2,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port A pin 5" ",TIM2_CH1/TIM2_ETR,,TIM8_CH1N,,SPI1_SCK/I2S1_CK,,,,,OTG_HS_ULPI_CK,,,,LCD_R4,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port A pin 4" ",,,,,SPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,USART2_CK,,,,,OTG_HS_SOF,DCMI_HSYNC,LCD_VSYNC,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port A pin 3" ",TIM2_CH4,TIM5_CH4,TIM9_CH2,,,,USART2_RX,,,OTG_HS_ULPI_D0,ETH_MII_COL,,,LCD_B5,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port A pin 2" ",TIM2_CH3,TIM5_CH3,TIM9_CH1,,,,USART2_TX,SAI2_SCK_B,,,ETH_MDIO,,,LCD_R1,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port A pin 1" ",TIM2_CH2,TIM5_CH2,,,,,USART2_RTS,UART4_RX,QUADSPI_BK1_IO3,SAI2_MCK_B,ETH_MII_RX_CLK/ETH_RMII_REF_CLK,,,LCD_R2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port A pin 0" ",TIM2_CH1/TIM2_ETR,TIM_5_CH1,TIM8_ETR,,,,USART2_CTS,UART4_TX,,SAI2_SD_B,ETH_MII_CRS,,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port A Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port A pin 15" "JTDI,TIM2_CH1/TIM2_ETR,,,HDMI_CEC,SPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,,UART4_RTS,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port A pin 14" "JTCK-SWCLK,,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port A pin 13" "JTMS-SWDIO,,,,,,,,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port A pin 12" ",TIM1_ETR,,,,,,USART1_RTS,SAI2_FS_B,CAN1_TX,OTG_FS_DP,,,,LCD_R5,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port A pin 11" ",TIM1_CH4,,,,,,USART1_CTS,,CAN1_RX,OTG_FS_DM,,,,LCD_R4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port A pin 10" ",TIM1_CH3,,,,,,USART1_RX,,,OTG_FS_ID,,,DCMI_D1,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port A pin 9" ",TIM1_CH2,,,I2C3_SMBA,SPI2_SCK/I2S2_CK,,USART1_TX,,,,,,DCMI_D0,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port A pin 8" "MCO1,TIM1_CH1,,TIM8_BKIN2,I2C3_SCL,,,USART1_CK,,,OTG_FS_SOF,,,,LCD_R6,EVENTOUT"
|
|
elif ((cpuis("STM32F767*")&&!cpuis("STM32F767V*"))||(cpuis("STM32F769*")&&!cpuis("STM32F769V*")&&!cpuis("STM32F769A*")))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port A Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port A pin 7" ",TIM1_CH1N,TIM3_CH2,TIM8_CH1N,,SPI1_MOSI/I2S1_SD,,,SPI6_MOSI,TIM14_CH1,,ETH_MII_RX_DV/ETH_RMII_CRS_DV,FMC_SDNWE,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port A pin 6" ",TIM1_BKIN,TIM3_CH1,TIM8_BKIN,,SPI1_MISO,,,SPI6_MISO,TIM13_CH1,,,MDIOS_MDC,DCMI_PIXCLK,LCD_G2,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port A pin 5" ",TIM2_CH1/TIM2_ETR,,TIM8_CH1N,,SPI1_SCK/I2S1_CK,,,SPI6_SCK,,OTG_HS_ULPI_CK,,,,LCD_R4,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port A pin 4" ",,,,,SPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,USART2_CK,SPI6_NSS,,,,OTG_HS_SOF,DCMI_HSYNC,LCD_VSYNC,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port A pin 3" ",TIM2_CH4,TIM5_CH4,TIM9_CH2,,,,USART2_RX,,LCD_B2,OTG_HS_ULPI_D0,ETH_MII_COL,,,LCD_B5,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port A pin 2" ",TIM2_CH3,TIM5_CH3,TIM9_CH1,,,,USART2_TX,SAI2_SCK_B,,,ETH_MDIO,MDIOS_MDIO,,LCD_R1,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port A pin 1" ",TIM2_CH2,TIM5_CH2,,,,,USART2_RTS,UART4_RX,QUADSPI_BK1_IO3,SAI2_MCK_B,ETH_MII_RX_CLK/ETH_RMII_REF_CLK,,,LCD_R2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port A pin 0" ",TIM2_CH1/TIM2_ETR,TIM_5_CH1,TIM8_ETR,,,,USART2_CTS,UART4_TX,,SAI2_SD_B,ETH_MII_CRS,,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port A Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port A pin 15" "JTDI,TIM2_CH1/TIM2_ETR,,,HDMI_CEC,SPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,SPI6_NSS,UART4_RTS,,,CAN3_TX,UART7_TX,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port A pin 14" "JTCK-SWCLK,,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port A pin 13" "JTMS-SWDIO,,,,,,,,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port A pin 12" ",TIM1_ETR,,,,SPI2_SCK/I2S2_CK,UART4_TX,USART1_RTS,SAI2_FS_B,CAN1_TX,OTG_FS_DP,,,,LCD_R5,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port A pin 11" ",TIM1_CH4,,,,SPI2_NSS/I2S2_WS,UART4_RX,USART1_CTS,,CAN1_RX,OTG_FS_DM,,,,LCD_R4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port A pin 10" ",TIM1_CH3,,,,,,USART1_RX,,LCD_B4,OTG_FS_ID,,MDIOS_MDIO,DCMI_D1,LCD_B1,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port A pin 9" ",TIM1_CH2,,,I2C3_SMBA,SPI2_SCK/I2S2_CK,,USART1_TX,,,,,,DCMI_D0,LCD_R5,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port A pin 8" "MCO1,TIM1_CH1,,TIM8_BKIN2,I2C3_SCL,,,USART1_CK,,,OTG_FS_SOF,CAN3_RX,UART7_RX,LCD_B3,LCD_R6,EVENTOUT"
|
|
elif cpuis("STM32F767V*")||cpuis("STM32F769V*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port A Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port A pin 7" ",TIM1_CH1N,TIM3_CH2,TIM8_CH1N,,SPI1_MOSI/I2S1_SD,,,,TIM14_CH1,,ETH_MII_RX_DV/ETH_RMII_CRS_DV,FMC_SDNWE,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port A pin 6" ",TIM1_BKIN,TIM3_CH1,TIM8_BKIN,,SPI1_MISO,,,,TIM13_CH1,,,MDIOS_MDC,DCMI_PIXCLK,LCD_G2,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port A pin 5" ",TIM2_CH1/TIM2_ETR,,TIM8_CH1N,,SPI1_SCK/I2S1_CK,,,,,OTG_HS_ULPI_CK,,,,LCD_R4,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port A pin 4" ",,,,,SPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,USART2_CK,,,,,OTG_HS_SOF,DCMI_HSYNC,LCD_VSYNC,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port A pin 3" ",TIM2_CH4,TIM5_CH4,TIM9_CH2,,,,USART2_RX,,LCD_B2,OTG_HS_ULPI_D0,ETH_MII_COL,,,LCD_B5,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port A pin 2" ",TIM2_CH3,TIM5_CH3,TIM9_CH1,,,,USART2_TX,SAI2_SCK_B,,,ETH_MDIO,MDIOS_MDIO,,LCD_R1,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port A pin 1" ",TIM2_CH2,TIM5_CH2,,,,,USART2_RTS,UART4_RX,QUADSPI_BK1_IO3,SAI2_MCK_B,ETH_MII_RX_CLK/ETH_RMII_REF_CLK,,,LCD_R2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port A pin 0" ",TIM2_CH1/TIM2_ETR,TIM_5_CH1,TIM8_ETR,,,,USART2_CTS,UART4_TX,,SAI2_SD_B,ETH_MII_CRS,,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port A Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port A pin 15" "JTDI,TIM2_CH1/TIM2_ETR,,,HDMI_CEC,SPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,,UART4_RTS,,,CAN3_TX,UART7_TX,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port A pin 14" "JTCK-SWCLK,,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port A pin 13" "JTMS-SWDIO,,,,,,,,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port A pin 12" ",TIM1_ETR,,,,SPI2_SCK/I2S2_CK,UART4_TX,USART1_RTS,SAI2_FS_B,CAN1_TX,OTG_FS_DP,,,,LCD_R5,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port A pin 11" ",TIM1_CH4,,,,SPI2_NSS/I2S2_WS,UART4_RX,USART1_CTS,,CAN1_RX,OTG_FS_DM,,,,LCD_R4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port A pin 10" ",TIM1_CH3,,,,,,USART1_RX,,LCD_B4,OTG_FS_ID,,MDIOS_MDIO,DCMI_D1,LCD_B1,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port A pin 9" ",TIM1_CH2,,,I2C3_SMBA,SPI2_SCK/I2S2_CK,,USART1_TX,,,,,,DCMI_D0,LCD_R5,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port A pin 8" "MCO1,TIM1_CH1,,TIM8_BKIN2,I2C3_SCL,,,USART1_CK,,,OTG_FS_SOF,CAN3_RX,UART7_RX,LCD_B3,LCD_R6,EVENTOUT"
|
|
elif (cpuis("STM32F765*")&&!cpuis("STM32F765V*"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port A Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port A pin 7" ",TIM1_CH1N,TIM3_CH2,TIM8_CH1N,,SPI1_MOSI/I2S1_SD,,,SPI6_MOSI,TIM14_CH1,,ETH_MII_RX_DV/ETH_RMII_CRS_DV,FMC_SDNWE,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port A pin 6" ",TIM1_BKIN,TIM3_CH1,TIM8_BKIN,,SPI1_MISO,,,SPI6_MISO,TIM13_CH1,,,MDIOS_MDC,DCMI_PIXCLK,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port A pin 5" ",TIM2_CH1/TIM2_ETR,,TIM8_CH1N,,SPI1_SCK/I2S1_CK,,,SPI6_SCK,,OTG_HS_ULPI_CK,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port A pin 4" ",,,,,SPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,USART2_CK,SPI6_NSS,,,,OTG_HS_SOF,DCMI_HSYNC,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port A pin 3" ",TIM2_CH4,TIM5_CH4,TIM9_CH2,,,,USART2_RX,,,OTG_HS_ULPI_D0,ETH_MII_COL,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port A pin 2" ",TIM2_CH3,TIM5_CH3,TIM9_CH1,,,,USART2_TX,SAI2_SCK_B,,,ETH_MDIO,MDIOS_MDIO,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port A pin 1" ",TIM2_CH2,TIM5_CH2,,,,,USART2_RTS,UART4_RX,QUADSPI_BK1_IO3,SAI2_MCK_B,ETH_MII_RX_CLK/ETH_RMII_REF_CLK,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port A pin 0" ",TIM2_CH1/TIM2_ETR,TIM_5_CH1,TIM8_ETR,,,,USART2_CTS,UART4_TX,,SAI2_SD_B,ETH_MII_CRS,,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port A Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port A pin 15" "JTDI,TIM2_CH1/TIM2_ETR,,,HDMI_CEC,SPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,SPI6_NSS,UART4_RTS,,,CAN3_TX,UART7_TX,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port A pin 14" "JTCK-SWCLK,,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port A pin 13" "JTMS-SWDIO,,,,,,,,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port A pin 12" ",TIM1_ETR,,,,SPI2_SCK/I2S2_CK,UART4_TX,USART1_RTS,SAI2_FS_B,CAN1_TX,OTG_FS_DP,,,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port A pin 11" ",TIM1_CH4,,,,SPI2_NSS/I2S2_WS,UART4_RX,USART1_CTS,,CAN1_RX,OTG_FS_DM,,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port A pin 10" ",TIM1_CH3,,,,,,USART1_RX,,,OTG_FS_ID,,MDIOS_MDIO,DCMI_D1,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port A pin 9" ",TIM1_CH2,,,I2C3_SMBA,SPI2_SCK/I2S2_CK,,USART1_TX,,,,,,DCMI_D0,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port A pin 8" "MCO1,TIM1_CH1,,TIM8_BKIN2,I2C3_SCL,,,USART1_CK,,,OTG_FS_SOF,CAN3_RX,UART7_RX,,,EVENTOUT"
|
|
elif (cpuis("STM32F765V*"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port A Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port A pin 7" ",TIM1_CH1N,TIM3_CH2,TIM8_CH1N,,SPI1_MOSI/I2S1_SD,,,,TIM14_CH1,,ETH_MII_RX_DV/ETH_RMII_CRS_DV,FMC_SDNWE,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port A pin 6" ",TIM1_BKIN,TIM3_CH1,TIM8_BKIN,,SPI1_MISO,,,,TIM13_CH1,,,MDIOS_MDC,DCMI_PIXCLK,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port A pin 5" ",TIM2_CH1/TIM2_ETR,,TIM8_CH1N,,SPI1_SCK/I2S1_CK,,,,,OTG_HS_ULPI_CK,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port A pin 4" ",,,,,SPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,USART2_CK,,,,,OTG_HS_SOF,DCMI_HSYNC,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port A pin 3" ",TIM2_CH4,TIM5_CH4,TIM9_CH2,,,,USART2_RX,,,OTG_HS_ULPI_D0,ETH_MII_COL,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port A pin 2" ",TIM2_CH3,TIM5_CH3,TIM9_CH1,,,,USART2_TX,SAI2_SCK_B,,,ETH_MDIO,MDIOS_MDIO,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port A pin 1" ",TIM2_CH2,TIM5_CH2,,,,,USART2_RTS,UART4_RX,QUADSPI_BK1_IO3,SAI2_MCK_B,ETH_MII_RX_CLK/ETH_RMII_REF_CLK,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port A pin 0" ",TIM2_CH1/TIM2_ETR,TIM_5_CH1,TIM8_ETR,,,,USART2_CTS,UART4_TX,,SAI2_SD_B,ETH_MII_CRS,,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port A Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port A pin 15" "JTDI,TIM2_CH1/TIM2_ETR,,,HDMI_CEC,SPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,,UART4_RTS,,,CAN3_TX,UART7_TX,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port A pin 14" "JTCK-SWCLK,,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port A pin 13" "JTMS-SWDIO,,,,,,,,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port A pin 12" ",TIM1_ETR,,,,SPI2_SCK/I2S2_CK,UART4_TX,USART1_RTS,SAI2_FS_B,CAN1_TX,OTG_FS_DP,,,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port A pin 11" ",TIM1_CH4,,,,SPI2_NSS/I2S2_WS,UART4_RX,USART1_CTS,,CAN1_RX,OTG_FS_DM,,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port A pin 10" ",TIM1_CH3,,,,,,USART1_RX,,,OTG_FS_ID,,MDIOS_MDIO,DCMI_D1,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port A pin 9" ",TIM1_CH2,,,I2C3_SMBA,SPI2_SCK/I2S2_CK,,USART1_TX,,,,,,DCMI_D0,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port A pin 8" "MCO1,TIM1_CH1,,TIM8_BKIN2,I2C3_SCL,,,USART1_CK,,,OTG_FS_SOF,CAN3_RX,UART7_RX,,,EVENTOUT"
|
|
elif ((cpuis("STM32F777*")&&!cpuis("STM32F777V*"))||(cpuis("STM32F779*")&&!cpuis("STM32F779A*")))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port A Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port A pin 7" ",TIM1_CH1N,TIM3_CH2,TIM8_CH1N,,SPI1_MOSI/I2S1_SD,,,SPI6_MOSI,TIM14_CH1,,ETH_MII_RX_DV/ETH_RMII_CRS_DV,FMC_SDNWE,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port A pin 6" ",TIM1_BKIN,TIM3_CH1,TIM8_BKIN,,SPI1_MISO,,,SPI6_MISO,TIM13_CH1,,,MDIOS_MDC,DCMI_PIXCLK,LCD_G2,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port A pin 5" ",TIM2_CH1/TIM2_ETR,,TIM8_CH1N,,SPI1_SCK/I2S1_CK,,,SPI6_SCK,,OTG_HS_ULPI_CK,,,,LCD_R4,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port A pin 4" ",,,,,SPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,USART2_CK,SPI6_NSS,,,,OTG_HS_SOF,DCMI_HSYNC,LCD_VSYNC,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port A pin 3" ",TIM2_CH4,TIM5_CH4,TIM9_CH2,,,,USART2_RX,,LCD_B2,OTG_HS_ULPI_D0,ETH_MII_COL,,,LCD_B5,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port A pin 2" ",TIM2_CH3,TIM5_CH3,TIM9_CH1,,,,USART2_TX,SAI2_SCK_B,,,ETH_MDIO,MDIOS_MDIO,,LCD_R1,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port A pin 1" ",TIM2_CH2,TIM5_CH2,,,,,USART2_RTS,UART4_RX,QUADSPI_BK1_IO3,SAI2_MCK_B,ETH_MII_RX_CLK/ETH_RMII_REF_CLK,,,LCD_R2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port A pin 0" ",TIM2_CH1/TIM2_ETR,TIM_5_CH1,TIM8_ETR,,,,USART2_CTS,UART4_TX,,SAI2_SD_B,ETH_MII_CRS,,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port A Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port A pin 15" "JTDI,TIM2_CH1/TIM2_ETR,,,HDMI_CEC,SPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,SPI6_NSS,UART4_RTS,,,CAN3_TX,UART7_TX,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port A pin 14" "JTCK-SWCLK,,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port A pin 13" "JTMS-SWDIO,,,,,,,,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port A pin 12" ",TIM1_ETR,,,,SPI2_SCK/I2S2_CK,UART4_TX,USART1_RTS,SAI2_FS_B,CAN1_TX,OTG_FS_DP,,,,LCD_R5,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port A pin 11" ",TIM1_CH4,,,,SPI2_NSS/I2S2_WS,UART4_RX,USART1_CTS,,CAN1_RX,OTG_FS_DM,,,,LCD_R4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port A pin 10" ",TIM1_CH3,,,,,,USART1_RX,,LCD_B4,OTG_FS_ID,,MDIOS_MDIO,DCMI_D1,LCD_B1,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port A pin 9" ",TIM1_CH2,,,I2C3_SMBA,SPI2_SCK/I2S2_CK,,USART1_TX,,,,,,DCMI_D0,LCD_R5,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port A pin 8" "MCO1,TIM1_CH1,,TIM8_BKIN2,I2C3_SCL,,,USART1_CK,,,OTG_FS_SOF,CAN3_RX,UART7_RX,LCD_B3,LCD_R6,EVENTOUT"
|
|
elif cpuis("STM32F777V*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port A Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port A pin 7" ",TIM1_CH1N,TIM3_CH2,TIM8_CH1N,,SPI1_MOSI/I2S1_SD,,,,TIM14_CH1,,ETH_MII_RX_DV/ETH_RMII_CRS_DV,FMC_SDNWE,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port A pin 6" ",TIM1_BKIN,TIM3_CH1,TIM8_BKIN,,SPI1_MISO,,,,TIM13_CH1,,,MDIOS_MDC,DCMI_PIXCLK,LCD_G2,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port A pin 5" ",TIM2_CH1/TIM2_ETR,,TIM8_CH1N,,SPI1_SCK/I2S1_CK,,,,,OTG_HS_ULPI_CK,,,,LCD_R4,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port A pin 4" ",,,,,SPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,USART2_CK,,,,,OTG_HS_SOF,DCMI_HSYNC,LCD_VSYNC,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port A pin 3" ",TIM2_CH4,TIM5_CH4,TIM9_CH2,,,,USART2_RX,,LCD_B2,OTG_HS_ULPI_D0,ETH_MII_COL,,,LCD_B5,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port A pin 2" ",TIM2_CH3,TIM5_CH3,TIM9_CH1,,,,USART2_TX,SAI2_SCK_B,,,ETH_MDIO,MDIOS_MDIO,,LCD_R1,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port A pin 1" ",TIM2_CH2,TIM5_CH2,,,,,USART2_RTS,UART4_RX,QUADSPI_BK1_IO3,SAI2_MCK_B,ETH_MII_RX_CLK/ETH_RMII_REF_CLK,,,LCD_R2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port A pin 0" ",TIM2_CH1/TIM2_ETR,TIM_5_CH1,TIM8_ETR,,,,USART2_CTS,UART4_TX,,SAI2_SD_B,ETH_MII_CRS,,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port A Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port A pin 15" "JTDI,TIM2_CH1/TIM2_ETR,,,HDMI_CEC,SPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,,UART4_RTS,,,CAN3_TX,UART7_TX,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port A pin 14" "JTCK-SWCLK,,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port A pin 13" "JTMS-SWDIO,,,,,,,,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port A pin 12" ",TIM1_ETR,,,,SPI2_SCK/I2S2_CK,UART4_TX,USART1_RTS,SAI2_FS_B,CAN1_TX,OTG_FS_DP,,,,LCD_R5,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port A pin 11" ",TIM1_CH4,,,,SPI2_NSS/I2S2_WS,UART4_RX,USART1_CTS,,CAN1_RX,OTG_FS_DM,,,,LCD_R4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port A pin 10" ",TIM1_CH3,,,,,,USART1_RX,,LCD_B4,OTG_FS_ID,,MDIOS_MDIO,DCMI_D1,LCD_B1,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port A pin 9" ",TIM1_CH2,,,I2C3_SMBA,SPI2_SCK/I2S2_CK,,USART1_TX,,,,,,DCMI_D0,LCD_R5,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port A pin 8" "MCO1,TIM1_CH1,,TIM8_BKIN2,I2C3_SCL,,,USART1_CK,,,OTG_FS_SOF,CAN3_RX,UART7_RX,LCD_B3,LCD_R6,EVENTOUT"
|
|
elif cpuis("STM32F768A*")||cpuis("STM32F769A*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port A Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port A pin 7" ",TIM1_CH1N,TIM3_CH2,TIM8_CH1N,,SPI1_MOSI/I2S1_SD,,,SPI6_MOSI,TIM14_CH1,,,FMC_SDNWE,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port A pin 6" ",TIM1_BKIN,TIM3_CH1,TIM8_BKIN,,SPI1_MISO,,,SPI6_MISO,TIM13_CH1,,,MDIOS_MDC,DCMI_PIXCLK,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port A pin 5" ",TIM2_CH1/TIM2_ETR,,TIM8_CH1N,,SPI1_SCK/I2S1_CK,,,SPI6_SCK,,OTG_HS_ULPI_CK,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port A pin 4" ",,,,,SPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,USART2_CK,SPI6_NSS,,,,OTG_HS_SOF,DCMI_HSYNC,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port A pin 3" ",TIM2_CH4,TIM5_CH4,TIM9_CH2,,,,USART2_RX,,,OTG_HS_ULPI_D0,,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port A pin 2" ",TIM2_CH3,TIM5_CH3,TIM9_CH1,,,,USART2_TX,SAI2_SCK_B,,,,MDIOS_MDIO,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port A pin 1" ",TIM2_CH2,TIM5_CH2,,,,,USART2_RTS,UART4_RX,QUADSPI_BK1_IO3,SAI2_MCK_B,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port A pin 0" ",TIM2_CH1/TIM2_ETR,TIM_5_CH1,TIM8_ETR,,,,USART2_CTS,UART4_TX,,SAI2_SD_B,,,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port A Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port A pin 15" "JTDI,TIM2_CH1/TIM2_ETR,,,HDMI_CEC,SPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,SPI6_NSS,UART4_RTS,,,CAN3_TX,UART7_TX,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port A pin 14" "JTCK-SWCLK,,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port A pin 13" "JTMS-SWDIO,,,,,,,,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port A pin 12" ",TIM1_ETR,,,,SPI2_SCK/I2S2_CK,UART4_TX,USART1_RTS,SAI2_FS_B,CAN1_TX,OTG_FS_DP,,,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port A pin 11" ",TIM1_CH4,,,,SPI2_NSS/I2S2_WS,UART4_RX,USART1_CTS,,CAN1_RX,OTG_FS_DM,,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port A pin 10" ",TIM1_CH3,,,,,,USART1_RX,,,OTG_FS_ID,,MDIOS_MDIO,DCMI_D1,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port A pin 9" ",TIM1_CH2,,,I2C3_SMBA,SPI2_SCK/I2S2_CK,,USART1_TX,,,,,,DCMI_D0,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port A pin 8" "MCO1,TIM1_CH1,,TIM8_BKIN2,I2C3_SCL,,,USART1_CK,,,OTG_FS_SOF,CAN3_RX,UART7_RX,,,EVENTOUT"
|
|
elif cpuis("STM32F778A*")||cpuis("STM32F779A*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port A Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port A pin 7" ",TIM1_CH1N,TIM3_CH2,TIM8_CH1N,,SPI1_MOSI/I2S1_SD,,,SPI6_MOSI,TIM14_CH1,,,FMC_SDNWE,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port A pin 6" ",TIM1_BKIN,TIM3_CH1,TIM8_BKIN,,SPI1_MISO,,,SPI6_MISO,TIM13_CH1,,,MDIOS_MDC,DCMI_PIXCLK,LCD_G2,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port A pin 5" ",TIM2_CH1/TIM2_ETR,,TIM8_CH1N,,SPI1_SCK/I2S1_CK,,,SPI6_SCK,,OTG_HS_ULPI_CK,,,,LCD_R4,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port A pin 4" ",,,,,SPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,USART2_CK,SPI6_NSS,,,,OTG_HS_SOF,DCMI_HSYNC,LCD_VSYNC,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port A pin 3" ",TIM2_CH4,TIM5_CH4,TIM9_CH2,,,,USART2_RX,,LCD_B2,OTG_HS_ULPI_D0,,,,LCD_B5,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port A pin 2" ",TIM2_CH3,TIM5_CH3,TIM9_CH1,,,,USART2_TX,SAI2_SCK_B,,,,MDIOS_MDIO,,LCD_R1,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port A pin 1" ",TIM2_CH2,TIM5_CH2,,,,,USART2_RTS,UART4_RX,QUADSPI_BK1_IO3,SAI2_MCK_B,,,,LCD_R2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port A pin 0" ",TIM2_CH1/TIM2_ETR,TIM_5_CH1,TIM8_ETR,,,,USART2_CTS,UART4_TX,,SAI2_SD_B,,,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port A Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port A pin 15" "JTDI,TIM2_CH1/TIM2_ETR,,,HDMI_CEC,SPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,SPI6_NSS,UART4_RTS,,,CAN3_TX,UART7_TX,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port A pin 14" "JTCK-SWCLK,,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port A pin 13" "JTMS-SWDIO,,,,,,,,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port A pin 12" ",TIM1_ETR,,,,SPI2_SCK/I2S2_CK,UART4_TX,USART1_RTS,SAI2_FS_B,CAN1_TX,OTG_FS_DP,,,,LCD_R5,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port A pin 11" ",TIM1_CH4,,,,SPI2_NSS/I2S2_WS,UART4_RX,USART1_CTS,,CAN1_RX,OTG_FS_DM,,,,LCD_R4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port A pin 10" ",TIM1_CH3,,,,,,USART1_RX,,LCD_B4,OTG_FS_ID,,MDIOS_MDIO,DCMI_D1,LCD_B1,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port A pin 9" ",TIM1_CH2,,,I2C3_SMBA,SPI2_SCK/I2S2_CK,,USART1_TX,,,,,,DCMI_D0,LCD_R5,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port A pin 8" "MCO1,TIM1_CH1,,TIM8_BKIN2,I2C3_SCL,,,USART1_CK,,,OTG_FS_SOF,CAN3_RX,UART7_RX,LCD_B3,LCD_R6,EVENTOUT"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO B"
|
|
base ad:0x40020400
|
|
width 13.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "MODER,GPIO Port B Mode Register"
|
|
bitfld.long 0x00 30.--31. " MODER[15] ,Port B pin 15 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " [14] ,Port B pin 14 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " [13] ,Port B pin 13 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 24.--25. " [12] ,Port B pin 12 mode" "Input,Output,Alternate function,Analog"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " [11] ,Port B pin 11 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " [10] ,Port B pin 10 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " [9] ,Port B pin 9 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " [8] ,Port B pin 8 mode" "Input,Output,Alternate function,Analog"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " [7] ,Port B pin 7 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " [6] ,Port B pin 6 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " [5] ,Port B pin 5 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " [4] ,Port B pin 4 mode" "Input,Output,Alternate function,Analog"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " [3] ,Port B pin 3 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " [2] ,Port B pin 2 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " [1] ,Port B pin 1 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " [0] ,Port B pin 0 mode" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "OTYPER,GPIO Port B Output Type Register"
|
|
bitfld.long 0x04 15. " OT[15] ,Port B pin 15 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " [14] ,Port B pin 14 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " [13] ,Port B pin 13 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 12. " [12] ,Port B pin 12 output type" "Push-pull,Open-drain"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Port B pin 11 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " [10] ,Port B pin 10 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 9. " [9] ,Port B pin 9 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " [8] ,Port B pin 8 output type" "Push-pull,Open-drain"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Port B pin 7 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " [6] ,Port B pin 6 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " [5] ,Port B pin 5 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " [4] ,Port B pin 4 output type" "Push-pull,Open-drain"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,Port B pin 3 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " [2] ,Port B pin 2 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " [1] ,Port B pin 1 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " [0] ,Port B pin 0 output type" "Push-pull,Open-drain"
|
|
line.long 0x08 "OSPEEDR,GPIO Port B Output Speed Register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR[15] ,Port B pin 15 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 28.--29. " [14] ,Port B pin 14 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 26.--27. " [13] ,Port B pin 13 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 24.--25. " [12] ,Port B pin 12 output speed" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x08 22.--23. " [11] ,Port B pin 11 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 20.--21. " [10] ,Port B pin 10 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 18.--19. " [9] ,Port B pin 9 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 16.--17. " [8] ,Port B pin 8 output speed" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x08 14.--15. " [7] ,Port B pin 7 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 12.--13. " [6] ,Port B pin 6 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 10.--11. " [5] ,Port B pin 5 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 8.--9. " [4] ,Port B pin 4 output speed" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x08 6.--7. " [3] ,Port B pin 3 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 4.--5. " [2] ,Port B pin 2 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 2.--3. " [1] ,Port B pin 1 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 0.--1. " [0] ,Port B pin 0 output speed" "Low,Medium,High,Very high"
|
|
line.long 0x0C "PUPDR,GPIO Port B Pull-up/Pull-down Register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR[15] ,Port B pin 15 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " [14] ,Port B pin 14 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " [13] ,Port B pin 13 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 24.--25. " [12] ,Port B pin 12 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
newline
|
|
bitfld.long 0x0C 22.--23. " [11] ,Port B pin 11 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " [10] ,Port B pin 10 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 18.--19. " [9] ,Port B pin 9 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " [8] ,Port B pin 8 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
newline
|
|
bitfld.long 0x0C 14.--15. " [7] ,Port B pin 7 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 12.--13. " [6] ,Port B pin 6 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " [5] ,Port B pin 5 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " [4] ,Port B pin 4 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
newline
|
|
bitfld.long 0x0C 6.--7. " [3] ,Port B pin 3 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " [2] ,Port B pin 2 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " [1] ,Port B pin 1 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " [0] ,Port B pin 0 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "IDR,GPIO Port B Input Data Register"
|
|
bitfld.long 0x00 15. " IDR[15] ,Port B pin 15 input data" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Port B pin 14 input data" "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Port B pin 13 input data" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Port B pin 12 input data" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Port B pin 11 input data" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Port B pin 10 input data" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,Port B pin 9 input data" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Port B pin 8 input data" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Port B pin 7 input data" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Port B pin 6 input data" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Port B pin 5 input data" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Port B pin 4 input data" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Port B pin 3 input data" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Port B pin 2 input data" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Port B pin 1 input data" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Port B pin 0 input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ODR_SET/CLR,GPIO Port B Output Data Set/Clear Register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR[15] ,Port B pin 15 output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " [14] ,Port B pin 14 output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " [13] ,Port B pin 13 output data" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " [12] ,Port B pin 12 output data" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " [11] ,Port B pin 11 output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " [10] ,Port B pin 10 output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " [9] ,Port B pin 9 output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " [8] ,Port B pin 8 output data" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " [7] ,Port B pin 7 output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " [6] ,Port B pin 6 output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " [5] ,Port B pin 5 output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " [4] ,Port B pin 4 output data" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " [3] ,Port B pin 3 output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " [2] ,Port B pin 2 output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " [1] ,Port B pin 1 output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " [0] ,Port B pin 0 output data" "Low,High"
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F750*")||cpuis("STM32F767BI"))
|
|
if ((per.l(ad:0x40020400+0x1C)&0x10000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO Port B Configuration Lock Register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
newline
|
|
bitfld.long 0x00 15. " LCK[15] ,Port B pin 15 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " [14] ,Port B pin 14 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " [13] ,Port B pin 13 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " [12] ,Port B pin 12 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Port B pin 11 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " [10] ,Port B pin 10 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " [9] ,Port B pin 9 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " [8] ,Port B pin 8 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Port B pin 7 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " [6] ,Port B pin 6 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " [5] ,Port B pin 5 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " [4] ,Port B pin 4 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Port B pin 3 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " [2] ,Port B pin 2 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " [1] ,Port B pin 1 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " [0] ,Port B pin 0 configuration lock" "Not locked,Locked"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO Port B Configuration Lock Register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
newline
|
|
rbitfld.long 0x00 15. " LCK[15] ,Port B pin 15 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 14. " [14] ,Port B pin 14 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 13. " [13] ,Port B pin 13 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 12. " [12] ,Port B pin 12 configuration lock" "Not locked,Locked"
|
|
newline
|
|
rbitfld.long 0x00 11. " [11] ,Port B pin 11 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 10. " [10] ,Port B pin 10 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 9. " [9] ,Port B pin 9 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 8. " [8] ,Port B pin 8 configuration lock" "Not locked,Locked"
|
|
newline
|
|
rbitfld.long 0x00 7. " [7] ,Port B pin 7 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 6. " [6] ,Port B pin 6 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 5. " [5] ,Port B pin 5 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 4. " [4] ,Port B pin 4 configuration lock" "Not locked,Locked"
|
|
newline
|
|
rbitfld.long 0x00 3. " [3] ,Port B pin 3 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 2. " [2] ,Port B pin 2 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 1. " [1] ,Port B pin 1 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 0. " [0] ,Port B pin 0 configuration lock" "Not locked,Locked"
|
|
endif
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO Port B Configuration Lock Register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
newline
|
|
bitfld.long 0x00 15. " LCK[15] ,Port B pin 15 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " [14] ,Port B pin 14 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " [13] ,Port B pin 13 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " [12] ,Port B pin 12 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Port B pin 11 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " [10] ,Port B pin 10 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " [9] ,Port B pin 9 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " [8] ,Port B pin 8 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Port B pin 7 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " [6] ,Port B pin 6 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " [5] ,Port B pin 5 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " [4] ,Port B pin 4 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Port B pin 3 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " [2] ,Port B pin 2 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " [1] ,Port B pin 1 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " [0] ,Port B pin 0 configuration lock" "Not locked,Locked"
|
|
endif
|
|
newline
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F732*")||cpuis("STM32F732*"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port B Alternate Function Low Register"
|
|
sif (cpuis("STM32F72?R*")||cpuis("STM32F73?R*"))
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port B pin 7" ",,TIM4_CH2,,I2C1_SDA,,,USART1_RX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port B pin 6" ",,TIM4_CH1,,I2C1_SCL,,,USART1_TX,,,QUADSPI_BK1_NCS,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port B pin 5" ",,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI/I2S1_SD,SPI3_MOSI/I2S3_SD,,,,OTG_HS_ULPI_D7,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port B pin 4" "NJTRST,,TIM3_CH1,,,SPI1_MISO,SPI3_MISO,SPI2_NSS/I2S2_WS,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port B pin 3" "JTDO/TRACESWO,TIM2_CH2,,,,SPI1_SCK/I2S1_CK,SPI3_SCK/I2S3_CK,,,,,,,,,EVENTOUT"
|
|
else
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port B pin 7" ",,TIM4_CH2,,I2C1_SDA,,,USART1_RX,,,,,FMC_NL,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port B pin 6" ",,TIM4_CH1,,I2C1_SCL,,,USART1_TX,,,QUADSPI_BK1_NCS,,FMC_SDNE1,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port B pin 5" ",,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI/I2S1_SD,SPI3_MOSI/I2S3_SD,,,,OTG_HS_ULPI_D7,,FMC_SDCKE1,,,EVENTOUT"
|
|
newline
|
|
sif (cpuis("STM32F723V*")||cpuis("STM32F733V*"))
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port B pin 4" "NJTRST,,TIM3_CH1,,,SPI1_MISO,SPI3_MISO,SPI2_NSS/I2S2_WS,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port B pin 3" "JTDO/TRACESWO,TIM2_CH2,,,,SPI1_SCK/I2S1_CK,SPI3_SCK/I2S3_CK,,,,,,,,,EVENTOUT"
|
|
else
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port B pin 4" "NJTRST,,TIM3_CH1,,,SPI1_MISO,SPI3_MISO,SPI2_NSS/I2S2_WS,,,SDMMC2_D3,,,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port B pin 3" "JTDO/TRACESWO,TIM2_CH2,,,,SPI1_SCK/I2S1_CK,SPI3_SCK/I2S3_CK,,,,SDMMC2_D2,,,,,EVENTOUT"
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port B pin 2" ",,,,,,SAI1_SD_A,SPI3_MOSI/I2S3_SD,,QUADSPI_CLK,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port B pin 1" ",TIM1_CH3N,TIM3_CH4,TIM8_CH3N,,,,,,,OTG_HS_ULPI_D2,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port B pin 0" ",TIM1_CH2N,TIM3_CH3,TIM8_CH2N,,,,,UART4_CTS,,OTG_HS_ULPI_D1,,,,,EVENTOUT"
|
|
newline
|
|
line.long 0x04 "AFRH,GPIO Port B Alternate Function High Register"
|
|
sif (cpuis("STM32F723Z*")||cpuis("STM32F733Z*"))
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port B pin 15" "RTC_REFIN,TIM1_CH3N,,TIM8_CH3N,,SPI2_MOSI/I2S2_SD,,,,,SDMMC2_D1,,OTG_HS_DP,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port B pin 14" ",TIM1_CH2N,,TIM8_CH2N,,SPI2_MISO,,USART3_RTS,,,SDMMC2_D0,,OTG_HS_DM,,,EVENTOUT"
|
|
elif (cpuis("STM32F72?R*")||cpuis("STM32F73?R*"))
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port B pin 15" "RTC_REFIN,TIM1_CH3N,,TIM8_CH3N,,SPI2_MOSI/I2S2_SD,,,,,,,OTG_HS_DP,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port B pin 14" ",TIM1_CH2N,,TIM8_CH2N,,SPI2_MISO,,USART3_RTS,,,,,OTG_HS_DM,,,EVENTOUT"
|
|
elif (cpuis("STM32F723V*")||cpuis("STM32F733V*"))
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port B pin 15" "RTC_REFIN,TIM1_CH3N,,TIM8_CH3N,,SPI2_MOSI/I2S2_SD,,,,,,,OTG_HS_DP,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port B pin 14" ",TIM1_CH2N,,TIM8_CH2N,,SPI2_MISO,,USART3_RTS,,,,,OTG_HS_DM,,,EVENTOUT"
|
|
else
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port B pin 15" "RTC_REFIN,TIM1_CH3N,,TIM8_CH3N,,SPI2_MOSI/I2S2_SD,,,,TIM12_CH2,SDMMC2_D1,,OTG_HS_DP,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port B pin 14" ",TIM1_CH2N,,TIM8_CH2N,,SPI2_MISO,,USART3_RTS,,TIM12_CH1,SDMMC2_D0,,OTG_HS_DM,,,EVENTOUT"
|
|
endif
|
|
sif (cpuis("STM32F72?R*")||cpuis("STM32F73?R*"))
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port B pin 13" ",TIM1_CH1N,,,,SPI2_SCK/I2S2_CK,,USART3_CTS,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port B pin 12" ",TIM1_BKIN,,,I2C2_SMBA,SPI2_NSS/I2S2_WS,,USART3_CK,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port B pin 11" ",TIM2_CH4,,,I2C2_SDA,,,USART3_RX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port B pin 10" ",TIM2_CH3,,,I2C2_SCL,SPI2_SCK/I2S2_CK,,USART3_TX,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port B pin 9" ",,TIM4_CH4,TIM11_CH1,I2C1_SDA,SPI2_NSS/I2S2_WS,,,,CAN1_TX,,,SDMMC1_D5,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port B pin 8" ",,TIM4_CH3,TIM10_CH1,I2C1_SCL,,,,,CAN1_RX,,,SDMMC1_D4,,,EVENTOUT"
|
|
else
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port B pin 13" ",TIM1_CH1N,,,,SPI2_SCK/I2S2_CK,,USART3_CTS,,,OTG_HS_ULPI_D6,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port B pin 12" ",TIM1_BKIN,,,I2C2_SMBA,SPI2_NSS/I2S2_WS,,USART3_CK,,,OTG_HS_ULPI_D5,,OTG_HS_ID,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port B pin 11" ",TIM2_CH4,,,I2C2_SDA,,,USART3_RX,,,OTG_HS_ULPI_D4,,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port B pin 10" ",TIM2_CH3,,,I2C2_SCL,SPI2_SCK/I2S2_CK,,USART3_TX,,,OTG_HS_ULPI_D3,,,,,EVENTOUT"
|
|
newline
|
|
sif (cpuis("STM32F723V*")||cpuis("STM32F733V*"))
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port B pin 9" ",,TIM4_CH4,TIM11_CH1,I2C1_SDA,SPI2_NSS/I2S2_WS,,,,CAN1_TX,,,SDMMC1_D5,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port B pin 8" ",,TIM4_CH3,TIM10_CH1,I2C1_SCL,,,,,CAN1_RX,,,SDMMC1_D4,,,EVENTOUT"
|
|
else
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port B pin 9" ",,TIM4_CH4,TIM11_CH1,I2C1_SDA,SPI2_NSS/I2S2_WS,,,,CAN1_TX,SDMMC2_D5,,SDMMC1_D5,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port B pin 8" ",,TIM4_CH3,TIM10_CH1,I2C1_SCL,,,,,CAN1_RX,SDMMC2_D4,,SDMMC1_D4,,,EVENTOUT"
|
|
endif
|
|
endif
|
|
elif cpuis("STM32F730*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port B Alternate Function Low Register"
|
|
sif cpuis("STM32F730R*")||cpuis("STM32F730V*")
|
|
sif cpuis("STM32F730R*")
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port B pin 7" ",,TIM4_CH2,,I2C1_SDA,,,USART1_RX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port B pin 6" ",,TIM4_CH1,,I2C1_SCL,,,USART1_TX,,,QUADSPI_BK1_NCS,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port B pin 5" ",,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI/I2S1_SD,SPI3_MOSI/I2S3_SD,,,,OTG_HS_ULPI_D7,,,,,EVENTOUT"
|
|
newline
|
|
elif cpuis("STM32F730V*")
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port B pin 7" ",,TIM4_CH2,,I2C1_SDA,,,USART1_RX,,,,,FMC_NL,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port B pin 6" ",,TIM4_CH1,,I2C1_SCL,,,USART1_TX,,,QUADSPI_BK1_NCS,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port B pin 5" ",,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI/I2S1_SD,SPI3_MOSI/I2S3_SD,,,,OTG_HS_ULPI_D7,,,,,EVENTOUT"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port B pin 4" "NJTRST,,TIM3_CH1,,,SPI1_MISO,SPI3_MISO,SPI2_NSS/I2S2_WS,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port B pin 3" "JTDO/TRACESWO,TIM2_CH2,,,,SPI1_SCK/I2S1_CK,SPI3_SCK/I2S3_CK,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port B pin 2" ",,,,,,SAI1_SD_A,SPI3_MOSI/I2S3_SD,,QUADSPI_CLK,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port B pin 1" ",TIM1_CH3N,TIM3_CH4,TIM8_CH3N,,,,,,,OTG_HS_ULPI_D2,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port B pin 0" ",TIM1_CH2N,TIM3_CH3,TIM8_CH2N,,,,,UART4_CTS,,,,,,,EVENTOUT"
|
|
else
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port B pin 7" ",,TIM4_CH2,,I2C1_SDA,,,USART1_RX,,,,,FMC_NL,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port B pin 6" ",,TIM4_CH1,,I2C1_SCL,,,USART1_TX,,,QUADSPI_BK1_NCS,,FMC_SDNE1,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port B pin 5" ",,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI/I2S1_SD,SPI3_MOSI/I2S3_SD,,,,,,FMC_SDCKE1,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port B pin 4" "NJTRST,,TIM3_CH1,,,SPI1_MISO,SPI3_MISO,SPI2_NSS/I2S2_WS,,,SDMMC2_D3,,,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port B pin 3" "JTDO/TRACESWO,TIM2_CH2,,,,SPI1_SCK/I2S1_CK,SPI3_SCK/I2S3_CK,,,,SDMMC2_D2,,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port B pin 2" ",,,,,,SAI1_SD_A,SPI3_MOSI/I2S3_SD,,QUADSPI_CLK,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port B pin 1" ",TIM1_CH3N,TIM3_CH4,TIM8_CH3N,,,,,,,OTG_HS_ULPI_D2,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port B pin 0" ",TIM1_CH2N,TIM3_CH3,TIM8_CH2N,,,,,UART4_CTS,,,,,,,EVENTOUT"
|
|
endif
|
|
newline
|
|
line.long 0x04 "AFRH,GPIO Port B Alternate Function High Register"
|
|
sif cpuis("STM32F730I*")
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port B pin 15" "RTC_REFIN,TIM1_CH3N,,TIM8_CH3N,,SPI2_MOSI/I2S2_SD,,,,TIM12_CH2,SDMMC2_D1,,OTG_HS_DP,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port B pin 14" ",TIM1_CH2N,,TIM8_CH2N,,SPI2_MISO,,USART3_RTS,,TIM12_CH1,SDMMC2_D0,,OTG_HS_DM,,,EVENTOUT"
|
|
newline
|
|
elif cpuis("STM32F730Z*")
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port B pin 15" "RTC_REFIN,TIM1_CH3N,,TIM8_CH3N,,SPI2_MOSI/I2S2_SD,,,,,SDMMC2_D1,,OTG_HS_DP,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port B pin 14" ",TIM1_CH2N,,TIM8_CH2N,,SPI2_MISO,,USART3_RTS,,,SDMMC2_D0,,OTG_HS_DM,,,EVENTOUT"
|
|
newline
|
|
elif cpuis("STM32F730R*")||cpuis("[32]F730V*")
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port B pin 15" "RTC_REFIN,TIM1_CH3N,,TIM8_CH3N,,SPI2_MOSI/I2S2_SD,,,,,,,OTG_HS_DP,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port B pin 14" ",TIM1_CH2N,,TIM8_CH2N,,SPI2_MISO,,USART3_RTS,,,,,OTG_HS_DM,,,EVENTOUT"
|
|
newline
|
|
endif
|
|
sif cpuis("STM32F730R*")||cpuis("STM32F730V*")
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port B pin 13" ",TIM1_CH1N,,,,SPI2_SCK/I2S2_CK,,USART3_CTS,,,OTG_HS_ULPI_D6,,,,,EVENTOUT"
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port B pin 12" ",TIM1_BKIN,,,I2C2_SMBA,SPI2_NSS/I2S2_WS,,USART3_CK,,,OTG_HS_ULPI_D5,,OTG_HS_ID,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port B pin 11" ",TIM2_CH4,,,I2C2_SDA,,,USART3_RX,,,OTG_HS_ULPI_D4,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port B pin 10" ",TIM2_CH3,,,I2C2_SCL,SPI2_SCK/I2S2_CK,,USART3_TX,,,OTG_HS_ULPI_D3,,,,,EVENTOUT"
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port B pin 9" ",,TIM4_CH4,TIM11_CH1,I2C1_SDA,SPI2_NSS/I2S2_WS,,,,CAN1_TX,,,SDMMC1_D5,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port B pin 8" ",,TIM4_CH3,TIM10_CH1,I2C1_SCL,,,,,CAN1_RX,,,SDMMC1_D4,,,EVENTOUT"
|
|
else
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port B pin 13" ",TIM1_CH1N,,,,SPI2_SCK/I2S2_CK,,USART3_CTS,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port B pin 12" ",TIM1_BKIN,,,I2C2_SMBA,SPI2_NSS/I2S2_WS,,USART3_CK,,,,,OTG_HS_ID,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port B pin 11" ",TIM2_CH4,,,I2C2_SDA,,,USART3_RX,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port B pin 10" ",TIM2_CH3,,,I2C2_SCL,SPI2_SCK/I2S2_CK,,USART3_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port B pin 9" ",,TIM4_CH4,TIM11_CH1,I2C1_SDA,SPI2_NSS/I2S2_WS,,,,CAN1_TX,SDMMC2_D5,,SDMMC1_D5,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port B pin 8" ",,TIM4_CH3,TIM10_CH1,I2C1_SCL,,,,,CAN1_RX,SDMMC2_D4,,SDMMC1_D4,,,EVENTOUT"
|
|
endif
|
|
elif cpuis("STM32F745V*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port B Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port B pin 7" ",,TIM4_CH2,,I2C1_SDA,,,USART1_RX,,,,I2S4_SDA,FMC_NL,DCMI_VSYNC,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port B pin 6" ",UART5_TX,TIM4_CH1,HDMICEC,I2C1_SCL,,,USART1_TX,,CAN2_TX,,I2C4_SCL,FMC_SDNE1,DCMI_D5,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port B pin 5" ",UART5_RX,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI/I2S1_SD,SPI3_MOSI/I2S3_SD,,,CAN2_RX,OTG_HS_ULPI_D7,ETH_PPS_OUT,FMC_SDCKE1,DCMI_D10,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port B pin 4" "NJTRST,TIM3_CH1,,,,SPI1_MISO,SPI3_MISO,SPI2_NSS/I2S2_WS,,,,,UART7_TX,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port B pin 3" "JTDO/TRACESWO,TIM2_CH2,,,,SPI1_SCK/I2S1_CK,SPI3_SCK/I2S3_CK,,,,,,UART7_RX,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port B pin 2" ",,,,,,SAI1_SD_A,SPI3_MOSI/I2S3_SD,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port B pin 1" ",TIM1_CH3N,TIM3_CH4,TIM8_CH3N,,,,,,,OTG_HS_ULPI_D2,ETH_MII_RXD3,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port B pin 0" ",TIM1_CH2N,TIM3_CH3,TIM8_CH2N,,,,,UART4_CTS,,OTG_HS_ULPI_D1,ETH_MII_RXD2,,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port B Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port B pin 15" "RTC_REFIN,TIM1_CH3N,,TIM8_CH3N,USART1_RX,SPI2_MOSI/I2S2_SD,,,UART4_CTS,TIM12_CH2,,,OTG_HS_DP,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port B pin 14" ",TIM1_CH2N,,TIM8_CH2N,USART1_TX,SPI2_MISO,,USART3_RTS,UART4_RTS,TIM12_CH1,,,OTG_HS_DM,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port B pin 13" ",TIM1_CH1N,,,,SPI2_SCK/I2S2_CK,,USART3_CTS,UART5_TX,CAN2_TX,OTG_HS_ULPI_D6,ETH_MII_TXD1/ETH_RMII_TXD1,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port B pin 12" ",TIM1_BKIN,,,I2C2_SMBA,SPI2_NSS/I2S2_WS,,USART3_CK,UART5_RX,CAN2_RX,OTG_HS_ULPI_D5,ETH_MII_TXD0/ETH_RMII_TXD0,OTG_HS_ID,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port B pin 11" ",TIM2_CH4,,,I2C2_SDA,,,USART3_RX,,,OTG_HS_ULPI_D4,ETH_MII_TX_EN/ETH_RMII_TX_EN,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port B pin 10" ",TIM2_CH3,,,I2C2_SCL,SPI2_SCK/I2S2_CK,,USART3_TX,,,OTG_HS_ULPI_D3,ETH_MII_RX_ER,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port B pin 9" ",I2S4_SDA,TIM4_CH4,TIM11_CH1,I2C1_SDA,SPI2_NSS/I2S2_WS,,UART5_TX,,CAN1_TX,,I2C4_SMBA,SDMMC_D5,DCMI_D7,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port B pin 8" ",I2C4_SCL,TIM4_CH3,TIM10_CH1,I2C1_SCL,,,UART5_RX,,CAN1_RX,,ETH_MII_TXD3,SDMMC_D4,DCMI_D6,,EVENTOUT"
|
|
elif cpuis("STM32F745*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port B Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port B pin 7" ",,TIM4_CH2,,I2C1_SDA,,,USART1_RX,,,,I2S4_SDA,FMC_NL,DCMI_VSYNC,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port B pin 6" ",UART5_TX,TIM4_CH1,HDMICEC,I2C1_SCL,,,USART1_TX,,CAN2_TX,,I2C4_SCL,FMC_SDNE1,DCMI_D5,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port B pin 5" ",UART5_RX,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI/I2S1_SD,SPI3_MOSI/I2S3_SD,,SPI6_MOSI,CAN2_RX,OTG_HS_ULPI_D7,ETH_PPS_OUT,FMC_SDCKE1,DCMI_D10,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port B pin 4" "NJTRST,TIM3_CH1,,,,SPI1_MISO,SPI3_MISO,SPI2_NSS/I2S2_WS,SPI6_MISO,,,,UART7_TX,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port B pin 3" "JTDO/TRACESWO,TIM2_CH2,,,,SPI1_SCK/I2S1_CK,SPI3_SCK/I2S3_CK,,SPI6_SCK,,,,UART7_RX,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port B pin 2" ",,,,,,SAI1_SD_A,SPI3_MOSI/I2S3_SD,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port B pin 1" ",TIM1_CH3N,TIM3_CH4,TIM8_CH3N,,,,,,,OTG_HS_ULPI_D2,ETH_MII_RXD3,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port B pin 0" ",TIM1_CH2N,TIM3_CH3,TIM8_CH2N,,,,,UART4_CTS,,OTG_HS_ULPI_D1,ETH_MII_RXD2,,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port B Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port B pin 15" "RTC_REFIN,TIM1_CH3N,,TIM8_CH3N,USART1_RX,SPI2_MOSI/I2S2_SD,,,UART4_CTS,TIM12_CH2,,,OTG_HS_DP,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port B pin 14" ",TIM1_CH2N,,TIM8_CH2N,USART1_TX,SPI2_MISO,,USART3_RTS,UART4_RTS,TIM12_CH1,,,OTG_HS_DM,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port B pin 13" ",TIM1_CH1N,,,,SPI2_SCK/I2S2_CK,,USART3_CTS,UART5_TX,CAN2_TX,OTG_HS_ULPI_D6,ETH_MII_TXD1/ETH_RMII_TXD1,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port B pin 12" ",TIM1_BKIN,,,I2C2_SMBA,SPI2_NSS/I2S2_WS,,USART3_CK,UART5_RX,CAN2_RX,OTG_HS_ULPI_D5,ETH_MII_TXD0/ETH_RMII_TXD0,OTG_HS_ID,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port B pin 11" ",TIM2_CH4,,,I2C2_SDA,,,USART3_RX,,,OTG_HS_ULPI_D4,ETH_MII_TX_EN/ETH_RMII_TX_EN,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port B pin 10" ",TIM2_CH3,,,I2C2_SCL,SPI2_SCK/I2S2_CK,,USART3_TX,,,OTG_HS_ULPI_D3,ETH_MII_RX_ER,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port B pin 9" ",I2S4_SDA,TIM4_CH4,TIM11_CH1,I2C1_SDA,SPI2_NSS/I2S2_WS,,UART5_TX,,CAN1_TX,,I2C4_SMBA,SDMMC_D5,DCMI_D7,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port B pin 8" ",I2C4_SCL,TIM4_CH3,TIM10_CH1,I2C1_SCL,,,UART5_RX,,CAN1_RX,,ETH_MII_TXD3,SDMMC_D4,DCMI_D6,,EVENTOUT"
|
|
elif cpuis("STM32F750*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port B Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port B pin 7" ",,TIM4_CH2,,I2C1_SDA,,,USART1_RX,,,,,FMC_NL,DCMI_VSYNC,,EVENTOUT"
|
|
sif cpuis("STM32F750V*")
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port B pin 6" ",,TIM4_CH1,HDMICEC,I2C1_SCL,,,USART1_TX,,CAN2_TX,QUADSPI_BK1_NCS,,,DCMI_D5,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port B pin 5" ",,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI/I2S1_SD,SPI3_MOSI/I2S3_SD,,,CAN2_RX,OTG_HS_ULPI_D7,ETH_PPS_OUT,,DCMI_D10,,EVENTOUT"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port B pin 6" ",,TIM4_CH1,HDMICEC,I2C1_SCL,,,USART1_TX,,CAN2_TX,QUADSPI_BK1_NCS,,FMC_SDNE1,DCMI_D5,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port B pin 5" ",,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI/I2S1_SD,SPI3_MOSI/I2S3_SD,,,CAN2_RX,OTG_HS_ULPI_D7,ETH_PPS_OUT,FMC_SDCKE1,DCMI_D10,,EVENTOUT"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port B pin 4" "NJTRST,TIM3_CH1,,,,SPI1_MISO,SPI3_MISO,SPI2_NSS/I2S2_WS,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port B pin 3" "JTDO/TRACESWO,TIM2_CH2,,,,SPI1_SCK/I2S1_CK,SPI3_SCK/I2S3_CK,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port B pin 2" ",,,,,,SAI1_SD_A,SPI3_MOSI/I2S3_SD,,QUADSPI_CLK,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port B pin 1" ",TIM1_CH3N,TIM3_CH4,TIM8_CH3N,,,,,,LCD_R6,OTG_HS_ULPI_D2,ETH_MII_RXD3,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port B pin 0" ",TIM1_CH2N,TIM3_CH3,TIM8_CH2N,,,,,UART4_CTS,LCD_R3,OTG_HS_ULPI_D1,ETH_MII_RXD2,,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port B Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port B pin 15" "RTC_REFIN,TIM1_CH3N,,TIM8_CH3N,,SPI2_MOSI/I2S2_SD,,,,TIM12_CH2,,,OTG_HS_DP,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port B pin 14" ",TIM1_CH2N,,TIM8_CH2N,,SPI2_MISO,,USART3_RTS,,TIM12_CH1,,,OTG_HS_DM,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port B pin 13" ",TIM1_CH1N,,,,SPI2_SCK/I2S2_CK,,USART3_CTS,,CAN2_TX,OTG_HS_ULPI_D6,ETH_MII_TXD1/ETH_RMII_TXD1,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port B pin 12" ",TIM1_BKIN,,,I2C2_SMBA,SPI2_NSS/I2S2_WS,,USART3_CK,UART5_RX,CAN2_RX,OTG_HS_ULPI_D5,ETH_MII_TXD0/ETH_RMII_TXD0,OTG_HS_ID,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port B pin 11" ",TIM2_CH4,,,I2C2_SDA,,,USART3_RX,,,OTG_HS_ULPI_D4,ETH_MII_TX_EN/ETH_RMII_TX_EN,,,LCD_G5,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port B pin 10" ",TIM2_CH3,,,I2C2_SCL,SPI2_SCK/I2S2_CK,,USART3_TX,,,OTG_HS_ULPI_D3,ETH_MII_RX_ER,,,LCD_G4,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port B pin 9" ",,TIM4_CH4,TIM11_CH1,I2C1_SDA,SPI2_NSS/I2S2_WS,,,,CAN1_TX,,,SDMMC1_D5,DCMI_D7,LCD_B7,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port B pin 8" ",,TIM4_CH3,TIM10_CH1,I2C1_SCL,,,,,CAN1_RX,,ETH_MII_TXD3,SDMMC_D4,DCMI_D6,LCD_B6,EVENTOUT"
|
|
elif cpuis("STM32F746V*")||cpuis("STM32F756V*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port B Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port B pin 7" ",,TIM4_CH2,,I2C1_SDA,,,USART1_RX,,,,I2S4_SDA,FMC_NL,DCMI_VSYNC,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port B pin 6" ",UART5_TX,TIM4_CH1,HDMICEC,I2C1_SCL,,,USART1_TX,,CAN2_TX,,I2C4_SCL,FMC_SDNE1,DCMI_D5,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port B pin 5" ",UART5_RX,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI/I2S1_SD,SPI3_MOSI/I2S3_SD,,,CAN2_RX,OTG_HS_ULPI_D7,ETH_PPS_OUT,FMC_SDCKE1,DCMI_D10,LCD_G7,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port B pin 4" "NJTRST,TIM3_CH1,,,,SPI1_MISO,SPI3_MISO,SPI2_NSS/I2S2_WS,,,,,UART7_TX,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port B pin 3" "JTDO/TRACESWO,TIM2_CH2,,,,SPI1_SCK/I2S1_CK,SPI3_SCK/I2S3_CK,,,,,,UART7_RX,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port B pin 2" ",,,,,,SAI1_SD_A,SPI3_MOSI/I2S3_SD,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port B pin 1" ",TIM1_CH3N,TIM3_CH4,TIM8_CH3N,,,,,,LCD_R6,OTG_HS_ULPI_D2,ETH_MII_RXD3,,,LCD_G0,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port B pin 0" ",TIM1_CH2N,TIM3_CH3,TIM8_CH2N,,,,,UART4_CTS,LCD_R3,OTG_HS_ULPI_D1,ETH_MII_RXD2,,,LCD_G1,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port B Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port B pin 15" "RTC_REFIN,TIM1_CH3N,,TIM8_CH3N,USART1_RX,SPI2_MOSI/I2S2_SD,,,UART4_CTS,TIM12_CH2,,,OTG_HS_DP,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port B pin 14" ",TIM1_CH2N,,TIM8_CH2N,USART1_TX,SPI2_MISO,,USART3_RTS,UART4_RTS,TIM12_CH1,,,OTG_HS_DM,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port B pin 13" ",TIM1_CH1N,,,,SPI2_SCK/I2S2_CK,,USART3_CTS,UART5_TX,CAN2_TX,OTG_HS_ULPI_D6,ETH_MII_TXD1/ETH_RMII_TXD1,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port B pin 12" ",TIM1_BKIN,,,I2C2_SMBA,SPI2_NSS/I2S2_WS,,USART3_CK,UART5_RX,CAN2_RX,OTG_HS_ULPI_D5,ETH_MII_TXD0/ETH_RMII_TXD0,OTG_HS_ID,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port B pin 11" ",TIM2_CH4,,,I2C2_SDA,,,USART3_RX,,,OTG_HS_ULPI_D4,ETH_MII_TX_EN/ETH_RMII_TX_EN,,,LCD_G5,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port B pin 10" ",TIM2_CH3,,,I2C2_SCL,SPI2_SCK/I2S2_CK,,USART3_TX,,,OTG_HS_ULPI_D3,ETH_MII_RX_ER,,,LCD_G4,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port B pin 9" ",I2S4_SDA,TIM4_CH4,TIM11_CH1,I2C1_SDA,SPI2_NSS/I2S2_WS,,UART5_TX,,CAN1_TX,,I2C4_SMBA,SDMMC_D5,DCMI_D7,LCD_B7,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port B pin 8" ",I2C4_SCL,TIM4_CH3,TIM10_CH1,I2C1_SCL,,,UART5_RX,,CAN1_RX,,ETH_MII_TXD3,SDMMC_D4,DCMI_D6,LCD_B6,EVENTOUT"
|
|
elif cpuis("STM32F746*")||cpuis("STM32F756*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port B Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port B pin 7" ",,TIM4_CH2,,I2C1_SDA,,,USART1_RX,,,,I2S4_SDA,FMC_NL,DCMI_VSYNC,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port B pin 6" ",UART5_TX,TIM4_CH1,HDMICEC,I2C1_SCL,,,USART1_TX,,CAN2_TX,,I2C4_SCL,FMC_SDNE1,DCMI_D5,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port B pin 5" ",UART5_RX,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI/I2S1_SD,SPI3_MOSI/I2S3_SD,,SPI6_MOSI,CAN2_RX,OTG_HS_ULPI_D7,ETH_PPS_OUT,FMC_SDCKE1,DCMI_D10,LCD_G7,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port B pin 4" "NJTRST,TIM3_CH1,,,,SPI1_MISO,SPI3_MISO,SPI2_NSS/I2S2_WS,SPI6_MISO,,,,UART7_TX,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port B pin 3" "JTDO/TRACESWO,TIM2_CH2,,,,SPI1_SCK/I2S1_CK,SPI3_SCK/I2S3_CK,,SPI6_SCK,,,,UART7_RX,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port B pin 2" ",,,,,,SAI1_SD_A,SPI3_MOSI/I2S3_SD,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port B pin 1" ",TIM1_CH3N,TIM3_CH4,TIM8_CH3N,,,,,,LCD_R6,OTG_HS_ULPI_D2,ETH_MII_RXD3,,,LCD_G0,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port B pin 0" ",TIM1_CH2N,TIM3_CH3,TIM8_CH2N,,,,,UART4_CTS,LCD_R3,OTG_HS_ULPI_D1,ETH_MII_RXD2,,,LCD_G1,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port B Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port B pin 15" "RTC_REFIN,TIM1_CH3N,,TIM8_CH3N,USART1_RX,SPI2_MOSI/I2S2_SD,,,UART4_CTS,TIM12_CH2,,,OTG_HS_DP,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port B pin 14" ",TIM1_CH2N,,TIM8_CH2N,USART1_TX,SPI2_MISO,,USART3_RTS,UART4_RTS,TIM12_CH1,,,OTG_HS_DM,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port B pin 13" ",TIM1_CH1N,,,,SPI2_SCK/I2S2_CK,,USART3_CTS,UART5_TX,CAN2_TX,OTG_HS_ULPI_D6,ETH_MII_TXD1/ETH_RMII_TXD1,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port B pin 12" ",TIM1_BKIN,,,I2C2_SMBA,SPI2_NSS/I2S2_WS,,USART3_CK,UART5_RX,CAN2_RX,OTG_HS_ULPI_D5,ETH_MII_TXD0/ETH_RMII_TXD0,OTG_HS_ID,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port B pin 11" ",TIM2_CH4,,,I2C2_SDA,,,USART3_RX,,,OTG_HS_ULPI_D4,ETH_MII_TX_EN/ETH_RMII_TX_EN,,,LCD_G5,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port B pin 10" ",TIM2_CH3,,,I2C2_SCL,SPI2_SCK/I2S2_CK,,USART3_TX,,,OTG_HS_ULPI_D3,ETH_MII_RX_ER,,,LCD_G4,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port B pin 9" ",I2S4_SDA,TIM4_CH4,TIM11_CH1,I2C1_SDA,SPI2_NSS/I2S2_WS,,UART5_TX,,CAN1_TX,,I2C4_SMBA,SDMMC_D5,DCMI_D7,LCD_B7,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port B pin 8" ",I2C4_SCL,TIM4_CH3,TIM10_CH1,I2C1_SCL,,,UART5_RX,,CAN1_RX,,ETH_MII_TXD3,SDMMC_D4,DCMI_D6,LCD_B6,EVENTOUT"
|
|
elif cpuis("STM32F765V*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port B Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port B pin 7" ",,TIM4_CH2,,I2C1_SDA,,DFSDM1_CKIN5,USART1_RX,,,,I2S4_SDA,FMC_NL,DCMI_VSYNC,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port B pin 6" ",UART5_TX,TIM4_CH1,HDMICEC,I2C1_SCL,,DFSDM1_DATIN5,USART1_TX,,CAN2_TX,QUADSPI_BK1_NCS,I2C4_SCL,FMC_SDNE1,DCMI_D5,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port B pin 5" ",UART5_RX,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI/I2S1_SD,SPI3_MOSI/I2S3_SD,,,CAN2_RX,OTG_HS_ULPI_D7,ETH_PPS_OUT,FMC_SDCKE1,DCMI_D10,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port B pin 4" "NJTRST,TIM3_CH1,,,,SPI1_MISO,SPI3_MISO,SPI2_NSS/I2S2_WS,,,,CAN3_TX,UART7_TX,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port B pin 3" "JTDO/TRACESWO,TIM2_CH2,,,,SPI1_SCK/I2S1_CK,SPI3_SCK/I2S3_CK,,,,,CAN3_RX,UART7_RX,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port B pin 2" ",,,,,,SAI1_SD_A,SPI3_MOSI/I2S3_SD,,QUADSPI_CLK,DFSDM1_CKIN1,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port B pin 1" ",TIM1_CH3N,TIM3_CH4,TIM8_CH3N,,,DFSDM1_DATIN1,,,,OTG_HS_ULPI_D2,ETH_MII_RXD3,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port B pin 0" ",TIM1_CH2N,TIM3_CH3,TIM8_CH2N,,,DFSDM1_CKOUT,,UART4_CTS,,OTG_HS_ULPI_D1,ETH_MII_RXD2,,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port B Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port B pin 15" "RTC_REFIN,TIM1_CH3N,,TIM8_CH3N,USART1_RX,SPI2_MOSI/I2S2_SD,DFSDM1_CKIN2,,UART4_CTS,TIM12_CH2,,,OTG_HS_DP,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port B pin 14" ",TIM1_CH2N,,TIM8_CH2N,USART1_TX,SPI2_MISO,DFSDM1_DATIN2,USART3_RTS,UART4_RTS,TIM12_CH1,,,OTG_HS_DM,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port B pin 13" ",TIM1_CH1N,,,,SPI2_SCK/I2S2_CK,DFSDM1_CKIN1,USART3_CTS,UART5_TX,CAN2_TX,OTG_HS_ULPI_D6,ETH_MII_TXD1/ETH_RMII_TXD1,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port B pin 12" ",TIM1_BKIN,,,I2C2_SMBA,SPI2_NSS/I2S2_WS,DFSDM1_DATIN1,USART3_CK,UART5_RX,CAN2_RX,OTG_HS_ULPI_D5,ETH_MII_TXD0/ETH_RMII_TXD0,OTG_HS_ID,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port B pin 11" ",TIM2_CH4,,,I2C2_SDA,,DFSDM1_CKIN7,USART3_RX,,,OTG_HS_ULPI_D4,ETH_MII_TX_EN/ETH_RMII_TX_EN,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port B pin 10" ",TIM2_CH3,,,I2C2_SCL,SPI2_SCK/I2S2_CK,DFSDM1_DATIN7,USART3_TX,,QUADSPI_BK1_NCS,OTG_HS_ULPI_D3,ETH_MII_RX_ER,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port B pin 9" ",I2S4_SDA,TIM4_CH4,TIM11_CH1,I2C1_SDA,SPI2_NSS/I2S2_WS,DFSDM1_DATIN7,UART5_TX,,CAN1_TX,,I2C4_SMBA,SDMMC_D5,DCMI_D7,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port B pin 8" ",I2C4_SCL,TIM4_CH3,TIM10_CH1,I2C1_SCL,,DFSDM1_CKIN7,UART5_RX,,CAN1_RX,,ETH_MII_TXD3,SDMMC_D4,DCMI_D6,,EVENTOUT"
|
|
elif cpuis("STM32F765*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port B Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port B pin 7" ",,TIM4_CH2,,I2C1_SDA,,DFSDM1_CKIN5,USART1_RX,,,,I2S4_SDA,FMC_NL,DCMI_VSYNC,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port B pin 6" ",UART5_TX,TIM4_CH1,HDMICEC,I2C1_SCL,,DFSDM1_DATIN5,USART1_TX,,CAN2_TX,QUADSPI_BK1_NCS,I2C4_SCL,FMC_SDNE1,DCMI_D5,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port B pin 5" ",UART5_RX,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI/I2S1_SD,SPI3_MOSI/I2S3_SD,,SPI6_MOSI,CAN2_RX,OTG_HS_ULPI_D7,ETH_PPS_OUT,FMC_SDCKE1,DCMI_D10,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port B pin 4" "NJTRST,TIM3_CH1,,,,SPI1_MISO,SPI3_MISO,SPI2_NSS/I2S2_WS,SPI6_MISO,,,CAN3_TX,UART7_TX,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port B pin 3" "JTDO/TRACESWO,TIM2_CH2,,,,SPI1_SCK/I2S1_CK,SPI3_SCK/I2S3_CK,,SPI6_SCK,,,CAN3_RX,UART7_RX,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port B pin 2" ",,,,,,SAI1_SD_A,SPI3_MOSI/I2S3_SD,,QUADSPI_CLK,DFSDM1_CKIN1,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port B pin 1" ",TIM1_CH3N,TIM3_CH4,TIM8_CH3N,,,DFSDM1_DATIN1,,,,OTG_HS_ULPI_D2,ETH_MII_RXD3,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port B pin 0" ",TIM1_CH2N,TIM3_CH3,TIM8_CH2N,,,DFSDM1_CKOUT,,UART4_CTS,,OTG_HS_ULPI_D1,ETH_MII_RXD2,,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port B Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port B pin 15" "RTC_REFIN,TIM1_CH3N,,TIM8_CH3N,USART1_RX,SPI2_MOSI/I2S2_SD,DFSDM1_CKIN2,,UART4_CTS,TIM12_CH2,,,OTG_HS_DP,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port B pin 14" ",TIM1_CH2N,,TIM8_CH2N,USART1_TX,SPI2_MISO,DFSDM1_DATIN2,USART3_RTS,UART4_RTS,TIM12_CH1,,,OTG_HS_DM,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port B pin 13" ",TIM1_CH1N,,,,SPI2_SCK/I2S2_CK,DFSDM1_CKIN1,USART3_CTS,UART5_TX,CAN2_TX,OTG_HS_ULPI_D6,ETH_MII_TXD1/ETH_RMII_TXD1,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port B pin 12" ",TIM1_BKIN,,,I2C2_SMBA,SPI2_NSS/I2S2_WS,DFSDM1_DATIN1,USART3_CK,UART5_RX,CAN2_RX,OTG_HS_ULPI_D5,ETH_MII_TXD0/ETH_RMII_TXD0,OTG_HS_ID,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port B pin 11" ",TIM2_CH4,,,I2C2_SDA,,DFSDM1_CKIN7,USART3_RX,,,OTG_HS_ULPI_D4,ETH_MII_TX_EN/ETH_RMII_TX_EN,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port B pin 10" ",TIM2_CH3,,,I2C2_SCL,SPI2_SCK/I2S2_CK,DFSDM1_DATIN7,USART3_TX,,QUADSPI_BK1_NCS,OTG_HS_ULPI_D3,ETH_MII_RX_ER,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port B pin 9" ",I2S4_SDA,TIM4_CH4,TIM11_CH1,I2C1_SDA,SPI2_NSS/I2S2_WS,DFSDM1_DATIN7,UART5_TX,,CAN1_TX,,I2C4_SMBA,SDMMC_D5,DCMI_D7,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port B pin 8" ",I2C4_SCL,TIM4_CH3,TIM10_CH1,I2C1_SCL,,DFSDM1_CKIN7,UART5_RX,,CAN1_RX,,ETH_MII_TXD3,SDMMC_D4,DCMI_D6,,EVENTOUT"
|
|
elif cpuis("STM32F767V*")||cpuis("STM32F769V*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port B Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port B pin 7" ",,TIM4_CH2,,I2C1_SDA,,DFSDM1_CKIN5,USART1_RX,,,,I2S4_SDA,FMC_NL,DCMI_VSYNC,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port B pin 6" ",UART5_TX,TIM4_CH1,HDMICEC,I2C1_SCL,,DFSDM1_DATIN5,USART1_TX,,CAN2_TX,QUADSPI_BK1_NCS,I2C4_SCL,FMC_SDNE1,DCMI_D5,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port B pin 5" ",UART5_RX,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI/I2S1_SD,SPI3_MOSI/I2S3_SD,,,CAN2_RX,OTG_HS_ULPI_D7,ETH_PPS_OUT,FMC_SDCKE1,DCMI_D10,LCD_G7,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port B pin 4" "NJTRST,TIM3_CH1,,,,SPI1_MISO,SPI3_MISO,SPI2_NSS/I2S2_WS,,,,CAN3_TX,UART7_TX,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port B pin 3" "JTDO/TRACESWO,TIM2_CH2,,,,SPI1_SCK/I2S1_CK,SPI3_SCK/I2S3_CK,,,,,CAN3_RX,UART7_RX,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port B pin 2" ",,,,,,SAI1_SD_A,SPI3_MOSI/I2S3_SD,,QUADSPI_CLK,DFSDM1_CKIN1,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port B pin 1" ",TIM1_CH3N,TIM3_CH4,TIM8_CH3N,,,DFSDM1_DATIN1,,,LCD_R6,OTG_HS_ULPI_D2,ETH_MII_RXD3,,,LCD_G0,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port B pin 0" ",TIM1_CH2N,TIM3_CH3,TIM8_CH2N,,,DFSDM1_CKOUT,,UART4_CTS,LCD_R3,OTG_HS_ULPI_D1,ETH_MII_RXD2,,,LCD_G1,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port B Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port B pin 15" "RTC_REFIN,TIM1_CH3N,,TIM8_CH3N,USART1_RX,SPI2_MOSI/I2S2_SD,DFSDM1_CKIN2,,UART4_CTS,TIM12_CH2,,,OTG_HS_DP,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port B pin 14" ",TIM1_CH2N,,TIM8_CH2N,USART1_TX,SPI2_MISO,DFSDM1_DATIN2,USART3_RTS,UART4_RTS,TIM12_CH1,,,OTG_HS_DM,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port B pin 13" ",TIM1_CH1N,,,,SPI2_SCK/I2S2_CK,DFSDM1_CKIN1,USART3_CTS,UART5_TX,CAN2_TX,OTG_HS_ULPI_D6,ETH_MII_TXD1/ETH_RMII_TXD1,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port B pin 12" ",TIM1_BKIN,,,I2C2_SMBA,SPI2_NSS/I2S2_WS,DFSDM1_DATIN1,USART3_CK,UART5_RX,CAN2_RX,OTG_HS_ULPI_D5,ETH_MII_TXD0/ETH_RMII_TXD0,OTG_HS_ID,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port B pin 11" ",TIM2_CH4,,,I2C2_SDA,,DFSDM1_CKIN7,USART3_RX,,,OTG_HS_ULPI_D4,ETH_MII_TX_EN/ETH_RMII_TX_EN,,,LCD_G5,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port B pin 10" ",TIM2_CH3,,,I2C2_SCL,SPI2_SCK/I2S2_CK,DFSDM1_DATIN7,USART3_TX,,QUADSPI_BK1_NCS,OTG_HS_ULPI_D3,ETH_MII_RX_ER,,,LCD_G4,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port B pin 9" ",I2S4_SDA,TIM4_CH4,TIM11_CH1,I2C1_SDA,SPI2_NSS/I2S2_WS,DFSDM1_DATIN7,UART5_TX,,CAN1_TX,,I2C4_SMBA,SDMMC_D5,DCMI_D7,LCD_B7,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port B pin 8" ",I2C4_SCL,TIM4_CH3,TIM10_CH1,I2C1_SCL,,DFSDM1_CKIN7,UART5_RX,,CAN1_RX,,ETH_MII_TXD3,SDMMC_D4,DCMI_D6,LCD_B6,EVENTOUT"
|
|
elif cpuis("STM32F777V*")||cpuis("STM32F778V*")||cpuis("STM32F779V*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port B Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port B pin 7" ",,TIM4_CH2,,I2C1_SDA,,DFSDM1_CKIN5,USART1_RX,,,,I2S4_SDA,FMC_NL,DCMI_VSYNC,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port B pin 6" ",UART5_TX,TIM4_CH1,HDMICEC,I2C1_SCL,,DFSDM1_DATIN5,USART1_TX,,CAN2_TX,QUADSPI_BK1_NCS,I2C4_SCL,FMC_SDNE1,DCMI_D5,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port B pin 5" ",UART5_RX,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI/I2S1_SD,SPI3_MOSI/I2S3_SD,,,CAN2_RX,OTG_HS_ULPI_D7,ETH_PPS_OUT,FMC_SDCKE1,DCMI_D10,LCD_G7,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port B pin 4" "NJTRST,TIM3_CH1,,,,SPI1_MISO,SPI3_MISO,SPI2_NSS/I2S2_WS,,,SDMMC2_D3,CAN3_TX,UART7_TX,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port B pin 3" "JTDO/TRACESWO,TIM2_CH2,,,,SPI1_SCK/I2S1_CK,SPI3_SCK/I2S3_CK,,,,SDMMC2_D2,CAN3_RX,UART7_RX,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port B pin 2" ",,,,,,SAI1_SD_A,SPI3_MOSI/I2S3_SD,,QUADSPI_CLK,DFSDM1_CKIN1,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port B pin 1" ",TIM1_CH3N,TIM3_CH4,TIM8_CH3N,,,DFSDM1_DATIN1,,,LCD_R6,OTG_HS_ULPI_D2,ETH_MII_RXD3,,,LCD_G0,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port B pin 0" ",TIM1_CH2N,TIM3_CH3,TIM8_CH2N,,,DFSDM1_CKOUT,,UART4_CTS,LCD_R3,OTG_HS_ULPI_D1,ETH_MII_RXD2,,,LCD_G1,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port B Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port B pin 15" "RTC_REFIN,TIM1_CH3N,,TIM8_CH3N,USART1_RX,SPI2_MOSI/I2S2_SD,DFSDM1_CKIN2,,UART4_CTS,TIM12_CH2,SDMMC2_D1,,OTG_HS_DP,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port B pin 14" ",TIM1_CH2N,,TIM8_CH2N,USART1_TX,SPI2_MISO,DFSDM1_DATIN2,USART3_RTS,UART4_RTS,TIM12_CH1,SDMMC2_D0,,OTG_HS_DM,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port B pin 13" ",TIM1_CH1N,,,,SPI2_SCK/I2S2_CK,DFSDM1_CKIN1,USART3_CTS,UART5_TX,CAN2_TX,OTG_HS_ULPI_D6,ETH_MII_TXD1/ETH_RMII_TXD1,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port B pin 12" ",TIM1_BKIN,,,I2C2_SMBA,SPI2_NSS/I2S2_WS,DFSDM1_DATIN1,USART3_CK,UART5_RX,CAN2_RX,OTG_HS_ULPI_D5,ETH_MII_TXD0/ETH_RMII_TXD0,OTG_HS_ID,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port B pin 11" ",TIM2_CH4,,,I2C2_SDA,,DFSDM1_CKIN7,USART3_RX,,,OTG_HS_ULPI_D4,ETH_MII_TX_EN/ETH_RMII_TX_EN,,,LCD_G5,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port B pin 10" ",TIM2_CH3,,,I2C2_SCL,SPI2_SCK/I2S2_CK,DFSDM1_DATIN7,USART3_TX,,QUADSPI_BK1_NCS,OTG_HS_ULPI_D3,ETH_MII_RX_ER,,,LCD_G4,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port B pin 9" ",I2S4_SDA,TIM4_CH4,TIM11_CH1,I2C1_SDA,SPI2_NSS/I2S2_WS,DFSDM1_DATIN7,UART5_TX,,CAN1_TX,SDMMC2_D5,I2C4_SMBA,SDMMC_D5,DCMI_D7,LCD_B7,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port B pin 8" ",I2C4_SCL,TIM4_CH3,TIM10_CH1,I2C1_SCL,,DFSDM1_CKIN7,UART5_RX,,CAN1_RX,SDMMC2_D4,ETH_MII_TXD3,SDMMC_D4,DCMI_D6,LCD_B6,EVENTOUT"
|
|
elif cpuis("STM32F767Z*")||cpuis("STM32F769Z*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port B Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port B pin 7" ",,TIM4_CH2,,I2C1_SDA,,DFSDM1_CKIN5,USART1_RX,,,,I2S4_SDA,FMC_NL,DCMI_VSYNC,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port B pin 6" ",UART5_TX,TIM4_CH1,HDMICEC,I2C1_SCL,,DFSDM1_DATIN5,USART1_TX,,CAN2_TX,QUADSPI_BK1_NCS,I2C4_SCL,FMC_SDNE1,DCMI_D5,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port B pin 5" ",UART5_RX,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI/I2S1_SD,SPI3_MOSI/I2S3_SD,,SPI6_MOSI,CAN2_RX,OTG_HS_ULPI_D7,ETH_PPS_OUT,FMC_SDCKE1,DCMI_D10,LCD_G7,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port B pin 4" "NJTRST,TIM3_CH1,,,,SPI1_MISO,SPI3_MISO,SPI2_NSS/I2S2_WS,SPI6_MISO,,,CAN3_TX,UART7_TX,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port B pin 3" "JTDO/TRACESWO,TIM2_CH2,,,,SPI1_SCK/I2S1_CK,SPI3_SCK/I2S3_CK,,SPI6_SCK,,,CAN3_RX,UART7_RX,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port B pin 2" ",,,,,,SAI1_SD_A,SPI3_MOSI/I2S3_SD,,QUADSPI_CLK,DFSDM1_CKIN1,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port B pin 1" ",TIM1_CH3N,TIM3_CH4,TIM8_CH3N,,,DFSDM1_DATIN1,,,LCD_R6,OTG_HS_ULPI_D2,ETH_MII_RXD3,,,LCD_G0,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port B pin 0" ",TIM1_CH2N,TIM3_CH3,TIM8_CH2N,,,DFSDM1_CKOUT,,UART4_CTS,LCD_R3,OTG_HS_ULPI_D1,ETH_MII_RXD2,,,LCD_G1,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port B Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port B pin 15" "RTC_REFIN,TIM1_CH3N,,TIM8_CH3N,USART1_RX,SPI2_MOSI/I2S2_SD,DFSDM1_CKIN2,,UART4_CTS,TIM12_CH2,,,OTG_HS_DP,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port B pin 14" ",TIM1_CH2N,,TIM8_CH2N,USART1_TX,SPI2_MISO,DFSDM1_DATIN2,USART3_RTS,UART4_RTS,TIM12_CH1,,,OTG_HS_DM,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port B pin 13" ",TIM1_CH1N,,,,SPI2_SCK/I2S2_CK,DFSDM1_CKIN1,USART3_CTS,UART5_TX,CAN2_TX,OTG_HS_ULPI_D6,ETH_MII_TXD1/ETH_RMII_TXD1,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port B pin 12" ",TIM1_BKIN,,,I2C2_SMBA,SPI2_NSS/I2S2_WS,DFSDM1_DATIN1,USART3_CK,UART5_RX,CAN2_RX,OTG_HS_ULPI_D5,ETH_MII_TXD0/ETH_RMII_TXD0,OTG_HS_ID,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port B pin 11" ",TIM2_CH4,,,I2C2_SDA,,DFSDM1_CKIN7,USART3_RX,,,OTG_HS_ULPI_D4,ETH_MII_TX_EN/ETH_RMII_TX_EN,,,LCD_G5,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port B pin 10" ",TIM2_CH3,,,I2C2_SCL,SPI2_SCK/I2S2_CK,DFSDM1_DATIN7,USART3_TX,,QUADSPI_BK1_NCS,OTG_HS_ULPI_D3,ETH_MII_RX_ER,,,LCD_G4,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port B pin 9" ",I2S4_SDA,TIM4_CH4,TIM11_CH1,I2C1_SDA,SPI2_NSS/I2S2_WS,DFSDM1_DATIN7,UART5_TX,,CAN1_TX,,I2C4_SMBA,SDMMC_D5,DCMI_D7,LCD_B7,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port B pin 8" ",I2C4_SCL,TIM4_CH3,TIM10_CH1,I2C1_SCL,,DFSDM1_CKIN7,UART5_RX,,CAN1_RX,,ETH_MII_TXD3,SDMMC_D4,DCMI_D6,LCD_B6,EVENTOUT"
|
|
elif cpuis("STM32F777Z*")||cpuis("STM32F778Z*")||cpuis("STM32F779Z*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port B Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port B pin 7" ",,TIM4_CH2,,I2C1_SDA,,DFSDM1_CKIN5,USART1_RX,,,,I2S4_SDA,FMC_NL,DCMI_VSYNC,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port B pin 6" ",UART5_TX,TIM4_CH1,HDMICEC,I2C1_SCL,,DFSDM1_DATIN5,USART1_TX,,CAN2_TX,QUADSPI_BK1_NCS,I2C4_SCL,FMC_SDNE1,DCMI_D5,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port B pin 5" ",UART5_RX,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI/I2S1_SD,SPI3_MOSI/I2S3_SD,,SPI6_MOSI,CAN2_RX,OTG_HS_ULPI_D7,ETH_PPS_OUT,FMC_SDCKE1,DCMI_D10,LCD_G7,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port B pin 4" "NJTRST,TIM3_CH1,,,,SPI1_MISO,SPI3_MISO,SPI2_NSS/I2S2_WS,SPI6_MISO,,SDMMC2_D3,CAN3_TX,UART7_TX,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port B pin 3" "JTDO/TRACESWO,TIM2_CH2,,,,SPI1_SCK/I2S1_CK,SPI3_SCK/I2S3_CK,,SPI6_SCK,,SDMMC2_D2,CAN3_RX,UART7_RX,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port B pin 2" ",,,,,,SAI1_SD_A,SPI3_MOSI/I2S3_SD,,QUADSPI_CLK,DFSDM1_CKIN1,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port B pin 1" ",TIM1_CH3N,TIM3_CH4,TIM8_CH3N,,,DFSDM1_DATIN1,,,LCD_R6,OTG_HS_ULPI_D2,ETH_MII_RXD3,,,LCD_G0,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port B pin 0" ",TIM1_CH2N,TIM3_CH3,TIM8_CH2N,,,DFSDM1_CKOUT,,UART4_CTS,LCD_R3,OTG_HS_ULPI_D1,ETH_MII_RXD2,,,LCD_G1,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port B Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port B pin 15" "RTC_REFIN,TIM1_CH3N,,TIM8_CH3N,USART1_RX,SPI2_MOSI/I2S2_SD,DFSDM1_CKIN2,,UART4_CTS,TIM12_CH2,SDMMC2_D1,,OTG_HS_DP,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port B pin 14" ",TIM1_CH2N,,TIM8_CH2N,USART1_TX,SPI2_MISO,DFSDM1_DATIN2,USART3_RTS,UART4_RTS,TIM12_CH1,SDMMC2_D0,,OTG_HS_DM,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port B pin 13" ",TIM1_CH1N,,,,SPI2_SCK/I2S2_CK,DFSDM1_CKIN1,USART3_CTS,UART5_TX,CAN2_TX,OTG_HS_ULPI_D6,ETH_MII_TXD1/ETH_RMII_TXD1,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port B pin 12" ",TIM1_BKIN,,,I2C2_SMBA,SPI2_NSS/I2S2_WS,DFSDM1_DATIN1,USART3_CK,UART5_RX,CAN2_RX,OTG_HS_ULPI_D5,ETH_MII_TXD0/ETH_RMII_TXD0,OTG_HS_ID,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port B pin 11" ",TIM2_CH4,,,I2C2_SDA,,DFSDM1_CKIN7,USART3_RX,,,OTG_HS_ULPI_D4,ETH_MII_TX_EN/ETH_RMII_TX_EN,,,LCD_G5,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port B pin 10" ",TIM2_CH3,,,I2C2_SCL,SPI2_SCK/I2S2_CK,DFSDM1_DATIN7,USART3_TX,,QUADSPI_BK1_NCS,OTG_HS_ULPI_D3,ETH_MII_RX_ER,,,LCD_G4,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port B pin 9" ",I2S4_SDA,TIM4_CH4,TIM11_CH1,I2C1_SDA,SPI2_NSS/I2S2_WS,DFSDM1_DATIN7,UART5_TX,,CAN1_TX,SDMMC2_D5,I2C4_SMBA,SDMMC_D5,DCMI_D7,LCD_B7,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port B pin 8" ",I2C4_SCL,TIM4_CH3,TIM10_CH1,I2C1_SCL,,DFSDM1_CKIN7,UART5_RX,,CAN1_RX,SDMMC2_D4,ETH_MII_TXD3,SDMMC_D4,DCMI_D6,LCD_B6,EVENTOUT"
|
|
elif cpuis("STM32F768A*")||cpuis("STM32F769A*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port B Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port B pin 7" ",,TIM4_CH2,,I2C1_SDA,,DFSDM1_CKIN5,USART1_RX,,,,I2S4_SDA,FMC_NL,DCMI_VSYNC,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port B pin 6" ",UART5_TX,TIM4_CH1,HDMICEC,I2C1_SCL,,DFSDM1_DATIN5,USART1_TX,,CAN2_TX,QUADSPI_BK1_NCS,I2C4_SCL,FMC_SDNE1,DCMI_D5,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port B pin 5" ",UART5_RX,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI/I2S1_SD,SPI3_MOSI/I2S3_SD,,SPI6_MOSI,CAN2_RX,OTG_HS_ULPI_D7,,FMC_SDCKE1,DCMI_D10,LCD_G7,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port B pin 4" "NJTRST,TIM3_CH1,,,,SPI1_MISO,SPI3_MISO,SPI2_NSS/I2S2_WS,SPI6_MISO,,,CAN3_TX,UART7_TX,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port B pin 3" "JTDO/TRACESWO,TIM2_CH2,,,,SPI1_SCK/I2S1_CK,SPI3_SCK/I2S3_CK,,SPI6_SCK,,,CAN3_RX,UART7_RX,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port B pin 2" ",,,,,,SAI1_SD_A,SPI3_MOSI/I2S3_SD,,QUADSPI_CLK,DFSDM1_CKIN1,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port B pin 1" ",TIM1_CH3N,TIM3_CH4,TIM8_CH3N,,,DFSDM1_DATIN1,,,LCD_R6,OTG_HS_ULPI_D2,,,,LCD_G0,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port B pin 0" ",TIM1_CH2N,TIM3_CH3,TIM8_CH2N,,,DFSDM1_CKOUT,,UART4_CTS,LCD_R3,OTG_HS_ULPI_D1,,,,LCD_G1,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port B Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port B pin 15" "RTC_REFIN,TIM1_CH3N,,TIM8_CH3N,USART1_RX,SPI2_MOSI/I2S2_SD,DFSDM1_CKIN2,,UART4_CTS,TIM12_CH2,,,OTG_HS_DP,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port B pin 14" ",TIM1_CH2N,,TIM8_CH2N,USART1_TX,SPI2_MISO,DFSDM1_DATIN2,USART3_RTS,UART4_RTS,TIM12_CH1,,,OTG_HS_DM,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port B pin 13" ",TIM1_CH1N,,,,SPI2_SCK/I2S2_CK,DFSDM1_CKIN1,USART3_CTS,UART5_TX,CAN2_TX,OTG_HS_ULPI_D6,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port B pin 12" ",TIM1_BKIN,,,I2C2_SMBA,SPI2_NSS/I2S2_WS,DFSDM1_DATIN1,USART3_CK,UART5_RX,CAN2_RX,OTG_HS_ULPI_D5,,OTG_HS_ID,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port B pin 11" ",TIM2_CH4,,,I2C2_SDA,,DFSDM1_CKIN7,USART3_RX,,,OTG_HS_ULPI_D4,,,DSI_TE,LCD_G5,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port B pin 10" ",TIM2_CH3,,,I2C2_SCL,SPI2_SCK/I2S2_CK,DFSDM1_DATIN7,USART3_TX,,QUADSPI_BK1_NCS,OTG_HS_ULPI_D3,,,,LCD_G4,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port B pin 9" ",I2S4_SDA,TIM4_CH4,TIM11_CH1,I2C1_SDA,SPI2_NSS/I2S2_WS,DFSDM1_DATIN7,UART5_TX,,CAN1_TX,,I2C4_SMBA,SDMMC_D5,DCMI_D7,LCD_B7,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port B pin 8" ",I2C4_SCL,TIM4_CH3,TIM10_CH1,I2C1_SCL,,DFSDM1_CKIN7,UART5_RX,,CAN1_RX,,,SDMMC_D4,DCMI_D6,LCD_B6,EVENTOUT"
|
|
elif cpuis("STM32F778A*")||cpuis("STM32F779A*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port B Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port B pin 7" ",,TIM4_CH2,,I2C1_SDA,,DFSDM1_CKIN5,USART1_RX,,,,I2S4_SDA,FMC_NL,DCMI_VSYNC,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port B pin 6" ",UART5_TX,TIM4_CH1,HDMICEC,I2C1_SCL,,DFSDM1_DATIN5,USART1_TX,,CAN2_TX,QUADSPI_BK1_NCS,I2C4_SCL,FMC_SDNE1,DCMI_D5,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port B pin 5" ",UART5_RX,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI/I2S1_SD,SPI3_MOSI/I2S3_SD,,SPI6_MOSI,CAN2_RX,OTG_HS_ULPI_D7,,FMC_SDCKE1,DCMI_D10,LCD_G7,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port B pin 4" "NJTRST,TIM3_CH1,,,,SPI1_MISO,SPI3_MISO,SPI2_NSS/I2S2_WS,SPI6_MISO,,SDMMC2_D3,CAN3_TX,UART7_TX,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port B pin 3" "JTDO/TRACESWO,TIM2_CH2,,,,SPI1_SCK/I2S1_CK,SPI3_SCK/I2S3_CK,,SPI6_SCK,,SDMMC2_D2,CAN3_RX,UART7_RX,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port B pin 2" ",,,,,,SAI1_SD_A,SPI3_MOSI/I2S3_SD,,QUADSPI_CLK,DFSDM1_CKIN1,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port B pin 1" ",TIM1_CH3N,TIM3_CH4,TIM8_CH3N,,,DFSDM1_DATIN1,,,LCD_R6,OTG_HS_ULPI_D2,,,,LCD_G0,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port B pin 0" ",TIM1_CH2N,TIM3_CH3,TIM8_CH2N,,,DFSDM1_CKOUT,,UART4_CTS,LCD_R3,OTG_HS_ULPI_D1,,,,LCD_G1,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port B Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port B pin 15" "RTC_REFIN,TIM1_CH3N,,TIM8_CH3N,USART1_RX,SPI2_MOSI/I2S2_SD,DFSDM1_CKIN2,,UART4_CTS,TIM12_CH2,SDMMC2_D1,,OTG_HS_DP,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port B pin 14" ",TIM1_CH2N,,TIM8_CH2N,USART1_TX,SPI2_MISO,DFSDM1_DATIN2,USART3_RTS,UART4_RTS,TIM12_CH1,SDMMC2_D0,,OTG_HS_DM,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port B pin 13" ",TIM1_CH1N,,,,SPI2_SCK/I2S2_CK,DFSDM1_CKIN1,USART3_CTS,UART5_TX,CAN2_TX,OTG_HS_ULPI_D6,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port B pin 12" ",TIM1_BKIN,,,I2C2_SMBA,SPI2_NSS/I2S2_WS,DFSDM1_DATIN1,USART3_CK,UART5_RX,CAN2_RX,OTG_HS_ULPI_D5,,OTG_HS_ID,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port B pin 11" ",TIM2_CH4,,,I2C2_SDA,,DFSDM1_CKIN7,USART3_RX,,,OTG_HS_ULPI_D4,,,DSI_TE,LCD_G5,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port B pin 10" ",TIM2_CH3,,,I2C2_SCL,SPI2_SCK/I2S2_CK,DFSDM1_DATIN7,USART3_TX,,QUADSPI_BK1_NCS,OTG_HS_ULPI_D3,,,,LCD_G4,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port B pin 9" ",I2S4_SDA,TIM4_CH4,TIM11_CH1,I2C1_SDA,SPI2_NSS/I2S2_WS,DFSDM1_DATIN7,UART5_TX,,CAN1_TX,SDMMC2_D5,I2C4_SMBA,SDMMC_D5,DCMI_D7,LCD_B7,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port B pin 8" ",I2C4_SCL,TIM4_CH3,TIM10_CH1,I2C1_SCL,,DFSDM1_CKIN7,UART5_RX,,CAN1_RX,SDMMC2_D4,,SDMMC_D4,DCMI_D6,LCD_B6,EVENTOUT"
|
|
elif cpuis("STM32F76*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port B Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port B pin 7" ",,TIM4_CH2,,I2C1_SDA,,DFSDM1_CKIN5,USART1_RX,,,,I2S4_SDA,FMC_NL,DCMI_VSYNC,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port B pin 6" ",UART5_TX,TIM4_CH1,HDMICEC,I2C1_SCL,,DFSDM1_DATIN5,USART1_TX,,CAN2_TX,QUADSPI_BK1_NCS,I2C4_SCL,FMC_SDNE1,DCMI_D5,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port B pin 5" ",UART5_RX,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI/I2S1_SD,SPI3_MOSI/I2S3_SD,,SPI6_MOSI,CAN2_RX,OTG_HS_ULPI_D7,ETH_PPS_OUT,FMC_SDCKE1,DCMI_D10,LCD_G7,EVENTOUT"
|
|
newline
|
|
sif (cpuis("STM32F767BI"))
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port B pin 4" "NJTRST,,TIM3_CH1,,,SPI1_MISO,SPI3_MISO,SPI2_NSS/I2S2_WS,SPI6_MISO,,SDMMC2_D3,CAN3_TX,UART7_TX,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port B pin 3" "JTDO/TRACESWO,TIM2_CH2,,,,SPI1_SCK/I2S1_CK,SPI3_SCK/I2S3_CK,,SPI6_SCK,,SDMMC2_D2,CAN3_RX,UART7_RX,,,EVENTOUT"
|
|
else
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port B pin 4" "NJTRST,TIM3_CH1,,,,SPI1_MISO,SPI3_MISO,SPI2_NSS/I2S2_WS,SPI6_MISO,,,CAN3_TX,UART7_TX,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port B pin 3" "JTDO/TRACESWO,TIM2_CH2,,,,SPI1_SCK/I2S1_CK,SPI3_SCK/I2S3_CK,,SPI6_SCK,,,CAN3_RX,UART7_RX,,,EVENTOUT"
|
|
endif
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port B pin 2" ",,,,,,SAI1_SD_A,SPI3_MOSI/I2S3_SD,,QUADSPI_CLK,DFSDM1_CKIN1,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port B pin 1" ",TIM1_CH3N,TIM3_CH4,TIM8_CH3N,,,DFSDM1_DATIN1,,,LCD_R6,OTG_HS_ULPI_D2,ETH_MII_RXD3,,,LCD_G0,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port B pin 0" ",TIM1_CH2N,TIM3_CH3,TIM8_CH2N,,,DFSDM1_CKOUT,,UART4_CTS,LCD_R3,OTG_HS_ULPI_D1,ETH_MII_RXD2,,,LCD_G1,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port B Alternate Function High Register"
|
|
sif (cpuis("STM32F767BI"))
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port B pin 15" "RTC_REFIN,TIM1_CH3N,,TIM8_CH3N,USART1_RX,SPI2_MOSI/I2S2_SD,DFSDM1_CKIN2,,UART4_CTS,TIM12_CH2,SDMMC2_D1,,OTG_HS_DP,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port B pin 14" ",TIM1_CH2N,,TIM8_CH2N,USART1_TX,SPI2_MISO,DFSDM1_DATIN2,USART3_RTS,UART4_RTS,TIM12_CH1,SDMMC2_D0,,OTG_HS_DM,,,EVENTOUT"
|
|
else
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port B pin 15" "RTC_REFIN,TIM1_CH3N,,TIM8_CH3N,USART1_RX,SPI2_MOSI/I2S2_SD,DFSDM1_CKIN2,,UART4_CTS,TIM12_CH2,,,OTG_HS_DP,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port B pin 14" ",TIM1_CH2N,,TIM8_CH2N,USART1_TX,SPI2_MISO,DFSDM1_DATIN2,USART3_RTS,UART4_RTS,TIM12_CH1,,,OTG_HS_DM,,,EVENTOUT"
|
|
endif
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port B pin 13" ",TIM1_CH1N,,,,SPI2_SCK/I2S2_CK,DFSDM1_CKIN1,USART3_CTS,UART5_TX,CAN2_TX,OTG_HS_ULPI_D6,ETH_MII_TXD1/ETH_RMII_TXD1,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port B pin 12" ",TIM1_BKIN,,,I2C2_SMBA,SPI2_NSS/I2S2_WS,DFSDM1_DATIN1,USART3_CK,UART5_RX,CAN2_RX,OTG_HS_ULPI_D5,ETH_MII_TXD0/ETH_RMII_TXD0,OTG_HS_ID,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port B pin 11" ",TIM2_CH4,,,I2C2_SDA,,DFSDM1_CKIN7,USART3_RX,,,OTG_HS_ULPI_D4,ETH_MII_TX_EN/ETH_RMII_TX_EN,,DSI_TE,LCD_G5,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port B pin 10" ",TIM2_CH3,,,I2C2_SCL,SPI2_SCK/I2S2_CK,DFSDM1_DATIN7,USART3_TX,,QUADSPI_BK1_NCS,OTG_HS_ULPI_D3,ETH_MII_RX_ER,,,LCD_G4,EVENTOUT"
|
|
newline
|
|
sif (cpuis("STM32F767BI"))
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port B pin 9" ",I2S4_SDA,TIM4_CH4,TIM11_CH1,I2C1_SDA,SPI2_NSS/I2S2_WS,DFSDM1_DATIN7,UART5_TX,,CAN1_TX,SDMMC2_D5,I2C4_SMBA,SDMMC_D5,DCMI_D7,LCD_B7,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port B pin 8" ",I2C4_SCL,TIM4_CH3,TIM10_CH1,I2C1_SCL,,DFSDM1_CKIN7,UART5_RX,,CAN1_RX,SDMMC2_D4,ETH_MII_TXD3,SDMMC_D4,DCMI_D6,LCD_B6,EVENTOUT"
|
|
else
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port B pin 9" ",I2S4_SDA,TIM4_CH4,TIM11_CH1,I2C1_SDA,SPI2_NSS/I2S2_WS,DFSDM1_DATIN7,UART5_TX,,CAN1_TX,,I2C4_SMBA,SDMMC_D5,DCMI_D7,LCD_B7,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port B pin 8" ",I2C4_SCL,TIM4_CH3,TIM10_CH1,I2C1_SCL,,DFSDM1_CKIN7,UART5_RX,,CAN1_RX,,ETH_MII_TXD3,SDMMC_D4,DCMI_D6,LCD_B6,EVENTOUT"
|
|
endif
|
|
else
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port B Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port B pin 7" ",,TIM4_CH2,,I2C1_SDA,,DFSDM1_CKIN5,USART1_RX,,,,I2S4_SDA,FMC_NL,DCMI_VSYNC,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port B pin 6" ",UART5_TX,TIM4_CH1,HDMICEC,I2C1_SCL,,DFSDM1_DATIN5,USART1_TX,,CAN2_TX,QUADSPI_BK1_NCS,I2C4_SCL,FMC_SDNE1,DCMI_D5,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port B pin 5" ",UART5_RX,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI/I2S1_SD,SPI3_MOSI/I2S3_SD,,SPI6_MOSI,CAN2_RX,OTG_HS_ULPI_D7,ETH_PPS_OUT,FMC_SDCKE1,DCMI_D10,LCD_G7,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port B pin 4" "NJTRST,TIM3_CH1,,,,SPI1_MISO,SPI3_MISO,SPI2_NSS/I2S2_WS,SPI6_MISO,,SDMMC2_D3,CAN3_TX,UART7_TX,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port B pin 3" "JTDO/TRACESWO,TIM2_CH2,,,,SPI1_SCK/I2S1_CK,SPI3_SCK/I2S3_CK,,SPI6_SCK,,SDMMC2_D2,CAN3_RX,UART7_RX,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port B pin 2" ",,,,,,SAI1_SD_A,SPI3_MOSI/I2S3_SD,,QUADSPI_CLK,DFSDM1_CKIN1,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port B pin 1" ",TIM1_CH3N,TIM3_CH4,TIM8_CH3N,,,DFSDM1_DATIN1,,,LCD_R6,OTG_HS_ULPI_D2,ETH_MII_RXD3,,,LCD_G0,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port B pin 0" ",TIM1_CH2N,TIM3_CH3,TIM8_CH2N,,,DFSDM1_CKOUT,,UART4_CTS,LCD_R3,OTG_HS_ULPI_D1,ETH_MII_RXD2,,,LCD_G1,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port B Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port B pin 15" "RTC_REFIN,TIM1_CH3N,,TIM8_CH3N,USART1_RX,SPI2_MOSI/I2S2_SD,DFSDM1_CKIN2,,UART4_CTS,TIM12_CH2,SDMMC2_D1,,OTG_HS_DP,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port B pin 14" ",TIM1_CH2N,,TIM8_CH2N,USART1_TX,SPI2_MISO,DFSDM1_DATIN2,USART3_RTS,UART4_RTS,TIM12_CH1,SDMMC2_D0,,OTG_HS_DM,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port B pin 13" ",TIM1_CH1N,,,,SPI2_SCK/I2S2_CK,DFSDM1_CKIN1,USART3_CTS,UART5_TX,CAN2_TX,OTG_HS_ULPI_D6,ETH_MII_TXD1/ETH_RMII_TXD1,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port B pin 12" ",TIM1_BKIN,,,I2C2_SMBA,SPI2_NSS/I2S2_WS,DFSDM1_DATIN1,USART3_CK,UART5_RX,CAN2_RX,OTG_HS_ULPI_D5,ETH_MII_TXD0/ETH_RMII_TXD0,OTG_HS_ID,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port B pin 11" ",TIM2_CH4,,,I2C2_SDA,,DFSDM1_CKIN7,USART3_RX,,,OTG_HS_ULPI_D4,ETH_MII_TX_EN/ETH_RMII_TX_EN,,DSI_TE,LCD_G5,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port B pin 10" ",TIM2_CH3,,,I2C2_SCL,SPI2_SCK/I2S2_CK,DFSDM1_DATIN7,USART3_TX,,QUADSPI_BK1_NCS,OTG_HS_ULPI_D3,ETH_MII_RX_ER,,,LCD_G4,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port B pin 9" ",I2S4_SDA,TIM4_CH4,TIM11_CH1,I2C1_SDA,SPI2_NSS/I2S2_WS,DFSDM1_DATIN7,UART5_TX,,CAN1_TX,SDMMC2_D5,I2C4_SMBA,SDMMC_D5,DCMI_D7,LCD_B7,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port B pin 8" ",I2C4_SCL,TIM4_CH3,TIM10_CH1,I2C1_SCL,,DFSDM1_CKIN7,UART5_RX,,CAN1_RX,SDMMC2_D4,ETH_MII_TXD3,SDMMC_D4,DCMI_D6,LCD_B6,EVENTOUT"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO C"
|
|
base ad:0x40020800
|
|
width 13.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "MODER,GPIO Port C Mode Register"
|
|
bitfld.long 0x00 30.--31. " MODER[15] ,Port C pin 15 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " [14] ,Port C pin 14 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " [13] ,Port C pin 13 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 24.--25. " [12] ,Port C pin 12 mode" "Input,Output,Alternate function,Analog"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " [11] ,Port C pin 11 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " [10] ,Port C pin 10 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " [9] ,Port C pin 9 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " [8] ,Port C pin 8 mode" "Input,Output,Alternate function,Analog"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " [7] ,Port C pin 7 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " [6] ,Port C pin 6 mode" "Input,Output,Alternate function,Analog"
|
|
sif !cpuis("STM32F730R8")
|
|
bitfld.long 0x00 10.--11. " [5] ,Port C pin 5 mode" "Input,Output,Alternate function,Analog"
|
|
else
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x00 8.--9. " [4] ,Port C pin 4 mode" "Input,Output,Alternate function,Analog"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " [3] ,Port C pin 3 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " [2] ,Port C pin 2 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " [1] ,Port C pin 1 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " [0] ,Port C pin 0 mode" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "OTYPER,GPIO Port C Output Type Register"
|
|
bitfld.long 0x04 15. " OT[15] ,Port C pin 15 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " [14] ,Port C pin 14 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " [13] ,Port C pin 13 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 12. " [12] ,Port C pin 12 output type" "Push-pull,Open-drain"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Port C pin 11 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " [10] ,Port C pin 10 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 9. " [9] ,Port C pin 9 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " [8] ,Port C pin 8 output type" "Push-pull,Open-drain"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Port C pin 7 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " [6] ,Port C pin 6 output type" "Push-pull,Open-drain"
|
|
sif !cpuis("STM32F730R8")
|
|
bitfld.long 0x04 5. " [5] ,Port C pin 5 output type" "Push-pull,Open-drain"
|
|
else
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x04 4. " [4] ,Port C pin 4 output type" "Push-pull,Open-drain"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,Port C pin 3 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " [2] ,Port C pin 2 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " [1] ,Port C pin 1 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " [0] ,Port C pin 0 output type" "Push-pull,Open-drain"
|
|
line.long 0x08 "OSPEEDR,GPIO Port C Output Speed Register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR[15] ,Port C pin 15 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 28.--29. " [14] ,Port C pin 14 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 26.--27. " [13] ,Port C pin 13 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 24.--25. " [12] ,Port C pin 12 output speed" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x08 22.--23. " [11] ,Port C pin 11 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 20.--21. " [10] ,Port C pin 10 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 18.--19. " [9] ,Port C pin 9 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 16.--17. " [8] ,Port C pin 8 output speed" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x08 14.--15. " [7] ,Port C pin 7 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 12.--13. " [6] ,Port C pin 6 output speed" "Low,Medium,High,Very high"
|
|
sif !cpuis("STM32F730R8")
|
|
bitfld.long 0x08 10.--11. " [5] ,Port C pin 5 output speed" "Low,Medium,High,Very high"
|
|
else
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x08 8.--9. " [4] ,Port C pin 4 output speed" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x08 6.--7. " [3] ,Port C pin 3 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 4.--5. " [2] ,Port C pin 2 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 2.--3. " [1] ,Port C pin 1 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 0.--1. " [0] ,Port C pin 0 output speed" "Low,Medium,High,Very high"
|
|
line.long 0x0C "PUPDR,GPIO Port C Pull-up/Pull-down Register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR[15] ,Port C pin 15 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " [14] ,Port C pin 14 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " [13] ,Port C pin 13 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 24.--25. " [12] ,Port C pin 12 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
newline
|
|
bitfld.long 0x0C 22.--23. " [11] ,Port C pin 11 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " [10] ,Port C pin 10 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 18.--19. " [9] ,Port C pin 9 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " [8] ,Port C pin 8 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
newline
|
|
bitfld.long 0x0C 14.--15. " [7] ,Port C pin 7 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 12.--13. " [6] ,Port C pin 6 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
sif !cpuis("STM32F730R8")
|
|
bitfld.long 0x0C 10.--11. " [5] ,Port C pin 5 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
else
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x0C 8.--9. " [4] ,Port C pin 4 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
newline
|
|
bitfld.long 0x0C 6.--7. " [3] ,Port C pin 3 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " [2] ,Port C pin 2 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " [1] ,Port C pin 1 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " [0] ,Port C pin 0 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "IDR,GPIO Port C Input Data Register"
|
|
bitfld.long 0x00 15. " IDR[15] ,Port C pin 15 input data" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Port C pin 14 input data" "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Port C pin 13 input data" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Port C pin 12 input data" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Port C pin 11 input data" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Port C pin 10 input data" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,Port C pin 9 input data" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Port C pin 8 input data" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Port C pin 7 input data" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Port C pin 6 input data" "Low,High"
|
|
sif !cpuis("STM32F730R8")
|
|
bitfld.long 0x00 5. " [5] ,Port C pin 5 input data" "Low,High"
|
|
else
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x00 4. " [4] ,Port C pin 4 input data" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Port C pin 3 input data" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Port C pin 2 input data" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Port C pin 1 input data" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Port C pin 0 input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ODR_SET/CLR,GPIO Port C Output Data Set/Clear Register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR[15] ,Port C pin 15 output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " [14] ,Port C pin 14 output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " [13] ,Port C pin 13 output data" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " [12] ,Port C pin 12 output data" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " [11] ,Port C pin 11 output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " [10] ,Port C pin 10 output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " [9] ,Port C pin 9 output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " [8] ,Port C pin 8 output data" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " [7] ,Port C pin 7 output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " [6] ,Port C pin 6 output data" "Low,High"
|
|
sif !cpuis("STM32F730R8")
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " [5] ,Port C pin 5 output data" "Low,High"
|
|
else
|
|
textfld " "
|
|
endif
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " [4] ,Port C pin 4 output data" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " [3] ,Port C pin 3 output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " [2] ,Port C pin 2 output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " [1] ,Port C pin 1 output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " [0] ,Port C pin 0 output data" "Low,High"
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F750*")||cpuis("STM32F767BI"))
|
|
if ((per.l(ad:0x40020800+0x1C)&0x10000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO Port C Configuration Lock Register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
newline
|
|
bitfld.long 0x00 15. " LCK[15] ,Port C pin 15 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " [14] ,Port C pin 14 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " [13] ,Port C pin 13 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " [12] ,Port C pin 12 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Port C pin 11 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " [10] ,Port C pin 10 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " [9] ,Port C pin 9 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " [8] ,Port C pin 8 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Port C pin 7 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " [6] ,Port C pin 6 configuration lock" "Not locked,Locked"
|
|
sif !cpuis("STM32F730R8")
|
|
bitfld.long 0x00 5. " [5] ,Port C pin 5 configuration lock" "Not locked,Locked"
|
|
else
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x00 4. " [4] ,Port C pin 4 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Port C pin 3 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " [2] ,Port C pin 2 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " [1] ,Port C pin 1 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " [0] ,Port C pin 0 configuration lock" "Not locked,Locked"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO Port C Configuration Lock Register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
newline
|
|
rbitfld.long 0x00 15. " LCK[15] ,Port C pin 15 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 14. " [14] ,Port C pin 14 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 13. " [13] ,Port C pin 13 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 12. " [12] ,Port C pin 12 configuration lock" "Not locked,Locked"
|
|
newline
|
|
rbitfld.long 0x00 11. " [11] ,Port C pin 11 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 10. " [10] ,Port C pin 10 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 9. " [9] ,Port C pin 9 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 8. " [8] ,Port C pin 8 configuration lock" "Not locked,Locked"
|
|
newline
|
|
rbitfld.long 0x00 7. " [7] ,Port C pin 7 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 6. " [6] ,Port C pin 6 configuration lock" "Not locked,Locked"
|
|
sif !cpuis("STM32F730R8")
|
|
rbitfld.long 0x00 5. " [5] ,Port C pin 5 configuration lock" "Not locked,Locked"
|
|
else
|
|
textfld " "
|
|
endif
|
|
rbitfld.long 0x00 4. " [4] ,Port C pin 4 configuration lock" "Not locked,Locked"
|
|
newline
|
|
rbitfld.long 0x00 3. " [3] ,Port C pin 3 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 2. " [2] ,Port C pin 2 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 1. " [1] ,Port C pin 1 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 0. " [0] ,Port C pin 0 configuration lock" "Not locked,Locked"
|
|
endif
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO Port C Configuration Lock Register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
newline
|
|
bitfld.long 0x00 15. " LCK[15] ,Port C pin 15 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " [14] ,Port C pin 14 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " [13] ,Port C pin 13 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " [12] ,Port C pin 12 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Port C pin 11 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " [10] ,Port C pin 10 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " [9] ,Port C pin 9 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " [8] ,Port C pin 8 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Port C pin 7 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " [6] ,Port C pin 6 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " [5] ,Port C pin 5 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " [4] ,Port C pin 4 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Port C pin 3 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " [2] ,Port C pin 2 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " [1] ,Port C pin 1 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " [0] ,Port C pin 0 configuration lock" "Not locked,Locked"
|
|
endif
|
|
newline
|
|
sif (cpuis("STM32F722*")||cpuis("STM32F723*")||cpuis("STM32F733*")||cpuis("STM32F732*"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port C Alternate Function Low Register"
|
|
sif (cpuis("STM32F723V*")||cpuis("STM32F733V*"))
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port C pin 7" ",,TIM3_CH2,TIM8_CH2,,,I2S3_MCK,,USART6_RX,,,,SDMMC1_D7,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port C pin 6" ",,TIM3_CH1,TIM8_CH1,,I2S2_MCK,,,USART6_TX,,,,SDMMC1_D6,,,EVENTOUT"
|
|
elif (cpuis("STM32F72?R*")||cpuis("STM32F73?R*"))
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port C pin 7" ",,TIM3_CH2,TIM8_CH2,,,I2S3_MCK,,USART6_RX,,,,SDMMC1_D7,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port C pin 6" ",,TIM3_CH1,TIM8_CH1,,I2S2_MCK,,,USART6_TX,,,,SDMMC1_D6,,,EVENTOUT"
|
|
else
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port C pin 7" ",,TIM3_CH2,TIM8_CH2,,,I2S3_MCK,,USART6_RX,,SDMMC2_D7,,SDMMC1_D7,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port C pin 6" ",,TIM3_CH1,TIM8_CH1,,I2S2_MCK,,,USART6_TX,,SDMMC2_D6,,SDMMC1_D6,,,EVENTOUT"
|
|
endif
|
|
sif (cpuis("STM32F72?R*")||cpuis("STM32F73?R*"))
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port C pin 5" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port C pin 4" ",,,,,I2S1_MCK,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port C pin 3" ",,,,,SPI2_MOSI/I2S2_SD,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port C pin 2" ",,,,,SPI2_MISO,,,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port C pin 1" "TRACED0,,,,,SPI2_MOSI/I2S2_SD,SAI1_SD_A,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port C pin 0" ",,,,,,,,SAI2_FS_B,,,,,,,EVENTOUT"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port C pin 5" ",,,,,,,,,,,,FMC_SDCKE0,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port C pin 4" ",,,,,I2S1_MCK,,,,,,,FMC_SDNE0,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port C pin 3" ",,,,,SPI2_MOSI/I2S2_SD,,,,,OTG_HS_ULPI_NXT,,FMC_SDCKE0,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port C pin 2" ",,,,,SPI2_MISO,,,,,OTG_HS_ULPI_DIR,,FMC_SDNE0,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port C pin 1" "TRACED0,,,,,SPI2_MOSI/I2S2_SD,SAI1_SD_A,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port C pin 0" ",,,,,,,,SAI2_FS_B,,OTG_HS_ULPI_STP,,FMC_SDNWE,,,EVENTOUT"
|
|
newline
|
|
endif
|
|
line.long 0x04 "AFRH,GPIO Port C Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port C pin 15" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port C pin 14" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port C pin 13" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port C pin 12" "TRACED3,,,,,,SPI3_MOSI/I2S3_SD,USART3_CK,UART5_TX,,,,SDMMC1_CK,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port C pin 11" ",,,,,,SPI3_MISO,USART3_RX,UART4_RX,QUADSPI_BK2_NCS,,,SDMMC1_D3,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port C pin 10" ",,,,,,SPI3_SCK/I2S3_CK,USART3_TX,UART4_TX,QUADSPI_BK1_IO1,,,SDMMC1_D2,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port C pin 9" "MCO2,,TIM3_CH4,TIM8_CH4,I2C3_SDA,I2S_CKIN,,UART5_CTS,,QUADSPI_BK1_IO0,,,SDMMC1_D1,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port C pin 8" "TRACED1,,TIM3_CH3,TIM8_CH3,,,,UART5_RTS,USART6_CK,,,,SDMMC1_D0,,,EVENTOUT"
|
|
elif cpuis("STM32F730*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port C Alternate Function Low Register"
|
|
sif cpuis("STM32F730R*")
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port C pin 7" ",,TIM3_CH2,TIM8_CH2,,,I2S3_MCK,,USART6_RX,,,,SDMMC1_D7,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port C pin 6" ",,TIM3_CH1,TIM8_CH1,,I2S2_MCK,,,USART6_TX,,,,SDMMC1_D6,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port C pin 4" ",,,,,I2S1_MCK,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port C pin 3" ",,,,,SPI2_MOSI/I2S2_SD,,,,,OTG_HS_ULPI_NXT,,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port C pin 2" ",,,,,SPI2_MISO,,,,,OTG_HS_ULPI_DIR,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port C pin 1" "TRACED0,,,,,SPI2_MOSI/I2S2_SD,SAI1_SD_A,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port C pin 0" ",,,,,,,,SAI2_FS_B,,OTG_HS_ULPI_STP,,,,,EVENTOUT"
|
|
newline
|
|
elif cpuis("STM32F730V*")
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port C pin 7" ",,TIM3_CH2,TIM8_CH2,,,I2S3_MCK,,USART6_RX,,,,SDMMC1_D7,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port C pin 6" ",,TIM3_CH1,TIM8_CH1,,I2S2_MCK,,,USART6_TX,,,,SDMMC1_D6,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port C pin 5" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port C pin 4" ",,,,,I2S1_MCK,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port C pin 3" ",,,,,SPI2_MOSI/I2S2_SD,,,,,OTG_HS_ULPI_NXT,,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port C pin 2" ",,,,,SPI2_MISO,,,,,OTG_HS_ULPI_DIR,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port C pin 1" "TRACED0,,,,,SPI2_MOSI/I2S2_SD,SAI1_SD_A,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port C pin 0" ",,,,,,,,SAI2_FS_B,,OTG_HS_ULPI_STP,,,,,EVENTOUT"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port C pin 7" ",,TIM3_CH2,TIM8_CH2,,,I2S3_MCK,,USART6_RX,,SDMMC2_D7,,SDMMC1_D7,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port C pin 6" ",,TIM3_CH1,TIM8_CH1,,I2S2_MCK,,,USART6_TX,,SDMMC2_D6,,SDMMC1_D6,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port C pin 5" ",,,,,,,,,,,,FMC_SDCKE0,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port C pin 4" ",,,,,I2S1_MCK,,,,,,,FMC_SDNE0,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port C pin 3" ",,,,,SPI2_MOSI/I2S2_SD,,,,,,,FMC_SDCKE0,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port C pin 2" ",,,,,SPI2_MISO,,,,,,,FMC_SDNE0,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port C pin 1" "TRACED0,,,,,SPI2_MOSI/I2S2_SD,SAI1_SD_A,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port C pin 0" ",,,,,,,,SAI2_FS_B,,,,FMC_SDNWE,,,EVENTOUT"
|
|
newline
|
|
endif
|
|
line.long 0x04 "AFRH,GPIO Port C Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port C pin 15" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port C pin 14" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port C pin 13" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port C pin 12" "TRACED3,,,,,,SPI3_MOSI/I2S3_SD,USART3_CK,UART5_TX,,,,SDMMC1_CK,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port C pin 11" ",,,,,,SPI3_MISO,USART3_RX,UART4_RX,QUADSPI_BK2_NCS,,,SDMMC1_D3,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port C pin 10" ",,,,,,SPI3_SCK/I2S3_CK,USART3_TX,UART4_TX,QUADSPI_BK1_IO1,,,SDMMC1_D2,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port C pin 9" "MCO2,,TIM3_CH4,TIM8_CH4,I2C3_SDA,I2S_CKIN,,UART5_CTS,,QUADSPI_BK1_IO0,,,SDMMC1_D1,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port C pin 8" "TRACED1,,TIM3_CH3,TIM8_CH3,,,,UART5_RTS,USART6_CK,,,,SDMMC1_D0,,,EVENTOUT"
|
|
elif cpuis("STM32F745*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port C Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port C pin 7" ",,TIM3_CH2,TIM8_CH2,,,I2S3_MCK,,USART6_RX,,,,SDMMC_D7,DCMI_D1,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port C pin 6" ",,TIM3_CH1,TIM8_CH1,,I2S2_MCK,,,USART6_TX,,,,SDMMC1_D6,DCMI_D0,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port C pin 5" ",,,,,,,,SPDIF_RX3,,,ETH_MII_RXD1/ETH_RMII_RXD1,FMC_SDCKE0,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port C pin 4" ",,,,,I2S1_MCK,,,SPDIF_RX2,,,ETH_MII_RXD0/ETH_RMII_RXD0,FMC_SDNE0,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port C pin 3" ",,,,,SPI2_MOSI/I2S2_SD,,,,,OTG_HS_ULPI_NXT,ETH_MII_TX_CLK,FMC_SDCKE0,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port C pin 2" ",,,,,SPI2_MISO,,,,,OTG_HS_ULPI_DIR,ETH_MII_TXD2,FMC_SDNE0,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port C pin 1" "TRACED0,,,,,SPI2_MOSI/I2S2_SD,SAI1_SD_A,,,,,ETH_MDC,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port C pin 0" ",,,,,,,,SAI2_FS_B,,OTG_HS_ULPI_STP,,FMC_SDNWE,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port C Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port C pin 15" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port C pin 14" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port C pin 13" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port C pin 12" "TRACED3,,,,,,SPI3_MOSI/I2S3_SD,USART3_CK,UART5_TX,,,,SDMMC_CK,DCMI_D9,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port C pin 11" ",,,,,,SPI3_MISO,USART3_RX,UART4_RX,,,,SDMMC_D3,DCMI_D4,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port C pin 10" ",,,,,,SPI3_SCK/I2S3_CK,USART3_TX,UART4_TX,,,,SDMMC_D2,DCMI_D8,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port C pin 9" "MCO2,,TIM3_CH4,TIM8_CH4,I2C3_SDA,I2S_CKIN,,UART5_CTS,,,,,SDMMC_D1,DCMI_D3,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port C pin 8" "TRACED1,,TIM3_CH3,TIM8_CH3,,,,UART5_RTS,USART6_CK,,,,SDMMC_D0,DCMI_D2,,EVENTOUT"
|
|
elif cpuis("STM32F746*")||cpuis("STM32F756*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port C Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port C pin 7" ",,TIM3_CH2,TIM8_CH2,,,I2S3_MCK,,USART6_RX,FMC_NE1,SDMMC2_D7,,SDMMC_D7,DCMI_D1,LCD_G6,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port C pin 6" ",,TIM3_CH1,TIM8_CH1,,I2S2_MCK,,,USART6_TX,FMC_NWAIT,SDMMC2_D6,,SDMMC_D6,DCMI_D0,LCD_HSYNC,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port C pin 5" ",,,,,,,,SPDIF_RX3,,,ETH_MII_RXD1/ETH_RMII_RXD1,FMC_SDCKE0,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port C pin 4" ",,,,,I2S1_MCK,,,SPDIF_RX2,,,ETH_MII_RXD0/ETH_RMII_RXD0,FMC_SDNE0,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port C pin 3" ",,,,,SPI2_MOSI/I2S2_SD,,,,,OTG_HS_ULPI_NXT,ETH_MII_TX_CLK,FMC_SDCKE0,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port C pin 2" ",,,,,SPI2_MISO,,,,,OTG_HS_ULPI_DIR,ETH_MII_TXD2,FMC_SDNE0,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port C pin 1" "TRACED0,,,,,SPI2_MOSI/I2S2_SD,SAI1_SD_A,,,,,ETH_MDC,MDIOS_MDC,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port C pin 0" ",,,,,,,,SAI2_FS_B,,OTG_HS_ULPI_STP,,FMC_SDNWE,,LCD_R5,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port C Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port C pin 15" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port C pin 14" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port C pin 13" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port C pin 12" "TRACED3,,,,,,SPI3_MOSI/I2S3_SD,USART3_CK,UART5_TX,,,,SDMMC_CK,DCMI_D9,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port C pin 11" ",,,,,,SPI3_MISO,USART3_RX,UART4_RX,,,,SDMMC_D3,DCMI_D4,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port C pin 10" ",,,,,,,USART3_TX,UART4_TX,,,,SDMMC_D2,DCMI_D8,LCD_R2,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port C pin 9" "MCO2,,TIM3_CH4,TIM8_CH4,I2C3_SDA,I2S_CKIN,,UART5_CTS,,,LCD_G3,LCD_B2,SDMMC_D1,DCMI_D3,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port C pin 8" "TRACED1,,TIM3_CH3,TIM8_CH3,,,,UART5_RTS,USART6_CK,FMC_NE2/FMC_NCE,,,SDMMC_D0,DCMI_D2,,EVENTOUT"
|
|
elif cpuis("STM32F750*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port C Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port C pin 7" ",,TIM3_CH2,TIM8_CH2,,,I2S3_MCK,,USART6_RX,,,,SDMMC1_D7,DCMI_D1,LCD_G6,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port C pin 6" ",,TIM3_CH1,TIM8_CH1,,I2S2_MCK,,,USART6_TX,,,,SDMMC1_D6,DCMI_D0,LCD_HSYNC,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port C pin 5" ",,,,,,,,SPDIF_RX3,,,ETH_MII_RXD1/ETH_RMII_RXD1,FMC_SDCKE0,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port C pin 4" ",,,,,I2S1_MCK,,,SPDIF_RX2,,,ETH_MII_RXD0/ETH_RMII_RXD0,FMC_SDNE0,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port C pin 3" ",,,,,SPI2_MOSI/I2S2_SD,,,,,OTG_HS_ULPI_NXT,ETH_MII_TX_CLK,FMC_SDCKE0,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port C pin 2" ",,,,,SPI2_MISO,,,,,OTG_HS_ULPI_DIR,ETH_MII_TXD2,FMC_SDNE0,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port C pin 1" "TRACED0,,,,,SPI2_MOSI/I2S2_SD,SAI1_SD_A,,,,,ETH_MDC,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port C pin 0" ",,,,,,,,SAI2_FS_B,,OTG_HS_ULPI_STP,,FMC_SDNWE,,LCD_R5,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port C Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port C pin 15" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port C pin 14" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port C pin 13" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port C pin 12" "TRACED3,,,,,,SPI3_MOSI/I2S3_SD,USART3_CK,UART5_TX,,,,SDMMC1_CK,DCMI_D9,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port C pin 11" ",,,,,,SPI3_MISO,USART3_RX,UART4_RX,QUADSPI_BK2_NCS,,,SDMMC1_D3,DCMI_D4,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port C pin 10" ",,,,,,SPI3_SCK/I2S3_CK,USART3_TX,UART4_TX,QUADSPI_BK1_IO1,,,SDMMC1_D2,DCMI_D8,LCD_R2,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port C pin 9" "MCO2,,TIM3_CH4,TIM8_CH4,I2C3_SDA,I2S_CKIN,,UART5_CTS,,QUADSPI_BK1_IO0,,,SDMMC1_D1,DCMI_D3,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port C pin 8" "TRACED1,,TIM3_CH3,TIM8_CH3,,,,UART5_RTS,USART6_CK,,,,SDMMC1_D0,DCMI_D2,,EVENTOUT"
|
|
elif cpuis("STM32F765*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port C Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port C pin 7" ",,TIM3_CH2,TIM8_CH2,,,I2S3_MCK,DFSDM1_DATAIN3,USART6_RX,FMC_NE1,SDMMC2_D7,,SDMMC_D7,DCMI_D1,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port C pin 6" ",,TIM3_CH1,TIM8_CH1,,I2S2_MCK,,DFSDM1_CKIN3,USART6_TX,FMC_NWAIT,SDMMC2_D6,,SDMMC_D6,DCMI_D0,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port C pin 5" ",,,DFSDM1_DATAIN2,,,,,SPDIF_RX3,,,ETH_MII_RXD1/ETH_RMII_RXD1,FMC_SDCKE0,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port C pin 4" ",,,DFSDM1_CKIN2,,I2S1_MCK,,,SPDIF_RX2,,,ETH_MII_RXD0/ETH_RMII_RXD0,FMC_SDNE0,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port C pin 3" ",,,DFSDM1_DATAIN1,,SPI2_MOSI/I2S2_SD,,,,,OTG_HS_ULPI_NXT,ETH_MII_TX_CLK,FMC_SDCKE0,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port C pin 2" ",,,DFSDM1_CKIN1,,SPI2_MISO,DFSDM1_CKOUT,,,,OTG_HS_ULPI_DIR,ETH_MII_TXD2,FMC_SDNE0,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port C pin 1" "TRACED0,,,DFSDM1_DATAIN0,,SPI2_MOSI/I2S2_SD,SAI1_SD_A,,,,DFSDM1_CKIN4,ETH_MDC,MDIOS_MDC,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port C pin 0" ",,,DFSDM1_CKIN0,,,DFSDM1_DATIN4,,SAI2_FS_B,,OTG_HS_ULPI_STP,,FMC_SDNWE,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port C Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port C pin 15" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port C pin 14" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port C pin 13" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port C pin 12" "TRACED3,,,,,,SPI3_MOSI/I2S3_SD,USART3_CK,UART5_TX,,,,SDMMC_CK,DCMI_D9,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port C pin 11" ",,,DFSDM1_DATAIN5,,,SPI3_MISO,USART3_RX,UART4_RX,QUADSPI_BK2_NCS,,,SDMMC_D3,DCMI_D4,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port C pin 10" ",,,DFSDM1_CKIN5,,,DFSDM1_CKIN5,USART3_TX,UART4_TX,QUADSPI_BK1_IO1,,,SDMMC_D2,DCMI_D8,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port C pin 9" "MCO2,,TIM3_CH4,TIM8_CH4,I2C3_SDA,I2S_CKIN,,UART5_CTS,,QUADSPI_BK1_IO0,,,SDMMC_D1,DCMI_D3,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port C pin 8" "TRACED1,,TIM3_CH3,TIM8_CH3,,,,UART5_RTS,USART6_CK,FMC_NE2/FMC_NCE,,,SDMMC_D0,DCMI_D2,,EVENTOUT"
|
|
elif cpuis("STM32F767V*")||cpuis("STM32F769V*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port C Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port C pin 7" ",,TIM3_CH2,TIM8_CH2,,,I2S3_MCK,DFSDM1_DATAIN3,USART6_RX,FMC_NE1,,,SDMMC_D7,DCMI_D1,LCD_G6,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port C pin 6" ",,TIM3_CH1,TIM8_CH1,,I2S2_MCK,,DFSDM1_CKIN3,USART6_TX,FMC_NWAIT,,,SDMMC_D6,DCMI_D0,LCD_HSYNC,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port C pin 5" ",,,DFSDM1_DATAIN2,,,,,SPDIF_RX3,,,ETH_MII_RXD1/ETH_RMII_RXD1,FMC_SDCKE0,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port C pin 4" ",,,DFSDM1_CKIN2,,I2S1_MCK,,,SPDIF_RX2,,,ETH_MII_RXD0/ETH_RMII_RXD0,FMC_SDNE0,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port C pin 3" ",,,DFSDM1_DATAIN1,,SPI2_MOSI/I2S2_SD,,,,,OTG_HS_ULPI_NXT,ETH_MII_TX_CLK,FMC_SDCKE0,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port C pin 2" ",,,DFSDM1_CKIN1,,SPI2_MISO,DFSDM1_CKOUT,,,,OTG_HS_ULPI_DIR,ETH_MII_TXD2,FMC_SDNE0,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port C pin 1" "TRACED0,,,DFSDM1_DATAIN0,,SPI2_MOSI/I2S2_SD,SAI1_SD_A,,,,DFSDM1_CKIN4,ETH_MDC,MDIOS_MDC,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port C pin 0" ",,,DFSDM1_CKIN0,,,DFSDM1_DATIN4,,SAI2_FS_B,,OTG_HS_ULPI_STP,,FMC_SDNWE,,LCD_R5,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port C Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port C pin 15" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port C pin 14" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port C pin 13" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port C pin 12" "TRACED3,,,,,,SPI3_MOSI/I2S3_SD,USART3_CK,UART5_TX,,,,SDMMC_CK,DCMI_D9,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port C pin 11" ",,,DFSDM1_DATAIN5,,,SPI3_MISO,USART3_RX,UART4_RX,QUADSPI_BK2_NCS,,,SDMMC_D3,DCMI_D4,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port C pin 10" ",,,DFSDM1_CKIN5,,,DFSDM1_CKIN5,USART3_TX,UART4_TX,QUADSPI_BK1_IO1,,,SDMMC_D2,DCMI_D8,LCD_R2,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port C pin 9" "MCO2,,TIM3_CH4,TIM8_CH4,I2C3_SDA,I2S_CKIN,,UART5_CTS,,QUADSPI_BK1_IO0,LCD_G3,LCD_B2,SDMMC_D1,DCMI_D3,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port C pin 8" "TRACED1,,TIM3_CH3,TIM8_CH3,,,,UART5_RTS,USART6_CK,FMC_NE2/FMC_NCE,,,SDMMC_D0,DCMI_D2,,EVENTOUT"
|
|
elif cpuis("STM32F777V*")||cpuis("STM32F778V*")||cpuis("STM32F779V*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port C Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port C pin 7" ",,TIM3_CH2,TIM8_CH2,,,I2S3_MCK,DFSDM1_DATAIN3,USART6_RX,FMC_NE1,SDMMC2_D7,,SDMMC_D7,DCMI_D1,LCD_G6,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port C pin 6" ",,TIM3_CH1,TIM8_CH1,,I2S2_MCK,,DFSDM1_CKIN3,USART6_TX,FMC_NWAIT,SDMMC2_D6,,SDMMC_D6,DCMI_D0,LCD_HSYNC,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port C pin 5" ",,,DFSDM1_DATAIN2,,,,,SPDIF_RX3,,,ETH_MII_RXD1/ETH_RMII_RXD1,FMC_SDCKE0,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port C pin 4" ",,,DFSDM1_CKIN2,,I2S1_MCK,,,SPDIF_RX2,,,ETH_MII_RXD0/ETH_RMII_RXD0,FMC_SDNE0,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port C pin 3" ",,,DFSDM1_DATAIN1,,SPI2_MOSI/I2S2_SD,,,,,OTG_HS_ULPI_NXT,ETH_MII_TX_CLK,FMC_SDCKE0,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port C pin 2" ",,,DFSDM1_CKIN1,,SPI2_MISO,DFSDM1_CKOUT,,,,OTG_HS_ULPI_DIR,ETH_MII_TXD2,FMC_SDNE0,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port C pin 1" "TRACED0,,,DFSDM1_DATAIN0,,SPI2_MOSI/I2S2_SD,SAI1_SD_A,,,,DFSDM1_CKIN4,ETH_MDC,MDIOS_MDC,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port C pin 0" ",,,DFSDM1_CKIN0,,,DFSDM1_DATIN4,,SAI2_FS_B,,OTG_HS_ULPI_STP,,FMC_SDNWE,,LCD_R5,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port C Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port C pin 15" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port C pin 14" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port C pin 13" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port C pin 12" "TRACED3,,,,,,SPI3_MOSI/I2S3_SD,USART3_CK,UART5_TX,,,,SDMMC_CK,DCMI_D9,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port C pin 11" ",,,DFSDM1_DATAIN5,,,SPI3_MISO,USART3_RX,UART4_RX,QUADSPI_BK2_NCS,,,SDMMC_D3,DCMI_D4,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port C pin 10" ",,,DFSDM1_CKIN5,,,DFSDM1_CKIN5,USART3_TX,UART4_TX,QUADSPI_BK1_IO1,,,SDMMC_D2,DCMI_D8,LCD_R2,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port C pin 9" "MCO2,,TIM3_CH4,TIM8_CH4,I2C3_SDA,I2S_CKIN,,UART5_CTS,,QUADSPI_BK1_IO0,LCD_G3,LCD_B2,SDMMC_D1,DCMI_D3,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port C pin 8" "TRACED1,,TIM3_CH3,TIM8_CH3,,,,UART5_RTS,USART6_CK,FMC_NE2/FMC_NCE,,,SDMMC_D0,DCMI_D2,,EVENTOUT"
|
|
elif cpuis("STM32F767Z*")||cpuis("STM32F769Z*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port C Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port C pin 7" ",,TIM3_CH2,TIM8_CH2,,,I2S3_MCK,DFSDM1_DATAIN3,USART6_RX,FMC_NE1,,,SDMMC_D7,DCMI_D1,LCD_G6,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port C pin 6" ",,TIM3_CH1,TIM8_CH1,,I2S2_MCK,,DFSDM1_CKIN3,USART6_TX,FMC_NWAIT,,,SDMMC_D6,DCMI_D0,LCD_HSYNC,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port C pin 5" ",,,DFSDM1_DATAIN2,,,,,SPDIF_RX3,,,ETH_MII_RXD1/ETH_RMII_RXD1,FMC_SDCKE0,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port C pin 4" ",,,DFSDM1_CKIN2,,I2S1_MCK,,,SPDIF_RX2,,,ETH_MII_RXD0/ETH_RMII_RXD0,FMC_SDNE0,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port C pin 3" ",,,DFSDM1_DATAIN1,,SPI2_MOSI/I2S2_SD,,,,,OTG_HS_ULPI_NXT,ETH_MII_TX_CLK,FMC_SDCKE0,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port C pin 2" ",,,DFSDM1_CKIN1,,SPI2_MISO,DFSDM1_CKOUT,,,,OTG_HS_ULPI_DIR,ETH_MII_TXD2,FMC_SDNE0,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port C pin 1" "TRACED0,,,DFSDM1_DATAIN0,,SPI2_MOSI/I2S2_SD,SAI1_SD_A,,,,DFSDM1_CKIN4,ETH_MDC,MDIOS_MDC,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port C pin 0" ",,,DFSDM1_CKIN0,,,DFSDM1_DATIN4,,SAI2_FS_B,,OTG_HS_ULPI_STP,,FMC_SDNWE,,LCD_R5,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port C Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port C pin 15" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port C pin 14" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port C pin 13" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port C pin 12" "TRACED3,,,,,,SPI3_MOSI/I2S3_SD,USART3_CK,UART5_TX,,,,SDMMC_CK,DCMI_D9,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port C pin 11" ",,,DFSDM1_DATAIN5,,,SPI3_MISO,USART3_RX,UART4_RX,QUADSPI_BK2_NCS,,,SDMMC_D3,DCMI_D4,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port C pin 10" ",,,DFSDM1_CKIN5,,,DFSDM1_CKIN5,USART3_TX,UART4_TX,QUADSPI_BK1_IO1,,,SDMMC_D2,DCMI_D8,LCD_R2,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port C pin 9" "MCO2,,TIM3_CH4,TIM8_CH4,I2C3_SDA,I2S_CKIN,,UART5_CTS,,QUADSPI_BK1_IO0,LCD_G3,LCD_B2,SDMMC_D1,DCMI_D3,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port C pin 8" "TRACED1,,TIM3_CH3,TIM8_CH3,,,,UART5_RTS,USART6_CK,FMC_NE2/FMC_NCE,,,SDMMC_D0,DCMI_D2,,EVENTOUT"
|
|
elif cpuis("STM32F777Z*")||cpuis("STM32F778Z*")||cpuis("STM32F779Z*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port C Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port C pin 7" ",,TIM3_CH2,TIM8_CH2,,,I2S3_MCK,DFSDM1_DATAIN3,USART6_RX,FMC_NE1,SDMMC2_D7,,SDMMC_D7,DCMI_D1,LCD_G6,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port C pin 6" ",,TIM3_CH1,TIM8_CH1,,I2S2_MCK,,DFSDM1_CKIN3,USART6_TX,FMC_NWAIT,SDMMC2_D6,,SDMMC_D6,DCMI_D0,LCD_HSYNC,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port C pin 5" ",,,DFSDM1_DATAIN2,,,,,SPDIF_RX3,,,ETH_MII_RXD1/ETH_RMII_RXD1,FMC_SDCKE0,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port C pin 4" ",,,DFSDM1_CKIN2,,I2S1_MCK,,,SPDIF_RX2,,,ETH_MII_RXD0/ETH_RMII_RXD0,FMC_SDNE0,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port C pin 3" ",,,DFSDM1_DATAIN1,,SPI2_MOSI/I2S2_SD,,,,,OTG_HS_ULPI_NXT,ETH_MII_TX_CLK,FMC_SDCKE0,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port C pin 2" ",,,DFSDM1_CKIN1,,SPI2_MISO,DFSDM1_CKOUT,,,,OTG_HS_ULPI_DIR,ETH_MII_TXD2,FMC_SDNE0,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port C pin 1" "TRACED0,,,DFSDM1_DATAIN0,,SPI2_MOSI/I2S2_SD,SAI1_SD_A,,,,DFSDM1_CKIN4,ETH_MDC,MDIOS_MDC,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port C pin 0" ",,,DFSDM1_CKIN0,,,DFSDM1_DATIN4,,SAI2_FS_B,,OTG_HS_ULPI_STP,,FMC_SDNWE,,LCD_R5,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port C Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port C pin 15" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port C pin 14" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port C pin 13" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port C pin 12" "TRACED3,,,,,,SPI3_MOSI/I2S3_SD,USART3_CK,UART5_TX,,,,SDMMC_CK,DCMI_D9,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port C pin 11" ",,,DFSDM1_DATAIN5,,,SPI3_MISO,USART3_RX,UART4_RX,QUADSPI_BK2_NCS,,,SDMMC_D3,DCMI_D4,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port C pin 10" ",,,DFSDM1_CKIN5,,,DFSDM1_CKIN5,USART3_TX,UART4_TX,QUADSPI_BK1_IO1,,,SDMMC_D2,DCMI_D8,LCD_R2,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port C pin 9" "MCO2,,TIM3_CH4,TIM8_CH4,I2C3_SDA,I2S_CKIN,,UART5_CTS,,QUADSPI_BK1_IO0,LCD_G3,LCD_B2,SDMMC_D1,DCMI_D3,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port C pin 8" "TRACED1,,TIM3_CH3,TIM8_CH3,,,,UART5_RTS,USART6_CK,FMC_NE2/FMC_NCE,,,SDMMC_D0,DCMI_D2,,EVENTOUT"
|
|
elif cpuis("STM32F768A*")||cpuis("STM32F769A*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port C Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port C pin 7" ",,TIM3_CH2,TIM8_CH2,,,I2S3_MCK,DFSDM1_DATAIN3,USART6_RX,FMC_NE1,,,SDMMC_D7,DCMI_D1,LCD_G6,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port C pin 6" ",,TIM3_CH1,TIM8_CH1,,I2S2_MCK,,DFSDM1_CKIN3,USART6_TX,FMC_NWAIT,,,SDMMC_D6,DCMI_D0,LCD_HSYNC,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port C pin 1" "TRACED0,,,DFSDM1_DATAIN0,,SPI2_MOSI/I2S2_SD,SAI1_SD_A,,,,DFSDM1_CKIN4,,MDIOS_MDC,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port C pin 0" ",,,DFSDM1_CKIN0,,,DFSDM1_DATIN4,,SAI2_FS_B,,OTG_HS_ULPI_STP,,FMC_SDNWE,,LCD_R5,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port C Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port C pin 15" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port C pin 14" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port C pin 13" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port C pin 12" "TRACED3,,,,,,SPI3_MOSI/I2S3_SD,USART3_CK,UART5_TX,,,,SDMMC_CK,DCMI_D9,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port C pin 11" ",,,DFSDM1_DATAIN5,,,SPI3_MISO,USART3_RX,UART4_RX,QUADSPI_BK2_NCS,,,SDMMC_D3,DCMI_D4,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port C pin 10" ",,,DFSDM1_CKIN5,,,DFSDM1_CKIN5,USART3_TX,UART4_TX,QUADSPI_BK1_IO1,,,SDMMC_D2,DCMI_D8,LCD_R2,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port C pin 9" "MCO2,,TIM3_CH4,TIM8_CH4,I2C3_SDA,I2S_CKIN,,UART5_CTS,,QUADSPI_BK1_IO0,LCD_G3,LCD_B2,SDMMC_D1,DCMI_D3,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port C pin 8" "TRACED1,,TIM3_CH3,TIM8_CH3,,,,UART5_RTS,USART6_CK,FMC_NE2/FMC_NCE,,,SDMMC_D0,DCMI_D2,,EVENTOUT"
|
|
elif cpuis("STM32F778A*")||cpuis("STM32F779A*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port C Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port C pin 7" ",,TIM3_CH2,TIM8_CH2,,,I2S3_MCK,DFSDM1_DATAIN3,USART6_RX,FMC_NE1,SDMMC2_D7,,SDMMC_D7,DCMI_D1,LCD_G6,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port C pin 6" ",,TIM3_CH1,TIM8_CH1,,I2S2_MCK,,DFSDM1_CKIN3,USART6_TX,FMC_NWAIT,SDMMC2_D6,,SDMMC_D6,DCMI_D0,LCD_HSYNC,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port C pin 1" "TRACED0,,,DFSDM1_DATAIN0,,SPI2_MOSI/I2S2_SD,SAI1_SD_A,,,,DFSDM1_CKIN4,,MDIOS_MDC,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port C pin 0" ",,,DFSDM1_CKIN0,,,DFSDM1_DATIN4,,SAI2_FS_B,,OTG_HS_ULPI_STP,,FMC_SDNWE,,LCD_R5,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port C Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port C pin 15" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port C pin 14" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port C pin 13" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port C pin 12" "TRACED3,,,,,,SPI3_MOSI/I2S3_SD,USART3_CK,UART5_TX,,,,SDMMC_CK,DCMI_D9,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port C pin 11" ",,,DFSDM1_DATAIN5,,,SPI3_MISO,USART3_RX,UART4_RX,QUADSPI_BK2_NCS,,,SDMMC_D3,DCMI_D4,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port C pin 10" ",,,DFSDM1_CKIN5,,,DFSDM1_CKIN5,USART3_TX,UART4_TX,QUADSPI_BK1_IO1,,,SDMMC_D2,DCMI_D8,LCD_R2,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port C pin 9" "MCO2,,TIM3_CH4,TIM8_CH4,I2C3_SDA,I2S_CKIN,,UART5_CTS,,QUADSPI_BK1_IO0,LCD_G3,LCD_B2,SDMMC_D1,DCMI_D3,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port C pin 8" "TRACED1,,TIM3_CH3,TIM8_CH3,,,,UART5_RTS,USART6_CK,FMC_NE2/FMC_NCE,,,SDMMC_D0,DCMI_D2,,EVENTOUT"
|
|
elif cpuis("STM32F76*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port C Alternate Function Low Register"
|
|
sif cpuis("STM32F767BI")
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port C pin 7" ",,TIM3_CH2,TIM8_CH2,,,I2S3_MCK,DFSDM1_DATAIN3,USART6_RX,FMC_NE1,SDMMC2_D7,,SDMMC_D7,DCMI_D1,LCD_G6,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port C pin 6" ",,TIM3_CH1,TIM8_CH1,,I2S2_MCK,,DFSDM1_CKIN3,USART6_TX,FMC_NWAIT,SDMMC2_D6,,SDMMC_D6,DCMI_D0,LCD_HSYNC,EVENTOUT"
|
|
else
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port C pin 7" ",,TIM3_CH2,TIM8_CH2,,,I2S3_MCK,DFSDM1_DATAIN3,USART6_RX,FMC_NE1,,,,DCMI_D1,LCD_G6,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port C pin 6" ",,TIM3_CH1,TIM8_CH1,,I2S2_MCK,,DFSDM1_CKIN3,USART6_TX,FMC_NWAIT,,,SDMMC_D6,DCMI_D0,LCD_HSYNC,EVENTOUT"
|
|
endif
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port C pin 5" ",,,DFSDM1_DATAIN2,,,,,SPDIF_RX3,,,ETH_MII_RXD1/ETH_RMII_RXD1,FMC_SDCKE0,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port C pin 4" ",,,DFSDM1_CKIN2,,I2S1_MCK,,,SPDIF_RX2,,,ETH_MII_RXD0/ETH_RMII_RXD0,FMC_SDNE0,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port C pin 3" ",,,DFSDM1_DATAIN1,,SPI2_MOSI/I2S2_SD,,,,,OTG_HS_ULPI_NXT,ETH_MII_TX_CLK,FMC_SDCKE0,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port C pin 2" ",,,DFSDM1_CKIN1,,SPI2_MISO,DFSDM1_CKOUT,,,,OTG_HS_ULPI_DIR,ETH_MII_TXD2,FMC_SDNE0,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port C pin 1" "TRACED0,,,DFSDM1_DATAIN0,,SPI2_MOSI/I2S2_SD,SAI1_SD_A,,,,DFSDM1_CKIN4,ETH_MDC,MDIOS_MDC,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port C pin 0" ",,,DFSDM1_CKIN0,,,DFSDM1_DATAIN4,,SAI2_FS_B,,OTG_HS_ULPI_STP,,FMC_SDNWE,,LCD_R5,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port C Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port C pin 15" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port C pin 14" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port C pin 13" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port C pin 12" "TRACED3,,,,,,SPI3_MOSI/I2S3_SD,USART3_CK,UART5_TX,,,,SDMMC_CK,DCMI_D9,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port C pin 11" ",,,DFSDM1_DATAIN5,,,SPI3_MISO,USART3_RX,UART4_RX,QUADSPI_BK2_NCS,,,SDMMC_D3,DCMI_D4,,EVENTOUT"
|
|
sif cpuis("STM32F767BI")
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port C pin 10" ",,,DFSDM1_CKIN5,,,SPI3_SCK/I2S3_CK,USART3_TX,UART4_TX,QUADSPI_BK1_IO1,,,SDMMC_D2,DCMI_D8,LCD_R2,EVENTOUT"
|
|
else
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port C pin 10" ",,,DFSDM1_CKIN5,,,DFSDM1_CKIN5,USART3_TX,UART4_TX,QUADSPI_BK1_IO1,,,SDMMC_D2,DCMI_D8,LCD_R2,EVENTOUT"
|
|
endif
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port C pin 9" "MCO2,,TIM3_CH4,TIM8_CH4,I2C3_SDA,I2S_CKIN,,UART5_CTS,,QUADSPI_BK1_IO0,LCD_G3,LCD_B2,SDMMC_D1,DCMI_D3,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port C pin 8" "TRACED1,,TIM3_CH3,TIM8_CH3,,,,UART5_RTS,USART6_CK,FMC_NE2/FMC_NCE,,,SDMMC_D0,DCMI_D2,,EVENTOUT"
|
|
else
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port C Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port C pin 7" ",,TIM3_CH2,TIM8_CH2,,,I2S3_MCK,DFSDM1_DATAIN3,USART6_RX,FMC_NE1,SDMMC2_D7,,SDMMC_D7,DCMI_D1,LCD_G6,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port C pin 6" ",,TIM3_CH1,TIM8_CH1,,I2S2_MCK,,DFSDM1_CKIN3,USART6_TX,FMC_NWAIT,SDMMC2_D6,,SDMMC_D6,DCMI_D0,LCD_HSYNC,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port C pin 5" ",,,DFSDM1_DATAIN2,,,,,SPDIF_RX3,,,ETH_MII_RXD1/ETH_RMII_RXD1,FMC_SDCKE0,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port C pin 4" ",,,DFSDM1_CKIN2,,I2S1_MCK,,,SPDIF_RX2,,,ETH_MII_RXD0/ETH_RMII_RXD0,FMC_SDNE0,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port C pin 3" ",,,DFSDM1_DATAIN1,,SPI2_MOSI/I2S2_SD,,,,,OTG_HS_ULPI_NXT,ETH_MII_TX_CLK,FMC_SDCKE0,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port C pin 2" ",,,DFSDM1_CKIN1,,SPI2_MISO,DFSDM1_CKOUT,,,,OTG_HS_ULPI_DIR,ETH_MII_TXD2,FMC_SDNE0,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port C pin 1" "TRACED0,,,DFSDM1_DATAIN0,,SPI2_MOSI/I2S2_SD,SAI1_SD_A,,,,DFSDM1_CKIN4,ETH_MDC,MDIOS_MDC,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port C pin 0" ",,,DFSDM1_CKIN0,,,DFSDM1_DATIN4,,SAI2_FS_B,,OTG_HS_ULPI_STP,,FMC_SDNWE,,LCD_R5,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port C Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port C pin 15" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port C pin 14" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port C pin 13" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port C pin 12" "TRACED3,,,,,,SPI3_MOSI/I2S3_SD,USART3_CK,UART5_TX,,,,SDMMC_CK,DCMI_D9,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port C pin 11" ",,,DFSDM1_DATAIN5,,,SPI3_MISO,USART3_RX,UART4_RX,QUADSPI_BK2_NCS,,,SDMMC_D3,DCMI_D4,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port C pin 10" ",,,DFSDM1_CKIN5,,,DFSDM1_CKIN5,USART3_TX,UART4_TX,QUADSPI_BK1_IO1,,,SDMMC_D2,DCMI_D8,LCD_R2,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port C pin 9" "MCO2,,TIM3_CH4,TIM8_CH4,I2C3_SDA,I2S_CKIN,,UART5_CTS,,QUADSPI_BK1_IO0,LCD_G3,LCD_B2,SDMMC_D1,DCMI_D3,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port C pin 8" "TRACED1,,TIM3_CH3,TIM8_CH3,,,,UART5_RTS,USART6_CK,FMC_NE2/FMC_NCE,,,SDMMC_D0,DCMI_D2,,EVENTOUT"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO D"
|
|
base ad:0x40020C00
|
|
width 13.
|
|
sif cpuis("STM32F72?R*")||cpuis("STM32F73?R*")
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "MODER,GPIO Port D Mode Register"
|
|
bitfld.long 0x00 4.--5. " MODER[2] ,Port D pin 2 mode" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "OTYPER,GPIO Port D Mode Register"
|
|
bitfld.long 0x04 2. " OT[2] ,Port D pin 2 output type" "Push-pull,Open-drain"
|
|
line.long 0x08 "OSPEEDR,GPIO Port D Output Speed Register"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR[2] ,Port D pin 2 output speed" "Low,Medium,High,Very high"
|
|
line.long 0x0C "PUPDR,GPIO Port D Pull-up/Pull-down Register"
|
|
bitfld.long 0x0C 4.--5. " PUPDR[2] ,Port D pin 2 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "IDR,GPIO Port D Input Data Register"
|
|
bitfld.long 0x00 2. " IDR[2] ,Port D pin 2 input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ODR_SET/CLR,GPIO Port D Output Data Set/Clear Register"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR[2] ,Port D pin 2 output data" "Low,High"
|
|
if ((per.l(ad:0x40020C00+0x1C)&0x10000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO Port D Configuration Lock Register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
newline
|
|
bitfld.long 0x00 2. " LCK[2] ,Port D pin 2 configuration lock" "Not locked,Locked"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO Port D Configuration Lock Register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
newline
|
|
rbitfld.long 0x00 2. " LCK[2] ,Port D pin 2 configuration lock" "Not locked,Locked"
|
|
endif
|
|
else
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "MODER,GPIO Port D Mode Register"
|
|
bitfld.long 0x00 30.--31. " MODER[15] ,Port D pin 15 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " [14] ,Port D pin 14 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " [13] ,Port D pin 13 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 24.--25. " [12] ,Port D pin 12 mode" "Input,Output,Alternate function,Analog"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " [11] ,Port D pin 11 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " [10] ,Port D pin 10 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " [9] ,Port D pin 9 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " [8] ,Port D pin 8 mode" "Input,Output,Alternate function,Analog"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " [7] ,Port D pin 7 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " [6] ,Port D pin 6 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " [5] ,Port D pin 5 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " [4] ,Port D pin 4 mode" "Input,Output,Alternate function,Analog"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " [3] ,Port D pin 3 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " [2] ,Port D pin 2 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " [1] ,Port D pin 1 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " [0] ,Port D pin 0 mode" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "OTYPER,GPIO Port D Output Type Register"
|
|
bitfld.long 0x04 15. " OT[15] ,Port D pin 15 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " [14] ,Port D pin 14 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " [13] ,Port D pin 13 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 12. " [12] ,Port D pin 12 output type" "Push-pull,Open-drain"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Port D pin 11 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " [10] ,Port D pin 10 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 9. " [9] ,Port D pin 9 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " [8] ,Port D pin 8 output type" "Push-pull,Open-drain"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Port D pin 7 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " [6] ,Port D pin 6 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " [5] ,Port D pin 5 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " [4] ,Port D pin 4 output type" "Push-pull,Open-drain"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,Port D pin 3 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " [2] ,Port D pin 2 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " [1] ,Port D pin 1 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " [0] ,Port D pin 0 output type" "Push-pull,Open-drain"
|
|
line.long 0x08 "OSPEEDR,GPIO Port D Output Speed Register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR[15] ,Port D pin 15 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 28.--29. " [14] ,Port D pin 14 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 26.--27. " [13] ,Port D pin 13 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 24.--25. " [12] ,Port D pin 12 output speed" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x08 22.--23. " [11] ,Port D pin 11 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 20.--21. " [10] ,Port D pin 10 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 18.--19. " [9] ,Port D pin 9 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 16.--17. " [8] ,Port D pin 8 output speed" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x08 14.--15. " [7] ,Port D pin 7 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 12.--13. " [6] ,Port D pin 6 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 10.--11. " [5] ,Port D pin 5 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 8.--9. " [4] ,Port D pin 4 output speed" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x08 6.--7. " [3] ,Port D pin 3 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 4.--5. " [2] ,Port D pin 2 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 2.--3. " [1] ,Port D pin 1 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 0.--1. " [0] ,Port D pin 0 output speed" "Low,Medium,High,Very high"
|
|
line.long 0x0C "PUPDR,GPIO Port D Pull-up/Pull-down Register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR[15] ,Port D pin 15 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " [14] ,Port D pin 14 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " [13] ,Port D pin 13 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 24.--25. " [12] ,Port D pin 12 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
newline
|
|
bitfld.long 0x0C 22.--23. " [11] ,Port D pin 11 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " [10] ,Port D pin 10 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 18.--19. " [9] ,Port D pin 9 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " [8] ,Port D pin 8 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
newline
|
|
bitfld.long 0x0C 14.--15. " [7] ,Port D pin 7 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 12.--13. " [6] ,Port D pin 6 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " [5] ,Port D pin 5 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " [4] ,Port D pin 4 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
newline
|
|
bitfld.long 0x0C 6.--7. " [3] ,Port D pin 3 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " [2] ,Port D pin 2 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " [1] ,Port D pin 1 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " [0] ,Port D pin 0 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "IDR,GPIO Port D Input Data Register"
|
|
bitfld.long 0x00 15. " IDR[15] ,Port D pin 15 input data" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Port D pin 14 input data" "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Port D pin 13 input data" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Port D pin 12 input data" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Port D pin 11 input data" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Port D pin 10 input data" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,Port D pin 9 input data" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Port D pin 8 input data" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Port D pin 7 input data" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Port D pin 6 input data" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Port D pin 5 input data" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Port D pin 4 input data" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Port D pin 3 input data" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Port D pin 2 input data" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Port D pin 1 input data" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Port D pin 0 input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ODR_SET/CLR,GPIO Port D Output Data Set/Clear Register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR[15] ,Port D pin 15 output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " [14] ,Port D pin 14 output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " [13] ,Port D pin 13 output data" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " [12] ,Port D pin 12 output data" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " [11] ,Port D pin 11 output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " [10] ,Port D pin 10 output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " [9] ,Port D pin 9 output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " [8] ,Port D pin 8 output data" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " [7] ,Port D pin 7 output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " [6] ,Port D pin 6 output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " [5] ,Port D pin 5 output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " [4] ,Port D pin 4 output data" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " [3] ,Port D pin 3 output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " [2] ,Port D pin 2 output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " [1] ,Port D pin 1 output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " [0] ,Port D pin 0 output data" "Low,High"
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F750*")||cpuis("STM32F767BI"))
|
|
if ((per.l(ad:0x40020C00+0x1C)&0x10000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO Port D Configuration Lock Register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
newline
|
|
bitfld.long 0x00 15. " LCK[15] ,Port D pin 15 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " [14] ,Port D pin 14 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " [13] ,Port D pin 13 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " [12] ,Port D pin 12 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Port D pin 11 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " [10] ,Port D pin 10 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " [9] ,Port D pin 9 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " [8] ,Port D pin 8 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Port D pin 7 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " [6] ,Port D pin 6 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " [5] ,Port D pin 5 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " [4] ,Port D pin 4 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Port D pin 3 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " [2] ,Port D pin 2 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " [1] ,Port D pin 1 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " [0] ,Port D pin 0 configuration lock" "Not locked,Locked"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO Port D Configuration Lock Register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
newline
|
|
rbitfld.long 0x00 15. " LCK[15] ,Port D pin 15 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 14. " [14] ,Port D pin 14 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 13. " [13] ,Port D pin 13 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 12. " [12] ,Port D pin 12 configuration lock" "Not locked,Locked"
|
|
newline
|
|
rbitfld.long 0x00 11. " [11] ,Port D pin 11 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 10. " [10] ,Port D pin 10 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 9. " [9] ,Port D pin 9 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 8. " [8] ,Port D pin 8 configuration lock" "Not locked,Locked"
|
|
newline
|
|
rbitfld.long 0x00 7. " [7] ,Port D pin 7 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 6. " [6] ,Port D pin 6 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 5. " [5] ,Port D pin 5 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 4. " [4] ,Port D pin 4 configuration lock" "Not locked,Locked"
|
|
newline
|
|
rbitfld.long 0x00 3. " [3] ,Port D pin 3 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 2. " [2] ,Port D pin 2 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 1. " [1] ,Port D pin 1 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 0. " [0] ,Port D pin 0 configuration lock" "Not locked,Locked"
|
|
endif
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO Port D Configuration Lock Register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
newline
|
|
bitfld.long 0x00 15. " LCK[15] ,Port D pin 15 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " [14] ,Port D pin 14 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " [13] ,Port D pin 13 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " [12] ,Port D pin 12 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Port D pin 11 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " [10] ,Port D pin 10 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " [9] ,Port D pin 9 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " [8] ,Port D pin 8 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Port D pin 7 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " [6] ,Port D pin 6 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " [5] ,Port D pin 5 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " [4] ,Port D pin 4 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Port D pin 3 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " [2] ,Port D pin 2 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " [1] ,Port D pin 1 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " [0] ,Port D pin 0 configuration lock" "Not locked,Locked"
|
|
endif
|
|
endif
|
|
newline
|
|
sif cpuis("STM32F745*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port D Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port D pin 7" ",,,,,SPI1_MOSI/I2S1_SD,,USART2_CK,SPDIF_RX0,,,,FMC_NE1,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port D pin 6" ",,,,,SPI3_MOSI/I2S3_SD,SAI1_SD_A,USART2_RX,,,,,FMC_NWAIT,DCMI_D10,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port D pin 5" ",,,,,,,USART2_TX,,,,,FMC_NWE,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port D pin 4" ",,,,,,,USART2_RTS,,,,,FMC_NOE,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port D pin 3" ",,,,,SPI2_SCK/I2S2_CK,,USART2_CTS,,,,,FMC_CLK,DCMI_D5,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port D pin 2" "TRACED2,,TIM3_ETR,,,,,,UART5_RX,,,,SDMMC_CMD,DCMI_D11,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port D pin 1" ",,,,,,,,UART4_TX,CAN1_TX,,,FMC_D3,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port D pin 0" ",,,,,,,,UART4_RX,CAN1_RX,,,FMC_D2,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port D Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port D pin 15" ",,TIM4_CH4,,,,,,UART8_RTS,,,,FMC_D1,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port D pin 14" ",,TIM4_CH3,,,,,,UART8_CTS,,,,FMC_D0,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port D pin 13" ",,TIM4_CH2,LPTIM1_OUT,I2C4_SDA,,,,,,SAI2_SCK_A,,FMC_A18,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port D pin 12" ",,TIM4_CH1,LPTIM1_IN1,I2C4_SCL,,,USART3_RTS,,,SAI2_FS_A,,FMC_A17/FMC_ALE,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port D pin 11" ",,,,I2C4_SMBA,,,USART3_CTS,,,SAI2_SD_A,,FMC_A16/FMC_CLE,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port D pin 10" ",,,,,,,USART3_CK,,,,,FMC_D15,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port D pin 9" ",,,,,,,USART3_RX,,,,,FMC_D14,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port D pin 8" ",,,,,,,USART3_TX,SPDIF_RX1,,,,FMC_D13,,,EVENTOUT"
|
|
elif cpuis("STM32F746*")||cpuis("STM32F756*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port D Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port D pin 7" ",,,,,SPI1_MOSI/I2S1_SD,,USART2_CK,SPDIF_RX0,,,,FMC_NE1,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port D pin 6" ",,,,,SPI3_MOSI/I2S3_SD,SAI1_SD_A,USART2_RX,,,,,FMC_NWAIT,DCMI_D10,LCD_B2,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port D pin 5" ",,,,,,,USART2_TX,,,,,FMC_NWE,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port D pin 4" ",,,,,,,USART2_RTS,,,,,FMC_NOE,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port D pin 3" ",,,,,SPI2_SCK/I2S2_CK,,USART2_CTS,,,,,FMC_CLK,DCMI_D5,LCD_G7,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port D pin 2" "TRACED2,,TIM3_ETR,,,,,,UART5_RX,,,,SDMMC_CMD,DCMI_D11,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port D pin 1" ",,,,,,,,UART4_TX,CAN1_TX,,,FMC_D3,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port D pin 0" ",,,,,,,,UART4_RX,CAN1_RX,,,FMC_D2,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port D Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port D pin 15" ",,TIM4_CH4,,,,,,UART8_RTS,,,,FMC_D1,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port D pin 14" ",,TIM4_CH3,,,,,,UART8_CTS,,,,FMC_D0,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port D pin 13" ",,TIM4_CH2,LPTIM1_OUT,I2C4_SDA,,,,,,SAI2_SCK_A,,FMC_A18,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port D pin 12" ",,TIM4_CH1,LPTIM1_IN1,I2C4_SCL,,,USART3_RTS,,,SAI2_FS_A,,FMC_A17/FMC_ALE,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port D pin 11" ",,,,I2C4_SMBA,,,USART3_CTS,,,SAI2_SD_A,,FMC_A16/FMC_CLE,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port D pin 10" ",,,,,,,USART3_CK,,,,,FMC_D15,,LCD_B3,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port D pin 9" ",,,,,,,USART3_RX,,,,,FMC_D14,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port D pin 8" ",,,,,,,USART3_TX,SPDIF_RX1,,,,FMC_D13,,,EVENTOUT"
|
|
elif cpuis("STM32F750*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port D Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port D pin 7" ",,,,,,,USART2_CK,SPDIF_RX0,,,,FMC_NE1,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port D pin 6" ",,,,,SPI3_MOSI/I2S3_SD,SAI1_SD_A,USART2_RX,,,,,FMC_NWAIT,DCMI_D10,LCD_B2,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port D pin 5" ",,,,,,,USART2_TX,,,,,FMC_NWE,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port D pin 4" ",,,,,,,USART2_RTS,,,,,FMC_NOE,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port D pin 3" ",,,,,SPI2_SCK/I2S2_CK,,USART2_CTS,,,,,FMC_CLK,DCMI_D5,LCD_G7,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port D pin 2" "TRACED2,,TIM3_ETR,,,,,,UART5_RX,,,,SDMMC1_CMD,DCMI_D11,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port D pin 1" ",,,,,,,,,CAN1_TX,,,FMC_D3,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port D pin 0" ",,,,,,,,,CAN1_RX,,,FMC_D2,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port D Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port D pin 15" ",,TIM4_CH4,,,,,,UART8_RTS,,,,FMC_D1,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port D pin 14" ",,TIM4_CH3,,,,,,UART8_CTS,,,,FMC_D0,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port D pin 13" ",,TIM4_CH2,LPTIM1_OUT,I2C4_SDA,,,,,QUADSPI_BK1_IO3,SAI2_SCK_A,,FMC_A18,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port D pin 12" ",,TIM4_CH1,LPTIM1_IN1,I2C4_SCL,,,USART3_RTS,,QUADSPI_BK1_IO1,SAI2_FS_A,,FMC_A17/FMC_ALE,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port D pin 11" ",,,,I2C4_SMBA,,,USART3_CTS,,QUADSPI_BK1_IO0,SAI2_SD_A,,FMC_A16/FMC_CLE,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port D pin 10" ",,,,,,,USART3_CK,,,,,FMC_D15,,LCD_B3,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port D pin 9" ",,,,,,,USART3_RX,,,,,FMC_D14,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port D pin 8" ",,,,,,,USART3_TX,SPDIF_RX1,,,,FMC_D13,,,EVENTOUT"
|
|
elif cpuis("STM32F765*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port D Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port D pin 7" ",,,DFSDM1_DATAIN4,,SPI1_MOSI/I2S1_SD,DFSDM1_CKIN1,USART2_CK,SPDIF_RX0,,,SDMMC2_CMD,FMC_NE1,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port D pin 6" ",,,DFSDM1_CKIN4,,SPI3_MOSI/I2S3_SD,SAI1_SD_A,USART2_RX,,,DFSDM1_DATAIN1,SDMMC2_CK,FMC_NWAIT,DCMI_D10,LCD_B2,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port D pin 5" ",,,,,,,USART2_TX,,,,,FMC_NWE,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port D pin 4" ",,,,,,DFSDM1_CKIN0,USART2_RTS,,,,,FMC_NOE,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port D pin 3" ",,,DFSDM1_CKOUT,,SPI2_SCK/I2S2_CK,DFSDM1_DATAIN0,USART2_CTS,,,,,FMC_CLK,DCMI_D5,LCD_G7,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port D pin 2" "TRACED2,,TIM3_ETR,,,,,,UART5_RX,,,,SDMMC_CMD,DCMI_D11,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port D pin 1" ",,,DFSDM1_DATAIN6,,,DFSDM1_CKIN7,,UART4_TX,CAN1_TX,,,FMC_D3,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port D pin 0" ",,,DFSDM1_CKIN6,,,DFSDM1_DATAIN7,,UART4_RX,CAN1_RX,,,FMC_D2,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port D Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port D pin 15" ",,TIM4_CH4,,,,,,UART8_RTS,,,,FMC_D1,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port D pin 14" ",,TIM4_CH3,,,,,,UART8_CTS,,,,FMC_D0,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port D pin 13" ",,TIM4_CH2,LPTIM1_OUT,I2C4_SDA,,,,,QUADSPI_BK1_IO3,SAI2_SCK_A,,FMC_A18,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port D pin 12" ",,TIM4_CH1,LPTIM1_IN1,I2C4_SCL,,,USART3_RTS,,QUADSPI_BK1_IO1,SAI2_FS_A,,FMC_A17/FMC_ALE,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port D pin 11" ",,,,I2C4_SMBA,,,USART3_CTS,,QUADSPI_BK1_IO0,SAI2_SD_A,,FMC_A16/FMC_CLE,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port D pin 10" ",,,DFSDM1_CKOUT,,,,USART3_CK,,,,,FMC_D15,,LCD_B3,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port D pin 9" ",,,DFSDM1_DATAIN3,,,,USART3_RX,,,,,FMC_D14,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port D pin 8" ",,,DFSDM1_CKIN3,,,,USART3_TX,SPDIF_RX1,,,,FMC_D13,,,EVENTOUT"
|
|
elif cpuis("STM32F76?A*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port D Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port D pin 7" ",,,DFSDM1_DATAIN4,,SPI1_MOSI/I2S1_SD,DFSDM1_CKIN1,USART2_CK,SPDIF_RX0,,,,FMC_NE1,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port D pin 6" ",,,DFSDM1_CKIN4,,SPI3_MOSI/I2S3_SD,SAI1_SD_A,USART2_RX,,,DFSDM1_DATAIN1,,FMC_NWAIT,DCMI_D10,LCD_B2,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port D pin 5" ",,,,,,,USART2_TX,,,,,FMC_NWE,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port D pin 4" ",,,,,,DFSDM1_CKIN0,USART2_RTS,,,,,FMC_NOE,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port D pin 3" ",,,DFSDM1_CKOUT,,SPI2_SCK/I2S2_CK,DFSDM1_DATAIN0,USART2_CTS,,,,,FMC_CLK,DCMI_D5,LCD_G7,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port D pin 2" "TRACED2,,TIM3_ETR,,,,,,UART5_RX,,,,SDMMC_CMD,DCMI_D11,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port D pin 1" ",,,DFSDM1_DATAIN6,,,DFSDM1_CKIN7,,UART4_TX,CAN1_TX,,,FMC_D3,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port D pin 0" ",,,DFSDM1_CKIN6,,,DFSDM1_DATAIN7,,UART4_RX,CAN1_RX,,,FMC_D2,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port D Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port D pin 15" ",,TIM4_CH4,,,,,,UART8_RTS,,,,FMC_D1,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port D pin 14" ",,TIM4_CH3,,,,,,UART8_CTS,,,,FMC_D0,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port D pin 13" ",,TIM4_CH2,LPTIM1_OUT,I2C4_SDA,,,,,QUADSPI_BK1_IO3,SAI2_SCK_A,,FMC_A18,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port D pin 12" ",,TIM4_CH1,LPTIM1_IN1,I2C4_SCL,,,USART3_RTS,,QUADSPI_BK1_IO1,SAI2_FS_A,,FMC_A17/FMC_ALE,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port D pin 11" ",,,,I2C4_SMBA,,,USART3_CTS,,QUADSPI_BK1_IO0,SAI2_SD_A,,FMC_A16/FMC_CLE,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port D pin 10" ",,,DFSDM1_CKOUT,,,,USART3_CK,,,,,FMC_D15,,LCD_B3,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port D pin 9" ",,,DFSDM1_DATAIN3,,,,USART3_RX,,,,,FMC_D14,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port D pin 8" ",,,DFSDM1_CKIN3,,,,USART3_TX,SPDIF_RX1,,,,FMC_D13,,,EVENTOUT"
|
|
newline
|
|
elif cpuis("STM32F76*")||cpuis("STM32F75*")||cpuis("STM32F74*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port D Alternate Function Low Register"
|
|
sif (cpuis("STM32F767BI"))
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port D pin 7" ",,,DFSDM1_DATAIN4,,SPI1_MOSI/I2S1_SD,DFSDM1_CKIN1,USART2_CK,SPDIF_RX0,,,SDMMC2_CMD,FMC_NE1,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port D pin 6" ",,,DFSDM1_CKIN4,,SPI3_MOSI/I2S3_SD,SAI1_SD_A,USART2_RX,,,DFSDM1_DATAIN1,SDMMC2_CK,FMC_NWAIT,DCMI_D10,LCD_B2,EVENTOUT"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port D pin 7" ",,,DFSDM1_DATAIN4,,SPI1_MOSI/I2S1_SD,DFSDM1_CKIN1,USART2_CK,SPDIF_RX0,,,,FMC_NE1,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port D pin 6" ",,,DFSDM1_CKIN4,,SPI3_MOSI/I2S3_SD,SAI1_SD_A,USART2_RX,,,DFSDM1_DATAIN1,,FMC_NWAIT,DCMI_D10,LCD_B2,EVENTOUT"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port D pin 5" ",,,,,,,USART2_TX,,,,,FMC_NWE,,,EVENTOUT"
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port D pin 4" ",,,,,,DFSDM1_CKIN0,USART2_RTS,,,,,FMC_NOE,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port D pin 3" ",,,DFSDM1_CKOUT,,SPI2_SCK/I2S2_CK,DFSDM1_DATAIN0,USART2_CTS,,,,,FMC_CLK,DCMI_D5,LCD_G7,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port D pin 2" "TRACED2,,TIM3_ETR,,,,,,UART5_RX,,,,SDMMC_CMD,DCMI_D11,,EVENTOUT"
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port D pin 1" ",,,DFSDM1_DATAIN6,,,DFSDM1_CKIN7,,UART4_TX,CAN1_TX,,,FMC_D3,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port D pin 0" ",,,DFSDM1_CKIN6,,,DFSDM1_DATAIN7,,UART4_RX,CAN1_RX,,,FMC_D2,,,EVENTOUT"
|
|
newline
|
|
line.long 0x04 "AFRH,GPIO Port D Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port D pin 15" ",,TIM4_CH4,,,,,,UART8_RTS,,,,FMC_D1,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port D pin 14" ",,TIM4_CH3,,,,,,UART8_CTS,,,,FMC_D0,,,EVENTOUT"
|
|
newline
|
|
sif (cpuis("STM32F767BI"))
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port D pin 13" ",,TIM4_CH2,LPTIM1_OUT,I2C4_SDA,,,,,QUADSPI_BK1_IO3,SAI2_SCK_A,,FMC_A18,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port D pin 12" ",,TIM4_CH1,LPTIM1_IN1,I2C4_SCL,,,USART3_RTS,,QUADSPI_BK1_IO1,SAI2_FS_A,,FMC_A17/FMC_ALE,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port D pin 11" ",,,,I2C4_SMBA,,,USART3_CTS,,QUADSPI_BK1_IO0,SAI2_SD_A,,FMC_A16/FMC_CLE,,,EVENTOUT"
|
|
else
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port D pin 13" ",,TIM4_CH2,LPTIM1_OUT,I2C4_SDA,,,,,,SAI2_SCK_A,,FMC_A18,,,EVENTOUT"
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port D pin 12" ",,TIM4_CH1,LPTIM1_IN1,I2C4_SCL,,,USART3_RTS,,,SAI2_FS_A,,FMC_A17/FMC_ALE,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port D pin 11" ",,,,I2C4_SMBA,,,USART3_CTS,,,SAI2_SD_A,,FMC_A16/FMC_CLE,,,EVENTOUT"
|
|
endif
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port D pin 10" ",,,DFSDM1_CKOUT,,,,USART3_CK,,,,,FMC_D15,,LCD_B3,EVENTOUT"
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port D pin 9" ",,,DFSDM1_DATAIN3,,,,USART3_RX,,,,,FMC_D14,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port D pin 8" ",,,DFSDM1_CKIN3,,,,USART3_TX,SPDIF_RX1,,,,FMC_D13,,,EVENTOUT"
|
|
elif (cpuis("STM32F722*")||cpuis("STM32F723*")||cpuis("STM32F732*")||cpuis("STM32F733*"))
|
|
sif (cpuis("STM32F72?R*")||cpuis("STM32F73?R*"))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "AFRL,GPIO Port D Alternate Function Low Register"
|
|
bitfld.long 0x00 8.--11. " AFRL[2] ,Alternate function selection for port D pin 2" "TRACED2,,TIM3_ETR,,,,,,UART5_RX,,,,SDMMC1_CMD,,,EVENTOUT"
|
|
else
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port D Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port D pin 7" ",,,,,,,USART2_CK,,,,SDMMC2_CMD,FMC_NE1,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port D pin 6" ",,,,,SPI3_MOSI/I2S3_SD,SAI1_SD_A,USART2_RX,,,,SDMMC2_CK,FMC_NWAIT,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port D pin 5" ",,,,,,,USART2_TX,,,,,FMC_NWE,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port D pin 4" ",,,,,,,USART2_RTS,,,,,FMC_NOE,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port D pin 3" ",,,,,SPI2_SCK/I2S2_CK,,USART2_CTS,,,,,FMC_CLK,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port D pin 2" "TRACED2,,TIM3_ETR,,,,,,UART5_RX,,,,SDMMC1_CMD,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port D pin 1" ",,,,,,,,,CAN1_TX,,,FMC_D3,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port D pin 0" ",,,,,,,,,CAN1_RX,,,FMC_D2,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port D Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port D pin 15" ",,TIM4_CH4,,,,,,UART8_RTS,,,,FMC_D1,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port D pin 14" ",,TIM4_CH3,,,,,,UART8_CTS,,,,FMC_D0,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port D pin 13" ",,TIM4_CH2,LPTIM1_OUT,,,,,,QUADSPI_BK1_IO3,SAI2_SCK_A,,FMC_A18,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port D pin 12" ",,TIM4_CH1,LPTIM1_IN1,,,,USART3_RTS,,QUADSPI_BK1_IO1,SAI2_FS_A,,FMC_A17/FMC_ALE,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port D pin 11" ",,,,,,,USART3_CTS,,QUADSPI_BK1_IO0,SAI2_SD_A,,FMC_A16/FMC_CLE,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port D pin 10" ",,,,,,,USART3_CK,,,,,FMC_D15,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port D pin 9" ",,,,,,,USART3_RX,,,,,FMC_D14,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port D pin 8" ",,,,,,,USART3_TX,,,,,FMC_D13,,,EVENTOUT"
|
|
endif
|
|
elif cpuis("STM32F730*")
|
|
sif cpuis("STM32F730R8")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "AFRL,GPIO Port D Alternate Function Low Register"
|
|
bitfld.long 0x00 8.--11. " AFRL[2] ,Alternate function selection for port D pin 2" "TRACED2,,TIM3_ETR,,,,,,UART5_RX,,,,SDMMC1_CMD,,,EVENTOUT"
|
|
else
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port D Alternate Function Low Register"
|
|
sif cpuis("STM32F730V8")
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port D pin 7" ",,,,,,,USART2_CK,,,,,FMC_NE1,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port D pin 6" ",,,,,SPI3_MOSI/I2S3_SD,SAI1_SD_A,USART2_RX,,,,,FMC_NWAIT,,,EVENTOUT"
|
|
else
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port D pin 7" ",,,,,,,USART2_CK,,,,SDMMC2_CMD,FMC_NE1,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port D pin 6" ",,,,,SPI3_MOSI/I2S3_SD,SAI1_SD_A,USART2_RX,,,,SDMMC2_CK,FMC_NWAIT,,,EVENTOUT"
|
|
endif
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port D pin 5" ",,,,,,,USART2_TX,,,,,FMC_NWE,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port D pin 4" ",,,,,,,USART2_RTS,,,,,FMC_NOE,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port D pin 3" ",,,,,SPI2_SCK/I2S2_CK,,USART2_CTS,,,,,FMC_CLK,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port D pin 2" "TRACED2,,TIM3_ETR,,,,,,UART5_RX,,,,SDMMC1_CMD,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port D pin 1" ",,,,,,,,,CAN1_TX,,,FMC_D3,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port D pin 0" ",,,,,,,,,CAN1_RX,,,FMC_D2,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port D Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port D pin 15" ",,TIM4_CH4,,,,,,UART8_RTS,,,,FMC_D1,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port D pin 14" ",,TIM4_CH3,,,,,,UART8_CTS,,,,FMC_D0,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port D pin 13" ",,TIM4_CH2,LPTIM1_OUT,,,,,,QUADSPI_BK1_IO3,SAI2_SCK_A,,FMC_A18,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port D pin 12" ",,TIM4_CH1,LPTIM1_IN1,,,,USART3_RTS,,QUADSPI_BK1_IO1,SAI2_FS_A,,FMC_A17/FMC_ALE,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port D pin 11" ",,,,,,,USART3_CTS,,QUADSPI_BK1_IO0,SAI2_SD_A,,FMC_A16/FMC_CLE,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port D pin 10" ",,,,,,,USART3_CK,,,,,FMC_D15,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port D pin 9" ",,,,,,,USART3_RX,,,,,FMC_D14,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port D pin 8" ",,,,,,,USART3_TX,,,,,FMC_D13,,,EVENTOUT"
|
|
endif
|
|
else
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port D Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port D pin 7" ",,,DFSDM1_DATAIN4,,SPI1_MOSI/I2S1_SD,DFSDM1_CKIN1,USART2_CK,SPDIF_RX0,,,SDMMC2_CMD,FMC_NE1,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port D pin 6" ",,,DFSDM1_CKIN4,,SPI3_MOSI/I2S3_SD,SAI1_SD_A,USART2_RX,,,DFSDM1_DATAIN1,SDMMC2_CK,FMC_NWAIT,DCMI_D10,LCD_B2,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port D pin 5" ",,,,,,,USART2_TX,,,,,FMC_NWE,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port D pin 4" ",,,,,,DFSDM1_CKIN0,USART2_RTS,,,,,FMC_NOE,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port D pin 3" ",,,DFSDM1_CKOUT,,SPI2_SCK/I2S2_CK,DFSDM1_DATAIN0,USART2_CTS,,,,,FMC_CLK,DCMI_D5,LCD_G7,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port D pin 2" "TRACED2,,TIM3_ETR,,,,,,UART5_RX,,,,SDMMC_CMD,DCMI_D11,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port D pin 1" ",,,DFSDM1_DATAIN6,,,DFSDM1_CKIN7,,UART4_TX,CAN1_TX,,,FMC_D3,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port D pin 0" ",,,DFSDM1_CKIN6,,,DFSDM1_DATAIN7,,UART4_RX,CAN1_RX,,,FMC_D2,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port D Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port D pin 15" ",,TIM4_CH4,,,,,,UART8_RTS,,,,FMC_D1,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port D pin 14" ",,TIM4_CH3,,,,,,UART8_CTS,,,,FMC_D0,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port D pin 13" ",,TIM4_CH2,LPTIM1_OUT,I2C4_SDA,,,,,QUADSPI_BK1_IO3,SAI2_SCK_A,,FMC_A18,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port D pin 12" ",,TIM4_CH1,LPTIM1_IN1,I2C4_SCL,,,USART3_RTS,,QUADSPI_BK1_IO1,SAI2_FS_A,,FMC_A17/FMC_ALE,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port D pin 11" ",,,,I2C4_SMBA,,,USART3_CTS,,QUADSPI_BK1_IO0,SAI2_SD_A,,FMC_A16/FMC_CLE,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port D pin 10" ",,,DFSDM1_CKOUT,,,,USART3_CK,,,,,FMC_D15,,LCD_B3,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port D pin 9" ",,,DFSDM1_DATAIN3,,,,USART3_RX,,,,,FMC_D14,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port D pin 8" ",,,DFSDM1_CKIN3,,,,USART3_TX,SPDIF_RX1,,,,FMC_D13,,,EVENTOUT"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif (!cpuis("STM32F72?R*")&&!cpuis("STM32F73?R*"))
|
|
tree "GPIO E"
|
|
base ad:0x40021000
|
|
width 13.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "MODER,GPIO Port E Mode Register"
|
|
bitfld.long 0x00 30.--31. " MODER[15] ,Port E pin 15 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " [14] ,Port E pin 14 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " [13] ,Port E pin 13 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 24.--25. " [12] ,Port E pin 12 mode" "Input,Output,Alternate function,Analog"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " [11] ,Port E pin 11 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " [10] ,Port E pin 10 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " [9] ,Port E pin 9 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " [8] ,Port E pin 8 mode" "Input,Output,Alternate function,Analog"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " [7] ,Port E pin 7 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " [6] ,Port E pin 6 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " [5] ,Port E pin 5 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " [4] ,Port E pin 4 mode" "Input,Output,Alternate function,Analog"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " [3] ,Port E pin 3 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " [2] ,Port E pin 2 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " [1] ,Port E pin 1 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " [0] ,Port E pin 0 mode" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "OTYPER,GPIO Port E Output Type Register"
|
|
bitfld.long 0x04 15. " OT[15] ,Port E pin 15 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " [14] ,Port E pin 14 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " [13] ,Port E pin 13 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 12. " [12] ,Port E pin 12 output type" "Push-pull,Open-drain"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Port E pin 11 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " [10] ,Port E pin 10 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 9. " [9] ,Port E pin 9 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " [8] ,Port E pin 8 output type" "Push-pull,Open-drain"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Port E pin 7 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " [6] ,Port E pin 6 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " [5] ,Port E pin 5 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " [4] ,Port E pin 4 output type" "Push-pull,Open-drain"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,Port E pin 3 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " [2] ,Port E pin 2 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " [1] ,Port E pin 1 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " [0] ,Port E pin 0 output type" "Push-pull,Open-drain"
|
|
line.long 0x08 "OSPEEDR,GPIO Port E Output Speed Register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR[15] ,Port E pin 15 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 28.--29. " [14] ,Port E pin 14 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 26.--27. " [13] ,Port E pin 13 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 24.--25. " [12] ,Port E pin 12 output speed" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x08 22.--23. " [11] ,Port E pin 11 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 20.--21. " [10] ,Port E pin 10 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 18.--19. " [9] ,Port E pin 9 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 16.--17. " [8] ,Port E pin 8 output speed" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x08 14.--15. " [7] ,Port E pin 7 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 12.--13. " [6] ,Port E pin 6 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 10.--11. " [5] ,Port E pin 5 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 8.--9. " [4] ,Port E pin 4 output speed" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x08 6.--7. " [3] ,Port E pin 3 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 4.--5. " [2] ,Port E pin 2 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 2.--3. " [1] ,Port E pin 1 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 0.--1. " [0] ,Port E pin 0 output speed" "Low,Medium,High,Very high"
|
|
line.long 0x0C "PUPDR,GPIO Port E Pull-up/Pull-down Register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR[15] ,Port E pin 15 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " [14] ,Port E pin 14 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " [13] ,Port E pin 13 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 24.--25. " [12] ,Port E pin 12 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
newline
|
|
bitfld.long 0x0C 22.--23. " [11] ,Port E pin 11 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " [10] ,Port E pin 10 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 18.--19. " [9] ,Port E pin 9 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " [8] ,Port E pin 8 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
newline
|
|
bitfld.long 0x0C 14.--15. " [7] ,Port E pin 7 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 12.--13. " [6] ,Port E pin 6 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " [5] ,Port E pin 5 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " [4] ,Port E pin 4 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
newline
|
|
bitfld.long 0x0C 6.--7. " [3] ,Port E pin 3 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " [2] ,Port E pin 2 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " [1] ,Port E pin 1 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " [0] ,Port E pin 0 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "IDR,GPIO Port E Input Data Register"
|
|
bitfld.long 0x00 15. " IDR[15] ,Port E pin 15 input data" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Port E pin 14 input data" "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Port E pin 13 input data" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Port E pin 12 input data" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Port E pin 11 input data" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Port E pin 10 input data" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,Port E pin 9 input data" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Port E pin 8 input data" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Port E pin 7 input data" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Port E pin 6 input data" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Port E pin 5 input data" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Port E pin 4 input data" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Port E pin 3 input data" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Port E pin 2 input data" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Port E pin 1 input data" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Port E pin 0 input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ODR_SET/CLR,GPIO Port E Output Data Set/Clear Register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR[15] ,Port E pin 15 output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " [14] ,Port E pin 14 output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " [13] ,Port E pin 13 output data" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " [12] ,Port E pin 12 output data" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " [11] ,Port E pin 11 output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " [10] ,Port E pin 10 output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " [9] ,Port E pin 9 output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " [8] ,Port E pin 8 output data" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " [7] ,Port E pin 7 output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " [6] ,Port E pin 6 output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " [5] ,Port E pin 5 output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " [4] ,Port E pin 4 output data" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " [3] ,Port E pin 3 output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " [2] ,Port E pin 2 output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " [1] ,Port E pin 1 output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " [0] ,Port E pin 0 output data" "Low,High"
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F750*")||cpuis("STM32F767BI"))
|
|
if ((per.l(ad:0x40021000+0x1C)&0x10000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO Port E Configuration Lock Register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
newline
|
|
bitfld.long 0x00 15. " LCK[15] ,Port E pin 15 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " [14] ,Port E pin 14 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " [13] ,Port E pin 13 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " [12] ,Port E pin 12 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Port E pin 11 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " [10] ,Port E pin 10 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " [9] ,Port E pin 9 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " [8] ,Port E pin 8 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Port E pin 7 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " [6] ,Port E pin 6 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " [5] ,Port E pin 5 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " [4] ,Port E pin 4 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Port E pin 3 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " [2] ,Port E pin 2 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " [1] ,Port E pin 1 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " [0] ,Port E pin 0 configuration lock" "Not locked,Locked"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO Port E Configuration Lock Register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
newline
|
|
rbitfld.long 0x00 15. " LCK[15] ,Port E pin 15 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 14. " [14] ,Port E pin 14 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 13. " [13] ,Port E pin 13 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 12. " [12] ,Port E pin 12 configuration lock" "Not locked,Locked"
|
|
newline
|
|
rbitfld.long 0x00 11. " [11] ,Port E pin 11 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 10. " [10] ,Port E pin 10 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 9. " [9] ,Port E pin 9 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 8. " [8] ,Port E pin 8 configuration lock" "Not locked,Locked"
|
|
newline
|
|
rbitfld.long 0x00 7. " [7] ,Port E pin 7 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 6. " [6] ,Port E pin 6 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 5. " [5] ,Port E pin 5 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 4. " [4] ,Port E pin 4 configuration lock" "Not locked,Locked"
|
|
newline
|
|
rbitfld.long 0x00 3. " [3] ,Port E pin 3 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 2. " [2] ,Port E pin 2 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 1. " [1] ,Port E pin 1 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 0. " [0] ,Port E pin 0 configuration lock" "Not locked,Locked"
|
|
endif
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO Port E Configuration Lock Register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
newline
|
|
bitfld.long 0x00 15. " LCK[15] ,Port E pin 15 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " [14] ,Port E pin 14 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " [13] ,Port E pin 13 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " [12] ,Port E pin 12 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Port E pin 11 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " [10] ,Port E pin 10 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " [9] ,Port E pin 9 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " [8] ,Port E pin 8 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Port E pin 7 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " [6] ,Port E pin 6 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " [5] ,Port E pin 5 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " [4] ,Port E pin 4 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Port E pin 3 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " [2] ,Port E pin 2 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " [1] ,Port E pin 1 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " [0] ,Port E pin 0 configuration lock" "Not locked,Locked"
|
|
endif
|
|
newline
|
|
sif cpuis("STM32F745*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port E Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port E pin 7" ",TIM1_ETR,,,,,,,UART7_Rx,,,,FMC_D4,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port E pin 6" "TRACED3,TIM1_BKIN2,,TIM9_CH2,,SPI4_MOSI,SAI1_SD_A,,,,SAI2_MCK_B,,FMC_A22,DCMI_D7,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port E pin 5" "TRACED2,,,TIM9_CH1,,SPI4_MISO,SAI1_SCK_A,,,,,,FMC_A21,DCMI_D6,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port E pin 4" "TRACED1,,,,,SPI4_NSS,SAI1_FS_A,,,,,,FMC_A20,DCMI_D4,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port E pin 3" "TRACED0,,,,,,SAI1_SD_B,,,,,,FMC_A19,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port E pin 2" "TRACECLK,,,,,SPI4_SCK,SAI1_MCLK_A,,,,,ETH_MII_TXD3,FMC_A23,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port E pin 1" ",,,LPTIM1_IN2,,,,,UART8_Tx,,,,FMC_NBL1,DCMI_D3,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port E pin 0" ",,,TIM4_ETR,LPTIM1_ETR,,,,UART8_Rx,,SAI2_MCK_A,,FMC_NBL0,DCMI_D2,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port E Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port E pin 15" ",TIM1_BKIN,,,,,,,,,,,FMC_D12,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port E pin 14" ",TIM1_CH4,,,,SPI4_MOSI,,,,,SAI2_MCK_B,,FMC_D11,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port E pin 13" ",TIM1_CH3,,,,SPI4_MISO,,,,,SAI2_FS_B,,FMC_D10,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port E pin 12" ",TIM1_CH3N,,,,SPI4_SCK,,,,,SAI2_SCK_B,,FMC_D9,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port E pin 11" ",TIM1_CH2,,,,SPI4_NSS,,,,,SAI2_SD_B,,FMC_D8,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port E pin 10" ",TIM1_CH2N,,,,,,,UART7_CTS,,,,FMC_D7,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port E pin 9" ",TIM1_CH1,,,,,,,UART7_RTS,,,,FMC_D6,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port E pin 8" ",TIM1_CH1N,,,,,,,UART7_Tx,,,,FMC_D5,,,EVENTOUT"
|
|
elif cpuis("STM32F746*")||cpuis("STM32F756*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port E Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port E pin 7" ",TIM1_ETR,,,,,,,UART7_Rx,,,,FMC_D4,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port E pin 6" "TRACED3,TIM1_BKIN2,,TIM9_CH2,,SPI4_MOSI,SAI1_SD_A,,,,SAI2_MCK_B,,FMC_A22,DCMI_D7,LCD_G1,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port E pin 5" "TRACED2,,,TIM9_CH1,,SPI4_MISO,SAI1_SCK_A,,,,,,FMC_A21,DCMI_D6,LCD_G0,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port E pin 4" "TRACED1,,,,,SPI4_NSS,SAI1_FS_A,,,,,,FMC_A20,DCMI_D4,LCD_B0,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port E pin 3" "TRACED0,,,,,,SAI1_SD_B,,,,,,FMC_A19,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port E pin 2" "TRACECLK,,,,,SPI4_SCK,SAI1_MCLK_A,,,,,ETH_MII_TXD3,FMC_A23,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port E pin 1" ",,,LPTIM1_IN2,,,,,UART8_Tx,,,,FMC_NBL1,DCMI_D3,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port E pin 0" ",,,TIM4_ETR,LPTIM1_ETR,,,,UART8_Rx,,SAI2_MCK_A,,FMC_NBL0,DCMI_D2,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port E Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port E pin 15" ",TIM1_BKIN,,,,,,,,,,,FMC_D12,,LCD_R7,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port E pin 14" ",TIM1_CH4,,,,SPI4_MOSI,,,,,SAI2_MCK_B,,FMC_D11,,LCD_CLK,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port E pin 13" ",TIM1_CH3,,,,SPI4_MISO,,,,,SAI2_FS_B,,FMC_D10,,LCD_DE,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port E pin 12" ",TIM1_CH3N,,,,SPI4_SCK,,,,,SAI2_SCK_B,,FMC_D9,,LCD_B4,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port E pin 11" ",TIM1_CH2,,,,SPI4_NSS,,,,,SAI2_SD_B,,FMC_D8,,LCD_G3,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port E pin 10" ",TIM1_CH2N,,,,,,,UART7_CTS,,,,FMC_D7,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port E pin 9" ",TIM1_CH1,,,,,,,UART7_RTS,,,,FMC_D6,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port E pin 8" ",TIM1_CH1N,,,,,,,UART7_Tx,,,,FMC_D5,,,EVENTOUT"
|
|
elif cpuis("STM32F750*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port E Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port E pin 7" ",TIM1_ETR,,,,,,,UART7_Rx,,QUADSPI_BK2_IO0,,FMC_D4,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port E pin 6" "TRACED3,TIM1_BKIN2,,TIM9_CH2,,SPI4_MOSI,SAI1_SD_A,,,,SAI2_MCK_B,,FMC_A22,DCMI_D7,LCD_G1,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port E pin 5" "TRACED2,,,TIM9_CH1,,SPI4_MISO,SAI1_SCK_A,,,,,,FMC_A21,DCMI_D6,LCD_G0,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port E pin 4" "TRACED1,,,,,SPI4_NSS,SAI1_FS_A,,,,,,FMC_A20,DCMI_D4,LCD_B0,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port E pin 3" "TRACED0,,,,,,SAI1_SD_B,,,,,,FMC_A19,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port E pin 2" "TRACECLK,,,,,SPI4_SCK,SAI1_MCLK_A,,,QUADSPI_BK1_IO2,,ETH_MII_TXD3,FMC_A23,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port E pin 1" ",,,LPTIM1_IN2,,,,,UART8_Tx,,,,FMC_NBL1,DCMI_D3,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port E pin 0" ",,,TIM4_ETR,LPTIM1_ETR,,,,UART8_Rx,,SAI2_MCK_A,,FMC_NBL0,DCMI_D2,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port E Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port E pin 15" ",TIM1_BKIN,,,,,,,,,,,FMC_D12,,LCD_R7,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port E pin 14" ",TIM1_CH4,,,,SPI4_MOSI,,,,,SAI2_MCK_B,,FMC_D11,,LCD_CLK,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port E pin 13" ",TIM1_CH3,,,,SPI4_MISO,,,,,SAI2_FS_B,,FMC_D10,,LCD_DE,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port E pin 12" ",TIM1_CH3N,,,,SPI4_SCK,,,,,SAI2_SCK_B,,FMC_D9,,LCD_B4,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port E pin 11" ",TIM1_CH2,,,,SPI4_NSS,,,,,SAI2_SD_B,,FMC_D8,,LCD_G3,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port E pin 10" ",TIM1_CH2N,,,,,,,UART7_CTS,,QUADSPI_BK2_IO3,,FMC_D7,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port E pin 9" ",TIM1_CH1,,,,,,,UART7_RTS,,QUADSPI_BK2_IO2,,FMC_D6,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port E pin 8" ",TIM1_CH1N,,,,,,,UART7_Tx,,QUADSPI_BK2_IO1,,FMC_D5,,,EVENTOUT"
|
|
elif cpuis("STM32F765*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port E Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port E pin 7" ",TIM1_ETR,,,,,DFSDM1_DATAIN2,,UART7_Rx,,QUADSPI_BK2_IO0,,FMC_D4,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port E pin 6" "TRACED3,TIM1_BKIN2,,TIM9_CH2,,SPI4_MOSI,SAI1_SD_A,,,,SAI2_MCK_B,,FMC_A22,DCMI_D7,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port E pin 5" "TRACED2,,,TIM9_CH1,,SPI4_MISO,SAI1_SCK_A,,,,DFSDM1_CKIN3,,FMC_A21,DCMI_D6,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port E pin 4" "TRACED1,,,,,SPI4_NSS,SAI1_FS_A,,,,DFSDM1_DATAIN3,,FMC_A20,DCMI_D4,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port E pin 3" "TRACED0,,,,,,SAI1_SD_B,,,,,,FMC_A19,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port E pin 2" "TRACECLK,,,,,SPI4_SCK,SAI1_MCLK_A,,,QUADSPI_BK1_IO2,,ETH_MII_TXD3,FMC_A23,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port E pin 1" ",,,LPTIM1_IN2,,,,,UART8_Tx,,,,FMC_NBL1,DCMI_D3,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port E pin 0" ",,,TIM4_ETR,LPTIM1_ETR,,,,UART8_Rx,,SAI2_MCK_A,,FMC_NBL0,DCMI_D2,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port E Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port E pin 15" ",TIM1_BKIN,,,,,,,,,,,FMC_D12,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port E pin 14" ",TIM1_CH4,,,,SPI4_MOSI,,,,,SAI2_MCK_B,,FMC_D11,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port E pin 13" ",TIM1_CH3,,,,SPI4_MISO,DFSDM1_CKIN5,,,,SAI2_FS_B,,FMC_D10,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port E pin 12" ",TIM1_CH3N,,,,SPI4_SCK,DFSDM1_DATAIN5,,,,SAI2_SCK_B,,FMC_D9,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port E pin 11" ",TIM1_CH2,,,,SPI4_NSS,DFSDM1_CKIN4,,,,SAI2_SD_B,,FMC_D8,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port E pin 10" ",TIM1_CH2N,,,,,DFSDM1_DATAIN4,,UART7_CTS,,QUADSPI_BK2_IO3,,FMC_D7,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port E pin 9" ",TIM1_CH1,,,,,DFSDM1_CKOUT,,UART7_RTS,,QUADSPI_BK2_IO2,,FMC_D6,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port E pin 8" ",TIM1_CH1N,,,,,DFSDM1_CKIN2,,UART7_Tx,,QUADSPI_BK2_IO1,,FMC_D5,,,EVENTOUT"
|
|
elif cpuis("STM32F768A*")||cpuis("STM32F769A*")||cpuis("STM32F778A*")||cpuis("STM32F779A*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port E Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port E pin 7" ",TIM1_ETR,,,,,DFSDM1_DATAIN2,,UART7_Rx,,QUADSPI_BK2_IO0,,FMC_D4,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port E pin 6" "TRACED3,TIM1_BKIN2,,TIM9_CH2,,SPI4_MOSI,SAI1_SD_A,,,,SAI2_MCK_B,,FMC_A22,DCMI_D7,LCD_G1,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port E pin 5" "TRACED2,,,TIM9_CH1,,SPI4_MISO,SAI1_SCK_A,,,,DFSDM1_CKIN3,,FMC_A21,DCMI_D6,LCD_G0,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port E pin 4" "TRACED1,,,,,SPI4_NSS,SAI1_FS_A,,,,DFSDM1_DATAIN3,,FMC_A20,DCMI_D4,LCD_B0,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port E pin 3" "TRACED0,,,,,,SAI1_SD_B,,,,,,FMC_A19,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port E pin 2" "TRACECLK,,,,,SPI4_SCK,SAI1_MCLK_A,,,QUADSPI_BK1_IO2,,,FMC_A23,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port E pin 1" ",,,LPTIM1_IN2,,,,,UART8_Tx,,,,FMC_NBL1,DCMI_D3,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port E pin 0" ",,,TIM4_ETR,LPTIM1_ETR,,,,UART8_Rx,,SAI2_MCK_A,,FMC_NBL0,DCMI_D2,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port E Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port E pin 15" ",TIM1_BKIN,,,,,,,,,,,FMC_D12,,LCD_R7,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port E pin 14" ",TIM1_CH4,,,,SPI4_MOSI,,,,,SAI2_MCK_B,,FMC_D11,,LCD_CLK,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port E pin 13" ",TIM1_CH3,,,,SPI4_MISO,DFSDM1_CKIN5,,,,SAI2_FS_B,,FMC_D10,,LCD_DE,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port E pin 12" ",TIM1_CH3N,,,,SPI4_SCK,DFSDM1_DATAIN5,,,,SAI2_SCK_B,,FMC_D9,,LCD_B4,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port E pin 11" ",TIM1_CH2,,,,SPI4_NSS,DFSDM1_CKIN4,,,,SAI2_SD_B,,FMC_D8,,LCD_G3,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port E pin 10" ",TIM1_CH2N,,,,,DFSDM1_DATAIN4,,UART7_CTS,,QUADSPI_BK2_IO3,,FMC_D7,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port E pin 9" ",TIM1_CH1,,,,,DFSDM1_CKOUT,,UART7_RTS,,QUADSPI_BK2_IO2,,FMC_D6,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port E pin 8" ",TIM1_CH1N,,,,,DFSDM1_CKIN2,,UART7_Tx,,QUADSPI_BK2_IO1,,FMC_D5,,,EVENTOUT"
|
|
elif (cpuis("STM32F767*"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port E Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port E pin 7" ",TIM1_ETR,,,,,DFSDM1_DATAIN2,,UART7_Rx,,QUADSPI_BK2_IO0,,FMC_D4,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port E pin 6" "TRACED3,TIM1_BKIN2,,TIM9_CH2,,SPI4_MOSI,SAI1_SD_A,,,,SAI2_MCK_B,,FMC_A22,DCMI_D7,LCD_G1,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port E pin 5" "TRACED2,,,TIM9_CH1,,SPI4_MISO,SAI1_SCK_A,,,,DFSDM1_CKIN3,,FMC_A21,DCMI_D6,LCD_G0,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port E pin 4" "TRACED1,,,,,SPI4_NSS,SAI1_FS_A,,,,DFSDM1_DATAIN3,,FMC_A20,DCMI_D4,LCD_B0,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port E pin 3" "TRACED0,,,,,,SAI1_SD_B,,,,,,FMC_A19,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port E pin 2" "TRACECLK,,,,,SPI4_SCK,SAI1_MCLK_A,,,QUADSPI_BK1_IO2,,ETH_MII_TXD3,FMC_A23,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port E pin 1" ",,,LPTIM1_IN2,,,,,UART8_Tx,,,,FMC_NBL1,DCMI_D3,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port E pin 0" ",,TIM4_ETR,LPTIM1_ETR,,,,,UART8_Rx,,SAI2_MCK_A,,FMC_NBL0,DCMI_D2,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port E Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port E pin 15" ",TIM1_BKIN,,,,,,,,,,,FMC_D12,,LCD_R7,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port E pin 14" ",TIM1_CH4,,,,SPI4_MOSI,,,,,SAI2_MCK_B,,FMC_D11,,LCD_CLK,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port E pin 13" ",TIM1_CH3,,,,SPI4_MISO,DFSDM1_CKIN5,,,,SAI2_FS_B,,FMC_D10,,LCD_DE,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port E pin 12" ",TIM1_CH3N,,,,SPI4_SCK,DFSDM1_DATAIN5,,,,SAI2_SCK_B,,FMC_D9,,LCD_B4,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port E pin 11" ",TIM1_CH2,,,,SPI4_NSS,DFSDM1_CKIN4,,,,SAI2_SD_B,,FMC_D8,,LCD_G3,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port E pin 10" ",TIM1_CH2N,,,,,DFSDM1_DATAIN4,,UART7_CTS,,QUADSPI_BK2_IO3,,FMC_D7,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port E pin 9" ",TIM1_CH1,,,,,DFSDM1_CKOUT,,UART7_RTS,,QUADSPI_BK2_IO2,,FMC_D6,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port E pin 8" ",TIM1_CH1N,,,,,DFSDM1_CKIN2,,UART7_Tx,,QUADSPI_BK2_IO1,,FMC_D5,,,EVENTOUT"
|
|
elif (cpuis("STM32F722*")||cpuis("STM32F723*")||cpuis("STM32F730*")||cpuis("STM32F732*")||cpuis("STM32F733*"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port E Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port E pin 7" ",TIM1_ETR,,,,,,,UART7_Rx,,QUADSPI_BK2_IO0,,FMC_D4,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port E pin 6" "TRACED3,TIM1_BKIN2,,TIM9_CH2,,SPI4_MOSI,SAI1_SD_A,,,,SAI2_MCK_B,,FMC_A22,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port E pin 5" "TRACED2,,,TIM9_CH1,,SPI4_MISO,SAI1_SCK_A,,,,,,FMC_A21,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port E pin 4" "TRACED1,,,,,SPI4_NSS,SAI1_FS_A,,,,,,FMC_A20,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port E pin 3" "TRACED0,,,,,,SAI1_SD_B,,,,,,FMC_A19,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port E pin 2" "TRACECLK,,,,,SPI4_SCK,SAI1_MCLK_A,,,QUADSPI_BK1_IO2,,,FMC_A23,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port E pin 1" ",,,LPTIM1_IN2,,,,,UART8_Tx,,,,FMC_NBL1,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port E pin 0" ",,TIM4_ETR,LPTIM1_ETR,,,,,UART8_Rx,,SAI2_MCK_A,,FMC_NBL0,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port E Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port E pin 15" ",TIM1_BKIN,,,,,,,,,,,FMC_D12,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port E pin 14" ",TIM1_CH4,,,,SPI4_MOSI,,,,,SAI2_MCK_B,,FMC_D11,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port E pin 13" ",TIM1_CH3,,,,SPI4_MISO,,,,,SAI2_FS_B,,FMC_D10,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port E pin 12" ",TIM1_CH3N,,,,SPI4_SCK,,,,,SAI2_SCK_B,,FMC_D9,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port E pin 11" ",TIM1_CH2,,,,SPI4_NSS,,,,,SAI2_SD_B,,FMC_D8,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port E pin 10" ",TIM1_CH2N,,,,,,,UART7_CTS,,QUADSPI_BK2_IO3,,FMC_D7,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port E pin 9" ",TIM1_CH1,,,,,,,UART7_RTS,,QUADSPI_BK2_IO2,,FMC_D6,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port E pin 8" ",TIM1_CH1N,,,,,,,UART7_Tx,,QUADSPI_BK2_IO1,,FMC_D5,,,EVENTOUT"
|
|
else
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port E Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port E pin 7" ",TIM1_ETR,,,,,DFSDM1_DATAIN2,,UART7_Rx,,QUADSPI_BK2_IO0,,FMC_D4,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port E pin 6" "TRACED3,TIM1_BKIN2,,TIM9_CH2,,SPI4_MOSI,SAI1_SD_A,,,,SAI2_MCK_B,,FMC_A22,DCMI_D7,LCD_G1,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port E pin 5" "TRACED2,,,TIM9_CH1,,SPI4_MISO,SAI1_SCK_A,,,,DFSDM1_CKIN3,,FMC_A21,DCMI_D6,LCD_G0,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port E pin 4" "TRACED1,,,,,SPI4_NSS,SAI1_FS_A,,,,DFSDM1_DATAIN3,,FMC_A20,DCMI_D4,LCD_B0,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port E pin 3" "TRACED0,,,,,,SAI1_SD_B,,,,,,FMC_A19,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port E pin 2" "TRACECLK,,,,,SPI4_SCK,SAI1_MCLK_A,,,QUADSPI_BK1_IO2,,ETH_MII_TXD3,FMC_A23,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port E pin 1" ",,,LPTIM1_IN2,,,,,UART8_Tx,,,,FMC_NBL1,DCMI_D3,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port E pin 0" ",,,TIM4_ETR,LPTIM1_ETR,,,,UART8_Rx,,SAI2_MCK_A,,FMC_NBL0,DCMI_D2,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port E Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port E pin 15" ",TIM1_BKIN,,,,,,,,,,,FMC_D12,,LCD_R7,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port E pin 14" ",TIM1_CH4,,,,SPI4_MOSI,,,,,SAI2_MCK_B,,FMC_D11,,LCD_CLK,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port E pin 13" ",TIM1_CH3,,,,SPI4_MISO,DFSDM1_CKIN5,,,,SAI2_FS_B,,FMC_D10,,LCD_DE,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port E pin 12" ",TIM1_CH3N,,,,SPI4_SCK,DFSDM1_DATAIN5,,,,SAI2_SCK_B,,FMC_D9,,LCD_B4,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port E pin 11" ",TIM1_CH2,,,,SPI4_NSS,DFSDM1_CKIN4,,,,SAI2_SD_B,,FMC_D8,,LCD_G3,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port E pin 10" ",TIM1_CH2N,,,,,DFSDM1_DATAIN4,,UART7_CTS,,QUADSPI_BK2_IO3,,FMC_D7,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port E pin 9" ",TIM1_CH1,,,,,DFSDM1_CKOUT,,UART7_RTS,,QUADSPI_BK2_IO2,,FMC_D6,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port E pin 8" ",TIM1_CH1N,,,,,DFSDM1_CKIN2,,UART7_Tx,,QUADSPI_BK2_IO1,,FMC_D5,,,EVENTOUT"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif cpuis("STM32F7??Z?")||cpuis("STM32F7??I?")||cpuis("STM32F7??B?")||cpuis("STM32F7??N?")||cpuis("STM32F7??A?")
|
|
tree "GPIO F"
|
|
base ad:0x40021400
|
|
width 13.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "MODER,GPIO Port F Mode Register"
|
|
bitfld.long 0x00 30.--31. " MODER[15] ,Port F pin 15 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " [14] ,Port F pin 14 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " [13] ,Port F pin 13 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 24.--25. " [12] ,Port F pin 12 mode" "Input,Output,Alternate function,Analog"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " [11] ,Port F pin 11 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " [10] ,Port F pin 10 mode" "Input,Output,Alternate function,Analog"
|
|
sif !cpuis("STM32F7??A*")
|
|
bitfld.long 0x00 18.--19. " [9] ,Port F pin 9 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " [8] ,Port F pin 8 mode" "Input,Output,Alternate function,Analog"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " [7] ,Port F pin 7 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " [6] ,Port F pin 6 mode" "Input,Output,Alternate function,Analog"
|
|
else
|
|
newline
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x00 10.--11. " [5] ,Port F pin 5 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " [4] ,Port F pin 4 mode" "Input,Output,Alternate function,Analog"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " [3] ,Port F pin 3 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " [2] ,Port F pin 2 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " [1] ,Port F pin 1 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " [0] ,Port F pin 0 mode" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "OTYPER,GPIO Port F Output Type Register"
|
|
bitfld.long 0x04 15. " OT[15] ,Port F pin 15 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " [14] ,Port F pin 14 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " [13] ,Port F pin 13 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 12. " [12] ,Port F pin 12 output type" "Push-pull,Open-drain"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Port F pin 11 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " [10] ,Port F pin 10 output type" "Push-pull,Open-drain"
|
|
sif !cpuis("STM32F7??A*")
|
|
bitfld.long 0x04 9. " [9] ,Port F pin 9 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " [8] ,Port F pin 8 output type" "Push-pull,Open-drain"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Port F pin 7 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " [6] ,Port F pin 6 output type" "Push-pull,Open-drain"
|
|
else
|
|
newline
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x04 5. " [5] ,Port F pin 5 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " [4] ,Port F pin 4 output type" "Push-pull,Open-drain"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,Port F pin 3 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " [2] ,Port F pin 2 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " [1] ,Port F pin 1 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " [0] ,Port F pin 0 output type" "Push-pull,Open-drain"
|
|
line.long 0x08 "OSPEEDR,GPIO Port F Output Speed Register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR[15] ,Port F pin 15 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 28.--29. " [14] ,Port F pin 14 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 26.--27. " [13] ,Port F pin 13 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 24.--25. " [12] ,Port F pin 12 output speed" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x08 22.--23. " [11] ,Port F pin 11 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 20.--21. " [10] ,Port F pin 10 output speed" "Low,Medium,High,Very high"
|
|
sif !cpuis("STM32F7??A*")
|
|
bitfld.long 0x08 18.--19. " [9] ,Port F pin 9 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 16.--17. " [8] ,Port F pin 8 output speed" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x08 14.--15. " [7] ,Port F pin 7 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 12.--13. " [6] ,Port F pin 6 output speed" "Low,Medium,High,Very high"
|
|
else
|
|
newline
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x08 10.--11. " [5] ,Port F pin 5 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 8.--9. " [4] ,Port F pin 4 output speed" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x08 6.--7. " [3] ,Port F pin 3 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 4.--5. " [2] ,Port F pin 2 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 2.--3. " [1] ,Port F pin 1 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 0.--1. " [0] ,Port F pin 0 output speed" "Low,Medium,High,Very high"
|
|
line.long 0x0C "PUPDR,GPIO Port F Pull-up/Pull-down Register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR[15] ,Port F pin 15 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " [14] ,Port F pin 14 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " [13] ,Port F pin 13 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 24.--25. " [12] ,Port F pin 12 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
newline
|
|
bitfld.long 0x0C 22.--23. " [11] ,Port F pin 11 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " [10] ,Port F pin 10 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
sif !cpuis("STM32F7??A*")
|
|
bitfld.long 0x0C 18.--19. " [9] ,Port F pin 9 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " [8] ,Port F pin 8 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
newline
|
|
bitfld.long 0x0C 14.--15. " [7] ,Port F pin 7 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 12.--13. " [6] ,Port F pin 6 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
else
|
|
newline
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x0C 10.--11. " [5] ,Port F pin 5 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " [4] ,Port F pin 4 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
newline
|
|
bitfld.long 0x0C 6.--7. " [3] ,Port F pin 3 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " [2] ,Port F pin 2 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " [1] ,Port F pin 1 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " [0] ,Port F pin 0 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "IDR,GPIO Port F Input Data Register"
|
|
bitfld.long 0x00 15. " IDR[15] ,Port F pin 15 input data" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Port F pin 14 input data" "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Port F pin 13 input data" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Port F pin 12 input data" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Port F pin 11 input data" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Port F pin 10 input data" "Low,High"
|
|
sif !cpuis("STM32F7??A*")
|
|
bitfld.long 0x00 9. " [9] ,Port F pin 9 input data" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Port F pin 8 input data" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Port F pin 7 input data" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Port F pin 6 input data" "Low,High"
|
|
else
|
|
newline
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x00 5. " [5] ,Port F pin 5 input data" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Port F pin 4 input data" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Port F pin 3 input data" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Port F pin 2 input data" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Port F pin 1 input data" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Port F pin 0 input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ODR_SET/CLR,GPIO Port F Output Data Set/Clear Register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR[15] ,Port F pin 15 output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " [14] ,Port F pin 14 output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " [13] ,Port F pin 13 output data" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " [12] ,Port F pin 12 output data" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " [11] ,Port F pin 11 output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " [10] ,Port F pin 10 output data" "Low,High"
|
|
sif !cpuis("STM32F7??A*")
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " [9] ,Port F pin 9 output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " [8] ,Port F pin 8 output data" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " [7] ,Port F pin 7 output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " [6] ,Port F pin 6 output data" "Low,High"
|
|
else
|
|
newline
|
|
textfld " "
|
|
endif
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " [5] ,Port F pin 5 output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " [4] ,Port F pin 4 output data" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " [3] ,Port F pin 3 output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " [2] ,Port F pin 2 output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " [1] ,Port F pin 1 output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " [0] ,Port F pin 0 output data" "Low,High"
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F750*")||cpuis("STM32F767BI"))
|
|
if ((per.l(ad:0x40021400+0x1C)&0x10000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO Port F Configuration Lock Register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
newline
|
|
bitfld.long 0x00 15. " LCK[15] ,Port F pin 15 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " [14] ,Port F pin 14 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " [13] ,Port F pin 13 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " [12] ,Port F pin 12 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Port F pin 11 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " [10] ,Port F pin 10 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " [9] ,Port F pin 9 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " [8] ,Port F pin 8 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Port F pin 7 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " [6] ,Port F pin 6 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " [5] ,Port F pin 5 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " [4] ,Port F pin 4 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Port F pin 3 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " [2] ,Port F pin 2 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " [1] ,Port F pin 1 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " [0] ,Port F pin 0 configuration lock" "Not locked,Locked"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO Port F Configuration Lock Register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
newline
|
|
rbitfld.long 0x00 15. " LCK[15] ,Port F pin 15 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 14. " [14] ,Port F pin 14 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 13. " [13] ,Port F pin 13 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 12. " [12] ,Port F pin 12 configuration lock" "Not locked,Locked"
|
|
newline
|
|
rbitfld.long 0x00 11. " [11] ,Port F pin 11 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 10. " [10] ,Port F pin 10 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 9. " [9] ,Port F pin 9 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 8. " [8] ,Port F pin 8 configuration lock" "Not locked,Locked"
|
|
newline
|
|
rbitfld.long 0x00 7. " [7] ,Port F pin 7 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 6. " [6] ,Port F pin 6 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 5. " [5] ,Port F pin 5 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 4. " [4] ,Port F pin 4 configuration lock" "Not locked,Locked"
|
|
newline
|
|
rbitfld.long 0x00 3. " [3] ,Port F pin 3 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 2. " [2] ,Port F pin 2 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 1. " [1] ,Port F pin 1 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 0. " [0] ,Port F pin 0 configuration lock" "Not locked,Locked"
|
|
endif
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO Port F Configuration Lock Register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
newline
|
|
bitfld.long 0x00 15. " LCK[15] ,Port F pin 15 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " [14] ,Port F pin 14 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " [13] ,Port F pin 13 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " [12] ,Port F pin 12 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Port F pin 11 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " [10] ,Port F pin 10 configuration lock" "Not locked,Locked"
|
|
sif !cpuis("STM32F7??A*")
|
|
bitfld.long 0x00 9. " [9] ,Port F pin 9 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " [8] ,Port F pin 8 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Port F pin 7 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " [6] ,Port F pin 6 configuration lock" "Not locked,Locked"
|
|
else
|
|
newline
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x00 5. " [5] ,Port F pin 5 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " [4] ,Port F pin 4 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Port F pin 3 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " [2] ,Port F pin 2 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " [1] ,Port F pin 1 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " [0] ,Port F pin 0 configuration lock" "Not locked,Locked"
|
|
endif
|
|
newline
|
|
sif cpuis("STM32F745*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port F Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port F pin 7" ",,,TIM11_CH1,,SPI5_SCK,SAI1_MCLK_B,,UART7_Tx,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port F pin 6" ",,,TIM10_CH1,,SPI5_NSS,SAI1_SD_B,,UART7_Rx,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port F pin 5" ",,,,,,,,,,,,FMC_A5,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port F pin 4" ",,,,,,,,,,,,FMC_A4,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port F pin 3" ",,,,,,,,,,,,FMC_A3,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port F pin 2" ",,,,I2C2_SMBA,,,,,,,,FMC_A2,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port F pin 1" ",,,,I2C2_SCL,,,,,,,,FMC_A1,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port F pin 0" ",,,,I2C2_SDA,,,,,,,,FMC_A0,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port F Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port F pin 15" ",,,,I2C4_SDA,,,,,,,,FMC_A9,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port F pin 14" ",,,,I2C4_SCL,,,,,,,,FMC_A8,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port F pin 13" ",,,,I2C4_SMBA,,,,,,,,FMC_A7,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port F pin 12" ",,,,,,,,,,,,FMC_A6,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port F pin 11" ",,,,,SPI5_MOSI,,,,,SAI2_SD_B,,FMC_SDNRAS,DCMI_D12,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port F pin 10" ",,,,,,,,,,10,,,DCMI_D11,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port F pin 9" ",,,,,SPI5_MOSI,SAI1_FS_B,,UART7_CTS,TIM14_CH1,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port F pin 8" ",,,,,SPI5_MISO,SAI1_SCK_B,,UART7_RTS,TIM13_CH1,,,,,,EVENTOUT"
|
|
elif cpuis("STM32F746*")||cpuis("STM32F756*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port F Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port F pin 7" ",,,TIM11_CH1,,SPI5_SCK,SAI1_MCLK_B,,UART7_Tx,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port F pin 6" ",,,TIM10_CH1,,SPI5_NSS,SAI1_SD_B,,UART7_Rx,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port F pin 5" ",,,,,,,,,,,,FMC_A5,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port F pin 4" ",,,,,,,,,,,,FMC_A4,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port F pin 3" ",,,,,,,,,,,,FMC_A3,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port F pin 2" ",,,,I2C2_SMBA,,,,,,,,FMC_A2,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port F pin 1" ",,,,I2C2_SCL,,,,,,,,FMC_A1,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port F pin 0" ",,,,I2C2_SDA,,,,,,,,FMC_A0,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port F Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port F pin 15" ",,,,I2C4_SDA,,,,,,,,FMC_A9,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port F pin 14" ",,,,I2C4_SCL,,,,,,,,FMC_A8,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port F pin 13" ",,,,I2C4_SMBA,,,,,,,,FMC_A7,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port F pin 12" ",,,,,,,,,,,,FMC_A6,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port F pin 11" ",,,,,SPI5_MOSI,,,,,SAI2_SD_B,,FMC_SDNRAS,DCMI_D12,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port F pin 10" ",,,,,,,,,,,,,DCMI_D11,LCD_DE,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port F pin 9" ",,,,,SPI5_MOSI,SAI1_FS_B,,UART7_CTS,TIM14_CH1,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port F pin 8" ",,,,,SPI5_MISO,SAI1_SCK_B,,UART7_RTS,TIM13_CH1,,,,,,EVENTOUT"
|
|
elif cpuis("STM32F750*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port F Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port F pin 7" ",,,TIM11_CH1,,SPI5_SCK,SAI1_MCLK_B,,UART7_Tx,QUADSPI_BK1_IO2,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port F pin 6" ",,,TIM10_CH1,,SPI5_NSS,SAI1_SD_B,,UART7_Rx,QUADSPI_BK1_IO3,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port F pin 5" ",,,,,,,,,,,,FMC_A5,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port F pin 4" ",,,,,,,,,,,,FMC_A4,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port F pin 3" ",,,,,,,,,,,,FMC_A3,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port F pin 2" ",,,,I2C2_SMBA,,,,,,,,FMC_A2,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port F pin 1" ",,,,I2C2_SCL,,,,,,,,FMC_A1,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port F pin 0" ",,,,I2C2_SDA,,,,,,,,FMC_A0,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port F Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port F pin 15" ",,,,I2C4_SDA,,,,,,,,FMC_A9,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port F pin 14" ",,,,I2C4_SCL,,,,,,,,FMC_A8,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port F pin 13" ",,,,I2C4_SMBA,,,,,,,,FMC_A7,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port F pin 12" ",,,,,,,,,,,,FMC_A6,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port F pin 11" ",,,,,SPI5_MOSI,,,,,SAI2_SD_B,,FMC_SDNRAS,DCMI_D12,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port F pin 10" ",,,,,,,,,,,,,DCMI_D11,LCD_DE,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port F pin 9" ",,,,,SPI5_MOSI,SAI1_FS_B,,UART7_CTS,TIM14_CH1,QUADSPI_BK1_IO1,,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port F pin 8" ",,,,,SPI5_MISO,SAI1_SCK_B,,UART7_RTS,TIM13_CH1,QUADSPI_BK1_IO0,,,,,EVENTOUT"
|
|
elif cpuis("STM32F765*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port F Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port F pin 7" ",,,TIM11_CH1,,SPI5_SCK,SAI1_MCLK_B,,UART7_Tx,QUADSPI_BK1_IO2,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port F pin 6" ",,,TIM10_CH1,,SPI5_NSS,SAI1_SD_B,,UART7_Rx,QUADSPI_BK1_IO3,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port F pin 5" ",,,,,,,,,,,,FMC_A5,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port F pin 4" ",,,,,,,,,,,,FMC_A4,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port F pin 3" ",,,,,,,,,,,,FMC_A3,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port F pin 2" ",,,,I2C2_SMBA,,,,,,,,FMC_A2,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port F pin 1" ",,,,I2C2_SCL,,,,,,,,FMC_A1,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port F pin 0" ",,,,I2C2_SDA,,,,,,,,FMC_A0,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port F Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port F pin 15" ",,,,I2C4_SDA,,,,,,,,FMC_A9,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port F pin 14" ",,,,I2C4_SCL,,DFSDM1_CKIN6,,,,,,FMC_A8,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port F pin 13" ",,,,I2C4_SMBA,,DFSDM1_DATAIN6,,,,,,FMC_A7,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port F pin 12" ",,,,,,,,,,,,FMC_A6,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port F pin 11" ",,,,,SPI5_MOSI,,,,,SAI2_SD_B,,FMC_SDNRAS,DCMI_D12,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port F pin 10" ",,,,,,,,,QUADSPI_CLK,,,,DCMI_D11,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port F pin 9" ",,,,,SPI5_MOSI,SAI1_FS_B,,UART7_CTS,TIM14_CH1,QUADSPI_BK1_IO1,,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port F pin 8" ",,,,,SPI5_MISO,SAI1_SCK_B,,UART7_RTS,TIM13_CH1,QUADSPI_BK1_IO0,,,,,EVENTOUT"
|
|
elif cpuis("STM32F767*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port F Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port F pin 7" ",,,TIM11_CH1,,SPI5_SCK,SAI1_MCLK_B,,UART7_Tx,QUADSPI_BK1_IO2,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port F pin 6" ",,,TIM10_CH1,,SPI5_NSS,SAI1_SD_B,,UART7_Rx,QUADSPI_BK1_IO3,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port F pin 5" ",,,,,,,,,,,,FMC_A5,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port F pin 4" ",,,,,,,,,,,,FMC_A4,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port F pin 3" ",,,,,,,,,,,,FMC_A3,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port F pin 2" ",,,,I2C2_SMBA,,,,,,,,FMC_A2,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port F pin 1" ",,,,I2C2_SCL,,,,,,,,FMC_A1,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port F pin 0" ",,,,I2C2_SDA,,,,,,,,FMC_A0,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port F Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port F pin 15" ",,,,I2C4_SDA,,,,,,,,FMC_A9,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port F pin 14" ",,,,I2C4_SCL,,DFSDM1_CKIN6,,,,,,FMC_A8,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port F pin 13" ",,,,I2C4_SMBA,,DFSDM1_DATAIN6,,,,,,FMC_A7,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port F pin 12" ",,,,,,,,,,,,FMC_A6,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port F pin 11" ",,,,,SPI5_MOSI,,,,,SAI2_SD_B,,FMC_SDNRAS,DCMI_D12,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port F pin 10" ",,,,,,,,,QUADSPI_CLK,,,,DCMI_D11,LCD_DE,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port F pin 9" ",,,,,SPI5_MOSI,SAI1_FS_B,,UART7_CTS,TIM14_CH1,QUADSPI_BK1_IO1,,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port F pin 8" ",,,,,SPI5_MISO,SAI1_SCK_B,,UART7_RTS,TIM13_CH1,QUADSPI_BK1_IO0,,,,,EVENTOUT"
|
|
elif cpuis("STM32F768A*")||cpuis("STM32F769A*")||cpuis("STM32F778A*")||cpuis("STM32F779A*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port F Alternate Function Low Register"
|
|
bitfld.long 0x00 20.--23. " AFRL[5] ,Alternate function selection for port F pin 5" ",,,,,,,,,,,,FMC_A5,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port F pin 4" ",,,,,,,,,,,,FMC_A4,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port F pin 3" ",,,,,,,,,,,,FMC_A3,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port F pin 2" ",,,,I2C2_SMBA,,,,,,,,FMC_A2,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port F pin 1" ",,,,I2C2_SCL,,,,,,,,FMC_A1,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port F pin 0" ",,,,I2C2_SDA,,,,,,,,FMC_A0,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port F Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port F pin 15" ",,,,I2C4_SDA,,,,,,,,FMC_A9,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port F pin 14" ",,,,I2C4_SCL,,DFSDM1_CKIN6,,,,,,FMC_A8,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port F pin 13" ",,,,I2C4_SMBA,,DFSDM1_DATAIN6,,,,,,FMC_A7,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port F pin 12" ",,,,,,,,,,,,FMC_A6,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port F pin 11" ",,,,,SPI5_MOSI,,,,,SAI2_SD_B,,FMC_SDNRAS,DCMI_D12,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port F pin 10" ",,,,,,,,,QUADSPI_CLK,,,,DCMI_D11,LCD_DE,EVENTOUT"
|
|
elif (cpuis("STM32F722*")||cpuis("STM32F723*")||cpuis("STM32F730*")||cpuis("STM32F732*")||cpuis("STM32F733*"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port F Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port F pin 7" ",,,TIM11_CH1,,SPI5_SCK,SAI1_MCLK_B,,UART7_Tx,QUADSPI_BK1_IO2,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port F pin 6" ",,,TIM10_CH1,,SPI5_NSS,SAI1_SD_B,,UART7_Rx,QUADSPI_BK1_IO3,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port F pin 5" ",,,,,,,,,,,,FMC_A5,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port F pin 4" ",,,,,,,,,,,,FMC_A4,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port F pin 3" ",,,,,,,,,,,,FMC_A3,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port F pin 2" ",,,,I2C2_SMBA,,,,,,,,FMC_A2,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port F pin 1" ",,,,I2C2_SCL,,,,,,,,FMC_A1,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port F pin 0" ",,,,I2C2_SDA,,,,,,,,FMC_A0,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port F Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port F pin 15" ",,,,,,,,,,,,FMC_A9,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port F pin 14" ",,,,,,,,,,,,FMC_A8,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port F pin 13" ",,,,,,,,,,,,FMC_A7,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port F pin 12" ",,,,,,,,,,,,FMC_A6,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port F pin 11" ",,,,,SPI5_MOSI,,,,,SAI2_SD_B,,FMC_SDNRAS,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port F pin 10" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port F pin 9" ",,,,,SPI5_MOSI,SAI1_FS_B,,UART7_CTS,TIM14_CH1,QUADSPI_BK1_IO1,,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port F pin 8" ",,,,,SPI5_MISO,SAI1_SCK_B,,UART7_RTS,TIM13_CH1,QUADSPI_BK1_IO0,,,,,EVENTOUT"
|
|
else
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port F Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port F pin 7" ",,,TIM11_CH1,,SPI5_SCK,SAI1_MCLK_B,,UART7_Tx,QUADSPI_BK1_IO2,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port F pin 6" ",,,TIM10_CH1,,SPI5_NSS,SAI1_SD_B,,UART7_Rx,QUADSPI_BK1_IO3,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port F pin 5" ",,,,,,,,,,,,FMC_A5,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port F pin 4" ",,,,,,,,,,,,FMC_A4,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port F pin 3" ",,,,,,,,,,,,FMC_A3,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port F pin 2" ",,,,I2C2_SMBA,,,,,,,,FMC_A2,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port F pin 1" ",,,,I2C2_SCL,,,,,,,,FMC_A1,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port F pin 0" ",,,,I2C2_SDA,,,,,,,,FMC_A0,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port F Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port F pin 15" ",,,,I2C4_SDA,,,,,,,,FMC_A9,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port F pin 14" ",,,,I2C4_SCL,,DFSDM1_CKIN6,,,,,,FMC_A8,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port F pin 13" ",,,,I2C4_SMBA,,DFSDM1_DATAIN6,,,,,,FMC_A7,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port F pin 12" ",,,,,,,,,,,,FMC_A6,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port F pin 11" ",,,,,SPI5_MOSI,,,,,SAI2_SD_B,,FMC_SDNRAS,DCMI_D12,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port F pin 10" ",,,,,,,,,QUADSPI_CLK,,,,DCMI_D11,LCD_DE,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port F pin 9" ",,,,,SPI5_MOSI,SAI1_FS_B,,UART7_CTS,TIM14_CH1,QUADSPI_BK1_IO1,,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port F pin 8" ",,,,,SPI5_MISO,SAI1_SCK_B,,UART7_RTS,TIM13_CH1,QUADSPI_BK1_IO0,,,,,EVENTOUT"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F7??Z?")||cpuis("STM32F7??I?")||cpuis("STM32F7??B?")||cpuis("STM32F7??N?")||cpuis("STM32F7??A?"))
|
|
tree "GPIO G"
|
|
base ad:0x40021800
|
|
width 13.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "MODER,GPIO Port G Mode Register"
|
|
bitfld.long 0x00 30.--31. " MODER[15] ,Port G pin 15 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " [14] ,Port G pin 14 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " [13] ,Port G pin 13 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 24.--25. " [12] ,Port G pin 12 mode" "Input,Output,Alternate function,Analog"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " [11] ,Port G pin 11 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " [10] ,Port G pin 10 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " [9] ,Port G pin 9 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " [8] ,Port G pin 8 mode" "Input,Output,Alternate function,Analog"
|
|
newline
|
|
sif !cpuis("STM32F730Z8")&&!cpuis("STM32F730I8")
|
|
bitfld.long 0x00 14.--15. " [7] ,Port G pin 7 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " [6] ,Port G pin 6 mode" "Input,Output,Alternate function,Analog"
|
|
else
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x00 10.--11. " [5] ,Port G pin 5 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " [4] ,Port G pin 4 mode" "Input,Output,Alternate function,Analog"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " [3] ,Port G pin 3 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " [2] ,Port G pin 2 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " [1] ,Port G pin 1 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " [0] ,Port G pin 0 mode" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "OTYPER,GPIO Port G Output Type Register"
|
|
bitfld.long 0x04 15. " OT[15] ,Port G pin 15 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " [14] ,Port G pin 14 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " [13] ,Port G pin 13 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 12. " [12] ,Port G pin 12 output type" "Push-pull,Open-drain"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Port G pin 11 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " [10] ,Port G pin 10 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 9. " [9] ,Port G pin 9 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " [8] ,Port G pin 8 output type" "Push-pull,Open-drain"
|
|
newline
|
|
sif !cpuis("STM32F730Z8")&&!cpuis("STM32F730I8")
|
|
bitfld.long 0x04 7. " [7] ,Port G pin 7 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " [6] ,Port G pin 6 output type" "Push-pull,Open-drain"
|
|
else
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x04 5. " [5] ,Port G pin 5 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " [4] ,Port G pin 4 output type" "Push-pull,Open-drain"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,Port G pin 3 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " [2] ,Port G pin 2 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " [1] ,Port G pin 1 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " [0] ,Port G pin 0 output type" "Push-pull,Open-drain"
|
|
line.long 0x08 "OSPEEDR,GPIO Port G Output Speed Register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR[15] ,Port G pin 15 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 28.--29. " [14] ,Port G pin 14 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 26.--27. " [13] ,Port G pin 13 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 24.--25. " [12] ,Port G pin 12 output speed" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x08 22.--23. " [11] ,Port G pin 11 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 20.--21. " [10] ,Port G pin 10 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 18.--19. " [9] ,Port G pin 9 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 16.--17. " [8] ,Port G pin 8 output speed" "Low,Medium,High,Very high"
|
|
newline
|
|
sif !cpuis("STM32F730Z8")&&!cpuis("STM32F730I8")
|
|
bitfld.long 0x08 14.--15. " [7] ,Port G pin 7 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 12.--13. " [6] ,Port G pin 6 output speed" "Low,Medium,High,Very high"
|
|
else
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x08 10.--11. " [5] ,Port G pin 5 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 8.--9. " [4] ,Port G pin 4 output speed" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x08 6.--7. " [3] ,Port G pin 3 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 4.--5. " [2] ,Port G pin 2 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 2.--3. " [1] ,Port G pin 1 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 0.--1. " [0] ,Port G pin 0 output speed" "Low,Medium,High,Very high"
|
|
line.long 0x0C "PUPDR,GPIO Port G Pull-up/Pull-down Register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR[15] ,Port G pin 15 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " [14] ,Port G pin 14 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " [13] ,Port G pin 13 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 24.--25. " [12] ,Port G pin 12 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
newline
|
|
bitfld.long 0x0C 22.--23. " [11] ,Port G pin 11 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " [10] ,Port G pin 10 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 18.--19. " [9] ,Port G pin 9 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " [8] ,Port G pin 8 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
newline
|
|
sif !cpuis("STM32F730Z8")&&!cpuis("STM32F730I8")
|
|
bitfld.long 0x0C 14.--15. " [7] ,Port G pin 7 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 12.--13. " [6] ,Port G pin 6 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
else
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x0C 10.--11. " [5] ,Port G pin 5 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " [4] ,Port G pin 4 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
newline
|
|
bitfld.long 0x0C 6.--7. " [3] ,Port G pin 3 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " [2] ,Port G pin 2 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " [1] ,Port G pin 1 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " [0] ,Port G pin 0 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "IDR,GPIO Port G Input Data Register"
|
|
bitfld.long 0x00 15. " IDR[15] ,Port G pin 15 input data" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Port G pin 14 input data" "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Port G pin 13 input data" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Port G pin 12 input data" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Port G pin 11 input data" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Port G pin 10 input data" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,Port G pin 9 input data" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Port G pin 8 input data" "Low,High"
|
|
newline
|
|
sif !cpuis("STM32F730Z8")&&!cpuis("STM32F730I8")
|
|
bitfld.long 0x00 7. " [7] ,Port G pin 7 input data" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Port G pin 6 input data" "Low,High"
|
|
else
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x00 5. " [5] ,Port G pin 5 input data" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Port G pin 4 input data" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Port G pin 3 input data" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Port G pin 2 input data" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Port G pin 1 input data" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Port G pin 0 input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ODR_SET/CLR,GPIO Port G Output Data Set/Clear Register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR[15] ,Port G pin 15 output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " [14] ,Port G pin 14 output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " [13] ,Port G pin 13 output data" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " [12] ,Port G pin 12 output data" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " [11] ,Port G pin 11 output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " [10] ,Port G pin 10 output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " [9] ,Port G pin 9 output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " [8] ,Port G pin 8 output data" "Low,High"
|
|
newline
|
|
sif !cpuis("STM32F730Z8")&&!cpuis("STM32F730I8")
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " [7] ,Port G pin 7 output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " [6] ,Port G pin 6 output data" "Low,High"
|
|
else
|
|
textfld " "
|
|
endif
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " [5] ,Port G pin 5 output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " [4] ,Port G pin 4 output data" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " [3] ,Port G pin 3 output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " [2] ,Port G pin 2 output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " [1] ,Port G pin 1 output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " [0] ,Port G pin 0 output data" "Low,High"
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F750*")||cpuis("STM32F767BI"))
|
|
if ((per.l(ad:0x40021800+0x1C)&0x10000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO Port G Configuration Lock Register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
newline
|
|
bitfld.long 0x00 15. " LCK[15] ,Port G pin 15 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " [14] ,Port G pin 14 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " [13] ,Port G pin 13 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " [12] ,Port G pin 12 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Port G pin 11 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " [10] ,Port G pin 10 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " [9] ,Port G pin 9 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " [8] ,Port G pin 8 configuration lock" "Not locked,Locked"
|
|
newline
|
|
sif !cpuis("STM32F730Z8")&&!cpuis("STM32F730I8")
|
|
bitfld.long 0x00 7. " [7] ,Port G pin 7 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " [6] ,Port G pin 6 configuration lock" "Not locked,Locked"
|
|
else
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x00 5. " [5] ,Port G pin 5 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " [4] ,Port G pin 4 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Port G pin 3 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " [2] ,Port G pin 2 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " [1] ,Port G pin 1 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " [0] ,Port G pin 0 configuration lock" "Not locked,Locked"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO Port G Configuration Lock Register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
newline
|
|
rbitfld.long 0x00 15. " LCK[15] ,Port G pin 15 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 14. " [14] ,Port G pin 14 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 13. " [13] ,Port G pin 13 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 12. " [12] ,Port G pin 12 configuration lock" "Not locked,Locked"
|
|
newline
|
|
rbitfld.long 0x00 11. " [11] ,Port G pin 11 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 10. " [10] ,Port G pin 10 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 9. " [9] ,Port G pin 9 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 8. " [8] ,Port G pin 8 configuration lock" "Not locked,Locked"
|
|
newline
|
|
sif !cpuis("STM32F730Z8")&&!cpuis("STM32F730I8")
|
|
rbitfld.long 0x00 7. " [7] ,Port G pin 7 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 6. " [6] ,Port G pin 6 configuration lock" "Not locked,Locked"
|
|
else
|
|
textfld " "
|
|
endif
|
|
rbitfld.long 0x00 5. " [5] ,Port G pin 5 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 4. " [4] ,Port G pin 4 configuration lock" "Not locked,Locked"
|
|
newline
|
|
rbitfld.long 0x00 3. " [3] ,Port G pin 3 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 2. " [2] ,Port G pin 2 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 1. " [1] ,Port G pin 1 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 0. " [0] ,Port G pin 0 configuration lock" "Not locked,Locked"
|
|
endif
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO Port G Configuration Lock Register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
newline
|
|
bitfld.long 0x00 15. " LCK[15] ,Port G pin 15 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " [14] ,Port G pin 14 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " [13] ,Port G pin 13 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " [12] ,Port G pin 12 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Port G pin 11 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " [10] ,Port G pin 10 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " [9] ,Port G pin 9 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " [8] ,Port G pin 8 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Port G pin 7 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " [6] ,Port G pin 6 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " [5] ,Port G pin 5 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " [4] ,Port G pin 4 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Port G pin 3 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " [2] ,Port G pin 2 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " [1] ,Port G pin 1 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " [0] ,Port G pin 0 configuration lock" "Not locked,Locked"
|
|
endif
|
|
newline
|
|
sif (cpuis("STM32F722*")||cpuis("STM32F723*")||cpuis("STM32F730*")||cpuis("STM32F732*")||cpuis("STM32F733*"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port G Alternate Function Low Register"
|
|
sif !cpuis("STM32F730*")
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port G pin 7" ",,,,,,,,USART6_CK,,,,FMC_INT,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port G pin 6" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port G pin 5" ",,,,,,,,,,,,FMC_A15/FMC_BA1,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port G pin 4" ",,,,,,,,,,,,FMC_A14/FMC_BA0,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port G pin 3" ",,,,,,,,,,,,FMC_A13,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port G pin 2" ",,,,,,,,,,,,FMC_A12,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port G pin 1" ",,,,,,,,,,,,FMC_A11,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port G pin 0" ",,,,,,,,,,,,FMC_A10,,,EVENTOUT"
|
|
else
|
|
bitfld.long 0x00 20.--23. " AFRL[5] ,Alternate function selection for port G pin 5" ",,,,,,,,,,,,FMC_A15/FMC_BA1,,,EVENTOUT"
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port G pin 4" ",,,,,,,,,,,,FMC_A14/FMC_BA0,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port G pin 3" ",,,,,,,,,,,,FMC_A13,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port G pin 2" ",,,,,,,,,,,,FMC_A12,,,EVENTOUT"
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port G pin 1" ",,,,,,,,,,,,FMC_A11,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port G pin 0" ",,,,,,,,,,,,FMC_A10,,,EVENTOUT"
|
|
endif
|
|
line.long 0x04 "AFRH,GPIO Port G Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port G pin 15" ",,,,,,,,USART6_CTS,,,,FMC_SDNCAS,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port G pin 14" "TRACED1,,,LPTIM1_ETR,,,,,USART6_TX,QUADSPI_BK2_IO3,,,FMC_A25,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port G pin 13" "TRACED0,,,LPTIM1_OUT,,,,,UART6_CTS,,,,FMC_A24,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port G pin 12" ",,,LPTIM1_IN1,,,,,USART6_RTS,,,SDMMC2_D3,FMC_NE4,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port G pin 11" ",,,,,,,,,,SDMMC2_D2,,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port G pin 10" ",,,,,,,,,,SAI2_SD_B,SDMMC2_D1,FMC_NE3,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port G pin 9" ",,,,,,,,USART6_RX,QUADSPI_BK2_IO2,SAI2_FS_B,SDMMC2_D0,FMC_NE2/FMC_NCE,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port G pin 8" ",,,,,,,,USART6_RTS,,,,FMC_SDCLK,,,EVENTOUT"
|
|
elif cpuis("STM32F745*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port G Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port G pin 7" ",,,,,,SAI1_MCLK_A,,USART6_CK,,,,FMC_INT,DCMI_D13,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port G pin 6" ",,,,,,,,,,,,FMC_NE3,DCMI_D12,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port G pin 5" ",,,,,,,,,,,,FMC_A15/FMC_BA1,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port G pin 4" ",,,,,,,,,,,,FMC_A14/FMC_BA0,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port G pin 3" ",,,,,,,,,,,,FMC_A13,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port G pin 2" ",,,,,,,,,,,,FMC_A12,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port G pin 1" ",,,,,,,,,,,,FMC_A11,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port G pin 0" ",,,,,,,,,,,,FMC_A10,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port G Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port G pin 15" ",,,,,,,,USART6_CTS,,,,FMC_SDNCAS,DCMI_D13,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port G pin 14" "TRACED1,,,LPTIM1_ETR,,SPI6_MOSI,,,UART6_TX,,,ETH_MII_TXD1/ETH_RMII_TXD1,FMC_A25,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port G pin 13" "TRACED0,,,LPTIM1_OUT,,SPI6_SCK,,,UART6_CTS,,,ETH_MII_TXD0/ETH_RMII_TXD0,FMC_A24,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port G pin 12" ",,,LPTIM1_IN1,,SPI6_MISO,,SPDIF_RX1,USART6_RTS,,,,FMC_NE4,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port G pin 11" ",,,,,SPI1_SCK/I2S1_WS,,SPDIF_RX0,,,,ETH_MII_TX_EN/ETH_RMII_TX_EN,,DCMI_D3,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port G pin 10" ",,,,,SPI1_NSS/I2S1_WS,,,,,SAI2_SD_B,,FMC_NE3,DCMI_D2,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port G pin 9" ",,,,,SPI6_NSS,,SPDIF_RX3,USART6_RX,QUADSPI_BK2_IO2,SAI2_FS_B,SDMMC2_D0,FMC_NE2/FMC_NCE,DCMI_VSYNC,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port G pin 8" ",,,,,SPI6_NSS,,SPDIF_RX2,USART6_RTS,,,ETH_PPS_OUT,FMC_SDCLK,,,EVENTOUT"
|
|
elif cpuis("STM32F750*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port G Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port G pin 7" ",,,,,,,,USART6_CK,,,,FMC_INT,DCMI_D13,LCD_CLK,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port G pin 6" ",,,,,,,,,,,,,DCMI_D12,LCD_R7,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port G pin 5" ",,,,,,,,,,,,FMC_A15/FMC_BA1,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port G pin 4" ",,,,,,,,,,,,FMC_A14/FMC_BA0,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port G pin 3" ",,,,,,,,,,,,FMC_A13,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port G pin 2" ",,,,,,,,,,,,FMC_A12,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port G pin 1" ",,,,,,,,,,,,FMC_A11,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port G pin 0" ",,,,,,,,,,,,FMC_A10,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port G Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port G pin 15" ",,,,,,,,USART6_CTS,,,,FMC_SDNCAS,DCMI_D13,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port G pin 14" "TRACED1,,,LPTIM1_ETR,,SPI6_MOSI,,,UART6_TX,QUADSPI_BK2_IO3,,ETH_MII_TXD1/ETH_RMII_TXD1,FMC_A25,,LCD_B0,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port G pin 13" "TRACED0,,,LPTIM1_OUT,,SPI6_SCK,,,UART6_CTS,,,ETH_MII_TXD0/ETH_RMII_TXD0,FMC_A24,,LCD_R0,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port G pin 12" ",,,LPTIM1_IN1,,SPI6_MISO,,SPDIFRX_IN1,USART6_RTS,LCD_B4,,,FMC_NE4,,LCD_B1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port G pin 11" ",,,,,,,SPDIFRX_IN0,,,,ETH_MII_TX_EN/ETH_RMII_TX_EN,,DCMI_D3,LCD_B3,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port G pin 10" ",,,,,,,,,LCD_G3,SAI2_SD_B,,FMC_NE3,DCMI_D2,LCD_B2,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port G pin 9" ",,,,,,,SPDIFRX3_IN3,USART6_RX,QUADSPI_BK2_IO2,SAI2_FS_B,,FMC_NE2/FMC_NCE,DCMI_VSYNC,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port G pin 8" ",,,,,SPI6_NSS,,SPDIFRX_IN2,USART6_RTS,,,ETH_PPS_OUT,FMC_SDCLK,,,EVENTOUT"
|
|
elif cpuis("STM32F7??A*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port G Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port G pin 7" ",,,,,,SAI1_MCLK_A,,USART6_CK,,,,FMC_INT,DCMI_D13,LCD_CLK,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port G pin 6" ",,,,,,,,,,,,FMC_NE3,DCMI_D12,LCD_R7,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port G pin 5" ",,,,,,,,,,,,FMC_A15/FMC_BA1,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port G pin 4" ",,,,,,,,,,,,FMC_A14/FMC_BA0,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port G pin 3" ",,,,,,,,,,,,FMC_A13,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port G pin 2" ",,,,,,,,,,,,FMC_A12,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port G pin 1" ",,,,,,,,,,,,FMC_A11,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port G pin 0" ",,,,,,,,,,,,FMC_A10,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port G Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port G pin 15" ",,,,,,,,USART6_CTS,,,,FMC_SDNCAS,DCMI_D13,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port G pin 13" "TRACED0,,,LPTIM1_OUT,,SPI6_SCK,,,UART6_CTS,,,,FMC_A24,,LCD_R0,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port G pin 12" ",,,LPTIM1_IN1,,SPI6_MISO,,SPDIF_RX1,USART6_RTS,LCD_B4,,SDMMC2_D3,FMC_NE4,,LCD_B1,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port G pin 11" ",,,,,SPI1_SCK/I2S1_WS,,SPDIF_RX0,,,SDMMC2_D2,,,DCMI_D3,LCD_B3,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port G pin 10" ",,,,,SPI1_NSS/I2S1_WS,,,,LCD_G3,SAI2_SD_B,SDMMC2_D1,FMC_NE3,DCMI_D2,LCD_B2,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port G pin 9" ",,,,,SPI6_NSS,,SPDIF_RX3,USART6_RX,QUADSPI_BK2_IO2,SAI2_FS_B,SDMMC2_D0,FMC_NE2/FMC_NCE,DCMI_VSYNC,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port G pin 8" ",,,,,SPI6_NSS,,SPDIF_RX2,USART6_RTS,,,,FMC_SDCLK,,LCD_G7,EVENTOUT"
|
|
else
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port G Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port G pin 7" ",,,,,,SAI1_MCLK_A,,USART6_CK,,,,FMC_INT,DCMI_D13,LCD_CLK,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port G pin 6" ",,,,,,,,,,,,FMC_NE3,DCMI_D12,LCD_R7,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port G pin 5" ",,,,,,,,,,,,FMC_A15/FMC_BA1,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port G pin 4" ",,,,,,,,,,,,FMC_A14/FMC_BA0,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port G pin 3" ",,,,,,,,,,,,FMC_A13,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port G pin 2" ",,,,,,,,,,,,FMC_A12,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port G pin 1" ",,,,,,,,,,,,FMC_A11,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port G pin 0" ",,,,,,,,,,,,FMC_A10,,,EVENTOUT"
|
|
newline
|
|
line.long 0x04 "AFRH,GPIO Port G Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port G pin 15" ",,,,,,,,USART6_CTS,,,,FMC_SDNCAS,DCMI_D13,,EVENTOUT"
|
|
newline
|
|
sif (cpuis("STM32F767BI"))
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port G pin 14" "TRACED1,,,LPTIM1_ETR,,SPI6_MOSI,,,USART6_TX,QUADSPI_BK2_IO3,,ETH_MII_TXD1/ETH_RMII_TXD1,FMC_A25,,LCD_B0,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port G pin 13" "TRACED0,,,LPTIM1_OUT,,SPI6_SCK,,,USART6_CTS,,,ETH_MII_TXD0/ETH_RMII_TXD0,FMC_A24,,LCD_R0,EVENTOUT"
|
|
newline
|
|
else
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port G pin 14" "TRACED1,,,LPTIM1_ETR,,SPI6_MOSI,,,USART6_TX,,,ETH_MII_TXD1/ETH_RMII_TXD1,FMC_A25,,LCD_B0,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port G pin 13" "TRACED0,,,LPTIM1_OUT,,SPI6_SCK,,,UART6_CTS,,,ETH_MII_TXD0/ETH_RMII_TXD0,FMC_A24,,LCD_R0,EVENTOUT"
|
|
endif
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port G pin 12" ",,,LPTIM1_IN1,,SPI6_MISO,,SPDIF_RX1,USART6_RTS,LCD_B4,,SDMMC2_D3,FMC_NE4,,LCD_B1,EVENTOUT"
|
|
sif (cpuis("STM32F767BI"))
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port G pin 11" ",,,,,SPI1_SCK/I2S1_CK,,SPDIF_RX0,,,SDMMC2_D2,ETH_MII_TX_EN/ETH_RMII_TX_EN,,DCMI_D3,LCD_B3,EVENTOUT"
|
|
else
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port G pin 11" ",,,,,SPI1_SCK/I2S1_WS,,SPDIF_RX0,,,SDMMC2_D2,ETH_MII_TX_EN/ETH_RMII_TX_EN,,DCMI_D3,LCD_B3,EVENTOUT"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port G pin 10" ",,,,,SPI1_NSS/I2S1_WS,,,,LCD_G3,SAI2_SD_B,SDMMC2_D1,FMC_NE3,DCMI_D2,LCD_B2,EVENTOUT"
|
|
newline
|
|
sif (cpuis("STM32F767BI"))
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port G pin 9" ",,,,,SPI1_MISO,,SPDIF_RX3,USART6_RX,QUADSPI_BK2_IO2,SAI2_FS_B,SDMMC2_D0,FMC_NE2/FMC_NCE,DCMI_VSYNC,,EVENTOUT"
|
|
newline
|
|
else
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port G pin 9" ",,,,,SPI6_NSS,,SPDIF_RX3,USART6_RX,QUADSPI_BK2_IO2,SAI2_FS_B,SDMMC2_D0,FMC_NE2/FMC_NCE,DCMI_VSYNC,,EVENTOUT"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port G pin 8" ",,,,,SPI6_NSS,,SPDIF_RX2,USART6_RTS,,,ETH_PPS_OUT,FMC_SDCLK,,LCD_G7,EVENTOUT"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F7??I?")||cpuis("STM32F7??B?")||cpuis("STM32F7??N?")||cpuis("STM32F7??A?"))
|
|
tree "GPIO H"
|
|
base ad:0x40021C00
|
|
width 13.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "MODER,GPIO Port H Mode Register"
|
|
bitfld.long 0x00 30.--31. " MODER[15] ,Port H pin 15 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " [14] ,Port H pin 14 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " [13] ,Port H pin 13 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 24.--25. " [12] ,Port H pin 12 mode" "Input,Output,Alternate function,Analog"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " [11] ,Port H pin 11 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " [10] ,Port H pin 10 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " [9] ,Port H pin 9 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " [8] ,Port H pin 8 mode" "Input,Output,Alternate function,Analog"
|
|
newline
|
|
sif !cpuis("STM32F7??A?")
|
|
bitfld.long 0x00 14.--15. " [7] ,Port H pin 7 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " [6] ,Port H pin 6 mode" "Input,Output,Alternate function,Analog"
|
|
else
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x00 10.--11. " [5] ,Port H pin 5 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " [4] ,Port H pin 4 mode" "Input,Output,Alternate function,Analog"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " [3] ,Port H pin 3 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " [2] ,Port H pin 2 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " [1] ,Port H pin 1 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " [0] ,Port H pin 0 mode" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "OTYPER,GPIO Port H Output Type Register"
|
|
bitfld.long 0x04 15. " OT[15] ,Port H pin 15 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " [14] ,Port H pin 14 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " [13] ,Port H pin 13 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 12. " [12] ,Port H pin 12 output type" "Push-pull,Open-drain"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Port H pin 11 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " [10] ,Port H pin 10 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 9. " [9] ,Port H pin 9 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " [8] ,Port H pin 8 output type" "Push-pull,Open-drain"
|
|
newline
|
|
sif !cpuis("STM32F7??A?")
|
|
bitfld.long 0x04 7. " [7] ,Port H pin 7 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " [6] ,Port H pin 6 output type" "Push-pull,Open-drain"
|
|
else
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x04 5. " [5] ,Port H pin 5 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " [4] ,Port H pin 4 output type" "Push-pull,Open-drain"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,Port H pin 3 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " [2] ,Port H pin 2 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " [1] ,Port H pin 1 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " [0] ,Port H pin 0 output type" "Push-pull,Open-drain"
|
|
line.long 0x08 "OSPEEDR,GPIO Port H Output Speed Register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR[15] ,Port H pin 15 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 28.--29. " [14] ,Port H pin 14 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 26.--27. " [13] ,Port H pin 13 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 24.--25. " [12] ,Port H pin 12 output speed" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x08 22.--23. " [11] ,Port H pin 11 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 20.--21. " [10] ,Port H pin 10 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 18.--19. " [9] ,Port H pin 9 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 16.--17. " [8] ,Port H pin 8 output speed" "Low,Medium,High,Very high"
|
|
newline
|
|
sif !cpuis("STM32F7??A?")
|
|
bitfld.long 0x08 14.--15. " [7] ,Port H pin 7 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 12.--13. " [6] ,Port H pin 6 output speed" "Low,Medium,High,Very high"
|
|
else
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x08 10.--11. " [5] ,Port H pin 5 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 8.--9. " [4] ,Port H pin 4 output speed" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x08 6.--7. " [3] ,Port H pin 3 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 4.--5. " [2] ,Port H pin 2 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 2.--3. " [1] ,Port H pin 1 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 0.--1. " [0] ,Port H pin 0 output speed" "Low,Medium,High,Very high"
|
|
line.long 0x0C "PUPDR,GPIO Port H Pull-up/Pull-down Register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR[15] ,Port H pin 15 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " [14] ,Port H pin 14 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " [13] ,Port H pin 13 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 24.--25. " [12] ,Port H pin 12 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
newline
|
|
bitfld.long 0x0C 22.--23. " [11] ,Port H pin 11 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " [10] ,Port H pin 10 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 18.--19. " [9] ,Port H pin 9 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " [8] ,Port H pin 8 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
newline
|
|
sif !cpuis("STM32F7??A?")
|
|
bitfld.long 0x0C 14.--15. " [7] ,Port H pin 7 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 12.--13. " [6] ,Port H pin 6 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
else
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x0C 10.--11. " [5] ,Port H pin 5 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " [4] ,Port H pin 4 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
newline
|
|
bitfld.long 0x0C 6.--7. " [3] ,Port H pin 3 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " [2] ,Port H pin 2 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " [1] ,Port H pin 1 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " [0] ,Port H pin 0 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "IDR,GPIO Port H Input Data Register"
|
|
bitfld.long 0x00 15. " IDR[15] ,Port H pin 15 input data" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Port H pin 14 input data" "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Port H pin 13 input data" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Port H pin 12 input data" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Port H pin 11 input data" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Port H pin 10 input data" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,Port H pin 9 input data" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Port H pin 8 input data" "Low,High"
|
|
newline
|
|
sif !cpuis("STM32F7??A?")
|
|
bitfld.long 0x00 7. " [7] ,Port H pin 7 input data" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Port H pin 6 input data" "Low,High"
|
|
else
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x00 5. " [5] ,Port H pin 5 input data" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Port H pin 4 input data" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Port H pin 3 input data" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Port H pin 2 input data" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Port H pin 1 input data" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Port H pin 0 input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ODR_SET/CLR,GPIO Port H Output Data Set/Clear Register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR[15] ,Port H pin 15 output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " [14] ,Port H pin 14 output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " [13] ,Port H pin 13 output data" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " [12] ,Port H pin 12 output data" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " [11] ,Port H pin 11 output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " [10] ,Port H pin 10 output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " [9] ,Port H pin 9 output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " [8] ,Port H pin 8 output data" "Low,High"
|
|
newline
|
|
sif !cpuis("STM32F7??A?")
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " [7] ,Port H pin 7 output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " [6] ,Port H pin 6 output data" "Low,High"
|
|
else
|
|
textfld " "
|
|
endif
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " [5] ,Port H pin 5 output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " [4] ,Port H pin 4 output data" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " [3] ,Port H pin 3 output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " [2] ,Port H pin 2 output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " [1] ,Port H pin 1 output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " [0] ,Port H pin 0 output data" "Low,High"
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F750*")||cpuis("STM32F767BI"))
|
|
if ((per.l(ad:0x40021C00+0x1C)&0x10000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO Port H Configuration Lock Register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
newline
|
|
bitfld.long 0x00 15. " LCK[15] ,Port H pin 15 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " [14] ,Port H pin 14 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " [13] ,Port H pin 13 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " [12] ,Port H pin 12 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Port H pin 11 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " [10] ,Port H pin 10 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " [9] ,Port H pin 9 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " [8] ,Port H pin 8 configuration lock" "Not locked,Locked"
|
|
newline
|
|
sif !cpuis("STM32F7??A?")
|
|
bitfld.long 0x00 7. " [7] ,Port H pin 7 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " [6] ,Port H pin 6 configuration lock" "Not locked,Locked"
|
|
else
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x00 5. " [5] ,Port H pin 5 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " [4] ,Port H pin 4 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Port H pin 3 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " [2] ,Port H pin 2 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " [1] ,Port H pin 1 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " [0] ,Port H pin 0 configuration lock" "Not locked,Locked"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO Port H Configuration Lock Register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
newline
|
|
rbitfld.long 0x00 15. " LCK[15] ,Port H pin 15 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 14. " [14] ,Port H pin 14 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 13. " [13] ,Port H pin 13 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 12. " [12] ,Port H pin 12 configuration lock" "Not locked,Locked"
|
|
newline
|
|
rbitfld.long 0x00 11. " [11] ,Port H pin 11 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 10. " [10] ,Port H pin 10 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 9. " [9] ,Port H pin 9 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 8. " [8] ,Port H pin 8 configuration lock" "Not locked,Locked"
|
|
newline
|
|
sif !cpuis("STM32F7??A?")
|
|
rbitfld.long 0x00 7. " [7] ,Port H pin 7 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 6. " [6] ,Port H pin 6 configuration lock" "Not locked,Locked"
|
|
else
|
|
textfld " "
|
|
endif
|
|
rbitfld.long 0x00 5. " [5] ,Port H pin 5 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 4. " [4] ,Port H pin 4 configuration lock" "Not locked,Locked"
|
|
newline
|
|
rbitfld.long 0x00 3. " [3] ,Port H pin 3 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 2. " [2] ,Port H pin 2 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 1. " [1] ,Port H pin 1 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 0. " [0] ,Port H pin 0 configuration lock" "Not locked,Locked"
|
|
endif
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO Port H Configuration Lock Register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
newline
|
|
bitfld.long 0x00 15. " LCK[15] ,Port H pin 15 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " [14] ,Port H pin 14 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " [13] ,Port H pin 13 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " [12] ,Port H pin 12 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Port H pin 11 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " [10] ,Port H pin 10 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " [9] ,Port H pin 9 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " [8] ,Port H pin 8 configuration lock" "Not locked,Locked"
|
|
newline
|
|
sif !cpuis("STM32F7??A?")
|
|
bitfld.long 0x00 7. " [7] ,Port H pin 7 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " [6] ,Port H pin 6 configuration lock" "Not locked,Locked"
|
|
else
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x00 5. " [5] ,Port H pin 5 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " [4] ,Port H pin 4 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Port H pin 3 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " [2] ,Port H pin 2 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " [1] ,Port H pin 1 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " [0] ,Port H pin 0 configuration lock" "Not locked,Locked"
|
|
endif
|
|
newline
|
|
sif cpuis("STM32F745*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port H Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port H pin 7" ",,,,I2C3_SCL,,,,,,,ETH_MII_RXD3,FMC_SDCKE1,DCMI_D9,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port H pin 6" ",,,,I2C2_SMBA,,,,,TIM12_CH1,,ETH_MII_RXD2,FMC_SDNE1,DCMI_D8,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port H pin 5" ",,,,I2C2_SDA,,,,,,,,FMC_SDNWE,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port H pin 4" ",,,,I2C2_SCL,,,,,,OTG_HS_ULPI_NXT,,,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port H pin 3" ",,,,,,,,,,SAI2_MCK_B,ETH_MII_COL,FMC_SDNE0,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port H pin 2" ",,,LPTIM1_IN2,,,,,,,SAI2_SCK_B,ETH_MII_CRS,FMC_SDCKE0,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port H pin 1" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port H pin 0" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port H Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port H pin 15" ",,,TIM8_CH3N,,,,,,,,,FMC_D23,DCMI_D11,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port H pin 14" ",,,TIM8_CH2N,,,,,UART4_RX,CAN1_RX,,,FMC_D22,DCMI_D4,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port H pin 13" ",,,TIM8_CH1N,,,,,UART4_TX,CAN1_TX,,,FMC_D21,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port H pin 12" ",,TIM5_CH3,,I2C4_SDA,,,,,,,,FMC_D20,DCMI_D3,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port H pin 11" ",,TIM5_CH2,,I2C4_SCL,,,,,,,,FMC_D19,DCMI_D2,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port H pin 10" ",,TIM5_CH1,3,I2C4_SMBA,,,,,,,,FMC_D18,DCMI_D1,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port H pin 9" ",,,,I2C3_SMBA,,,,,TIM12_CH2,,,FMC_D17,DCMI_D0,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port H pin 8" ",,,,I2C3_SDA,,,,,,,,FMC_D16,DCMI_HSYNC,,EVENTOUT"
|
|
elif cpuis("STM32F746*")||cpuis("STM32F756*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port H Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port H pin 7" ",,,,I2C3_SCL,,,,,,,ETH_MII_RXD3,FMC_SDCKE1,DCMI_D9,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port H pin 6" ",,,,I2C2_SMBA,,,,,TIM12_CH1,,ETH_MII_RXD2,FMC_SDNE1,DCMI_D8,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port H pin 5" ",,,,I2C2_SDA,,,,,,,,FMC_SDNWE,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port H pin 4" ",,,,I2C2_SCL,,,,,LCD_G5,OTG_HS_ULPI_NXT,,,,LCD_G4,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port H pin 3" ",,,,,,,,,,SAI2_MCK_B,ETH_MII_COL,FMC_SDNE0,,LCD_R1,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port H pin 2" ",,,LPTIM1_IN2,,,,,,,SAI2_SCK_B,ETH_MII_CRS,FMC_SDCKE0,,LCD_R0,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port H pin 1" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port H pin 0" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port H Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port H pin 15" ",,,TIM8_CH3N,,,,,,,,,FMC_D23,DCMI_D11,LCD_G4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port H pin 14" ",,,TIM8_CH2N,,,,,UART4_RX,CAN1_RX,,,FMC_D22,DCMI_D4,LCD_G3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port H pin 13" ",,,TIM8_CH1N,,,,,UART4_TX,CAN1_TX,,,FMC_D21,,LCD_G2,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port H pin 12" ",,TIM5_CH3,,I2C4_SDA,,,,,,,,FMC_D20,DCMI_D3,LCD_R6,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port H pin 11" ",,TIM5_CH2,,I2C4_SCL,,,,,,,,FMC_D19,DCMI_D2,LCD_R5,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port H pin 10" ",,TIM5_CH1,,I2C4_SMBA,,,,,,,,FMC_D18,DCMI_D1,LCD_R4,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port H pin 9" ",,,,I2C3_SMBA,,,,,TIM12_CH2,,,FMC_D17,DCMI_D0,LCD_R3,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port H pin 8" ",,,,I2C3_SDA,,,,,,,,FMC_D16,DCMI_HSYNC,LCD_R2,EVENTOUT"
|
|
elif cpuis("STM32F750*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port H Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port H pin 7" ",,,,I2C3_SCL,SPI5_MISO,,,,,,ETH_MII_RXD3,FMC_SDCKE1,DCMI_D9,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port H pin 6" ",,,,I2C2_SMBA,SPI5_SCK,,,,TIM12_CH1,,ETH_MII_RXD2,FMC_SDNE1,DCMI_D8,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port H pin 5" ",,,,I2C2_SDA,SPI5_NSS,,,,,,,FMC_SDNWE,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port H pin 4" ",,,,I2C2_SCL,,,,,,OTG_HS_ULPI_NXT,,,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port H pin 3" ",,,,,,,,,QUADSPI_BK2_IO1,SAI2_MCK_B,ETH_MII_COL,FMC_SDNE0,,LCD_R1,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port H pin 2" ",,,LPTIM1_IN2,,,,,,QUADSPI_BK2_IO0,SAI2_SCK_B,ETH_MII_CRS,FMC_SDCKE0,,LCD_R0,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port H pin 1" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port H pin 0" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port H Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port H pin 15" ",,,TIM8_CH3N,,,,,,,,,FMC_D23,DCMI_D11,LCD_G4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port H pin 14" ",,,TIM8_CH2N,,,,,,,,,FMC_D22,DCMI_D4,LCD_G3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port H pin 13" ",,,TIM8_CH1N,,,,,,CAN1_TX,,,FMC_D21,,LCD_G2,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port H pin 12" ",,TIM5_CH3,,I2C4_SDA,,,,,,,,FMC_D20,DCMI_D3,LCD_R6,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port H pin 11" ",,TIM5_CH2,,I2C4_SCL,,,,,,,,FMC_D19,DCMI_D2,LCD_R5,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port H pin 10" ",,TIM5_CH1,,I2C4_SMBA,,,,,,,,FMC_D18,DCMI_D1,LCD_R4,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port H pin 9" ",,,,I2C3_SMBA,,,,,TIM12_CH2,,,FMC_D17,DCMI_D0,LCD_R3,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port H pin 8" ",,,,I2C3_SDA,,,,,,,,FMC_D16,DCMI_HSYNC,LCD_R2,EVENTOUT"
|
|
elif cpuis("STM32F765*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port H Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port H pin 7" ",,,,I2C3_SCL,SPI5_MISO,,,,,,ETH_MII_RXD3,FMC_SDCKE1,DCMI_D9,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port H pin 6" ",,,,I2C2_SMBA,SPI5_SCK,,,,TIM12_CH1,,ETH_MII_RXD2,FMC_SDNE1,DCMI_D8,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port H pin 5" ",,,,I2C2_SDA,SPI5_NSS,,,,,,,FMC_SDNWE,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port H pin 4" ",,,,I2C2_SCL,,,,,,OTG_HS_ULPI_NXT,,,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port H pin 3" ",,,,,,,,,QUADSPI_BK2_IO1,SAI2_MCK_B,ETH_MII_COL,FMC_SDNE0,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port H pin 2" ",,,LPTIM1_IN2,,,,,,QUADSPI_BK2_IO0,SAI2_SCK_B,ETH_MII_CRS,FMC_SDCKE0,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port H pin 1" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port H pin 0" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port H Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port H pin 15" ",,,TIM8_CH3N,,,,,,,,,FMC_D23,DCMI_D11,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port H pin 14" ",,,TIM8_CH2N,,,,,UART4_RX,CAN1_RX,,,FMC_D22,DCMI_D4,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port H pin 13" ",,,TIM8_CH1N,,,,,UART4_TX,CAN1_TX,,,FMC_D21,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port H pin 12" ",,TIM5_CH3,,I2C4_SDA,,,,,,,,FMC_D20,DCMI_D3,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port H pin 11" ",,TIM5_CH2,,I2C4_SCL,,,,,,,,FMC_D19,DCMI_D2,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port H pin 10" ",,TIM5_CH1,3,I2C4_SMBA,,,,,,,,FMC_D18,DCMI_D1,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port H pin 9" ",,,,I2C3_SMBA,,,,,TIM12_CH2,,,FMC_D17,DCMI_D0,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port H pin 8" ",,,,I2C3_SDA,,,,,,,,FMC_D16,DCMI_HSYNC,,EVENTOUT"
|
|
elif cpuis("STM32F769I*")||cpuis("STM32F779I*")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "AFRL,GPIO Port H Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port H pin 7" ",,,,I2C3_SCL,SPI5_MISO,,,,,,ETH_MII_RXD3,FMC_SDCKE1,DCMI_D9,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port H pin 6" ",,,,I2C2_SMBA,SPI5_SCK,,,,TIM12_CH1,,ETH_MII_RXD2,FMC_SDNE1,DCMI_D8,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port H pin 5" ",,,,I2C2_SDA,SPI5_NSS,,,,,,,FMC_SDNWE,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port H pin 4" ",,,,I2C2_SCL,,,,,LCD_G5,OTG_HS_ULPI_NXT,,,,LCD_G4,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port H pin 3" ",,,,,,,,,QUADSPI_BK2_IO1,SAI2_MCK_B,ETH_MII_COL,FMC_SDNE0,,LCD_R1,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port H pin 2" ",,,LPTIM1_IN2,,,,,,QUADSPI_BK2_IO0,SAI2_SCK_B,ETH_MII_CRS,FMC_SDCKE0,,LCD_R0,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port H pin 1" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port H pin 0" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
elif cpuis("STM32F768A*")||cpuis("STM32F769A*")||cpuis("STM32F778A*")||cpuis("STM32F779A*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port H Alternate Function Low Register"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port H pin 5" ",,,,I2C2_SDA,SPI5_NSS,,,,,,,FMC_SDNWE,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port H pin 4" ",,,,I2C2_SCL,,,,,LCD_G5,OTG_HS_ULPI_NXT,,,,LCD_G4,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port H pin 3" ",,,,,,,,,QUADSPI_BK2_IO1,SAI2_MCK_B,,FMC_SDNE0,,LCD_R1,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port H pin 2" ",,,LPTIM1_IN2,,,,,,QUADSPI_BK2_IO0,SAI2_SCK_B,,FMC_SDCKE0,,LCD_R0,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port H pin 1" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port H pin 0" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port H Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port H pin 15" ",,,TIM8_CH3N,,,,,,,,,FMC_D23,DCMI_D11,LCD_G4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port H pin 14" ",,,TIM8_CH2N,,,,,UART4_RX,CAN1_RX,,,FMC_D22,DCMI_D4,LCD_G3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port H pin 13" ",,,TIM8_CH1N,,,,,UART4_TX,CAN1_TX,,,FMC_D21,,LCD_G2,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port H pin 12" ",,TIM5_CH3,,I2C4_SDA,,,,,,,,FMC_D20,DCMI_D3,LCD_R6,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port H pin 11" ",,TIM5_CH2,,I2C4_SCL,,,,,,,,FMC_D19,DCMI_D2,LCD_R5,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port H pin 10" ",,TIM5_CH1,3,I2C4_SMBA,,,,,,,,FMC_D18,DCMI_D1,LCD_R4,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port H pin 9" ",,,,I2C3_SMBA,,,,,TIM12_CH2,,,FMC_D17,DCMI_D0,LCD_R3,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port H pin 8" ",,,,I2C3_SDA,,,,,,,,FMC_D16,DCMI_HSYNC,LCD_R2,EVENTOUT"
|
|
elif (cpuis("STM32F722*")||cpuis("STM32F723*")||cpuis("STM32F730*")||cpuis("STM32F732*")||cpuis("STM32F733*"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port H Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port H pin 7" ",,,,I2C3_SCL,SPI5_MISO,,,,,,,FMC_SDCKE1,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port H pin 6" ",,,,I2C2_SMBA,SPI5_SCK,,,,TIM12_CH1,,,FMC_SDNE1,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port H pin 5" ",,,,I2C2_SDA,SPI5_NSS,,,,,,,FMC_SDNWE,,,EVENTOUT"
|
|
newline
|
|
sif cpuis("STM32F730*")
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port H pin 4" ",,,,I2C2_SCL,,,,,,,,,,,EVENTOUT"
|
|
else
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port H pin 4" ",,,,I2C2_SCL,,,,,,OTG_HS_ULPI_NXT,,,,,EVENTOUT"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port H pin 3" ",,,,,,,,,QUADSPI_BK2_IO1,SAI2_MCK_B,,FMC_SDNE0,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port H pin 2" ",,,LPTIM1_IN2,,,,,,QUADSPI_BK2_IO0,SAI2_SCK_B,,FMC_SDCKE0,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port H pin 1" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port H pin 0" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port H Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port H pin 15" ",,,TIM8_CH3N,,,,,,,,,FMC_D23,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port H pin 14" ",,,TIM8_CH2N,,,,,UART4_RX,CAN1_RX,,,FMC_D22,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port H pin 13" ",,,TIM8_CH1N,,,,,UART4_TX,CAN1_TX,,,FMC_D21,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port H pin 12" ",,TIM5_CH3,,,,,,,,,,FMC_D20,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port H pin 11" ",,TIM5_CH2,,,,,,,,,,FMC_D19,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port H pin 10" ",,TIM5_CH1,,,,,,,,,,FMC_D18,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port H pin 9" ",,,,I2C3_SMBA,,,,,TIM12_CH2,,,FMC_D17,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port H pin 8" ",,,,I2C3_SDA,,,,,,,,FMC_D16,,,EVENTOUT"
|
|
else
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port H Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port H pin 7" ",,,,I2C3_SCL,SPI5_MISO,,,,,,ETH_MII_RXD3,FMC_SDCKE1,DCMI_D9,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port H pin 6" ",,,,I2C2_SMBA,SPI5_SCK,,,,TIM12_CH1,,ETH_MII_RXD2,FMC_SDNE1,DCMI_D8,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port H pin 5" ",,,,I2C2_SDA,SPI5_NSS,,,,,,,FMC_SDNWE,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port H pin 4" ",,,,I2C2_SCL,,,,,LCD_G5,OTG_HS_ULPI_NXT,,,,LCD_G4,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port H pin 3" ",,,,,,,,,QUADSPI_BK2_IO1,SAI2_MCK_B,ETH_MII_COL,FMC_SDNE0,,LCD_R1,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port H pin 2" ",,,LPTIM1_IN2,,,,,,QUADSPI_BK2_IO0,SAI2_SCK_B,ETH_MII_CRS,FMC_SDCKE0,,LCD_R0,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port H pin 1" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port H pin 0" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port H Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port H pin 15" ",,,TIM8_CH3N,,,,,,,,,FMC_D23,DCMI_D11,LCD_G4,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port H pin 14" ",,,TIM8_CH2N,,,,,UART4_RX,CAN1_RX,,,FMC_D22,DCMI_D4,LCD_G3,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port H pin 13" ",,,TIM8_CH1N,,,,,UART4_TX,CAN1_TX,,,FMC_D21,,LCD_G2,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port H pin 12" ",,TIM5_CH3,,I2C4_SDA,,,,,,,,FMC_D20,DCMI_D3,LCD_R6,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port H pin 11" ",,TIM5_CH2,,I2C4_SCL,,,,,,,,FMC_D19,DCMI_D2,LCD_R5,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port H pin 10" ",,TIM5_CH1,,I2C4_SMBA,,,,,,,,FMC_D18,DCMI_D1,LCD_R4,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port H pin 9" ",,,,I2C3_SMBA,,,,,TIM12_CH2,,,FMC_D17,DCMI_D0,LCD_R3,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port H pin 8" ",,,,I2C3_SDA,,,,,,,,FMC_D16,DCMI_HSYNC,LCD_R2,EVENTOUT"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
tree "GPIO H"
|
|
base ad:0x40021C00
|
|
width 13.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "MODER,GPIO Port H Mode Register"
|
|
sif (cpuis("STM32F767*")||cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F750*"))
|
|
bitfld.long 0x00 2.--3. " MODER[1] ,Port H pin 1 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " [0] ,Port H pin 0 mode" "Input,Output,Alternate function,Analog"
|
|
else
|
|
bitfld.long 0x00 2.--3. " MODER[1] ,Port H pin 1 mode" "Input,Output,,Analog"
|
|
bitfld.long 0x00 0.--1. " [0] ,Port H pin 0 mode" "Input,Output,,Analog"
|
|
endif
|
|
line.long 0x04 "OTYPER,GPIO Port H Mode Register"
|
|
bitfld.long 0x04 1. " OT[1] ,Port H pin 1 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " [0] ,Port H pin 0 output type" "Push-pull,Open-drain"
|
|
line.long 0x08 "OSPEEDR,GPIO Port H Output Speed Register"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR[1] ,Port H pin 1 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 0.--1. " [0] ,Port H pin 0 output speed" "Low,Medium,High,Very high"
|
|
line.long 0x0C "PUPDR,GPIO Port H Pull-up/pull-down Register"
|
|
bitfld.long 0x0C 2.--3. " PUPDR[1] ,Port H pin 1 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " [0] ,Port H pin 0 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "IDR,GPIO Port H Input Data Register"
|
|
bitfld.long 0x00 1. " IDR[1] ,Port H pin 1 input data" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Port H pin 0 input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ODR_SET/CLR,GPIO Port H Output Data Set/Clear Register"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR[1] ,Port H pin 1 output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " [0] ,Port H pin 0 output data" "Low,High"
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F750*")||cpuis("STM32F767BI"))
|
|
if ((per.l(ad:0x40021C00+0x1C)&0x10000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO Port H Configuration Lock Register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
newline
|
|
bitfld.long 0x00 1. " LCK[1] ,Port H pin 1 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " [0] ,Port H pin 0 configuration lock" "Not locked,Locked"
|
|
else
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO Port H Configuration Lock Register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
newline
|
|
rbitfld.long 0x00 1. " LCK[1] ,Port H pin 1 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 0. " [0] ,Port H pin 0 configuration lock" "Not locked,Locked"
|
|
endif
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO Port H Configuration Lock Register"
|
|
bitfld.long 0x00 1. " LCK[1] ,Port H pin 1 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " [0] ,Port H pin 0 configuration lock" "Not locked,Locked"
|
|
endif
|
|
sif (!cpuis("STM32F401*")||cpuis("STM32F401?E")||cpuis("STM32F401?D"))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "AFRL,GPIO Alternate Function Low Register"
|
|
bitfld.long 0x00 4.--7. " AFRL[1] ,Alternate function selection for port H bit 1" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port H bit 0" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
else
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "AFRL,GPIO Alternate Function Low Register"
|
|
endif
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "AFRH,GPIO Alternate Function High Register"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F7??I?")||cpuis("STM32F7??B?")||cpuis("STM32F7??N?")||cpuis("STM32F7??A?"))
|
|
tree "GPIO I"
|
|
base ad:0x40022000
|
|
width 13.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "MODER,GPIO Port I Mode Register"
|
|
sif !cpuis("STM32F7??I*")&&!cpuis("STM32F7??A*")
|
|
bitfld.long 0x00 30.--31. " MODER[15] ,Port I pin 15 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " [14] ,Port I pin 14 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " [13] ,Port I pin 13 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 24.--25. " [12] ,Port I pin 12 mode" "Input,Output,Alternate function,Analog"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " [11] ,Port I pin 11 mode" "Input,Output,Alternate function,Analog"
|
|
else
|
|
bitfld.long 0x00 22.--23. " MODER[11] ,Port I pin 11 mode" "Input,Output,Alternate function,Analog"
|
|
endif
|
|
bitfld.long 0x00 20.--21. " [10] ,Port I pin 10 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " [9] ,Port I pin 9 mode" "Input,Output,Alternate function,Analog"
|
|
sif !cpuis("STM32F7??A*")
|
|
bitfld.long 0x00 16.--17. " [8] ,Port I pin 8 mode" "Input,Output,Alternate function,Analog"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " [7] ,Port I pin 7 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " [6] ,Port I pin 6 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " [5] ,Port I pin 5 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " [4] ,Port I pin 4 mode" "Input,Output,Alternate function,Analog"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " [3] ,Port I pin 3 mode" "Input,Output,Alternate function,Analog"
|
|
sif !cpuis("STM32F769I*")&&!cpuis("STM32F779I*")
|
|
bitfld.long 0x00 4.--5. " [2] ,Port I pin 2 mode" "Input,Output,Alternate function,Analog"
|
|
else
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x00 2.--3. " [1] ,Port I pin 1 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " [0] ,Port I pin 0 mode" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "OTYPER,GPIO Port I Output Type Register"
|
|
sif !cpuis("STM32F7??I*")&&!cpuis("STM32F7??A*")
|
|
bitfld.long 0x04 15. " OT[15] ,Port I pin 15 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " [14] ,Port I pin 14 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " [13] ,Port I pin 13 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 12. " [12] ,Port I pin 12 output type" "Push-pull,Open-drain"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Port I pin 11 output type" "Push-pull,Open-drain"
|
|
else
|
|
bitfld.long 0x04 11. " OT[11] ,Port I pin 11 output type" "Push-pull,Open-drain"
|
|
endif
|
|
bitfld.long 0x04 10. " [10] ,Port I pin 10 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 9. " [9] ,Port I pin 9 output type" "Push-pull,Open-drain"
|
|
sif !cpuis("STM32F7??A*")
|
|
bitfld.long 0x04 8. " [8] ,Port I pin 8 output type" "Push-pull,Open-drain"
|
|
endif
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Port I pin 7 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " [6] ,Port I pin 6 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " [5] ,Port I pin 5 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " [4] ,Port I pin 4 output type" "Push-pull,Open-drain"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,Port I pin 3 output type" "Push-pull,Open-drain"
|
|
sif !cpuis("STM32F769I*")&&!cpuis("STM32F779I*")
|
|
bitfld.long 0x04 2. " [2] ,Port I pin 2 output type" "Push-pull,Open-drain"
|
|
else
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x04 1. " [1] ,Port I pin 1 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " [0] ,Port I pin 0 output type" "Push-pull,Open-drain"
|
|
line.long 0x08 "OSPEEDR,GPIO Port I Output Speed Register"
|
|
sif !cpuis("STM32F7??I*")&&!cpuis("STM32F7??A*")
|
|
bitfld.long 0x08 30.--31. " OSPEEDR[15] ,Port I pin 15 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 28.--29. " [14] ,Port I pin 14 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 26.--27. " [13] ,Port I pin 13 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 24.--25. " [12] ,Port I pin 12 output speed" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x08 22.--23. " [11] ,Port I pin 11 output speed" "Low,Medium,High,Very high"
|
|
else
|
|
bitfld.long 0x08 22.--23. " OSPEEDR[11] ,Port I pin 11 output speed" "Low,Medium,High,Very high"
|
|
endif
|
|
bitfld.long 0x08 20.--21. " [10] ,Port I pin 10 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 18.--19. " [9] ,Port I pin 9 output speed" "Low,Medium,High,Very high"
|
|
sif !cpuis("STM32F7??A*")
|
|
bitfld.long 0x08 16.--17. " [8] ,Port I pin 8 output speed" "Low,Medium,High,Very high"
|
|
endif
|
|
newline
|
|
bitfld.long 0x08 14.--15. " [7] ,Port I pin 7 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 12.--13. " [6] ,Port I pin 6 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 10.--11. " [5] ,Port I pin 5 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 8.--9. " [4] ,Port I pin 4 output speed" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x08 6.--7. " [3] ,Port I pin 3 output speed" "Low,Medium,High,Very high"
|
|
sif !cpuis("STM32F769I*")&&!cpuis("STM32F779I*")
|
|
bitfld.long 0x08 4.--5. " [2] ,Port I pin 2 output speed" "Low,Medium,High,Very high"
|
|
else
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x08 2.--3. " [1] ,Port I pin 1 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 0.--1. " [0] ,Port I pin 0 output speed" "Low,Medium,High,Very high"
|
|
line.long 0x0C "PUPDR,GPIO Port I Pull-up/Pull-down Register"
|
|
sif !cpuis("STM32F7??I*")&&!cpuis("STM32F7??A*")
|
|
bitfld.long 0x0C 30.--31. " PUPDR[15] ,Port I pin 15 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " [14] ,Port I pin 14 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " [13] ,Port I pin 13 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 24.--25. " [12] ,Port I pin 12 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
newline
|
|
bitfld.long 0x0C 22.--23. " [11] ,Port I pin 11 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
else
|
|
bitfld.long 0x0C 22.--23. " PUPDR[11] ,Port I pin 11 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
endif
|
|
bitfld.long 0x0C 20.--21. " [10] ,Port I pin 10 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 18.--19. " [9] ,Port I pin 9 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
sif !cpuis("STM32F7??A*")
|
|
bitfld.long 0x0C 16.--17. " [8] ,Port I pin 8 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x0C 14.--15. " [7] ,Port I pin 7 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 12.--13. " [6] ,Port I pin 6 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " [5] ,Port I pin 5 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " [4] ,Port I pin 4 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
newline
|
|
bitfld.long 0x0C 6.--7. " [3] ,Port I pin 3 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
sif !cpuis("STM32F769I*")&&!cpuis("STM32F779I*")
|
|
bitfld.long 0x0C 4.--5. " [2] ,Port I pin 2 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
else
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x0C 2.--3. " [1] ,Port I pin 1 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " [0] ,Port I pin 0 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "IDR,GPIO Port I Input Data Register"
|
|
sif !cpuis("STM32F7??I*")&&!cpuis("STM32F7??A*")
|
|
bitfld.long 0x00 15. " IDR[15] ,Port I pin 15 input data" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Port I pin 14 input data" "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Port I pin 13 input data" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Port I pin 12 input data" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Port I pin 11 input data" "Low,High"
|
|
else
|
|
bitfld.long 0x00 11. " IDR[11] ,Port I pin 11 input data" "Low,High"
|
|
endif
|
|
bitfld.long 0x00 10. " [10] ,Port I pin 10 input data" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,Port I pin 9 input data" "Low,High"
|
|
sif !cpuis("STM32F7??A*")
|
|
bitfld.long 0x00 8. " [8] ,Port I pin 8 input data" "Low,High"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Port I pin 7 input data" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Port I pin 6 input data" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Port I pin 5 input data" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Port I pin 4 input data" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Port I pin 3 input data" "Low,High"
|
|
sif !cpuis("STM32F769I*")&&!cpuis("STM32F779I*")
|
|
bitfld.long 0x00 2. " [2] ,Port I pin 2 input data" "Low,High"
|
|
else
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x00 1. " [1] ,Port I pin 1 input data" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Port I pin 0 input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ODR_SET/CLR,GPIO Port I Output Data Set/Clear Register"
|
|
sif !cpuis("STM32F7??I*")&&!cpuis("STM32F7??A*")
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR[15] ,Port I pin 15 output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " [14] ,Port I pin 14 output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " [13] ,Port I pin 13 output data" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " [12] ,Port I pin 12 output data" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " [11] ,Port I pin 11 output data" "Low,High"
|
|
else
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR[11] ,Port I pin 11 output data" "Low,High"
|
|
endif
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " [10] ,Port I pin 10 output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " [9] ,Port I pin 9 output data" "Low,High"
|
|
sif !cpuis("STM32F7??A*")
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " [8] ,Port I pin 8 output data" "Low,High"
|
|
endif
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " [7] ,Port I pin 7 output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " [6] ,Port I pin 6 output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " [5] ,Port I pin 5 output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " [4] ,Port I pin 4 output data" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " [3] ,Port I pin 3 output data" "Low,High"
|
|
sif !cpuis("STM32F769I*")&&!cpuis("STM32F779I*")
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " [2] ,Port I pin 2 output data" "Low,High"
|
|
else
|
|
textfld " "
|
|
endif
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " [1] ,Port I pin 1 output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " [0] ,Port I pin 0 output data" "Low,High"
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F750*")||cpuis("STM32F767BI"))
|
|
if ((per.l(ad:0x40022000+0x1C)&0x10000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO Port I Configuration Lock Register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
newline
|
|
sif !cpuis("STM32F7??I*")&&!cpuis("STM32F7??A*")
|
|
bitfld.long 0x00 15. " LCK[15] ,Port I pin 15 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " [14] ,Port I pin 14 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " [13] ,Port I pin 13 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " [12] ,Port I pin 12 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Port I pin 11 configuration lock" "Not locked,Locked"
|
|
else
|
|
bitfld.long 0x00 11. " LCK[11] ,Port I pin 11 configuration lock" "Not locked,Locked"
|
|
endif
|
|
bitfld.long 0x00 10. " [10] ,Port I pin 10 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " [9] ,Port I pin 9 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " [8] ,Port I pin 8 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Port I pin 7 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " [6] ,Port I pin 6 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " [5] ,Port I pin 5 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " [4] ,Port I pin 4 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Port I pin 3 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " [2] ,Port I pin 2 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " [1] ,Port I pin 1 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " [0] ,Port I pin 0 configuration lock" "Not locked,Locked"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO Port I Configuration Lock Register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
newline
|
|
sif !cpuis("STM32F7??I*")&&!cpuis("STM32F7??A*")
|
|
rbitfld.long 0x00 15. " LCK[15] ,Port I pin 15 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 14. " [14] ,Port I pin 14 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 13. " [13] ,Port I pin 13 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 12. " [12] ,Port I pin 12 configuration lock" "Not locked,Locked"
|
|
newline
|
|
rbitfld.long 0x00 11. " [11] ,Port I pin 11 configuration lock" "Not locked,Locked"
|
|
else
|
|
rbitfld.long 0x00 11. " LCK[11] ,Port I pin 11 configuration lock" "Not locked,Locked"
|
|
endif
|
|
rbitfld.long 0x00 10. " [10] ,Port I pin 10 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 9. " [9] ,Port I pin 9 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 8. " [8] ,Port I pin 8 configuration lock" "Not locked,Locked"
|
|
newline
|
|
rbitfld.long 0x00 7. " [7] ,Port I pin 7 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 6. " [6] ,Port I pin 6 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 5. " [5] ,Port I pin 5 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 4. " [4] ,Port I pin 4 configuration lock" "Not locked,Locked"
|
|
newline
|
|
rbitfld.long 0x00 3. " [3] ,Port I pin 3 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 2. " [2] ,Port I pin 2 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 1. " [1] ,Port I pin 1 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 0. " [0] ,Port I pin 0 configuration lock" "Not locked,Locked"
|
|
endif
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO Port I Configuration Lock Register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
newline
|
|
bitfld.long 0x00 15. " LCK[15] ,Port I pin 15 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " [14] ,Port I pin 14 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " [13] ,Port I pin 13 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " [12] ,Port I pin 12 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Port I pin 11 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " [10] ,Port I pin 10 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " [9] ,Port I pin 9 configuration lock" "Not locked,Locked"
|
|
sif !cpuis("STM32F7??A*")
|
|
bitfld.long 0x00 8. " [8] ,Port I pin 8 configuration lock" "Not locked,Locked"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Port I pin 7 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " [6] ,Port I pin 6 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " [5] ,Port I pin 5 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " [4] ,Port I pin 4 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Port I pin 3 configuration lock" "Not locked,Locked"
|
|
sif !cpuis("STM32F769I*")&&!cpuis("STM32F779I*")
|
|
bitfld.long 0x00 2. " [2] ,Port I pin 2 configuration lock" "Not locked,Locked"
|
|
else
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x00 1. " [1] ,Port I pin 1 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " [0] ,Port I pin 0 configuration lock" "Not locked,Locked"
|
|
endif
|
|
newline
|
|
sif (cpuis("STM32F732*")||cpuis("STM32F733*")||cpuis("STM32F723*")||cpuis("STM32F722*")||cpuis("STM32F730*"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port I Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port I pin 7" ",,,TIM8_CH3,,,,,,,SAI2_FS_A,,FMC_D29,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port I pin 6" ",,,TIM8_CH2,,,,,,,SAI2_SD_A,,FMC_D28,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port I pin 5" ",,,TIM8_CH1,,,,,,,SAI2_SCK_A,,FMC_NBL3,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port I pin 4" ",,,TIM8_BKIN,,,,,,,SAI2_MCK_A,,FMC_NBL2,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port I pin 3" ",,,TIM8_ETR,,SPI2_MOSI/I2S2_SD,,,,,,,FMC_D27,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port I pin 2" ",,,TIM8_CH4,,SPI2_MISO,,,,,,,FMC_D26,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port I pin 1" ",,,TIM8_BKIN2,,SPI2_SCK/I2S2_CK,,,,,,,FMC_D25,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port I pin 0" ",,TIM5_CH4,,,SPI2_NSS/I2S2_WS,,,,,,,FMC_D24,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port I Alternate Function High Register"
|
|
sif !cpuis("STM32F730*")
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port I pin 15" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port I pin 14" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port I pin 13" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port I pin 12" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port I pin 11" ",,,,,,,,,,OTG_HS_ULPI_DIR,,,,,EVENTOUT"
|
|
newline
|
|
else
|
|
bitfld.long 0x04 12.--15. " AFRH[11] ,Alternate function selection for port I pin 11" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port I pin 10" ",,,,,,,,,,,,FMC_D31,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port I pin 9" ",,,,,,,,UART4_RX,CAN1_RX,,,FMC_D30,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port I pin 8" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
elif cpuis("STM32F745I*")||cpuis("STM32F746I*")||cpuis("STM32F756I*")||cpuis("STM32F765I*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port I Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port I pin 7" ",,,TIM8_CH3,,,,,,,SAI2_FS_A,,FMC_D29,DCMI_D7,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port I pin 6" ",,,TIM8_CH2,,,,,,,SAI2_SD_A,,FMC_D28,DCMI_D6,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port I pin 5" ",,,TIM8_CH1,,,,,,,SAI2_SCK_A,,FMC_NBL3,DCMI_VSYNC,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port I pin 4" ",,,TIM8_BKIN,,,,,,,SAI2_MCK_A,,FMC_NBL2,DCMI_D5,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port I pin 3" ",,,TIM8_ETR,,SPI2_MOSI/I2S2_SD,,,,,,,FMC_D27,DCMI_D10,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port I pin 2" ",,,TIM8_CH4,,SPI2_MISO,,,,,,,FMC_D26,DCMI_D9,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port I pin 1" ",,,TIM8_BKIN2,,SPI2_SCK/I2S2_CK,,,,,,,FMC_D25,DCMI_D8,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port I pin 0" ",,TIM5_CH4,,,SPI2_NSS/I2S2_WS,,,,,,,FMC_D24,DCMI_D13,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port I Alternate Function High Register"
|
|
bitfld.long 0x04 12.--15. " AFRH[11] ,Alternate function selection for port I pin 11" ",,,,,,,,,,OTG_HS_ULPI_DIR,,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port I pin 10" ",,,,,,,,,,,ETH_MII_RX_ER,FMC_D31,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port I pin 9" ",,,,,,,,UART4_RX,CAN1_RX,,,FMC_D30,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port I pin 8" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
elif cpuis("STM32F745*")||cpuis("STM32F746*")||cpuis("STM32F756*")||cpuis("STM32F765*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port I Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port I pin 7" ",,,TIM8_CH3,,,,,,,SAI2_FS_A,,FMC_D29,DCMI_D7,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port I pin 6" ",,,TIM8_CH2,,,,,,,SAI2_SD_A,,FMC_D28,DCMI_D6,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port I pin 5" ",,,TIM8_CH1,,,,,,,SAI2_SCK_A,,FMC_NBL3,DCMI_VSYNC,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port I pin 4" ",,,TIM8_BKIN,,,,,,,SAI2_MCK_A,,FMC_NBL2,DCMI_D5,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port I pin 3" ",,,TIM8_ETR,,SPI2_MOSI/I2S2_SD,,,,,,,FMC_D27,DCMI_D10,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port I pin 2" ",,,TIM8_CH4,,SPI2_MISO,,,,,,,FMC_D26,DCMI_D9,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port I pin 1" ",,,TIM8_BKIN2,,SPI2_SCK/I2S2_CK,,,,,,,FMC_D25,DCMI_D8,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port I pin 0" ",,TIM5_CH4,,,SPI2_NSS/I2S2_WS,,,,,,,FMC_D24,DCMI_D13,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port I Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port I pin 15" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port I pin 14" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port I pin 13" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port I pin 12" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port I pin 11" ",,,,,,,,,,OTG_HS_ULPI_DIR,,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port I pin 10" ",,,,,,,,,,,ETH_MII_RX_ER,FMC_D31,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port I pin 9" ",,,,,,,,UART4_RX,CAN1_RX,,,FMC_D30,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port I pin 8" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
elif cpuis("STM32F750*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port I Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port I pin 7" ",,,TIM8_CH3,,,,,,,SAI2_FS_A,,FMC_D29,DCMI_D7,LCD_B7,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port I pin 6" ",,,TIM8_CH2,,,,,,,SAI2_SD_A,,FMC_D28,DCMI_D6,LCD_B6,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port I pin 5" ",,,TIM8_CH1,,,,,,,SAI2_SCK_A,,FMC_NBL3,DCMI_VSYNC,LCD_B5,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port I pin 4" ",,,TIM8_BKIN,,,,,,,SAI2_MCK_A,,FMC_NBL2,DCMI_D5,LCD_B4,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port I pin 3" ",,,TIM8_ETR,,SPI2_MOSI/I2S2_SD,,,,,,,FMC_D27,DCMI_D10,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port I pin 2" ",,,TIM8_CH4,,SPI2_MISO,,,,,,,FMC_D26,DCMI_D9,LCD_G7,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port I pin 1" ",,,TIM8_BKIN2,,SPI2_SCK/I2S2_CK,,,,,,,FMC_D25,DCMI_D8,LCD_G6,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port I pin 0" ",,TIM5_CH4,,,SPI2_NSS/I2S2_WS,,,,,,,FMC_D24,DCMI_D13,LCD_G5,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port I Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port I pin 15" ",,,,,,,,,,,,,,LCD_R0,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port I pin 14" ",,,,,,,,,,,,,,LCD_CLK,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port I pin 13" ",,,,,,,,,,,,,,LCD_VSYNC,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port I pin 12" ",,,,,,,,,,,,,,LCD_HSYNC,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port I pin 11" ",,,,,,,,,,OTG_HS_ULPI_DIR,,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port I pin 10" ",,,,,,,,,,,ETH_MII_RX_ER,FMC_D31,,LCD_HSYNC,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port I pin 9" ",,,,,,,,,CAN1_RX,,,FMC_D30,,LCD_VSYNC,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port I pin 8" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
elif cpuis("STM32F769I*")||cpuis("STM32F779I*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port I Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port I pin 7" ",,,TIM8_CH3,,,,,,,SAI2_FS_A,,FMC_D29,DCMI_D7,LCD_B7,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port I pin 6" ",,,TIM8_CH2,,,,,,,SAI2_SD_A,,FMC_D28,DCMI_D6,LCD_B6,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port I pin 5" ",,,TIM8_CH1,,,,,,,SAI2_SCK_A,,FMC_NBL3,DCMI_VSYNC,LCD_B5,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port I pin 4" ",,,TIM8_BKIN,,,,,,,SAI2_MCK_A,,FMC_NBL2,DCMI_D5,LCD_B4,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port I pin 3" ",,,TIM8_ETR,,SPI2_MOSI/I2S2_SD,,,,,,,FMC_D27,DCMI_D10,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port I pin 1" ",,,TIM8_BKIN2,,SPI2_SCK/I2S2_CK,,,,,,,FMC_D25,DCMI_D8,LCD_G6,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port I pin 0" ",,TIM5_CH4,,,SPI2_NSS/I2S2_WS,,,,,,,FMC_D24,DCMI_D13,LCD_G5,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port I Alternate Function High Register"
|
|
bitfld.long 0x04 12.--15. " AFRH[11] ,Alternate function selection for port I pin 11" ",,,,,,,,,LCD_G6,OTG_HS_ULPI_DIR,,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port I pin 10" ",,,,,,,,,,,ETH_MII_RX_ER,FMC_D31,,LCD_HSYNC,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port I pin 9" ",,,,,,,,UART4_RX,CAN1_RX,,,FMC_D30,,LCD_VSYNC,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port I pin 8" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
elif cpuis("STM32F768A*")||cpuis("STM32F769A*")||cpuis("STM32F778A*")||cpuis("STM32F779A*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port I Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port I pin 7" ",,,TIM8_CH3,,,,,,,SAI2_FS_A,,FMC_D29,DCMI_D7,LCD_B7,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port I pin 6" ",,,TIM8_CH2,,,,,,,SAI2_SD_A,,FMC_D28,DCMI_D6,LCD_B6,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port I pin 5" ",,,TIM8_CH1,,,,,,,SAI2_SCK_A,,FMC_NBL3,DCMI_VSYNC,LCD_B5,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port I pin 4" ",,,TIM8_BKIN,,,,,,,SAI2_MCK_A,,FMC_NBL2,DCMI_D5,LCD_B4,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port I pin 3" ",,,TIM8_ETR,,SPI2_MOSI/I2S2_SD,,,,,,,FMC_D27,DCMI_D10,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port I pin 2" ",,,TIM8_CH4,,SPI2_MISO,,,,,,,FMC_D26,DCMI_D9,LCD_G7,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port I pin 1" ",,,TIM8_BKIN2,,SPI2_SCK/I2S2_CK,,,,,,,FMC_D25,DCMI_D8,LCD_G6,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port I pin 0" ",,TIM5_CH4,,,SPI2_NSS/I2S2_WS,,,,,,,FMC_D24,DCMI_D13,LCD_G5,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port I Alternate Function High Register"
|
|
bitfld.long 0x04 12.--15. " AFRH[11] ,Alternate function selection for port I pin 11" ",,,,,,,,,LCD_G6,OTG_HS_ULPI_DIR,,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port I pin 10" ",,,,,,,,,,,,FMC_D31,,LCD_HSYNC,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port I pin 9" ",,,,,,,,UART4_RX,CAN1_RX,,,FMC_D30,,LCD_VSYNC,EVENTOUT"
|
|
elif cpuis("STM32F7??I*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port I Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port I pin 7" ",,,TIM8_CH3,,,,,,,SAI2_FS_A,,FMC_D29,DCMI_D7,LCD_B7,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port I pin 6" ",,,TIM8_CH2,,,,,,,SAI2_SD_A,,FMC_D28,DCMI_D6,LCD_B6,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port I pin 5" ",,,TIM8_CH1,,,,,,,SAI2_SCK_A,,FMC_NBL3,DCMI_VSYNC,LCD_B5,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port I pin 4" ",,,TIM8_BKIN,,,,,,,SAI2_MCK_A,,FMC_NBL2,DCMI_D5,LCD_B4,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port I pin 3" ",,,TIM8_ETR,,SPI2_MOSI/I2S2_SD,,,,,,,FMC_D27,DCMI_D10,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port I pin 2" ",,,TIM8_CH4,,SPI2_MISO,,,,,,,FMC_D26,DCMI_D9,LCD_G7,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port I pin 1" ",,,TIM8_BKIN2,,SPI2_SCK/I2S2_CK,,,,,,,FMC_D25,DCMI_D8,LCD_G6,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port I pin 0" ",,TIM5_CH4,,,SPI2_NSS/I2S2_WS,,,,,,,FMC_D24,DCMI_D13,LCD_G5,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port I Alternate Function High Register"
|
|
bitfld.long 0x04 12.--15. " AFRH[11] ,Alternate function selection for port I pin 11" ",,,,,,,,,LCD_G6,OTG_HS_ULPI_DIR,,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port I pin 10" ",,,,,,,,,,,ETH_MII_RX_ER,FMC_D31,,LCD_HSYNC,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port I pin 9" ",,,,,,,,UART4_RX,CAN1_RX,,,FMC_D30,,LCD_VSYNC,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port I pin 8" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
else
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port I Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port I pin 7" ",,,TIM8_CH3,,,,,,,SAI2_FS_A,,FMC_D29,DCMI_D7,LCD_B7,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port I pin 6" ",,,TIM8_CH2,,,,,,,SAI2_SD_A,,FMC_D28,DCMI_D6,LCD_B6,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port I pin 5" ",,,TIM8_CH1,,,,,,,SAI2_SCK_A,,FMC_NBL3,DCMI_VSYNC,LCD_B5,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port I pin 4" ",,,TIM8_BKIN,,,,,,,SAI2_MCK_A,,FMC_NBL2,DCMI_D5,LCD_B4,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port I pin 3" ",,,TIM8_ETR,,SPI2_MOSI/I2S2_SD,,,,,,,FMC_D27,DCMI_D10,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port I pin 2" ",,,TIM8_CH4,,SPI2_MISO,,,,,,,FMC_D26,DCMI_D9,LCD_G7,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port I pin 1" ",,,TIM8_BKIN2,,SPI2_SCK/I2S2_CK,,,,,,,FMC_D25,DCMI_D8,LCD_G6,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port I pin 0" ",,TIM5_CH4,,,SPI2_NSS/I2S2_WS,,,,,,,FMC_D24,DCMI_D13,LCD_G5,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port I Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port I pin 15" ",,,,,,,,,LCD_G2,,,,,LCD_R0,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port I pin 14" ",,,,,,,,,,,,,,LCD_CLK,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port I pin 13" ",,,,,,,,,,,,,,LCD_VSYNC,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port I pin 12" ",,,,,,,,,,,,,,LCD_HSYNC,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port I pin 11" ",,,,,,,,,LCD_G6,OTG_HS_ULPI_DIR,,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port I pin 10" ",,,,,,,,,,,ETH_MII_RX_ER,FMC_D31,,LCD_HSYNC,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port I pin 9" ",,,,,,,,UART4_RX,CAN1_RX,,,FMC_D30,,LCD_VSYNC,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port I pin 8" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F7??B?")||cpuis("STM32F7??N?"))
|
|
tree "GPIO J"
|
|
base ad:0x40022400
|
|
width 13.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "MODER,GPIO Port J Mode Register"
|
|
bitfld.long 0x00 30.--31. " MODER[15] ,Port J pin 15 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " [14] ,Port J pin 14 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " [13] ,Port J pin 13 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 24.--25. " [12] ,Port J pin 12 mode" "Input,Output,Alternate function,Analog"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " [11] ,Port J pin 11 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " [10] ,Port J pin 10 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " [9] ,Port J pin 9 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " [8] ,Port J pin 8 mode" "Input,Output,Alternate function,Analog"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " [7] ,Port J pin 7 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " [6] ,Port J pin 6 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " [5] ,Port J pin 5 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " [4] ,Port J pin 4 mode" "Input,Output,Alternate function,Analog"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " [3] ,Port J pin 3 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " [2] ,Port J pin 2 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " [1] ,Port J pin 1 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " [0] ,Port J pin 0 mode" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "OTYPER,GPIO Port J Output Type Register"
|
|
bitfld.long 0x04 15. " OT[15] ,Port J pin 15 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " [14] ,Port J pin 14 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " [13] ,Port J pin 13 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 12. " [12] ,Port J pin 12 output type" "Push-pull,Open-drain"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Port J pin 11 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " [10] ,Port J pin 10 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 9. " [9] ,Port J pin 9 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " [8] ,Port J pin 8 output type" "Push-pull,Open-drain"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Port J pin 7 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " [6] ,Port J pin 6 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " [5] ,Port J pin 5 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " [4] ,Port J pin 4 output type" "Push-pull,Open-drain"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,Port J pin 3 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " [2] ,Port J pin 2 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " [1] ,Port J pin 1 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " [0] ,Port J pin 0 output type" "Push-pull,Open-drain"
|
|
line.long 0x08 "OSPEEDR,GPIO Port J Output Speed Register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR[15] ,Port J pin 15 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 28.--29. " [14] ,Port J pin 14 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 26.--27. " [13] ,Port J pin 13 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 24.--25. " [12] ,Port J pin 12 output speed" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x08 22.--23. " [11] ,Port J pin 11 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 20.--21. " [10] ,Port J pin 10 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 18.--19. " [9] ,Port J pin 9 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 16.--17. " [8] ,Port J pin 8 output speed" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x08 14.--15. " [7] ,Port J pin 7 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 12.--13. " [6] ,Port J pin 6 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 10.--11. " [5] ,Port J pin 5 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 8.--9. " [4] ,Port J pin 4 output speed" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x08 6.--7. " [3] ,Port J pin 3 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 4.--5. " [2] ,Port J pin 2 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 2.--3. " [1] ,Port J pin 1 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 0.--1. " [0] ,Port J pin 0 output speed" "Low,Medium,High,Very high"
|
|
line.long 0x0C "PUPDR,GPIO Port J Pull-up/Pull-down Register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR[15] ,Port J pin 15 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " [14] ,Port J pin 14 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " [13] ,Port J pin 13 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 24.--25. " [12] ,Port J pin 12 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
newline
|
|
bitfld.long 0x0C 22.--23. " [11] ,Port J pin 11 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " [10] ,Port J pin 10 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 18.--19. " [9] ,Port J pin 9 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " [8] ,Port J pin 8 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
newline
|
|
bitfld.long 0x0C 14.--15. " [7] ,Port J pin 7 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 12.--13. " [6] ,Port J pin 6 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " [5] ,Port J pin 5 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " [4] ,Port J pin 4 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
newline
|
|
bitfld.long 0x0C 6.--7. " [3] ,Port J pin 3 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " [2] ,Port J pin 2 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " [1] ,Port J pin 1 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " [0] ,Port J pin 0 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "IDR,GPIO Port J Input Data Register"
|
|
bitfld.long 0x00 15. " IDR[15] ,Port J pin 15 input data" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Port J pin 14 input data" "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Port J pin 13 input data" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Port J pin 12 input data" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Port J pin 11 input data" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Port J pin 10 input data" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,Port J pin 9 input data" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Port J pin 8 input data" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Port J pin 7 input data" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Port J pin 6 input data" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Port J pin 5 input data" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Port J pin 4 input data" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Port J pin 3 input data" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Port J pin 2 input data" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Port J pin 1 input data" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Port J pin 0 input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ODR_SET/CLR,GPIO Port J Output Data Set/Clear Register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR[15] ,Port J pin 15 output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " [14] ,Port J pin 14 output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " [13] ,Port J pin 13 output data" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " [12] ,Port J pin 12 output data" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " [11] ,Port J pin 11 output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " [10] ,Port J pin 10 output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " [9] ,Port J pin 9 output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " [8] ,Port J pin 8 output data" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " [7] ,Port J pin 7 output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " [6] ,Port J pin 6 output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " [5] ,Port J pin 5 output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " [4] ,Port J pin 4 output data" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " [3] ,Port J pin 3 output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " [2] ,Port J pin 2 output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " [1] ,Port J pin 1 output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " [0] ,Port J pin 0 output data" "Low,High"
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F750*")||cpuis("STM32F767BI"))
|
|
if ((per.l(ad:0x40022400+0x1C)&0x10000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO Port J Configuration Lock Register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
newline
|
|
bitfld.long 0x00 15. " LCK[15] ,Port J pin 15 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " [14] ,Port J pin 14 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " [13] ,Port J pin 13 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " [12] ,Port J pin 12 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Port J pin 11 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " [10] ,Port J pin 10 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " [9] ,Port J pin 9 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " [8] ,Port J pin 8 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Port J pin 7 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " [6] ,Port J pin 6 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " [5] ,Port J pin 5 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " [4] ,Port J pin 4 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Port J pin 3 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " [2] ,Port J pin 2 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " [1] ,Port J pin 1 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " [0] ,Port J pin 0 configuration lock" "Not locked,Locked"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO Port J Configuration Lock Register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
newline
|
|
rbitfld.long 0x00 15. " LCK[15] ,Port J pin 15 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 14. " [14] ,Port J pin 14 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 13. " [13] ,Port J pin 13 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 12. " [12] ,Port J pin 12 configuration lock" "Not locked,Locked"
|
|
newline
|
|
rbitfld.long 0x00 11. " [11] ,Port J pin 11 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 10. " [10] ,Port J pin 10 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 9. " [9] ,Port J pin 9 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 8. " [8] ,Port J pin 8 configuration lock" "Not locked,Locked"
|
|
newline
|
|
rbitfld.long 0x00 7. " [7] ,Port J pin 7 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 6. " [6] ,Port J pin 6 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 5. " [5] ,Port J pin 5 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 4. " [4] ,Port J pin 4 configuration lock" "Not locked,Locked"
|
|
newline
|
|
rbitfld.long 0x00 3. " [3] ,Port J pin 3 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 2. " [2] ,Port J pin 2 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 1. " [1] ,Port J pin 1 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 0. " [0] ,Port J pin 0 configuration lock" "Not locked,Locked"
|
|
endif
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO Port J Configuration Lock Register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
newline
|
|
bitfld.long 0x00 15. " LCK[15] ,Port J pin 15 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " [14] ,Port J pin 14 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " [13] ,Port J pin 13 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " [12] ,Port J pin 12 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Port J pin 11 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " [10] ,Port J pin 10 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " [9] ,Port J pin 9 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " [8] ,Port J pin 8 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Port J pin 7 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " [6] ,Port J pin 6 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " [5] ,Port J pin 5 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " [4] ,Port J pin 4 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Port J pin 3 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " [2] ,Port J pin 2 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " [1] ,Port J pin 1 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " [0] ,Port J pin 0 configuration lock" "Not locked,Locked"
|
|
endif
|
|
newline
|
|
sif cpuis("STM32F7?5B*")||cpuis("STM32F7?5N*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port J Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port J pin 7" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port J pin 6" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port J pin 5" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port J pin 4" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port J pin 3" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port J pin 2" ",,,,,,,,,,,,,DSI_TE,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port J pin 1" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port J pin 0" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port J Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port J pin 15" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port J pin 14" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port J pin 13" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port J pin 12" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port J pin 11" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port J pin 10" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port J pin 9" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port J pin 8" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
elif cpuis("STM32F745*")||cpuis("STM32F746*")||cpuis("STM32F750*")||cpuis("STM32F756*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port J Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port J pin 7" ",,,,,,,,,,,,,,LCD_G0,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port J pin 6" ",,,,,,,,,,,,,,LCD_R7,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port J pin 5" ",,,,,,,,,,,,,,LCD_R6,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port J pin 4" ",,,,,,,,,,,,,,LCD_R5,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port J pin 3" ",,,,,,,,,,,,,,LCD_R4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port J pin 2" ",,,,,,,,,,,,,,LCD_R3,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port J pin 1" ",,,,,,,,,,,,,,LCD_R2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port J pin 0" ",,,,,,,,,,,,,,LCD_R1,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port J Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port J pin 15" ",,,,,,,,,,,,,,LCD_B3,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port J pin 14" ",,,,,,,,,,,,,,LCD_B2,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port J pin 13" ",,,,,,,,,,,,,,LCD_B1,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port J pin 12" ",,,,,,,,,,,,,,LCD_B0,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port J pin 11" ",,,,,,,,,,,,,,LCD_G4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port J pin 10" ",,,,,,,,,,,,,,LCD_G3,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port J pin 9" ",,,,,,,,,,,,,,LCD_G2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port J pin 8" ",,,,,,,,,,,,,,LCD_G1,EVENTOUT"
|
|
elif cpuis("STM32F769B*")||cpuis("STM32F779N*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port J Alternate Function Low Register"
|
|
bitfld.long 0x00 20.--23. " AFRL[5] ,Alternate function selection for port J pin 5" ",,,,,,,,,,,,,,LCD_R6,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port J pin 4" ",,,,,,,,,,,,,,LCD_R5,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port J pin 3" ",,,,,,,,,,,,,,LCD_R4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port J pin 2" ",,,,,,,,,,,,,DSI_TE,LCD_R3,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port J pin 1" ",,,,,,,,,,,,,,LCD_R2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port J pin 0" ",,,,,,,,,LCD_R7,,,,,LCD_R1,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port J Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port J pin 15" ",,,,,,,,,,,,,,LCD_B3,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port J pin 14" ",,,,,,,,,,,,,,LCD_B2,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port J pin 13" ",,,,,,,,,LCD_G4,,,,,LCD_B1,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port J pin 12" ",,,,,,,,,LCD_G3,,,,,LCD_B0,EVENTOUT"
|
|
else
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "AFRL,GPIO Port J Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port J pin 7" ",,,,,,,,,,,,,,LCD_G0,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port J pin 6" ",,,,,,,,,,,,,,LCD_R7,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port J pin 5" ",,,,,,,,,,,,,,LCD_R6,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port J pin 4" ",,,,,,,,,,,,,,LCD_R5,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port J pin 3" ",,,,,,,,,,,,,,LCD_R4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port J pin 2" ",,,,,,,,,,,,,DSI_TE,LCD_R3,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port J pin 1" ",,,,,,,,,,,,,,LCD_R2,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port J pin 0" ",,,,,,,,,LCD_R7,,,,,LCD_R1,EVENTOUT"
|
|
line.long 0x04 "AFRH,GPIO Port J Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH[15] ,Alternate function selection for port J pin 15" ",,,,,,,,,,,,,,LCD_B3,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " [14] ,Alternate function selection for port J pin 14" ",,,,,,,,,,,,,,LCD_B2,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " [13] ,Alternate function selection for port J pin 13" ",,,,,,,,,LCD_G4,,,,,LCD_B1,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " [12] ,Alternate function selection for port J pin 12" ",,,,,,,,,LCD_G3,,,,,LCD_B0,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " [11] ,Alternate function selection for port J pin 11" ",,,,,,,,,,,,,,LCD_G4,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " [10] ,Alternate function selection for port J pin 10" ",,,,,,,,,,,,,,LCD_G3,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " [9] ,Alternate function selection for port J pin 9" ",,,,,,,,,,,,,,LCD_G2,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " [8] ,Alternate function selection for port J pin 8" ",,,,,,,,,,,,,,LCD_G1,EVENTOUT"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO K"
|
|
base ad:0x40022800
|
|
width 13.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "MODER,GPIO Port K Mode Register"
|
|
bitfld.long 0x00 14.--15. " MODER[7] ,Port K pin 7 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " [6] ,Port K pin 6 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " [5] ,Port K pin 5 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " [4] ,Port K pin 4 mode" "Input,Output,Alternate function,Analog"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " [3] ,Port K pin 3 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " [2] ,Port K pin 2 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " [1] ,Port K pin 1 mode" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " [0] ,Port K pin 0 mode" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "OTYPER,GPIO Port K Output Type Register"
|
|
bitfld.long 0x04 7. " OT[7] ,Port K pin 7 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " [6] ,Port K pin 6 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " [5] ,Port K pin 5 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " [4] ,Port K pin 4 output type" "Push-pull,Open-drain"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,Port K pin 3 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " [2] ,Port K pin 2 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " [1] ,Port K pin 1 output type" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " [0] ,Port K pin 0 output type" "Push-pull,Open-drain"
|
|
line.long 0x08 "OSPEEDR,GPIO Port K Output Speed Register"
|
|
bitfld.long 0x08 14.--15. " OSPEEDR[7] ,Port K pin 7 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 12.--13. " [6] ,Port K pin 6 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 10.--11. " [5] ,Port K pin 5 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 8.--9. " [4] ,Port K pin 4 output speed" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x08 6.--7. " [3] ,Port K pin 3 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 4.--5. " [2] ,Port K pin 2 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 2.--3. " [1] ,Port K pin 1 output speed" "Low,Medium,High,Very high"
|
|
bitfld.long 0x08 0.--1. " [0] ,Port K pin 0 output speed" "Low,Medium,High,Very high"
|
|
line.long 0x0C "PUPDR,GPIO Port K Pull-up/Pull-down Register"
|
|
bitfld.long 0x0C 14.--15. " PUPDR[7] ,Port K pin 7 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 12.--13. " [6] ,Port K pin 6 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " [5] ,Port K pin 5 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " [4] ,Port K pin 4 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
newline
|
|
bitfld.long 0x0C 6.--7. " [3] ,Port K pin 3 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " [2] ,Port K pin 2 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " [1] ,Port K pin 1 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " [0] ,Port K pin 0 pull-up/pull-down" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "IDR,GPIO Port K Input Data Register"
|
|
bitfld.long 0x00 7. " IDR[7] ,Port K pin 7 input data" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Port K pin 6 input data" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Port K pin 5 input data" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Port K pin 4 input data" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Port K pin 3 input data" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Port K pin 2 input data" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Port K pin 1 input data" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Port K pin 0 input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ODR_SET/CLR,GPIO Port K Output Data Set/Clear Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR[7] ,Port K pin 7 output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " [6] ,Port K pin 6 output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " [5] ,Port K pin 5 output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " [4] ,Port K pin 4 output data" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " [3] ,Port K pin 3 output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " [2] ,Port K pin 2 output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " [1] ,Port K pin 1 output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " [0] ,Port K pin 0 output data" "Low,High"
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F750*")||cpuis("STM32F767BI"))
|
|
if ((per.l(ad:0x40022800+0x1C)&0x10000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO Port K Configuration Lock Register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
newline
|
|
bitfld.long 0x00 7. " LCK[7] ,Port K pin 7 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " [6] ,Port K pin 6 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " [5] ,Port K pin 5 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " [4] ,Port K pin 4 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Port K pin 3 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " [2] ,Port K pin 2 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " [1] ,Port K pin 1 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " [0] ,Port K pin 0 configuration lock" "Not locked,Locked"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO Port K Configuration Lock Register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
newline
|
|
rbitfld.long 0x00 7. " LCK[7] ,Port K pin 7 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 6. " [6] ,Port K pin 6 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 5. " [5] ,Port K pin 5 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 4. " [4] ,Port K pin 4 configuration lock" "Not locked,Locked"
|
|
newline
|
|
rbitfld.long 0x00 3. " [3] ,Port K pin 3 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 2. " [2] ,Port K pin 2 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 1. " [1] ,Port K pin 1 configuration lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 0. " [0] ,Port K pin 0 configuration lock" "Not locked,Locked"
|
|
endif
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LCKR,GPIO Port K Configuration Lock Register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
newline
|
|
bitfld.long 0x00 7. " LCK[7] ,Port K pin 7 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " [6] ,Port K pin 6 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " [5] ,Port K pin 5 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " [4] ,Port K pin 4 configuration lock" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Port K pin 3 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " [2] ,Port K pin 2 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " [1] ,Port K pin 1 configuration lock" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " [0] ,Port K pin 0 configuration lock" "Not locked,Locked"
|
|
endif
|
|
newline
|
|
sif (cpuis("STM32F7?5B*")||cpuis("STM32F7?5N*"))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "AFRL,GPIO Port K Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port K pin 7" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port K pin 6" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port K pin 5" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port K pin 4" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port K pin 3" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port K pin 2" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port K pin 1" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port K pin 0" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
elif (cpuis("STM32F769B*")||cpuis("STM32F779N*"))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "AFRL,GPIO Port K Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port K pin 7" ",,,,,,,,,,,,,,LCD_DE,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port K pin 6" ",,,,,,,,,,,,,,LCD_B7,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port K pin 5" ",,,,,,,,,,,,,,LCD_B6,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port K pin 4" ",,,,,,,,,,,,,,LCD_B5,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port K pin 3" ",,,,,,,,,,,,,,LCD_B4,EVENTOUT"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "AFRL,GPIO Port K Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL[7] ,Alternate function selection for port K pin 7" ",,,,,,,,,,,,,,LCD_DE,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " [6] ,Alternate function selection for port K pin 6" ",,,,,,,,,,,,,,LCD_B7,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " [5] ,Alternate function selection for port K pin 5" ",,,,,,,,,,,,,,LCD_B6,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " [4] ,Alternate function selection for port K pin 4" ",,,,,,,,,,,,,,LCD_B5,EVENTOUT"
|
|
bitfld.long 0x00 12.--15. " [3] ,Alternate function selection for port K pin 3" ",,,,,,,,,,,,,,LCD_B4,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " [2] ,Alternate function selection for port K pin 2" ",,,,,,,,,,,,,,LCD_G7,EVENTOUT"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " [1] ,Alternate function selection for port K pin 1" ",,,,,,,,,,,,,,LCD_G6,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " [0] ,Alternate function selection for port K pin 0" ",,,,,,,,,,,,,,LCD_G5,EVENTOUT"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "SYSCFG (System Configuration Controller)"
|
|
base ad:0x40013800
|
|
width 9.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "MEMRMP,SYSCFG Memory Remap Register"
|
|
sif !cpuis("STM32F730R8")
|
|
bitfld.long 0x00 10.--11. " SWP_FMC ,FMC memory mapping swap" "Not swapped,Swapped,?..."
|
|
newline
|
|
endif
|
|
sif cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
bitfld.long 0x00 8. " SWP_FB ,Flash bank swap" "Not swapped,Swapped"
|
|
newline
|
|
endif
|
|
rbitfld.long 0x00 0. " MEM_BOOT ,Memory boot mapping" "BOOT_ADD0,BOOT_ADD1"
|
|
line.long 0x04 "PMC,SYSCFG Peripheral Mode Configuration Register"
|
|
sif cpuis("STM32F72*")||cpuis("STM32F73*")
|
|
bitfld.long 0x04 18. " ADC2DC2 ,ADC2 accuracy option" "No effect,Enabled"
|
|
bitfld.long 0x04 17. " ADC1DC2 ,ADC1 accuracy option" "No effect,Enabled"
|
|
bitfld.long 0x04 16. " ADC0DC2 ,ADC0 accuracy option" "No effect,Enabled"
|
|
bitfld.long 0x04 7. " PB9_FMP ,PB9 pin fast mode + enable" "Default,FM+"
|
|
newline
|
|
bitfld.long 0x04 6. " PB8_FMP ,PB8 pin fast mode + enable" "Default,FM+"
|
|
bitfld.long 0x04 5. " PB7_FMP ,PB7 pin fast mode + enable" "Default,FM+"
|
|
bitfld.long 0x04 4. " PB6_FMP ,PB6 pin fast mode + enable" "Default,FM+"
|
|
bitfld.long 0x04 2. " I2C3_FMP ,I2C3 pin fast mode + enable" "Default,FM+"
|
|
newline
|
|
bitfld.long 0x04 1. " I2C2_FMP ,I2C2 pin fast mode + enable" "Default,FM+"
|
|
bitfld.long 0x04 0. " I2C1_FMP ,I2C1 pin fast mode + enable" "Default,FM+"
|
|
else
|
|
bitfld.long 0x04 23. " MII_RMII_SEL ,Ethernet PHY interface selection" "MII,RMII PHY"
|
|
bitfld.long 0x04 18. " ADC3DC2 ,ADC3 accuracy option 2" "No effect,Enabled"
|
|
bitfld.long 0x04 17. " ADC2DC2 ,ADC2 accuracy option 2" "No effect,Enabled"
|
|
bitfld.long 0x04 16. " ADC1DC2 ,ADC1 accuracy option 2" "No effect,Enabled"
|
|
sif cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
newline
|
|
bitfld.long 0x04 7. " PB9_FMP ,PB9 pin fast mode + enable" "Default,FM+"
|
|
bitfld.long 0x04 6. " PB8_FMP ,PB8 pin fast mode + enable" "Default,FM+"
|
|
bitfld.long 0x04 5. " PB7_FMP ,PB7 pin fast mode + enable" "Default,FM+"
|
|
bitfld.long 0x04 4. " PB6_FMP ,PB6 pin fast mode + enable" "Default,FM+"
|
|
newline
|
|
bitfld.long 0x04 3. " I2C4_FMP ,I2C4 pin fast mode + enable" "Default,FM+"
|
|
bitfld.long 0x04 2. " I2C3_FMP ,I2C3 pin fast mode + enable" "Default,FM+"
|
|
bitfld.long 0x04 1. " I2C2_FMP ,I2C2 pin fast mode + enable" "Default,FM+"
|
|
bitfld.long 0x04 0. " I2C1_FMP ,I2C1 pin fast mode + enable" "Default,FM+"
|
|
endif
|
|
endif
|
|
sif cpuis("STM32F7??V?")
|
|
group.long 0x08++0x0F
|
|
line.long 0x00 "EXTICR1,SYSCFG External Interrupt Configuration Register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,PC3,PD3,PE3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,PB2,PC2,PD2,PE2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,PC1,PD1,PE1,,,PH1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,PC0,PD0,PE0,,,PH0,?..."
|
|
line.long 0x04 "EXTICR2,SYSCFG External Interrupt Configuration Register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,PC7,PD7,PE7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,PC6,PD6,PE6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,PC5,PD5,PE5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,PC4,PD4,PE4,?..."
|
|
line.long 0x08 "EXTICR3,SYSCFG External Interrupt Configuration Register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,PB11,PC11,PD11,PE11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,PB10,PC10,PD10,PE10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,PC9,PD9,PE9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,PC8,PD8,PE8,?..."
|
|
line.long 0x0C "EXTICR4,SYSCFG External Interrupt Configuration Register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,PD15,PE15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,PB14,PC14,PD14,PE14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,PB13,PC13,PD13,PE13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,PB12,PC12,PD12,PE12,?..."
|
|
elif cpuis("STM32F722R?")||cpuis("STM32F732R?")||cpuis("STM32F730R?")
|
|
group.long 0x08++0x0F
|
|
line.long 0x00 "EXTICR1,SYSCFG External Interrupt Configuration Register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,PC3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,PB2,PC2,PD2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,PC1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,PC0,?..."
|
|
line.long 0x04 "EXTICR2,SYSCFG External Interrupt Configuration Register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,PC7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,PC6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,PC4,?..."
|
|
line.long 0x08 "EXTICR3,SYSCFG External Interrupt Configuration Register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,PB11,PC11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,PB10,PC10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,PC9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,PC8,?..."
|
|
line.long 0x0C "EXTICR4,SYSCFG External Interrupt Configuration Register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,PB14,PC14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,PB13,PC13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,PB12,PC12,?..."
|
|
elif cpuis("STM32F7??Z?")
|
|
group.long 0x08++0x0F
|
|
line.long 0x00 "EXTICR1,SYSCFG External Interrupt Configuration Register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,PC3,PD3,PE3,PF3,PG3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,PB2,PC2,PD2,PE2,PF2,PG2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,PC1,PD1,PE1,PF1,PG1,PH1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,PC0,PD0,PE0,PF0,PG0,PH0,?..."
|
|
line.long 0x04 "EXTICR2,SYSCFG External Interrupt Configuration Register 2"
|
|
sif !cpuis("STM32F730Z8")
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,PC7,PD7,PE7,PF7,PG7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,PC6,PD6,PE6,PF6,PG6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,PC5,PD5,PE5,PF5,PG5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,PC4,PD4,PE4,PF4,PG4,?..."
|
|
else
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,PC7,PD7,PE7,PF7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,PC6,PD6,PE6,PF6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,PC5,PD5,PE5,PF5,PG5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,PC4,PD4,PE4,PF4,PG4,?..."
|
|
endif
|
|
line.long 0x08 "EXTICR3,SYSCFG External Interrupt Configuration Register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,PB11,PC11,PD11,PE11,PF11,PG11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,PB10,PC10,PD10,PE10,PF10,PG10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,PC9,PD9,PE9,PF9,PG9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,PC8,PD8,PE8,PF8,PG8,?..."
|
|
line.long 0x0C "EXTICR4,SYSCFG External Interrupt Configuration Register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,PD15,PE15,PF15,PG15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,PB14,PC14,PD14,PE14,PF14,PG14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,PB13,PC13,PD13,PE13,PF13,PG13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,PB12,PC12,PD12,PE12,PF12,PG12,?..."
|
|
elif cpuis("STM32F7??I?")
|
|
group.long 0x08++0x0F
|
|
line.long 0x00 "EXTICR1,SYSCFG External Interrupt Configuration Register 1"
|
|
sif cpuis("STM32F730I8")
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,PC3,PD3,PE3,PF3,PG3,PH3,PI3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,PB2,PC2,PD2,PE2,PF2,PG2,PH2,PI2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,PC1,PD1,PE1,PF1,PG1,PH1,PI1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,PC0,PD0,PE0,PF0,PG0,PH0,PI0,?..."
|
|
else
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,PC3,PD3,PE3,PF3,PG3,PH3,PI3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,PB2,PC2,PD2,PE2,PF2,PG2,PH2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,PC1,PD1,PE1,PF1,PG1,PH1,PI1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,PC0,PD0,PE0,PF0,PG0,PH0,PI0,?..."
|
|
endif
|
|
line.long 0x04 "EXTICR2,SYSCFG External Interrupt Configuration Register 2"
|
|
sif !cpuis("STM32F730I8")
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,PC7,PD7,PE7,PF7,PG7,PH7,PI7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,PC6,PD6,PE6,PF6,PG6,PH6,PI6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,PC5,PD5,PE5,PF5,PG5,PH5,PI5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,PC4,PD4,PE4,PF4,PG4,PH4,PI4,?..."
|
|
else
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,PC7,PD7,PE7,PF7,,PH7,PI7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,PC6,PD6,PE6,PF6,,PH6,PI6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,PC5,PD5,PE5,PF5,PG5,PH5,PI5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,PC4,PD4,PE4,PF4,PG4,PH4,PI4,?..."
|
|
endif
|
|
line.long 0x08 "EXTICR3,SYSCFG External Interrupt Configuration Register 3"
|
|
sif !cpuis("STM32F730I8")
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,PB11,PC11,PD11,PE11,PF11,PG11,,PI11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,PB10,PC10,PD10,PE10,PF10,PG10,,PI10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,PC9,PD9,PE9,PF9,PG9,,PI9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,PC8,PD8,PE8,PF8,PG8,,PI8,?..."
|
|
else
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,PB11,PC11,PD11,PE11,PF11,PG11,PH11,PI11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,PB10,PC10,PD10,PE10,PF10,PG10,PH10,PI10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,PC9,PD9,PE9,PF9,PG9,PH9,PI9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,PC8,PD8,PE8,PF8,PG8,PH8,PI8,?..."
|
|
endif
|
|
line.long 0x0C "EXTICR4,SYSCFG External Interrupt Configuration Register 4"
|
|
sif !cpuis("STM32F730I8")
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,PD15,PE15,PF15,PG15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,PB14,PC14,PD14,PE14,PF14,PG14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,PB13,PC13,PD13,PE13,PF13,PG13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,PB12,PC12,PD12,PE12,PF12,PG12,?..."
|
|
else
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,PD15,PE15,PF15,PG15,PH15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,PB14,PC14,PD14,PE14,PF14,PG14,PH14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,PB13,PC13,PD13,PE13,PF13,PG13,PH13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,PB12,PC12,PD12,PE12,PF12,PG12,PH12,?..."
|
|
endif
|
|
elif (cpuis("STM32F7??B?")||cpuis("STM32F7??N?"))
|
|
group.long 0x08++0x0F
|
|
line.long 0x00 "EXTICR1,SYSCFG External Interrupt Configuration Register 1"
|
|
sif !cpuis("STM32F750N8")
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,PC3,PD3,PE3,PF3,PG3,PH3,PI3,PJ3,PK3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,PB2,PC2,PD2,PE2,PF2,PG2,PH2,PI2,PJ2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,PC1,PD1,PE1,PF1,PG1,PH1,PI1,PJ1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,PC0,PD0,PE0,PF0,PG0,PH0,PI0,PJ0,?..."
|
|
else
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,PC3,PD3,PE3,PF3,PG3,PH3,PI3,PJ3,PK3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,PB2,PC2,PD2,PE2,PF2,PG2,PH2,PI2,PJ2,PK2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,PC1,PD1,PE1,PF1,PG1,PH1,PI1,PJ1,PK1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,PC0,PD0,PE0,PF0,PG0,PH0,PI0,PJ0,PK0,?..."
|
|
endif
|
|
line.long 0x04 "EXTICR2,SYSCFG External Interrupt Configuration Register 2"
|
|
sif !cpuis("STM32F750N8")
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,PC7,PD7,PE7,PF7,PG7,PH7,PI7,,PK7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,PC6,PD6,PE6,PF6,PG6,PH6,PI6,,PK6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,PC5,PD5,PE5,PF5,PG5,PH5,PI5,PJ5,PK5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,PC4,PD4,PE4,PF4,PG4,PH4,PI4,PJ4,PK4,?..."
|
|
else
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,PC7,PD7,PE7,PF7,PG7,PH7,PI7,PJ7,PK7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,PC6,PD6,PE6,PF6,PG6,PH6,PI6,PJ6,PK6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,PC5,PD5,PE5,PF5,PG5,PH5,PI5,PJ5,PK5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,PC4,PD4,PE4,PF4,PG4,PH4,PI4,PJ4,PK4,?..."
|
|
endif
|
|
line.long 0x08 "EXTICR3,SYSCFG External Interrupt Configuration Register 3"
|
|
sif !cpuis("STM32F750N8")
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,PB11,PC11,PD11,PE11,PF11,PG11,PH11,PI11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,PB10,PC10,PD10,PE10,PF10,PG10,PH10,PI10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,PC9,PD9,PE9,PF9,PG9,PH9,PI9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,PC8,PD8,PE8,PF8,PG8,PH8,PI8,?..."
|
|
else
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,PB11,PC11,PD11,PE11,PF11,PG11,PH11,PI11,PJ11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,PB10,PC10,PD10,PE10,PF10,PG10,PH10,PI10,PJ10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,PC9,PD9,PE9,PF9,PG9,PH9,PI9,PJ9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,PC8,PD8,PE8,PF8,PG8,PH8,PI8,PJ8,?..."
|
|
endif
|
|
line.long 0x0C "EXTICR4,SYSCFG External Interrupt Configuration Register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,PD15,PE15,PF15,PG15,PH15,PI15,PJ15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,PB14,PC14,PD14,PE14,PF14,PG14,PH14,PI14,PJ14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,PB13,PC13,PD13,PE13,PF13,PG13,PH13,PI13,PJ13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,PB12,PC12,PD12,PE12,PF12,PG12,PH12,PI12,PJ12,?..."
|
|
elif cpuis("STM32F769A*")
|
|
group.long 0x08++0x0F
|
|
line.long 0x00 "EXTICR1,SYSCFG External Interrupt Configuration Register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,,,PD3,PE3,PF3,PG3,PH3,PI3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,PB2,,PD2,PE2,PF2,PG2,PH2,PI2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,PC1,PD1,PE1,PF1,PG1,,PI1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" ",PB0,PC0,PD0,PE0,PF0,PG0,,PI0,?..."
|
|
line.long 0x04 "EXTICR2,SYSCFG External Interrupt Configuration Register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,PC7,PD7,PE7,,PG7,,PI7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,PC6,PD6,PE6,,PG6,,PI6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,,PD5,PE5,PF5,PG5,PH5,PI5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,,,PD4,PE4,PF4,PG4,PH4,PI4,?..."
|
|
line.long 0x08 "EXTICR3,SYSCFG External Interrupt Configuration Register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,PB11,PC11,PD11,PE11,PF11,PG11,PH11,PI11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,PB10,PC10,PD10,PE10,PF10,PG10,PH10,PI10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,PC9,PD9,PE9,,PG9,PH9,PI9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,PC8,PD8,PE8,,PG8,PH8,?..."
|
|
line.long 0x0C "EXTICR4,SYSCFG External Interrupt Configuration Register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,PD15,PE15,PF15,PG15,PH15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" ",PB14,,,PE14,PF14,,PH14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" ",PB13,PC13,PD13,PE13,PF13,PG13,PH13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,PB12,PC12,PD12,PE12,PF12,PG12,PH12,?..."
|
|
endif
|
|
sif cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CBR,Class B Register"
|
|
bitfld.long 0x00 2. " PVDL ,PVD lock" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " CLL ,Core lockup lock" "Not locked,Locked"
|
|
endif
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CMPCR,Compensation Cell Control Register"
|
|
rbitfld.long 0x00 8. " READY ,Compensation cell ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " CMP_PD ,Compensation cell power-down" "Powered-down,Cell enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "DMA (Direct Memory Access Controller)"
|
|
tree "DMA 1"
|
|
base ad:0x40026000
|
|
width 7.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "LISR,DMA Low Interrupt Status Register"
|
|
bitfld.long 0x00 27. " TCIF3 ,Stream 3 transfer complete interrupt flag" "Not completed,Completed"
|
|
bitfld.long 0x00 26. " HTIF3 ,Stream 3 half transfer interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 25. " TEIF3 ,Stream 3 transfer error interrupt flag" "No error,Error"
|
|
bitfld.long 0x00 24. " DMEIF3 ,Stream 3 direct mode error interrupt flag" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 22. " FEIF3 ,Stream 3 FIFO error interrupt flag" "No error,Error"
|
|
bitfld.long 0x00 21. " TCIF2 ,Stream 2 transfer complete interrupt flag" "Not completed,Completed"
|
|
bitfld.long 0x00 20. " HTIF2 ,Stream 2 half transfer interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 19. " TEIF2 ,Stream 2 transfer error interrupt flag" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 18. " DMEIF2 ,Stream 2 direct mode error interrupt flag" "No error,Error"
|
|
bitfld.long 0x00 16. " FEIF2 ,Stream 2 FIFO error interrupt flag" "No error,Error"
|
|
bitfld.long 0x00 11. " TCIF1 ,Stream 1 transfer complete interrupt flag" "Not completed,Completed"
|
|
bitfld.long 0x00 10. " HTIF1 ,Stream 1 half transfer interrupt flag" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 9. " TEIF1 ,Stream 1 transfer error interrupt flag" "No error,Error"
|
|
bitfld.long 0x00 8. " DMEIF1 ,Stream 1 direct mode error interrupt flag" "No error,Error"
|
|
bitfld.long 0x00 6. " FEIF1 ,Stream 1 FIFO error interrupt flag" "No error,Error"
|
|
bitfld.long 0x00 5. " TCIF0 ,Stream 0 transfer complete interrupt flag" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x00 4. " HTIF0 ,Stream 0 half transfer interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " TEIF0 ,Stream 0 transfer error interrupt flag" "No error,Error"
|
|
bitfld.long 0x00 2. " DMEIF0 ,Stream 0 direct mode error interrupt flag" "No error,Error"
|
|
bitfld.long 0x00 0. " FEIF0 ,Stream 0 FIFO error interrupt flag" "No error,Error"
|
|
line.long 0x04 "HISR,DMA High Interrupt Status Register"
|
|
bitfld.long 0x04 27. " TCIF7 ,Stream 7 transfer complete interrupt flag" "Not completed,Completed"
|
|
bitfld.long 0x04 26. " HTIF7 ,Stream 7 half transfer interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 25. " TEIF7 ,Stream 7 transfer error interrupt flag" "No error,Error"
|
|
bitfld.long 0x04 24. " DMEIF7 ,Stream 7 direct mode error interrupt flag" "No error,Error"
|
|
newline
|
|
bitfld.long 0x04 22. " FEIF7 ,Stream 7 FIFO error interrupt flag" "No error,Error"
|
|
bitfld.long 0x04 21. " TCIF6 ,Stream 6 transfer complete interrupt flag" "Not completed,Completed"
|
|
bitfld.long 0x04 20. " HTIF6 ,Stream 6 half transfer interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 19. " TEIF6 ,Stream 6 transfer error interrupt flag" "No error,Error"
|
|
newline
|
|
bitfld.long 0x04 18. " DMEIF6 ,Stream 6 direct mode error interrupt flag" "No error,Error"
|
|
bitfld.long 0x04 16. " FEIF6 ,Stream 6 FIFO error interrupt flag" "No error,Error"
|
|
bitfld.long 0x04 11. " TCIF5 ,Stream 5 transfer complete interrupt flag" "Not completed,Completed"
|
|
bitfld.long 0x04 10. " HTIF5 ,Stream 5 half transfer interrupt flag" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x04 9. " TEIF5 ,Stream 5 transfer error interrupt flag" "No error,Error"
|
|
bitfld.long 0x04 8. " DMEIF5 ,Stream 5 direct mode error interrupt flag" "No error,Error"
|
|
bitfld.long 0x04 6. " FEIF5 ,Stream 5 FIFO error interrupt flag" "No error,Error"
|
|
bitfld.long 0x04 5. " TCIF4 ,Stream 4 transfer complete interrupt flag" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x04 4. " HTIF4 ,Stream 4 half transfer interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 3. " TEIF4 ,Stream 4 transfer error interrupt flag" "No error,Error"
|
|
bitfld.long 0x04 2. " DMEIF4 ,Stream 4 direct mode error interrupt flag" "No error,Error"
|
|
bitfld.long 0x04 0. " FEIF4 ,Stream 4 FIFO error interrupt flag" "No error,Error"
|
|
sif (cpuis("STM32F4*")||cpuis("STM32F7*")||cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32H742*")||cpuis("STM32H750*"))
|
|
wgroup.long 0x08++0x07
|
|
line.long 0x00 "LIFCR,DMA Low Interrupt Flag Clear Register"
|
|
bitfld.long 0x00 27. " CTCIF3 ,Stream 3 clear transfer complete interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 26. " CHTIF3 ,Stream 3 clear half transfer interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 25. " CTEIF3 ,Stream 3 clear transfer error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 24. " CDMEIF3 ,Stream 3 clear direct mode error interrupt flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 22. " CFEIF3 ,Stream 3 clear FIFO error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 21. " CTCIF2 ,Stream 2 clear transfer complete interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 20. " CHTIF2 ,Stream 2 clear half transfer interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 19. " CTEIF2 ,Stream 2 clear transfer error interrupt flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 18. " CDMEIF2 ,Stream 2 clear direct mode error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 16. " CFEIF2 ,Stream 2 clear FIFO error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 11. " CTCIF1 ,Stream 1 clear transfer complete interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CHTIF1 ,Stream 1 clear half transfer interrupt flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 9. " CTEIF1 ,Stream 1 clear transfer error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 8. " CDMEIF1 ,Stream 1 clear direct mode error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 6. " CFEIF1 ,Stream 1 clear FIFO error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 5. " CTCIF0 ,Stream 0 clear transfer complete interrupt flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 4. " CHTIF0 ,Stream 0 clear half transfer interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 3. " CTEIF0 ,Stream 0 transfer error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CDMEIF0 ,Stream 0 clear direct mode error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CFEIF0 ,Stream 0 clear FIFO error interrupt flag" "No effect,Clear"
|
|
line.long 0x04 "HIFCR,DMA High Interrupt Flag Clear Register"
|
|
bitfld.long 0x04 27. " CTCIF7 ,Stream 7 clear transfer complete interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 26. " CHTIF7 ,Stream 7 clear half transfer interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 25. " CTEIF7 ,Stream 7 clear transfer error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 24. " CDMEIF7 ,Stream 7 clear direct mode error interrupt flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 22. " CFEIF7 ,Stream 7 clear FIFO error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 21. " CTCIF6 ,Stream 6 clear transfer complete interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 20. " CHTIF6 ,Stream 6 clear half transfer interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 19. " CTEIF6 ,Stream 6 transfer error interrupt flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 18. " CDMEIF6 ,Stream 6 clear direct mode error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 16. " CFEIF6 ,Stream 6 clear FIFO error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 11. " CTCIF5 ,Stream 5 clear transfer complete interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 10. " CHTIF5 ,Stream 5 clear half transfer interrupt flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 9. " CTEIF5 ,Stream 5 transfer error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 8. " CDMEIF5 ,Stream 5 clear direct mode error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 6. " CFEIF5 ,Stream 5 clear FIFO error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 5. " CTCIF4 ,Stream 4 clear transfer complete interrupt flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 4. " CHTIF4 ,Stream 4 clear half transfer interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 3. " CTEIF4 ,Stream 4 transfer error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 2. " CDMEIF4 ,Stream 4 clear direct mode error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 0. " CFEIF4 ,Stream 4 clear FIFO error interrupt flag" "No effect,Clear"
|
|
else
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "LIFCR,DMA Low Interrupt Flag Clear Register"
|
|
bitfld.long 0x00 27. " CTCIF3 ,Stream 3 clear transfer complete interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 26. " CHTIF3 ,Stream 3 clear half transfer interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 25. " CTEIF3 ,Stream 3 clear transfer error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 24. " CDMEIF3 ,Stream 3 clear direct mode error interrupt flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 22. " CFEIF3 ,Stream 3 clear FIFO error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 21. " CTCIF2 ,Stream 2 clear transfer complete interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 20. " CHTIF2 ,Stream 2 clear half transfer interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 19. " CTEIF2 ,Stream 2 clear transfer error interrupt flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 18. " CDMEIF2 ,Stream 2 clear direct mode error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 16. " CFEIF2 ,Stream 2 clear FIFO error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 11. " CTCIF1 ,Stream 1 clear transfer complete interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CHTIF1 ,Stream 1 clear half transfer interrupt flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 9. " CTEIF1 ,Stream 1 clear transfer error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 8. " CDMEIF1 ,Stream 1 clear direct mode error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 6. " CFEIF1 ,Stream 1 clear FIFO error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 5. " CTCIF0 ,Stream 0 clear transfer complete interrupt flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 4. " CHTIF0 ,Stream 0 clear half transfer interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 3. " CTEIF0 ,Stream 0 transfer error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CDMEIF0 ,Stream 0 clear direct mode error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CFEIF0 ,Stream 0 clear FIFO error interrupt flag" "No effect,Clear"
|
|
line.long 0x04 "HIFCR,DMA High Interrupt Flag Clear Register"
|
|
bitfld.long 0x04 27. " CTCIF7 ,Stream 7 clear transfer complete interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 26. " CHTIF7 ,Stream 7 clear half transfer interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 25. " CTEIF7 ,Stream 7 clear transfer error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 24. " CDMEIF7 ,Stream 7 clear direct mode error interrupt flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 22. " CFEIF7 ,Stream 7 clear FIFO error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 21. " CTCIF6 ,Stream 6 clear transfer complete interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 20. " CHTIF6 ,Stream 6 clear half transfer interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 19. " CTEIF6 ,Stream 6 transfer error interrupt flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 18. " CDMEIF6 ,Stream 6 clear direct mode error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 16. " CFEIF6 ,Stream 6 clear FIFO error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 11. " CTCIF5 ,Stream 5 clear transfer complete interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 10. " CHTIF5 ,Stream 5 clear half transfer interrupt flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 9. " CTEIF5 ,Stream 5 transfer error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 8. " CDMEIF5 ,Stream 5 clear direct mode error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 6. " CFEIF5 ,Stream 5 clear FIFO error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 5. " CTCIF4 ,Stream 4 clear transfer complete interrupt flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 4. " CHTIF4 ,Stream 4 clear half transfer interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 3. " CTEIF4 ,Stream 4 transfer error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 2. " CDMEIF4 ,Stream 4 clear direct mode error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 0. " CFEIF4 ,Stream 4 clear FIFO error interrupt flag" "No effect,Clear"
|
|
endif
|
|
width 8.
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*")&&!cpuis("STM32H742*")&&!cpuis("STM32H750*"))
|
|
tree "Stream 0 registers"
|
|
if (((per.l(ad:0x40026000+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "S0CR,DMA Stream 0 Configuration Register"
|
|
sif (cpuis("STM32F74*")||cpuis("STM32F75*"))
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPI3_RX,I2C1_RX,TIM4_CH1,,UART5_RX,UART8_TX,TIM5_CH3/TIM5_UP,?..."
|
|
newline
|
|
elif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SPI3_RX,I2C1_RX,TIM4_CH1,,UART5_RX,UART8_TX,TIM5_CH3/TIM5_UP,,I2C3_TX,?..."
|
|
newline
|
|
elif cpuis("STM32F72*")||cpuis("STM32F732*")||cpuis("STM32F733*")
|
|
sif (cpuis("STM32F72?R*")||cpuis("STM32F73?R*"))
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPI3_RX,I2C1_RX,TIM4_CH1,,UART5_RX,,TIM5_CH3/TIM5_UP,?..."
|
|
else
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPI3_RX,I2C1_RX,TIM4_CH1,,UART5_RX,UART8_TX,TIM5_CH3/TIM5_UP,?..."
|
|
endif
|
|
newline
|
|
elif cpuis("STM32F730*")
|
|
sif cpuis("STM32F73?R*")
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SPI3_RX,I2C1_RX,TIM4_CH1,,UART5_RX,,TIM5_CH3/TIM5_UP,?..."
|
|
else
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SPI3_RX,I2C1_RX,TIM4_CH1,,UART5_RX,UART8_TX,TIM5_CH3/TIM5_UP,?..."
|
|
endif
|
|
newline
|
|
else
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPI3_RX,I2C1_RX,TIM4_CH1,I2S3_EXT_RX,UART5_RX,,TIM5_CH3/TIM5_UP,?..."
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
newline
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "S0NDTR,DMA Stream 0 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S0PAR,DMA Stream 0 Peripheral Address Register"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "S0CR,DMA Stream 0 Configuration Register"
|
|
sif (cpuis("STM32F74*")||cpuis("STM32F75*"))
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPI3_RX,I2C1_RX,TIM4_CH1,,UART5_RX,UART8_TX,TIM5_CH3/TIM5_UP,?..."
|
|
newline
|
|
elif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SPI3_RX,I2C1_RX,TIM4_CH1,,UART5_RX,UART8_TX,TIM5_CH3/TIM5_UP,,I2C3_TX,?..."
|
|
newline
|
|
elif cpuis("STM32F72*")||cpuis("STM32F732*")||cpuis("STM32F733*")
|
|
sif (cpuis("STM32F72?R*")||cpuis("STM32F73?R*"))
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPI3_RX,I2C1_RX,TIM4_CH1,,UART5_RX,,TIM5_CH3/TIM5_UP,?..."
|
|
else
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPI3_RX,I2C1_RX,TIM4_CH1,,UART5_RX,UART8_TX,TIM5_CH3/TIM5_UP,?..."
|
|
endif
|
|
newline
|
|
elif cpuis("STM32F730*")
|
|
sif cpuis("STM32F73?R*")
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SPI3_RX,I2C1_RX,TIM4_CH1,,UART5_RX,,TIM5_CH3/TIM5_UP,?..."
|
|
else
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SPI3_RX,I2C1_RX,TIM4_CH1,,UART5_RX,UART8_TX,TIM5_CH3/TIM5_UP,?..."
|
|
endif
|
|
newline
|
|
else
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPI3_RX,I2C1_RX,TIM4_CH1,I2S3_EXT_RX,UART5_RX,,TIM5_CH3/TIM5_UP,?..."
|
|
newline
|
|
endif
|
|
newline
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
newline
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "S0NDTR,DMA Stream 0 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S0PAR,DMA Stream 0 Peripheral Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0x10))&0x01)==0x00)||((((per.l(ad:0x40026000+0x10))&0x01)==0x01)&&(((per.l(ad:0x40026000+0x10))&0x80000)==0x80000))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "S0M0AR,DMA Stream 0 Memory 0 Address Register"
|
|
else
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "S0M0AR,DMA Stream 0 Memory 0 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0x10))&0x01)==0x00)||((((per.l(ad:0x40026000+0x10))&0x01)==0x01)&&(((per.l(ad:0x40026000+0x10))&0x80000)==0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "S0M1AR,DMA Stream 0 Memory 1 Address Register"
|
|
else
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "S0M1AR,DMA Stream 0 Memory 1 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0x10))&0x01)==0x00)
|
|
if (((per.l(ad:0x40026000+0x24))&0x04)==0x04)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "S0FCR,DMA Stream 0 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "S0FCR,DMA Stream 0 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40026000+0x24))&0x04)==0x04)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "S0FCR,DMA Stream 0 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
rbitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "S0FCR,DMA Stream 0 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Stream 1 registers"
|
|
if (((per.l(ad:0x40026000+0x28))&0x01)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "S1CR,DMA Stream 1 Configuration Register"
|
|
sif (cpuis("STM32F74*")||cpuis("STM32F75*"))
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPDIFRX_DT,I2C3_RX,,TIM2_UP/TIM2_CH3,USART3_RX,UART7_TX,TIM5_CH4/TIM5_TRIG,TIM6_UP"
|
|
newline
|
|
elif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SPDIFRX_DT,I2C3_RX,,TIM2_UP/TIM2_CH3,USART3_RX,UART7_TX,TIM5_CH4/TIM5_TRIG,TIM6_UP,I2C4_RX,SPI2_RX,?..."
|
|
newline
|
|
elif (cpuis("STM32F72*")||cpuis("STM32F732*")||cpuis("STM32F733*"))
|
|
sif (cpuis("STM32F72?R*")||cpuis("STM32F73?R*"))
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" ",I2C3_RX,,TIM2_UP/TIM2_CH3,USART3_RX,,TIM5_CH4/TIM5_TRIG,TIM6_UP"
|
|
else
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" ",I2C3_RX,,TIM2_UP/TIM2_CH3,USART3_RX,UART7_TX,TIM5_CH4/TIM5_TRIG,TIM6_UP"
|
|
endif
|
|
newline
|
|
elif cpuis("STM32F730*")
|
|
sif cpuis("STM32F73?R*")
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" ",I2C3_RX,,TIM2_UP/TIM2_CH3,USART3_RX,,TIM5_CH4/TIM5_TRIG,TIM6_UP,?..."
|
|
else
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" ",I2C3_RX,,TIM2_UP/TIM2_CH3,USART3_RX,UART7_TX,TIM5_CH4/TIM5_TRIG,TIM6_UP,?..."
|
|
endif
|
|
newline
|
|
else
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" ",,,TIM2_UP/TIM2_CH3,USART3_RX,,TIM5_CH4/TIM5_TRIG,TIM6_UP"
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
newline
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
group.long 0x2C++0x07
|
|
line.long 0x00 "S1NDTR,DMA Stream 1 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S1PAR,DMA Stream 1 Peripheral Address Register"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "S1CR,DMA Stream 1 Configuration Register"
|
|
sif (cpuis("STM32F74*")||cpuis("STM32F75*"))
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPDIFRX_DT,I2C3_RX,,TIM2_UP/TIM2_CH3,USART3_RX,UART7_TX,TIM5_CH4/TIM5_TRIG,TIM6_UP"
|
|
newline
|
|
elif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SPDIFRX_DT,I2C3_RX,,TIM2_UP/TIM2_CH3,USART3_RX,UART7_TX,TIM5_CH4/TIM5_TRIG,TIM6_UP,I2C4_RX,SPI2_RX,?..."
|
|
newline
|
|
elif (cpuis("STM32F72*")||cpuis("STM32F732*")||cpuis("STM32F733*"))
|
|
sif (cpuis("STM32F72?R*")||cpuis("STM32F73?R*"))
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" ",I2C3_RX,,TIM2_UP/TIM2_CH3,USART3_RX,,TIM5_CH4/TIM5_TRIG,TIM6_UP"
|
|
else
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" ",I2C3_RX,,TIM2_UP/TIM2_CH3,USART3_RX,UART7_TX,TIM5_CH4/TIM5_TRIG,TIM6_UP"
|
|
endif
|
|
newline
|
|
elif cpuis("STM32F730*")
|
|
sif cpuis("STM32F73?R*")
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" ",I2C3_RX,,TIM2_UP/TIM2_CH3,USART3_RX,,TIM5_CH4/TIM5_TRIG,TIM6_UP,?..."
|
|
else
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" ",I2C3_RX,,TIM2_UP/TIM2_CH3,USART3_RX,UART7_TX,TIM5_CH4/TIM5_TRIG,TIM6_UP,?..."
|
|
endif
|
|
newline
|
|
else
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" ",,,TIM2_UP/TIM2_CH3,USART3_RX,,TIM5_CH4/TIM5_TRIG,TIM6_UP"
|
|
newline
|
|
endif
|
|
newline
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
newline
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
rgroup.long 0x2C++0x07
|
|
line.long 0x00 "S1NDTR,DMA Stream 1 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S1PAR,DMA Stream 1 Peripheral Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0x28))&0x01)==0x00)||((((per.l(ad:0x40026000+0x28))&0x01)==0x01)&&(((per.l(ad:0x40026000+0x28))&0x80000)==0x8000))
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "S1M0AR,DMA Stream 1 Memory 0 Address Register"
|
|
else
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "S1M0AR,DMA Stream 1 Memory 0 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0x28))&0x01)==0x00)||((((per.l(ad:0x40026000+0x28))&0x01)==0x01)&&(((per.l(ad:0x40026000+0x28))&0x80000)==0x8000))
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "S1M1AR,DMA Stream 1 Memory 1 Address Register"
|
|
else
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "S1M1AR,DMA Stream 1 Memory 1 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0x28))&0x01)==0x00)
|
|
if (((per.l(ad:0x40026000+0x3C))&0x04)==0x04)
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "S1FCR,DMA Stream 1 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "S1FCR,DMA Stream 1 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40026000+0x3C))&0x04)==0x04)
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "S1FCR,DMA Stream 1 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
rbitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "S1FCR,DMA Stream 1 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Stream 2 registers"
|
|
if (((per.l(ad:0x40026000+0x40))&0x01)==0x00)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "S2CR,DMA Stream 2 Configuration Register"
|
|
sif (cpuis("STM32F74*")||cpuis("STM32F75*"))
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPI3_RX,TIM7_UP,I2C4_RX,I2C3_RX,UART4_RX,TIM3_CH4/TIM3_UP,TIM5_CH1,I2C2_RX"
|
|
newline
|
|
elif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SPI3_RX,TIM7_UP,I2C4_RX,I2C3_RX,UART4_RX,TIM3_CH4/TIM3_UP,TIM5_CH1,I2C2_RX,?..."
|
|
newline
|
|
elif (cpuis("STM32F72*")||cpuis("STM32F732*")||cpuis("STM32F733*"))
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPI3_RX,TIM7_UP,,I2C3_RX,UART4_RX,TIM3_CH4/TIM3_UP,TIM5_CH1,I2C2_RX"
|
|
newline
|
|
elif cpuis("STM32F730*")
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SPI3_RX,TIM7_UP,,I2C3_RX,UART4_RX,TIM3_CH4/TIM3_UP,TIM5_CH1,I2C2_RX,?..."
|
|
newline
|
|
else
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPI3_RX,,I2S3_EXT_RX,I2C3_RX,,TIM3_CH4/TIM3_UP,TIM5_CH1,I2C2_RX"
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
newline
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
group.long 0x44++0x07
|
|
line.long 0x00 "S2NDTR,DMA Stream 2 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S2PAR,DMA Stream 2 Peripheral Address Register"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "S2CR,DMA Stream 2 Configuration Register"
|
|
sif (cpuis("STM32F74*")||cpuis("STM32F75*"))
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPI3_RX,TIM7_UP,I2C4_RX,I2C3_RX,UART4_RX,TIM3_CH4/TIM3_UP,TIM5_CH1,I2C2_RX"
|
|
newline
|
|
elif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SPI3_RX,TIM7_UP,I2C4_RX,I2C3_RX,UART4_RX,TIM3_CH4/TIM3_UP,TIM5_CH1,I2C2_RX,?..."
|
|
newline
|
|
elif (cpuis("STM32F72*")||cpuis("STM32F732*")||cpuis("STM32F733*"))
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPI3_RX,TIM7_UP,,I2C3_RX,UART4_RX,TIM3_CH4/TIM3_UP,TIM5_CH1,I2C2_RX"
|
|
newline
|
|
elif cpuis("STM32F730*")
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SPI3_RX,TIM7_UP,,I2C3_RX,UART4_RX,TIM3_CH4/TIM3_UP,TIM5_CH1,I2C2_RX,?..."
|
|
newline
|
|
else
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPI3_RX,,I2S3_EXT_RX,I2C3_RX,,TIM3_CH4/TIM3_UP,TIM5_CH1,I2C2_RX"
|
|
newline
|
|
endif
|
|
newline
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
newline
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
rgroup.long 0x44++0x07
|
|
line.long 0x00 "S2NDTR,DMA Stream 2 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S2PAR,DMA Stream 2 Peripheral Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0x40))&0x01)==0x00)||((((per.l(ad:0x40026000+0x40))&0x01)==0x01)&&(((per.l(ad:0x40026000+0x40))&0x80000)==0x80000))
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "S2M0AR,DMA Stream 2 Memory 0 Address Register"
|
|
else
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "S2M0AR,DMA Stream 2 Memory 0 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0x40))&0x01)==0x00)||((((per.l(ad:0x40026000+0x40))&0x01)==0x01)&&(((per.l(ad:0x40026000+0x40))&0x80000)==0x00))
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "S2M1AR,DMA Stream 2 Memory 1 Address Register"
|
|
else
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "S2M1AR,DMA Stream 2 Memory 1 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0x40))&0x01)==0x00)
|
|
if (((per.l(ad:0x40026000+0x54))&0x04)==0x04)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "S2FCR,DMA Stream 2 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "S2FCR,DMA Stream 2 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40026000+0x54))&0x04)==0x04)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "S2FCR,DMA Stream 2 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
rbitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "S2FCR,DMA Stream 2 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Stream 3 registers"
|
|
if (((per.l(ad:0x40026000+0x58))&0x01)==0x00)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "S3CR,DMA Stream 3 Configuration Register"
|
|
sif (cpuis("STM32F74*")||cpuis("STM32F75*"))
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPI2_RX,,TIM4_CH2,,USART3_TX,USART7_RX,TIM5_CH4/TIM5_TRIG,I2C2_RX"
|
|
newline
|
|
elif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SPI2_RX,,TIM4_CH2,,USART3_TX,UART7_RX,TIM5_CH4/TIM5_TRIG,I2C2_RX,?..."
|
|
newline
|
|
elif (cpuis("STM32F72*")||cpuis("STM32F732*")||cpuis("STM32F733*"))
|
|
sif (cpuis("STM32F72?R*")||cpuis("STM32F73?R*"))
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPI2_RX,,TIM4_CH2,,USART3_TX,,TIM5_CH4/TIM5_TRIG,I2C2_RX"
|
|
else
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPI2_RX,,TIM4_CH2,,USART3_TX,UART7_RX,TIM5_CH4/TIM5_TRIG,I2C2_RX"
|
|
endif
|
|
newline
|
|
elif cpuis("STM32F730*")
|
|
sif cpuis("STM32F73?R*")
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SPI2_RX,,TIM4_CH2,,USART3_TX,,TIM5_CH4/TIM5_TRIG,I2C2_RX,?..."
|
|
else
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SPI2_RX,,TIM4_CH2,,USART3_TX,UART7_RX,TIM5_CH4/TIM5_TRIG,I2C2_RX,?..."
|
|
endif
|
|
newline
|
|
else
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPI2_RX,,TIM4_CH2,I2S2_EXT_RX,USART3_TX,,TIM5_CH4/TIM5_TRIG,I2C2_RX"
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
newline
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
group.long 0x5C++0x07
|
|
line.long 0x00 "S3NDTR,DMA Stream 3 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S3PAR,DMA Stream 3 Peripheral Address Register"
|
|
else
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "S3CR,DMA Stream 3 Configuration Register"
|
|
sif (cpuis("STM32F74*")||cpuis("STM32F75*"))
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPI2_RX,,TIM4_CH2,,USART3_TX,USART7_RX,TIM5_CH4/TIM5_TRIG,I2C2_RX"
|
|
newline
|
|
elif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SPI2_RX,,TIM4_CH2,,USART3_TX,UART7_RX,TIM5_CH4/TIM5_TRIG,I2C2_RX,?..."
|
|
newline
|
|
elif (cpuis("STM32F72*")||cpuis("STM32F732*")||cpuis("STM32F733*"))
|
|
sif (cpuis("STM32F72?R*")||cpuis("STM32F73?R*"))
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPI2_RX,,TIM4_CH2,,USART3_TX,,TIM5_CH4/TIM5_TRIG,I2C2_RX"
|
|
else
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPI2_RX,,TIM4_CH2,,USART3_TX,UART7_RX,TIM5_CH4/TIM5_TRIG,I2C2_RX"
|
|
endif
|
|
newline
|
|
elif cpuis("STM32F730*")
|
|
sif cpuis("STM32F73?R*")
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SPI2_RX,,TIM4_CH2,,USART3_TX,,TIM5_CH4/TIM5_TRIG,I2C2_RX,?..."
|
|
else
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SPI2_RX,,TIM4_CH2,,USART3_TX,UART7_RX,TIM5_CH4/TIM5_TRIG,I2C2_RX,?..."
|
|
endif
|
|
newline
|
|
else
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPI2_RX,,TIM4_CH2,I2S2_EXT_RX,USART3_TX,,TIM5_CH4/TIM5_TRIG,I2C2_RX"
|
|
newline
|
|
endif
|
|
newline
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
newline
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
rgroup.long 0x5C++0x07
|
|
line.long 0x00 "S3NDTR,DMA Stream 3 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S3PAR,DMA Stream 3 Peripheral Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0x58))&0x01)==0x00)||((((per.l(ad:0x40026000+0x58))&0x01)==0x01)&&(((per.l(ad:0x40026000+0x58))&0x80000)==0x80000))
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "S3M0AR,DMA Stream 3 Memory 0 Address Register"
|
|
else
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "S3M0AR,DMA Stream 3 Memory 0 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0x58))&0x01)==0x00)||((((per.l(ad:0x40026000+0x58))&0x01)==0x01)&&(((per.l(ad:0x40026000+0x58))&0x80000)==0x00))
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "S3M1AR,DMA Stream 3 Memory 1 Address Register"
|
|
else
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "S3M1AR,DMA Stream 3 Memory 1 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0x58))&0x01)==0x00)
|
|
if (((per.l(ad:0x40026000+0x6C))&0x04)==0x04)
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "S3FCR,DMA Stream 3 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "S3FCR,DMA Stream 3 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40026000+0x6C))&0x04)==0x04)
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "S3FCR,DMA Stream 3 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
rbitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "S3FCR,DMA Stream 3 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Stream 4 registers"
|
|
if (((per.l(ad:0x40026000+0x70))&0x01)==0x00)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "S4CR,DMA Stream 4 Configuration Register"
|
|
sif (cpuis("STM32F74*")||cpuis("STM32F75*"))
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPI2_TX,TIM7_UP,,I2C3_TX,UART4_TX,TIM3_CH1/TIM3_TRIG,TIM5_CH2,USART3_TX"
|
|
newline
|
|
elif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SPI2_TX,TIM7_UP,,I2C3_TX,UART4_TX,TIM3_CH1/TIM3_TRIG,TIM5_CH2,USART3_TX,I2C2_TX,?..."
|
|
newline
|
|
elif (cpuis("STM32F72*")||cpuis("STM32F732*")||cpuis("STM32F733*"))
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPI2_TX,TIM7_UP,,I2C3_TX,UART4_TX,TIM3_CH1/TIM3_TRIG,TIM5_CH2,USART3_TX"
|
|
newline
|
|
elif cpuis("STM32F730*")
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SPI2_TX,TIM7_UP,,I2C3_TX,UART4_TX,TIM3_CH1/TIM3_TRIG,TIM5_CH2,USART3_TX,?..."
|
|
newline
|
|
else
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPI2_TX,,I2S2_EXT_TX,I2C3_TX,,TIM3_CH1/TIM3_TRIG,TIM5_CH2,?..."
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
newline
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
group.long 0x74++0x07
|
|
line.long 0x00 "S4NDTR,DMA Stream 4 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S4PAR,DMA Stream 4 Peripheral Address Register"
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "S4CR,DMA Stream 4 Configuration Register"
|
|
sif (cpuis("STM32F74*")||cpuis("STM32F75*"))
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPI2_TX,TIM7_UP,,I2C3_TX,UART4_TX,TIM3_CH1/TIM3_TRIG,TIM5_CH2,USART3_TX"
|
|
newline
|
|
elif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SPI2_TX,TIM7_UP,,I2C3_TX,UART4_TX,TIM3_CH1/TIM3_TRIG,TIM5_CH2,USART3_TX,I2C2_TX,?..."
|
|
newline
|
|
elif (cpuis("STM32F72*")||cpuis("STM32F732*")||cpuis("STM32F733*"))
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPI2_TX,TIM7_UP,,I2C3_TX,UART4_TX,TIM3_CH1/TIM3_TRIG,TIM5_CH2,USART3_TX"
|
|
newline
|
|
elif cpuis("STM32F730*")
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SPI2_TX,TIM7_UP,,I2C3_TX,UART4_TX,TIM3_CH1/TIM3_TRIG,TIM5_CH2,USART3_TX,?..."
|
|
newline
|
|
else
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPI2_TX,,I2S2_EXT_TX,I2C3_TX,,TIM3_CH1/TIM3_TRIG,TIM5_CH2,?..."
|
|
newline
|
|
endif
|
|
newline
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
newline
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
rgroup.long 0x74++0x07
|
|
line.long 0x00 "S4NDTR,DMA Stream 4 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S4PAR,DMA Stream 4 Peripheral Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0x70))&0x01)==0x00)||((((per.l(ad:0x40026000+0x70))&0x01)==0x01)&&(((per.l(ad:0x40026000+0x70))&0x80000)==0x80000))
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "S4M0AR,DMA Stream 4 Memory 0 Address Register"
|
|
else
|
|
rgroup.long 0x7C++0x03
|
|
line.long 0x00 "S4M0AR,DMA Stream 4 Memory 0 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0x70))&0x01)==0x00)||((((per.l(ad:0x40026000+0x70))&0x01)==0x01)&&(((per.l(ad:0x40026000+0x70))&0x80000)==0x00))
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "S4M1AR,DMA Stream 4 Memory 1 Address Register"
|
|
else
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "S4M1AR,DMA Stream 4 Memory 1 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0x28))&0x01)==0x00)
|
|
if (((per.l(ad:0x40026000+0x84))&0x04)==0x04)
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "S4FCR,DMA Stream 4 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "S4FCR,DMA Stream 4 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40026000+0x84))&0x04)==0x04)
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "S4FCR,DMA Stream 4 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
rbitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "S4FCR,DMA Stream 4 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Stream 5 registers"
|
|
if (((per.l(ad:0x40026000+0x88))&0x01)==0x00)
|
|
group.long 0x88++0x0B
|
|
line.long 0x00 "S5CR,DMA Stream 5 Configuration Register"
|
|
sif (cpuis("STM32F74*")||cpuis("STM32F75*"))
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPI3_TX,I2C1_RX,I2C4_TX,TIM2_CH1,USART2_RX,TIM3_CH2,,DAC1"
|
|
newline
|
|
elif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SPI3_TX,I2C1_RX,I2C4_RX,TIM2_CH1,USART2_RX,TIM3_CH2,,DAC1,?..."
|
|
newline
|
|
elif (cpuis("STM32F72*")||cpuis("STM32F732*")||cpuis("STM32F733*"))
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPI3_TX,I2C1_RX,,TIM2_CH1,USART2_RX,TIM3_CH2,,DAC1"
|
|
newline
|
|
elif cpuis("STM32F730*")
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SPI3_TX,I2C1_RX,,TIM2_CH1,USART2_RX,TIM3_CH2,,DAC1,?..."
|
|
newline
|
|
else
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPI3_TX,I2C1_RX,I2S3_EXT_TX,TIM2_CH1,USART2_RX,TIM3_CH2,,DAC1"
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
newline
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
line.long 0x04 "S5NDTR,DMA Stream 5 Number Of Data Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x08 "S5PAR,DMA Stream 5 Peripheral Address Register"
|
|
else
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "S5CR,DMA Stream 5 Configuration Register"
|
|
sif (cpuis("STM32F74*")||cpuis("STM32F75*"))
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPI3_TX,I2C1_RX,I2C4_TX,TIM2_CH1,USART2_RX,TIM3_CH2,,DAC1"
|
|
newline
|
|
elif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SPI3_TX,I2C1_RX,I2C4_RX,TIM2_CH1,USART2_RX,TIM3_CH2,,DAC1,?..."
|
|
newline
|
|
elif (cpuis("STM32F72*")||cpuis("STM32F732*")||cpuis("STM32F733*"))
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPI3_TX,I2C1_RX,,TIM2_CH1,USART2_RX,TIM3_CH2,,DAC1"
|
|
newline
|
|
elif cpuis("STM32F730*")
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SPI3_TX,I2C1_RX,,TIM2_CH1,USART2_RX,TIM3_CH2,,DAC1,?..."
|
|
newline
|
|
else
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPI3_TX,I2C1_RX,I2S3_EXT_TX,TIM2_CH1,USART2_RX,TIM3_CH2,,DAC1"
|
|
newline
|
|
endif
|
|
newline
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
newline
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
rgroup.long 0x8C++0x07
|
|
line.long 0x00 "S5NDTR,DMA Stream 5 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S5PAR,DMA Stream 5 Peripheral Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0x88))&0x01)==0x00)||((((per.l(ad:0x40026000+0x88))&0x01)==0x01)&&(((per.l(ad:0x40026000+0x88))&0x80000)==0x80000))
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "S5M0AR,DMA Stream 5 Memory 0 Address Register"
|
|
else
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "S5M0AR,DMA Stream 5 Memory 0 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0x88))&0x01)==0x00)||((((per.l(ad:0x40026000+0x88))&0x01)==0x01)&&(((per.l(ad:0x40026000+0x88))&0x80000)==0x00))
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "S5M1AR,DMA Stream 5 Memory 1 Address Register"
|
|
else
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "S5M1AR,DMA Stream 5 Memory 1 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0x88))&0x01)==0x00)
|
|
if (((per.l(ad:0x40026000+0x9C))&0x04)==0x04)
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "S5FCR,DMA Stream 5 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "S5FCR,DMA Stream 5 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40026000+0x9C))&0x04)==0x04)
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "S5FCR,DMA Stream 5 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
rbitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "S5FCR,DMA Stream 5 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Stream 6 registers"
|
|
if (((per.l(ad:0x40026000+0xA0))&0x01)==0x00)
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "S6CR,DMA Stream 6 Configuration Register"
|
|
sif (cpuis("STM32F74*")||cpuis("STM32F75*"))
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPDIFRX_CS,I2C1_TX,TIM4_UP,TIM2_CH2/TIM2_CH4,USART2_TX,UART8_RX,TIM5_UP,DAC2"
|
|
newline
|
|
elif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SPDIFRX_CS,I2C1_TX,TIM4_UP,TIM2_CH2/TIM2_CH4,USART2_TX,UART8_RX,TIM5_UP,DAC2,I2C4_TX,SPI2_TX,?..."
|
|
newline
|
|
elif (cpuis("STM32F72*")||cpuis("STM32F732*")||cpuis("STM32F733*"))
|
|
sif (cpuis("STM32F72?R*")||cpuis("STM32F73?R*"))
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" ",I2C1_TX,TIM4_UP,TIM2_CH2/TIM2_CH4,USART2_TX,,TIM5_UP,DAC2"
|
|
else
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" ",I2C1_TX,TIM4_UP,TIM2_CH2/TIM2_CH4,USART2_TX,UART8_RX,TIM5_UP,DAC2"
|
|
endif
|
|
newline
|
|
elif cpuis("STM32F730*")
|
|
sif cpuis("STM32F73?R*")
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" ",I2C1_TX,TIM4_UP,TIM2_CH2/TIM2_CH4,USART2_TX,,TIM5_UP,DAC2,?..."
|
|
else
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" ",I2C1_TX,TIM4_UP,TIM2_CH2/TIM2_CH4,USART2_TX,UART8_RX,TIM5_UP,DAC2,?..."
|
|
endif
|
|
newline
|
|
else
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" ",I2C1_TX,TIM4_UP,TIM2_CH2/TIM2_CH4,USART2_TX,,TIM5_UP,DAC2"
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
newline
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
group.long 0xA4++0x07
|
|
line.long 0x00 "S6NDTR,DMA Stream 6 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S6PAR,DMA Stream 6 Peripheral Address Register"
|
|
else
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "S6CR,DMA Stream 6 Configuration Register"
|
|
sif (cpuis("STM32F74*")||cpuis("STM32F75*"))
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPDIFRX_CS,I2C1_TX,TIM4_UP,TIM2_CH2/TIM2_CH4,USART2_TX,UART8_RX,TIM5_UP,DAC2"
|
|
newline
|
|
elif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SPDIFRX_CS,I2C1_TX,TIM4_UP,TIM2_CH2/TIM2_CH4,USART2_TX,UART8_RX,TIM5_UP,DAC2,I2C4_TX,SPI2_TX,?..."
|
|
newline
|
|
elif (cpuis("STM32F72*")||cpuis("STM32F732*")||cpuis("STM32F733*"))
|
|
sif (cpuis("STM32F72?R*")||cpuis("STM32F73?R*"))
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" ",I2C1_TX,TIM4_UP,TIM2_CH2/TIM2_CH4,USART2_TX,,TIM5_UP,DAC2"
|
|
else
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" ",I2C1_TX,TIM4_UP,TIM2_CH2/TIM2_CH4,USART2_TX,UART8_RX,TIM5_UP,DAC2"
|
|
endif
|
|
newline
|
|
elif cpuis("STM32F730*")
|
|
sif cpuis("STM32F73?R*")
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" ",I2C1_TX,TIM4_UP,TIM2_CH2/TIM2_CH4,USART2_TX,,TIM5_UP,DAC2,?..."
|
|
else
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" ",I2C1_TX,TIM4_UP,TIM2_CH2/TIM2_CH4,USART2_TX,UART8_RX,TIM5_UP,DAC2,?..."
|
|
endif
|
|
newline
|
|
else
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" ",I2C1_TX,TIM4_UP,TIM2_CH2/TIM2_CH4,USART2_TX,,TIM5_UP,DAC2"
|
|
newline
|
|
endif
|
|
newline
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
newline
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
rgroup.long 0xA4++0x07
|
|
line.long 0x00 "S6NDTR,DMA Stream 6 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S6PAR,DMA Stream 6 Peripheral Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0xA0))&0x01)==0x00)||((((per.l(ad:0x40026000+0xA0))&0x01)==0x01)&&(((per.l(ad:0x40026000+0xA0))&0x80000)==0x80000))
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "S6M0AR,DMA Stream 6 Memory 0 Address Register"
|
|
else
|
|
rgroup.long 0xAC++0x03
|
|
line.long 0x00 "S6M0AR,DMA Stream 6 Memory 0 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0xA0))&0x01)==0x00)||((((per.l(ad:0x40026000+0xA0))&0x01)==0x01)&&(((per.l(ad:0x40026000+0xA0))&0x80000)==0x00))
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "S6M1AR,DMA Stream 6 Memory 1 Address Register"
|
|
else
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "S6M1AR,DMA Stream 6 Memory 1 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0xA0))&0x01)==0x00)
|
|
if (((per.l(ad:0x40026000+0xB4))&0x04)==0x04)
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "S6FCR,DMA Stream 6 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "S6FCR,DMA Stream 6 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40026000+0xB4))&0x04)==0x04)
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "S6FCR,DMA Stream 6 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
rbitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "S6FCR,DMA Stream 6 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Stream 7 registers"
|
|
if (((per.l(ad:0x40026000+0xB8))&0x01)==0x00)
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "S7CR,DMA Stream 7 Configuration Register"
|
|
sif (cpuis("STM32F74*")||cpuis("STM32F75*"))
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPI3_TX,I2C1_TX,TIM4_CH3,TIM2_UP/TIM2_CH4,UART5_TX,TIM3_CH3,,I2C2_TX"
|
|
newline
|
|
elif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SPI3_TX,I2C1_TX,TIM4_CH3,TIM2_UP/TIM2_CH4,UART5_TX,TIM3_CH3,,I2C2_TX,?..."
|
|
newline
|
|
elif (cpuis("STM32F72*")||cpuis("STM32F732*")||cpuis("STM32F733*"))
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPI3_TX,I2C1_TX,TIM4_CH3,TIM2_UP/TIM2_CH4,UART5_TX,TIM3_CH3,,I2C2_TX"
|
|
newline
|
|
elif cpuis("STM32F730*")
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SPI3_TX,I2C1_TX,TIM4_CH3,TIM2_UP/TIM2_CH4,UART5_TX,TIM3_CH3,,I2C2_TX,?..."
|
|
newline
|
|
else
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPI3_TX,I2C1_TX,TIM4_CH3,TIM2_UP/TIM2_CH4,UART5_TX,TIM3_CH3,,I2C2_TX"
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
newline
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
group.long 0xBC++0x07
|
|
line.long 0x00 "S7NDTR,DMA Stream 7 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S7PAR,DMA Stream 7 Peripheral Address Register"
|
|
else
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "S7CR,DMA Stream 7 Configuration Register"
|
|
sif (cpuis("STM32F74*")||cpuis("STM32F75*"))
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPI3_TX,I2C1_TX,TIM4_CH3,TIM2_UP/TIM2_CH4,UART5_TX,TIM3_CH3,,I2C2_TX"
|
|
newline
|
|
elif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SPI3_TX,I2C1_TX,TIM4_CH3,TIM2_UP/TIM2_CH4,UART5_TX,TIM3_CH3,,I2C2_TX,?..."
|
|
newline
|
|
elif (cpuis("STM32F72*")||cpuis("STM32F732*")||cpuis("STM32F733*"))
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPI3_TX,I2C1_TX,TIM4_CH3,TIM2_UP/TIM2_CH4,UART5_TX,TIM3_CH3,,I2C2_TX"
|
|
newline
|
|
elif cpuis("STM32F730*")
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SPI3_TX,I2C1_TX,TIM4_CH3,TIM2_UP/TIM2_CH4,UART5_TX,TIM3_CH3,,I2C2_TX,?..."
|
|
newline
|
|
else
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SPI3_TX,I2C1_TX,TIM4_CH3,TIM2_UP/TIM2_CH4,UART5_TX,TIM3_CH3,,I2C2_TX"
|
|
newline
|
|
endif
|
|
newline
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
newline
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
rgroup.long 0xBC++0x07
|
|
line.long 0x00 "S7NDTR,DMA Stream 7 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S7PAR,DMA Stream 7 Peripheral Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0xB8))&0x01)==0x00)||((((per.l(ad:0x40026000+0xB8))&0x01)==0x01)&&(((per.l(ad:0x40026000+0xB8))&0x80000)==0x80000))
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "S7M0AR,DMA Stream 7 Memory 0 Address Register"
|
|
else
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "S7M0AR,DMA Stream 7 Memory 0 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0xB8))&0x01)==0x00)||((((per.l(ad:0x40026000+0xB8))&0x01)==0x01)&&(((per.l(ad:0x40026000+0xB8))&0x80000)==0x00))
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "S7M1AR,DMA Stream 7 Memory 1 Address Register"
|
|
else
|
|
rgroup.long 0xC8++0x03
|
|
line.long 0x00 "S7M1AR,DMA Stream 7 Memory 1 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0xB8))&0x01)==0x00)
|
|
if (((per.l(ad:0x40026000+0xCC))&0x04)==0x04)
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "S7FCR,DMA Stream 7 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "S7FCR,DMA Stream 7 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40026000+0xCC))&0x04)==0x04)
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "S7FCR,DMA Stream 7 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
rbitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "S7FCR,DMA Stream 7 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
endif
|
|
endif
|
|
tree.end
|
|
else
|
|
if (((per.l(ad:0x40026000+0x10))&0x01)==0x00)
|
|
if (((per.l(ad:0x40026000+0x10))&0x40000)==0x40000)
|
|
group.long 0x10++0x03 "Stream 0 Registers"
|
|
line.long 0x00 "S0CR,DMA Stream 0 Configuration Register"
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
newline
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03 "Stream 0 Registers"
|
|
line.long 0x00 "S0CR,DMA Stream 0 Configuration Register"
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
newline
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x10+0x04)++0x07
|
|
line.long 0x00 "S0NDTR,DMA Stream 0 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S0PAR,DMA Stream 0 Peripheral Address Register"
|
|
else
|
|
if (((per.l(ad:0x40026000+0x10))&0x40000)==0x40000)
|
|
group.long 0x10++0x03 "Stream 0 Registers"
|
|
line.long 0x00 "S0CR,DMA Stream 0 Configuration Register"
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
newline
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03 "Stream 0 Registers"
|
|
line.long 0x00 "S0CR,DMA Stream 0 Configuration Register"
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
newline
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
newline
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long (0x10+0x04)++0x07
|
|
line.long 0x00 "S0NDTR,DMA Stream 0 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S0PAR,DMA Stream 0 Peripheral Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0x10))&0x01)==0x00)||((((per.l(ad:0x40026000+0x10))&0x01)==0x01)&&(((per.l(ad:0x40026000+0x10))&0x80000)==0x80000))
|
|
group.long (0x10+0x0C)++0x07
|
|
line.long 0x00 "S0M0AR,DMA Stream 0 Memory 0 Address Register"
|
|
line.long 0x04 "S0M1AR,DMA Stream 0 Memory 1 Address Register"
|
|
else
|
|
rgroup.long (0x10+0x0C)++0x07
|
|
line.long 0x00 "S0M0AR,DMA Stream 0 Memory 0 Address Register"
|
|
line.long 0x04 "S0M1AR,DMA Stream 0 Memory 1 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0x10))&0x01)==0x00)
|
|
group.long (0x10+0x14)++0x03
|
|
line.long 0x00 "S0FCR,DMA Stream 0 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long (0x10+0x14)++0x03
|
|
line.long 0x00 "S0FCR,DMA Stream 0 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
rbitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0x28))&0x01)==0x00)
|
|
if (((per.l(ad:0x40026000+0x28))&0x40000)==0x40000)
|
|
group.long 0x28++0x03 "Stream 1 Registers"
|
|
line.long 0x00 "S1CR,DMA Stream 1 Configuration Register"
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
newline
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x28++0x03 "Stream 1 Registers"
|
|
line.long 0x00 "S1CR,DMA Stream 1 Configuration Register"
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
newline
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x28+0x04)++0x07
|
|
line.long 0x00 "S1NDTR,DMA Stream 1 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S1PAR,DMA Stream 1 Peripheral Address Register"
|
|
else
|
|
if (((per.l(ad:0x40026000+0x28))&0x40000)==0x40000)
|
|
group.long 0x28++0x03 "Stream 1 Registers"
|
|
line.long 0x00 "S1CR,DMA Stream 1 Configuration Register"
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
newline
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x28++0x03 "Stream 1 Registers"
|
|
line.long 0x00 "S1CR,DMA Stream 1 Configuration Register"
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
newline
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
newline
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long (0x28+0x04)++0x07
|
|
line.long 0x00 "S1NDTR,DMA Stream 1 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S1PAR,DMA Stream 1 Peripheral Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0x28))&0x01)==0x00)||((((per.l(ad:0x40026000+0x28))&0x01)==0x01)&&(((per.l(ad:0x40026000+0x28))&0x80000)==0x80000))
|
|
group.long (0x28+0x0C)++0x07
|
|
line.long 0x00 "S1M0AR,DMA Stream 1 Memory 0 Address Register"
|
|
line.long 0x04 "S1M1AR,DMA Stream 1 Memory 1 Address Register"
|
|
else
|
|
rgroup.long (0x28+0x0C)++0x07
|
|
line.long 0x00 "S1M0AR,DMA Stream 1 Memory 0 Address Register"
|
|
line.long 0x04 "S1M1AR,DMA Stream 1 Memory 1 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0x28))&0x01)==0x00)
|
|
group.long (0x28+0x14)++0x03
|
|
line.long 0x00 "S1FCR,DMA Stream 1 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long (0x28+0x14)++0x03
|
|
line.long 0x00 "S1FCR,DMA Stream 1 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
rbitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0x40))&0x01)==0x00)
|
|
if (((per.l(ad:0x40026000+0x40))&0x40000)==0x40000)
|
|
group.long 0x40++0x03 "Stream 2 Registers"
|
|
line.long 0x00 "S2CR,DMA Stream 2 Configuration Register"
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
newline
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x40++0x03 "Stream 2 Registers"
|
|
line.long 0x00 "S2CR,DMA Stream 2 Configuration Register"
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
newline
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x40+0x04)++0x07
|
|
line.long 0x00 "S2NDTR,DMA Stream 2 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S2PAR,DMA Stream 2 Peripheral Address Register"
|
|
else
|
|
if (((per.l(ad:0x40026000+0x40))&0x40000)==0x40000)
|
|
group.long 0x40++0x03 "Stream 2 Registers"
|
|
line.long 0x00 "S2CR,DMA Stream 2 Configuration Register"
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
newline
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x40++0x03 "Stream 2 Registers"
|
|
line.long 0x00 "S2CR,DMA Stream 2 Configuration Register"
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
newline
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
newline
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long (0x40+0x04)++0x07
|
|
line.long 0x00 "S2NDTR,DMA Stream 2 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S2PAR,DMA Stream 2 Peripheral Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0x40))&0x01)==0x00)||((((per.l(ad:0x40026000+0x40))&0x01)==0x01)&&(((per.l(ad:0x40026000+0x40))&0x80000)==0x80000))
|
|
group.long (0x40+0x0C)++0x07
|
|
line.long 0x00 "S2M0AR,DMA Stream 2 Memory 0 Address Register"
|
|
line.long 0x04 "S2M1AR,DMA Stream 2 Memory 1 Address Register"
|
|
else
|
|
rgroup.long (0x40+0x0C)++0x07
|
|
line.long 0x00 "S2M0AR,DMA Stream 2 Memory 0 Address Register"
|
|
line.long 0x04 "S2M1AR,DMA Stream 2 Memory 1 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0x40))&0x01)==0x00)
|
|
group.long (0x40+0x14)++0x03
|
|
line.long 0x00 "S2FCR,DMA Stream 2 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long (0x40+0x14)++0x03
|
|
line.long 0x00 "S2FCR,DMA Stream 2 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
rbitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0x58))&0x01)==0x00)
|
|
if (((per.l(ad:0x40026000+0x58))&0x40000)==0x40000)
|
|
group.long 0x58++0x03 "Stream 3 Registers"
|
|
line.long 0x00 "S3CR,DMA Stream 3 Configuration Register"
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
newline
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x58++0x03 "Stream 3 Registers"
|
|
line.long 0x00 "S3CR,DMA Stream 3 Configuration Register"
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
newline
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x58+0x04)++0x07
|
|
line.long 0x00 "S3NDTR,DMA Stream 3 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S3PAR,DMA Stream 3 Peripheral Address Register"
|
|
else
|
|
if (((per.l(ad:0x40026000+0x58))&0x40000)==0x40000)
|
|
group.long 0x58++0x03 "Stream 3 Registers"
|
|
line.long 0x00 "S3CR,DMA Stream 3 Configuration Register"
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
newline
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x58++0x03 "Stream 3 Registers"
|
|
line.long 0x00 "S3CR,DMA Stream 3 Configuration Register"
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
newline
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
newline
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long (0x58+0x04)++0x07
|
|
line.long 0x00 "S3NDTR,DMA Stream 3 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S3PAR,DMA Stream 3 Peripheral Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0x58))&0x01)==0x00)||((((per.l(ad:0x40026000+0x58))&0x01)==0x01)&&(((per.l(ad:0x40026000+0x58))&0x80000)==0x80000))
|
|
group.long (0x58+0x0C)++0x07
|
|
line.long 0x00 "S3M0AR,DMA Stream 3 Memory 0 Address Register"
|
|
line.long 0x04 "S3M1AR,DMA Stream 3 Memory 1 Address Register"
|
|
else
|
|
rgroup.long (0x58+0x0C)++0x07
|
|
line.long 0x00 "S3M0AR,DMA Stream 3 Memory 0 Address Register"
|
|
line.long 0x04 "S3M1AR,DMA Stream 3 Memory 1 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0x58))&0x01)==0x00)
|
|
group.long (0x58+0x14)++0x03
|
|
line.long 0x00 "S3FCR,DMA Stream 3 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long (0x58+0x14)++0x03
|
|
line.long 0x00 "S3FCR,DMA Stream 3 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
rbitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0x70))&0x01)==0x00)
|
|
if (((per.l(ad:0x40026000+0x70))&0x40000)==0x40000)
|
|
group.long 0x70++0x03 "Stream 4 Registers"
|
|
line.long 0x00 "S4CR,DMA Stream 4 Configuration Register"
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
newline
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x70++0x03 "Stream 4 Registers"
|
|
line.long 0x00 "S4CR,DMA Stream 4 Configuration Register"
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
newline
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x70+0x04)++0x07
|
|
line.long 0x00 "S4NDTR,DMA Stream 4 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S4PAR,DMA Stream 4 Peripheral Address Register"
|
|
else
|
|
if (((per.l(ad:0x40026000+0x70))&0x40000)==0x40000)
|
|
group.long 0x70++0x03 "Stream 4 Registers"
|
|
line.long 0x00 "S4CR,DMA Stream 4 Configuration Register"
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
newline
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x70++0x03 "Stream 4 Registers"
|
|
line.long 0x00 "S4CR,DMA Stream 4 Configuration Register"
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
newline
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
newline
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long (0x70+0x04)++0x07
|
|
line.long 0x00 "S4NDTR,DMA Stream 4 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S4PAR,DMA Stream 4 Peripheral Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0x70))&0x01)==0x00)||((((per.l(ad:0x40026000+0x70))&0x01)==0x01)&&(((per.l(ad:0x40026000+0x70))&0x80000)==0x80000))
|
|
group.long (0x70+0x0C)++0x07
|
|
line.long 0x00 "S4M0AR,DMA Stream 4 Memory 0 Address Register"
|
|
line.long 0x04 "S4M1AR,DMA Stream 4 Memory 1 Address Register"
|
|
else
|
|
rgroup.long (0x70+0x0C)++0x07
|
|
line.long 0x00 "S4M0AR,DMA Stream 4 Memory 0 Address Register"
|
|
line.long 0x04 "S4M1AR,DMA Stream 4 Memory 1 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0x70))&0x01)==0x00)
|
|
group.long (0x70+0x14)++0x03
|
|
line.long 0x00 "S4FCR,DMA Stream 4 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long (0x70+0x14)++0x03
|
|
line.long 0x00 "S4FCR,DMA Stream 4 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
rbitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0x88))&0x01)==0x00)
|
|
if (((per.l(ad:0x40026000+0x88))&0x40000)==0x40000)
|
|
group.long 0x88++0x03 "Stream 5 Registers"
|
|
line.long 0x00 "S5CR,DMA Stream 5 Configuration Register"
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
newline
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x88++0x03 "Stream 5 Registers"
|
|
line.long 0x00 "S5CR,DMA Stream 5 Configuration Register"
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
newline
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x88+0x04)++0x07
|
|
line.long 0x00 "S5NDTR,DMA Stream 5 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S5PAR,DMA Stream 5 Peripheral Address Register"
|
|
else
|
|
if (((per.l(ad:0x40026000+0x88))&0x40000)==0x40000)
|
|
group.long 0x88++0x03 "Stream 5 Registers"
|
|
line.long 0x00 "S5CR,DMA Stream 5 Configuration Register"
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
newline
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x88++0x03 "Stream 5 Registers"
|
|
line.long 0x00 "S5CR,DMA Stream 5 Configuration Register"
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
newline
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
newline
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long (0x88+0x04)++0x07
|
|
line.long 0x00 "S5NDTR,DMA Stream 5 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S5PAR,DMA Stream 5 Peripheral Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0x88))&0x01)==0x00)||((((per.l(ad:0x40026000+0x88))&0x01)==0x01)&&(((per.l(ad:0x40026000+0x88))&0x80000)==0x80000))
|
|
group.long (0x88+0x0C)++0x07
|
|
line.long 0x00 "S5M0AR,DMA Stream 5 Memory 0 Address Register"
|
|
line.long 0x04 "S5M1AR,DMA Stream 5 Memory 1 Address Register"
|
|
else
|
|
rgroup.long (0x88+0x0C)++0x07
|
|
line.long 0x00 "S5M0AR,DMA Stream 5 Memory 0 Address Register"
|
|
line.long 0x04 "S5M1AR,DMA Stream 5 Memory 1 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0x88))&0x01)==0x00)
|
|
group.long (0x88+0x14)++0x03
|
|
line.long 0x00 "S5FCR,DMA Stream 5 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long (0x88+0x14)++0x03
|
|
line.long 0x00 "S5FCR,DMA Stream 5 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
rbitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0xA0))&0x01)==0x00)
|
|
if (((per.l(ad:0x40026000+0xA0))&0x40000)==0x40000)
|
|
group.long 0xA0++0x03 "Stream 6 Registers"
|
|
line.long 0x00 "S6CR,DMA Stream 6 Configuration Register"
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
newline
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA0++0x03 "Stream 6 Registers"
|
|
line.long 0x00 "S6CR,DMA Stream 6 Configuration Register"
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
newline
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xA0+0x04)++0x07
|
|
line.long 0x00 "S6NDTR,DMA Stream 6 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S6PAR,DMA Stream 6 Peripheral Address Register"
|
|
else
|
|
if (((per.l(ad:0x40026000+0xA0))&0x40000)==0x40000)
|
|
group.long 0xA0++0x03 "Stream 6 Registers"
|
|
line.long 0x00 "S6CR,DMA Stream 6 Configuration Register"
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
newline
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA0++0x03 "Stream 6 Registers"
|
|
line.long 0x00 "S6CR,DMA Stream 6 Configuration Register"
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
newline
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
newline
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long (0xA0+0x04)++0x07
|
|
line.long 0x00 "S6NDTR,DMA Stream 6 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S6PAR,DMA Stream 6 Peripheral Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0xA0))&0x01)==0x00)||((((per.l(ad:0x40026000+0xA0))&0x01)==0x01)&&(((per.l(ad:0x40026000+0xA0))&0x80000)==0x80000))
|
|
group.long (0xA0+0x0C)++0x07
|
|
line.long 0x00 "S6M0AR,DMA Stream 6 Memory 0 Address Register"
|
|
line.long 0x04 "S6M1AR,DMA Stream 6 Memory 1 Address Register"
|
|
else
|
|
rgroup.long (0xA0+0x0C)++0x07
|
|
line.long 0x00 "S6M0AR,DMA Stream 6 Memory 0 Address Register"
|
|
line.long 0x04 "S6M1AR,DMA Stream 6 Memory 1 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0xA0))&0x01)==0x00)
|
|
group.long (0xA0+0x14)++0x03
|
|
line.long 0x00 "S6FCR,DMA Stream 6 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long (0xA0+0x14)++0x03
|
|
line.long 0x00 "S6FCR,DMA Stream 6 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
rbitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0xB8))&0x01)==0x00)
|
|
if (((per.l(ad:0x40026000+0xB8))&0x40000)==0x40000)
|
|
group.long 0xB8++0x03 "Stream 7 Registers"
|
|
line.long 0x00 "S7CR,DMA Stream 7 Configuration Register"
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
newline
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB8++0x03 "Stream 7 Registers"
|
|
line.long 0x00 "S7CR,DMA Stream 7 Configuration Register"
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
newline
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xB8+0x04)++0x07
|
|
line.long 0x00 "S7NDTR,DMA Stream 7 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S7PAR,DMA Stream 7 Peripheral Address Register"
|
|
else
|
|
if (((per.l(ad:0x40026000+0xB8))&0x40000)==0x40000)
|
|
group.long 0xB8++0x03 "Stream 7 Registers"
|
|
line.long 0x00 "S7CR,DMA Stream 7 Configuration Register"
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
newline
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB8++0x03 "Stream 7 Registers"
|
|
line.long 0x00 "S7CR,DMA Stream 7 Configuration Register"
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
newline
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
newline
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long (0xB8+0x04)++0x07
|
|
line.long 0x00 "S7NDTR,DMA Stream 7 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S7PAR,DMA Stream 7 Peripheral Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0xB8))&0x01)==0x00)||((((per.l(ad:0x40026000+0xB8))&0x01)==0x01)&&(((per.l(ad:0x40026000+0xB8))&0x80000)==0x80000))
|
|
group.long (0xB8+0x0C)++0x07
|
|
line.long 0x00 "S7M0AR,DMA Stream 7 Memory 0 Address Register"
|
|
line.long 0x04 "S7M1AR,DMA Stream 7 Memory 1 Address Register"
|
|
else
|
|
rgroup.long (0xB8+0x0C)++0x07
|
|
line.long 0x00 "S7M0AR,DMA Stream 7 Memory 0 Address Register"
|
|
line.long 0x04 "S7M1AR,DMA Stream 7 Memory 1 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026000+0xB8))&0x01)==0x00)
|
|
group.long (0xB8+0x14)++0x03
|
|
line.long 0x00 "S7FCR,DMA Stream 7 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long (0xB8+0x14)++0x03
|
|
line.long 0x00 "S7FCR,DMA Stream 7 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
rbitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA 2"
|
|
base ad:0x40026400
|
|
width 7.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "LISR,DMA Low Interrupt Status Register"
|
|
bitfld.long 0x00 27. " TCIF3 ,Stream 3 transfer complete interrupt flag" "Not completed,Completed"
|
|
bitfld.long 0x00 26. " HTIF3 ,Stream 3 half transfer interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 25. " TEIF3 ,Stream 3 transfer error interrupt flag" "No error,Error"
|
|
bitfld.long 0x00 24. " DMEIF3 ,Stream 3 direct mode error interrupt flag" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 22. " FEIF3 ,Stream 3 FIFO error interrupt flag" "No error,Error"
|
|
bitfld.long 0x00 21. " TCIF2 ,Stream 2 transfer complete interrupt flag" "Not completed,Completed"
|
|
bitfld.long 0x00 20. " HTIF2 ,Stream 2 half transfer interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 19. " TEIF2 ,Stream 2 transfer error interrupt flag" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 18. " DMEIF2 ,Stream 2 direct mode error interrupt flag" "No error,Error"
|
|
bitfld.long 0x00 16. " FEIF2 ,Stream 2 FIFO error interrupt flag" "No error,Error"
|
|
bitfld.long 0x00 11. " TCIF1 ,Stream 1 transfer complete interrupt flag" "Not completed,Completed"
|
|
bitfld.long 0x00 10. " HTIF1 ,Stream 1 half transfer interrupt flag" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 9. " TEIF1 ,Stream 1 transfer error interrupt flag" "No error,Error"
|
|
bitfld.long 0x00 8. " DMEIF1 ,Stream 1 direct mode error interrupt flag" "No error,Error"
|
|
bitfld.long 0x00 6. " FEIF1 ,Stream 1 FIFO error interrupt flag" "No error,Error"
|
|
bitfld.long 0x00 5. " TCIF0 ,Stream 0 transfer complete interrupt flag" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x00 4. " HTIF0 ,Stream 0 half transfer interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " TEIF0 ,Stream 0 transfer error interrupt flag" "No error,Error"
|
|
bitfld.long 0x00 2. " DMEIF0 ,Stream 0 direct mode error interrupt flag" "No error,Error"
|
|
bitfld.long 0x00 0. " FEIF0 ,Stream 0 FIFO error interrupt flag" "No error,Error"
|
|
line.long 0x04 "HISR,DMA High Interrupt Status Register"
|
|
bitfld.long 0x04 27. " TCIF7 ,Stream 7 transfer complete interrupt flag" "Not completed,Completed"
|
|
bitfld.long 0x04 26. " HTIF7 ,Stream 7 half transfer interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 25. " TEIF7 ,Stream 7 transfer error interrupt flag" "No error,Error"
|
|
bitfld.long 0x04 24. " DMEIF7 ,Stream 7 direct mode error interrupt flag" "No error,Error"
|
|
newline
|
|
bitfld.long 0x04 22. " FEIF7 ,Stream 7 FIFO error interrupt flag" "No error,Error"
|
|
bitfld.long 0x04 21. " TCIF6 ,Stream 6 transfer complete interrupt flag" "Not completed,Completed"
|
|
bitfld.long 0x04 20. " HTIF6 ,Stream 6 half transfer interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 19. " TEIF6 ,Stream 6 transfer error interrupt flag" "No error,Error"
|
|
newline
|
|
bitfld.long 0x04 18. " DMEIF6 ,Stream 6 direct mode error interrupt flag" "No error,Error"
|
|
bitfld.long 0x04 16. " FEIF6 ,Stream 6 FIFO error interrupt flag" "No error,Error"
|
|
bitfld.long 0x04 11. " TCIF5 ,Stream 5 transfer complete interrupt flag" "Not completed,Completed"
|
|
bitfld.long 0x04 10. " HTIF5 ,Stream 5 half transfer interrupt flag" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x04 9. " TEIF5 ,Stream 5 transfer error interrupt flag" "No error,Error"
|
|
bitfld.long 0x04 8. " DMEIF5 ,Stream 5 direct mode error interrupt flag" "No error,Error"
|
|
bitfld.long 0x04 6. " FEIF5 ,Stream 5 FIFO error interrupt flag" "No error,Error"
|
|
bitfld.long 0x04 5. " TCIF4 ,Stream 4 transfer complete interrupt flag" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x04 4. " HTIF4 ,Stream 4 half transfer interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 3. " TEIF4 ,Stream 4 transfer error interrupt flag" "No error,Error"
|
|
bitfld.long 0x04 2. " DMEIF4 ,Stream 4 direct mode error interrupt flag" "No error,Error"
|
|
bitfld.long 0x04 0. " FEIF4 ,Stream 4 FIFO error interrupt flag" "No error,Error"
|
|
sif (cpuis("STM32F4*")||cpuis("STM32F7*")||cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32H742*")||cpuis("STM32H750*"))
|
|
wgroup.long 0x08++0x07
|
|
line.long 0x00 "LIFCR,DMA Low Interrupt Flag Clear Register"
|
|
bitfld.long 0x00 27. " CTCIF3 ,Stream 3 clear transfer complete interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 26. " CHTIF3 ,Stream 3 clear half transfer interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 25. " CTEIF3 ,Stream 3 clear transfer error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 24. " CDMEIF3 ,Stream 3 clear direct mode error interrupt flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 22. " CFEIF3 ,Stream 3 clear FIFO error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 21. " CTCIF2 ,Stream 2 clear transfer complete interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 20. " CHTIF2 ,Stream 2 clear half transfer interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 19. " CTEIF2 ,Stream 2 clear transfer error interrupt flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 18. " CDMEIF2 ,Stream 2 clear direct mode error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 16. " CFEIF2 ,Stream 2 clear FIFO error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 11. " CTCIF1 ,Stream 1 clear transfer complete interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CHTIF1 ,Stream 1 clear half transfer interrupt flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 9. " CTEIF1 ,Stream 1 clear transfer error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 8. " CDMEIF1 ,Stream 1 clear direct mode error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 6. " CFEIF1 ,Stream 1 clear FIFO error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 5. " CTCIF0 ,Stream 0 clear transfer complete interrupt flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 4. " CHTIF0 ,Stream 0 clear half transfer interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 3. " CTEIF0 ,Stream 0 transfer error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CDMEIF0 ,Stream 0 clear direct mode error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CFEIF0 ,Stream 0 clear FIFO error interrupt flag" "No effect,Clear"
|
|
line.long 0x04 "HIFCR,DMA High Interrupt Flag Clear Register"
|
|
bitfld.long 0x04 27. " CTCIF7 ,Stream 7 clear transfer complete interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 26. " CHTIF7 ,Stream 7 clear half transfer interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 25. " CTEIF7 ,Stream 7 clear transfer error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 24. " CDMEIF7 ,Stream 7 clear direct mode error interrupt flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 22. " CFEIF7 ,Stream 7 clear FIFO error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 21. " CTCIF6 ,Stream 6 clear transfer complete interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 20. " CHTIF6 ,Stream 6 clear half transfer interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 19. " CTEIF6 ,Stream 6 transfer error interrupt flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 18. " CDMEIF6 ,Stream 6 clear direct mode error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 16. " CFEIF6 ,Stream 6 clear FIFO error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 11. " CTCIF5 ,Stream 5 clear transfer complete interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 10. " CHTIF5 ,Stream 5 clear half transfer interrupt flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 9. " CTEIF5 ,Stream 5 transfer error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 8. " CDMEIF5 ,Stream 5 clear direct mode error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 6. " CFEIF5 ,Stream 5 clear FIFO error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 5. " CTCIF4 ,Stream 4 clear transfer complete interrupt flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 4. " CHTIF4 ,Stream 4 clear half transfer interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 3. " CTEIF4 ,Stream 4 transfer error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 2. " CDMEIF4 ,Stream 4 clear direct mode error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 0. " CFEIF4 ,Stream 4 clear FIFO error interrupt flag" "No effect,Clear"
|
|
else
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "LIFCR,DMA Low Interrupt Flag Clear Register"
|
|
bitfld.long 0x00 27. " CTCIF3 ,Stream 3 clear transfer complete interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 26. " CHTIF3 ,Stream 3 clear half transfer interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 25. " CTEIF3 ,Stream 3 clear transfer error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 24. " CDMEIF3 ,Stream 3 clear direct mode error interrupt flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 22. " CFEIF3 ,Stream 3 clear FIFO error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 21. " CTCIF2 ,Stream 2 clear transfer complete interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 20. " CHTIF2 ,Stream 2 clear half transfer interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 19. " CTEIF2 ,Stream 2 clear transfer error interrupt flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 18. " CDMEIF2 ,Stream 2 clear direct mode error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 16. " CFEIF2 ,Stream 2 clear FIFO error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 11. " CTCIF1 ,Stream 1 clear transfer complete interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CHTIF1 ,Stream 1 clear half transfer interrupt flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 9. " CTEIF1 ,Stream 1 clear transfer error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 8. " CDMEIF1 ,Stream 1 clear direct mode error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 6. " CFEIF1 ,Stream 1 clear FIFO error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 5. " CTCIF0 ,Stream 0 clear transfer complete interrupt flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 4. " CHTIF0 ,Stream 0 clear half transfer interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 3. " CTEIF0 ,Stream 0 transfer error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CDMEIF0 ,Stream 0 clear direct mode error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CFEIF0 ,Stream 0 clear FIFO error interrupt flag" "No effect,Clear"
|
|
line.long 0x04 "HIFCR,DMA High Interrupt Flag Clear Register"
|
|
bitfld.long 0x04 27. " CTCIF7 ,Stream 7 clear transfer complete interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 26. " CHTIF7 ,Stream 7 clear half transfer interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 25. " CTEIF7 ,Stream 7 clear transfer error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 24. " CDMEIF7 ,Stream 7 clear direct mode error interrupt flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 22. " CFEIF7 ,Stream 7 clear FIFO error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 21. " CTCIF6 ,Stream 6 clear transfer complete interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 20. " CHTIF6 ,Stream 6 clear half transfer interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 19. " CTEIF6 ,Stream 6 transfer error interrupt flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 18. " CDMEIF6 ,Stream 6 clear direct mode error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 16. " CFEIF6 ,Stream 6 clear FIFO error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 11. " CTCIF5 ,Stream 5 clear transfer complete interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 10. " CHTIF5 ,Stream 5 clear half transfer interrupt flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 9. " CTEIF5 ,Stream 5 transfer error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 8. " CDMEIF5 ,Stream 5 clear direct mode error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 6. " CFEIF5 ,Stream 5 clear FIFO error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 5. " CTCIF4 ,Stream 4 clear transfer complete interrupt flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 4. " CHTIF4 ,Stream 4 clear half transfer interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 3. " CTEIF4 ,Stream 4 transfer error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 2. " CDMEIF4 ,Stream 4 clear direct mode error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x04 0. " CFEIF4 ,Stream 4 clear FIFO error interrupt flag" "No effect,Clear"
|
|
endif
|
|
width 8.
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*")&&!cpuis("STM32H742*")&&!cpuis("STM32H750*"))
|
|
tree "Stream 0 registers"
|
|
if (((per.l(ad:0x40026400+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "S0CR,DMA Stream 0 Configuration Register"
|
|
sif (cpuis("STM32F74*")||cpuis("STM32F75*"))
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "ADC1,,ADC3,SPI1_RX,SPI4_RX,,TIM1_TRIG,?..."
|
|
newline
|
|
elif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "ADC1,,ADC3,SPI1_RX,SPI4_RX,,TIM1_TRIG,,DFSDM1_FLT0,JPEG_IN,SAI1_B,SDMMC2,?..."
|
|
newline
|
|
elif cpuis("STM32F72*")||cpuis("STM32F732*")||cpuis("STM32F733*")
|
|
sif (cpuis("STM32F72?R*")||cpuis("STM32F73?R*"))
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "ADC1,,ADC3,SPI1_RX,,,TIM1_TRIG,?..."
|
|
else
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "ADC1,,ADC3,SPI1_RX,SPI4_RX,,TIM1_TRIG,?..."
|
|
endif
|
|
newline
|
|
elif cpuis("STM32F730*")
|
|
sif cpuis("STM32F73?R*")
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "ADC1,,ADC3,SPI1_RX,,,TIM1_TRIG,?..."
|
|
else
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "ADC1,,ADC3,SPI1_RX,SPI4_RX,,TIM1_TRIG,,,,,SDMMC2,?..."
|
|
endif
|
|
newline
|
|
else
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "ADC1,,ADC3,SPI1_RX,,,TIM1_TRIG,?..."
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
newline
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "S0NDTR,DMA Stream 0 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S0PAR,DMA Stream 0 Peripheral Address Register"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "S0CR,DMA Stream 0 Configuration Register"
|
|
sif (cpuis("STM32F74*")||cpuis("STM32F75*"))
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "ADC1,,ADC3,SPI1_RX,SPI4_RX,,TIM1_TRIG,?..."
|
|
newline
|
|
elif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "ADC1,,ADC3,SPI1_RX,SPI4_RX,,TIM1_TRIG,,DFSDM1_FLT0,JPEG_IN,SAI1_B,SDMMC2,?..."
|
|
newline
|
|
elif cpuis("STM32F72*")||cpuis("STM32F732*")||cpuis("STM32F733*")
|
|
sif (cpuis("STM32F72?R*")||cpuis("STM32F73?R*"))
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "ADC1,,ADC3,SPI1_RX,,,TIM1_TRIG,?..."
|
|
else
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "ADC1,,ADC3,SPI1_RX,SPI4_RX,,TIM1_TRIG,?..."
|
|
endif
|
|
newline
|
|
elif cpuis("STM32F730*")
|
|
sif cpuis("STM32F73?R*")
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "ADC1,,ADC3,SPI1_RX,,,TIM1_TRIG,?..."
|
|
else
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "ADC1,,ADC3,SPI1_RX,SPI4_RX,,TIM1_TRIG,,,,,SDMMC2,?..."
|
|
endif
|
|
newline
|
|
else
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "ADC1,,ADC3,SPI1_RX,,,TIM1_TRIG,?..."
|
|
newline
|
|
endif
|
|
newline
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
newline
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "S0NDTR,DMA Stream 0 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S0PAR,DMA Stream 0 Peripheral Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0x10))&0x01)==0x00)||((((per.l(ad:0x40026400+0x10))&0x01)==0x01)&&(((per.l(ad:0x40026400+0x10))&0x80000)==0x80000))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "S0M0AR,DMA Stream 0 Memory 0 Address Register"
|
|
else
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "S0M0AR,DMA Stream 0 Memory 0 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0x10))&0x01)==0x00)||((((per.l(ad:0x40026400+0x10))&0x01)==0x01)&&(((per.l(ad:0x40026400+0x10))&0x80000)==0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "S0M1AR,DMA Stream 0 Memory 1 Address Register"
|
|
else
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "S0M1AR,DMA Stream 0 Memory 1 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0x10))&0x01)==0x00)
|
|
if (((per.l(ad:0x40026400+0x24))&0x04)==0x04)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "S0FCR,DMA Stream 0 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "S0FCR,DMA Stream 0 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40026400+0x24))&0x04)==0x04)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "S0FCR,DMA Stream 0 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
rbitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "S0FCR,DMA Stream 0 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Stream 1 registers"
|
|
if (((per.l(ad:0x40026400+0x28))&0x01)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "S1CR,DMA Stream 1 Configuration Register"
|
|
sif (cpuis("STM32F74*")||cpuis("STM32F75*"))
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SAI1_A,DCMI,ADC3,,SPI4_TX,USART6_RX,TIM1_CH1,TIM8_UP"
|
|
newline
|
|
elif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SAI1_A,DCMI,ADC3,,SPI4_TX,USART6_RX,TIM1_CH1,TIM8_UP,DFSDM1_FLT1,JPEG_OUT,SAI2_B,?..."
|
|
newline
|
|
elif (cpuis("STM32F72*")||cpuis("STM32F732*")||cpuis("STM32F733*"))
|
|
sif (cpuis("STM32F72?R*")||cpuis("STM32F73?R*"))
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SAI1_A,,ADC3,,,USART6_RX,TIM1_CH1,TIM8_UP"
|
|
else
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SAI1_A,,ADC3,,SPI4_TX,USART6_RX,TIM1_CH1,TIM8_UP"
|
|
endif
|
|
newline
|
|
elif cpuis("STM32F730*")
|
|
sif cpuis("STM32F73?R*")
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SAI1_A,,ADC3,,,USART6_RX,TIM1_CH1,TIM8_UP,?..."
|
|
else
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SAI1_A,,ADC3,,SPI4_TX,USART6_RX,TIM1_CH1,TIM8_UP,?..."
|
|
endif
|
|
newline
|
|
else
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" ",DCMI,ADC3,,,USART6_RX,TIM1_CH1,TIM8_UP"
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
newline
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
group.long 0x2C++0x07
|
|
line.long 0x00 "S1NDTR,DMA Stream 1 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S1PAR,DMA Stream 1 Peripheral Address Register"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "S1CR,DMA Stream 1 Configuration Register"
|
|
sif (cpuis("STM32F74*")||cpuis("STM32F75*"))
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SAI1_A,DCMI,ADC3,,SPI4_TX,USART6_RX,TIM1_CH1,TIM8_UP"
|
|
newline
|
|
elif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SAI1_A,DCMI,ADC3,,SPI4_TX,USART6_RX,TIM1_CH1,TIM8_UP,DFSDM1_FLT1,JPEG_OUT,SAI2_B,?..."
|
|
newline
|
|
elif (cpuis("STM32F72*")||cpuis("STM32F732*")||cpuis("STM32F733*"))
|
|
sif (cpuis("STM32F72?R*")||cpuis("STM32F73?R*"))
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SAI1_A,,ADC3,,,USART6_RX,TIM1_CH1,TIM8_UP"
|
|
else
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SAI1_A,,ADC3,,SPI4_TX,USART6_RX,TIM1_CH1,TIM8_UP"
|
|
endif
|
|
newline
|
|
elif cpuis("STM32F730*")
|
|
sif cpuis("STM32F73?R*")
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SAI1_A,,ADC3,,,USART6_RX,TIM1_CH1,TIM8_UP,?..."
|
|
else
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SAI1_A,,ADC3,,SPI4_TX,USART6_RX,TIM1_CH1,TIM8_UP,?..."
|
|
endif
|
|
newline
|
|
else
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" ",DCMI,ADC3,,,USART6_RX,TIM1_CH1,TIM8_UP"
|
|
newline
|
|
endif
|
|
newline
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
newline
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
rgroup.long 0x2C++0x07
|
|
line.long 0x00 "S1NDTR,DMA Stream 1 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S1PAR,DMA Stream 1 Peripheral Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0x28))&0x01)==0x00)||((((per.l(ad:0x40026400+0x28))&0x01)==0x01)&&(((per.l(ad:0x40026400+0x28))&0x80000)==0x8000))
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "S1M0AR,DMA Stream 1 Memory 0 Address Register"
|
|
else
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "S1M0AR,DMA Stream 1 Memory 0 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0x28))&0x01)==0x00)||((((per.l(ad:0x40026400+0x28))&0x01)==0x01)&&(((per.l(ad:0x40026400+0x28))&0x80000)==0x8000))
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "S1M1AR,DMA Stream 1 Memory 1 Address Register"
|
|
else
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "S1M1AR,DMA Stream 1 Memory 1 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0x28))&0x01)==0x00)
|
|
if (((per.l(ad:0x40026400+0x3C))&0x04)==0x04)
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "S1FCR,DMA Stream 1 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "S1FCR,DMA Stream 1 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40026400+0x3C))&0x04)==0x04)
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "S1FCR,DMA Stream 1 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
rbitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "S1FCR,DMA Stream 1 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Stream 2 registers"
|
|
if (((per.l(ad:0x40026400+0x40))&0x01)==0x00)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "S2CR,DMA Stream 2 Configuration Register"
|
|
sif (cpuis("STM32F74*")||cpuis("STM32F75*"))
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "TIM8_CH1/2/3,ADC2,,SPI1_RX,USART1_RX,USART6_RX,TIM1_CH2,TIM8_CH1"
|
|
newline
|
|
elif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "TIM8_CH1/TIM8_CH2/TIM8_CH3,ADC2,,SPI1_RX,USART1_RX,USART6_RX,TIM1_CH2,TIM8_CH1,DFSDM1_FLT2,SPI4_TX,SAI2_A,QUADSPI,?..."
|
|
newline
|
|
elif (cpuis("STM32F72*")||cpuis("STM32F732*")||cpuis("STM32F733*"))
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "TIM8_CH1/TIM8_CH2/TIM8_CH3,ADC2,,SPI1_RX,USART1_RX,USART6_RX,TIM1_CH2,TIM8_CH1"
|
|
newline
|
|
elif cpuis("STM32F730*")
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "TIM8_CH1/TIM8_CH2/TIM8_CH3,ADC2,,SPI1_RX,USART1_RX,USART6_RX,TIM1_CH2,TIM8_CH1,?..."
|
|
newline
|
|
else
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" ",,,SPI1_RX,USART1_RX,USART6_RX,TIM1_CH2,?..."
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
newline
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
group.long 0x44++0x07
|
|
line.long 0x00 "S2NDTR,DMA Stream 2 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S2PAR,DMA Stream 2 Peripheral Address Register"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "S2CR,DMA Stream 2 Configuration Register"
|
|
sif (cpuis("STM32F74*")||cpuis("STM32F75*"))
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "TIM8_CH1/2/3,ADC2,,SPI1_RX,USART1_RX,USART6_RX,TIM1_CH2,TIM8_CH1"
|
|
newline
|
|
elif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "TIM8_CH1/TIM8_CH2/TIM8_CH3,ADC2,,SPI1_RX,USART1_RX,USART6_RX,TIM1_CH2,TIM8_CH1,DFSDM1_FLT2,SPI4_TX,SAI2_A,QUADSPI,?..."
|
|
newline
|
|
elif (cpuis("STM32F72*")||cpuis("STM32F732*")||cpuis("STM32F733*"))
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "TIM8_CH1/TIM8_CH2/TIM8_CH3,ADC2,,SPI1_RX,USART1_RX,USART6_RX,TIM1_CH2,TIM8_CH1"
|
|
newline
|
|
elif cpuis("STM32F730*")
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "TIM8_CH1/TIM8_CH2/TIM8_CH3,ADC2,,SPI1_RX,USART1_RX,USART6_RX,TIM1_CH2,TIM8_CH1,?..."
|
|
newline
|
|
else
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" ",,,SPI1_RX,USART1_RX,USART6_RX,TIM1_CH2,?..."
|
|
newline
|
|
endif
|
|
newline
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
newline
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
rgroup.long 0x44++0x07
|
|
line.long 0x00 "S2NDTR,DMA Stream 2 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S2PAR,DMA Stream 2 Peripheral Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0x40))&0x01)==0x00)||((((per.l(ad:0x40026400+0x40))&0x01)==0x01)&&(((per.l(ad:0x40026400+0x40))&0x80000)==0x80000))
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "S2M0AR,DMA Stream 2 Memory 0 Address Register"
|
|
else
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "S2M0AR,DMA Stream 2 Memory 0 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0x40))&0x01)==0x00)||((((per.l(ad:0x40026400+0x40))&0x01)==0x01)&&(((per.l(ad:0x40026400+0x40))&0x80000)==0x00))
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "S2M1AR,DMA Stream 2 Memory 1 Address Register"
|
|
else
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "S2M1AR,DMA Stream 2 Memory 1 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0x40))&0x01)==0x00)
|
|
if (((per.l(ad:0x40026400+0x54))&0x04)==0x04)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "S2FCR,DMA Stream 2 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "S2FCR,DMA Stream 2 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40026400+0x54))&0x04)==0x04)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "S2FCR,DMA Stream 2 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
rbitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "S2FCR,DMA Stream 2 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Stream 3 registers"
|
|
if (((per.l(ad:0x40026400+0x58))&0x01)==0x00)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "S3CR,DMA Stream 3 Configuration Register"
|
|
sif (cpuis("STM32F74*")||cpuis("STM32F75*"))
|
|
sif cpuis("STM32F750V*")
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SAI1_A,ADC2,,SPI1_TX,SDMMC1,SPI4_RX,TIM1_CH1,TIM8_CH2"
|
|
else
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SAI1_A,ADC2,SPI5_RX,SPI1_TX,SDMMC1,SPI4_RX,TIM1_CH1,TIM8_CH2"
|
|
endif
|
|
newline
|
|
elif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SAI1_A,ADC2,SPI5_RX,SPI1_TX,SDMMC1,SPI4_RX,TIM1_CH1,TIM8_CH2,DFSDM1_FLT3,JPEG_IN,?..."
|
|
newline
|
|
elif (cpuis("STM32F72*")||cpuis("STM32F732*")||cpuis("STM32F733*"))
|
|
sif (cpuis("STM32F72?R*")||cpuis("STM32F73?R*"))
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SAI1_A,ADC2,,SPI1_TX,SDMMC1,,TIM1_CH1,TIM8_CH2"
|
|
elif (cpuis("STM32F72?V*")||cpuis("STM32F73?V*"))
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SAI1_A,ADC2,,SPI1_TX,SDMMC1,SPI4_RX,TIM1_CH1,TIM8_CH2"
|
|
else
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SAI1_A,ADC2,SPI5_RX,SPI1_TX,SDMMC1,SPI4_RX,TIM1_CH1,TIM8_CH2"
|
|
endif
|
|
newline
|
|
elif cpuis("STM32F730*")
|
|
sif cpuis("STM32F73?R*")
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SAI1_A,ADC2,,SPI1_TX,SDMMC1,,TIM1_CH1,TIM8_CH2,?..."
|
|
elif cpuis("STM32F73?V*")
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SAI1_A,ADC2,,SPI1_TX,SDMMC1,SPI4_RX,TIM1_CH1,TIM8_CH2,?..."
|
|
else
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SAI1_A,ADC2,SPI5_RX,SPI1_TX,SDMMC1,SPI4_RX,TIM1_CH1,TIM8_CH2,?..."
|
|
endif
|
|
newline
|
|
else
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" ",ADC2,,SPI1_TX,SDIO,,TIM1_CH1,TIM8_CH2"
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
newline
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
group.long 0x5C++0x07
|
|
line.long 0x00 "S3NDTR,DMA Stream 3 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S3PAR,DMA Stream 3 Peripheral Address Register"
|
|
else
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "S3CR,DMA Stream 3 Configuration Register"
|
|
sif (cpuis("STM32F74*")||cpuis("STM32F75*"))
|
|
sif cpuis("STM32F750V*")
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SAI1_A,ADC2,,SPI1_TX,SDMMC1,SPI4_RX,TIM1_CH1,TIM8_CH2"
|
|
else
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SAI1_A,ADC2,SPI5_RX,SPI1_TX,SDMMC1,SPI4_RX,TIM1_CH1,TIM8_CH2"
|
|
endif
|
|
newline
|
|
elif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SAI1_A,ADC2,SPI5_RX,SPI1_TX,SDMMC1,SPI4_RX,TIM1_CH1,TIM8_CH2,DFSDM1_FLT3,JPEG_IN,?..."
|
|
newline
|
|
elif (cpuis("STM32F72*")||cpuis("STM32F732*")||cpuis("STM32F733*"))
|
|
sif (cpuis("STM32F72?R*")||cpuis("STM32F73?R*"))
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SAI1_A,ADC2,,SPI1_TX,SDMMC1,,TIM1_CH1,TIM8_CH2"
|
|
elif (cpuis("STM32F72?V*")||cpuis("STM32F73?V*"))
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SAI1_A,ADC2,,SPI1_TX,SDMMC1,SPI4_RX,TIM1_CH1,TIM8_CH2"
|
|
else
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SAI1_A,ADC2,SPI5_RX,SPI1_TX,SDMMC1,SPI4_RX,TIM1_CH1,TIM8_CH2"
|
|
endif
|
|
newline
|
|
elif cpuis("STM32F730*")
|
|
sif cpuis("STM32F73?R*")
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SAI1_A,ADC2,,SPI1_TX,SDMMC1,,TIM1_CH1,TIM8_CH2,?..."
|
|
elif cpuis("STM32F73?V*")
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SAI1_A,ADC2,,SPI1_TX,SDMMC1,SPI4_RX,TIM1_CH1,TIM8_CH2,?..."
|
|
else
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SAI1_A,ADC2,SPI5_RX,SPI1_TX,SDMMC1,SPI4_RX,TIM1_CH1,TIM8_CH2,?..."
|
|
endif
|
|
newline
|
|
else
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" ",ADC2,,SPI1_TX,SDIO,,TIM1_CH1,TIM8_CH2"
|
|
newline
|
|
endif
|
|
newline
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
newline
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
rgroup.long 0x5C++0x07
|
|
line.long 0x00 "S3NDTR,DMA Stream 3 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S3PAR,DMA Stream 3 Peripheral Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0x58))&0x01)==0x00)||((((per.l(ad:0x40026400+0x58))&0x01)==0x01)&&(((per.l(ad:0x40026400+0x58))&0x80000)==0x80000))
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "S3M0AR,DMA Stream 3 Memory 0 Address Register"
|
|
else
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "S3M0AR,DMA Stream 3 Memory 0 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0x58))&0x01)==0x00)||((((per.l(ad:0x40026400+0x58))&0x01)==0x01)&&(((per.l(ad:0x40026400+0x58))&0x80000)==0x00))
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "S3M1AR,DMA Stream 3 Memory 1 Address Register"
|
|
else
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "S3M1AR,DMA Stream 3 Memory 1 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0x58))&0x01)==0x00)
|
|
if (((per.l(ad:0x40026400+0x6C))&0x04)==0x04)
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "S3FCR,DMA Stream 3 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "S3FCR,DMA Stream 3 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40026400+0x6C))&0x04)==0x04)
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "S3FCR,DMA Stream 3 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
rbitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "S3FCR,DMA Stream 3 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Stream 4 registers"
|
|
if (((per.l(ad:0x40026400+0x70))&0x01)==0x00)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "S4CR,DMA Stream 4 Configuration Register"
|
|
sif (cpuis("STM32F74*")||cpuis("STM32F75*"))
|
|
sif cpuis("STM32F750V*")
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "ADC1,SAI1_B,,SAI2_A,,SPI4_TX,TIM1_CH4/TIM1_TRIG/TIM1_COM,TIM8_CH3"
|
|
else
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "ADC1,SAI1_B,SPI5_TX,SAI2_A,,SPI4_TX,TIM1_CH4/TIM1_TRIG/TIM1_COM,TIM8_CH3"
|
|
endif
|
|
newline
|
|
elif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "ADC1,SAI1_B,SPI5_TX,SAI2_A,,SPI4_TX,TIM1_CH4/TIM1_TRIG/TIM1_COM,TIM8_CH3,DFSDM1_FLT0,JPEG_OUT,?..."
|
|
newline
|
|
elif (cpuis("STM32F72*")||cpuis("STM32F732*")||cpuis("STM32F733*"))
|
|
sif (cpuis("STM32F72?R*")||cpuis("STM32F73?R"))
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "ADC1,SAI1_B,,SAI2_A,,,TIM1_CH4/TIM1_TRIG/TIM1_COM,TIM8_CH3"
|
|
elif (cpuis("STM32F72?V*")||cpuis("STM32F73?V*"))
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "ADC1,SAI1_B,,SAI2_A,,SPI4_TX,TIM1_CH4/TIM1_TRIG/TIM1_COM,TIM8_CH3"
|
|
else
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "ADC1,SAI1_B,SPI5_TX,SAI2_A,,SPI4_TX,TIM1_CH4/TIM1_TRIG/TIM1_COM,TIM8_CH3"
|
|
endif
|
|
newline
|
|
elif cpuis("STM32F730*")
|
|
sif cpuis("STM32F73?R")
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "ADC1,SAI1_B,,SAI2_A,,,TIM1_CH4/TIM1_TRIG/TIM1_COM,TIM8_CH3,?..."
|
|
elif cpuis("STM32F73?V*")
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "ADC1,SAI1_B,,SAI2_A,,SPI4_TX,TIM1_CH4/TIM1_TRIG/TIM1_COM,TIM8_CH3,?..."
|
|
else
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "ADC1,SAI1_B,SPI5_TX,SAI2_A,,SPI4_TX,TIM1_CH4/TIM1_TRIG/TIM1_COM,TIM8_CH3,?..."
|
|
endif
|
|
newline
|
|
else
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "ADC1,,,,,,TIM1_CH4/TRIG/COM,TIM8_CH3"
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
newline
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
group.long 0x74++0x07
|
|
line.long 0x00 "S4NDTR,DMA Stream 4 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S4PAR,DMA Stream 4 Peripheral Address Register"
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "S4CR,DMA Stream 4 Configuration Register"
|
|
sif (cpuis("STM32F74*")||cpuis("STM32F75*"))
|
|
sif cpuis("STM32F750V*")
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "ADC1,SAI1_B,,SAI2_A,,SPI4_TX,TIM1_CH4/TIM1_TRIG/TIM1_COM,TIM8_CH3"
|
|
else
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "ADC1,SAI1_B,SPI5_TX,SAI2_A,,SPI4_TX,TIM1_CH4/TIM1_TRIG/TIM1_COM,TIM8_CH3"
|
|
endif
|
|
newline
|
|
elif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "ADC1,SAI1_B,SPI5_TX,SAI2_A,,SPI4_TX,TIM1_CH4/TIM1_TRIG/TIM1_COM,TIM8_CH3,DFSDM1_FLT0,JPEG_OUT,?..."
|
|
newline
|
|
elif (cpuis("STM32F72*")||cpuis("STM32F732*")||cpuis("STM32F733*"))
|
|
sif (cpuis("STM32F72?R*")||cpuis("STM32F73?R"))
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "ADC1,SAI1_B,,SAI2_A,,,TIM1_CH4/TIM1_TRIG/TIM1_COM,TIM8_CH3"
|
|
elif (cpuis("STM32F72?V*")||cpuis("STM32F73?V*"))
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "ADC1,SAI1_B,,SAI2_A,,SPI4_TX,TIM1_CH4/TIM1_TRIG/TIM1_COM,TIM8_CH3"
|
|
else
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "ADC1,SAI1_B,SPI5_TX,SAI2_A,,SPI4_TX,TIM1_CH4/TIM1_TRIG/TIM1_COM,TIM8_CH3"
|
|
endif
|
|
newline
|
|
elif cpuis("STM32F730*")
|
|
sif cpuis("STM32F73?R")
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "ADC1,SAI1_B,,SAI2_A,,,TIM1_CH4/TIM1_TRIG/TIM1_COM,TIM8_CH3,?..."
|
|
elif cpuis("STM32F73?V*")
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "ADC1,SAI1_B,,SAI2_A,,SPI4_TX,TIM1_CH4/TIM1_TRIG/TIM1_COM,TIM8_CH3,?..."
|
|
else
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "ADC1,SAI1_B,SPI5_TX,SAI2_A,,SPI4_TX,TIM1_CH4/TIM1_TRIG/TIM1_COM,TIM8_CH3,?..."
|
|
endif
|
|
newline
|
|
else
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "ADC1,,,,,,TIM1_CH4/TRIG/COM,TIM8_CH3"
|
|
newline
|
|
endif
|
|
newline
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
newline
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
rgroup.long 0x74++0x07
|
|
line.long 0x00 "S4NDTR,DMA Stream 4 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S4PAR,DMA Stream 4 Peripheral Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0x70))&0x01)==0x00)||((((per.l(ad:0x40026400+0x70))&0x01)==0x01)&&(((per.l(ad:0x40026400+0x70))&0x80000)==0x80000))
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "S4M0AR,DMA Stream 4 Memory 0 Address Register"
|
|
else
|
|
rgroup.long 0x7C++0x03
|
|
line.long 0x00 "S4M0AR,DMA Stream 4 Memory 0 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0x70))&0x01)==0x00)||((((per.l(ad:0x40026400+0x70))&0x01)==0x01)&&(((per.l(ad:0x40026400+0x70))&0x80000)==0x00))
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "S4M1AR,DMA Stream 4 Memory 1 Address Register"
|
|
else
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "S4M1AR,DMA Stream 4 Memory 1 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0x28))&0x01)==0x00)
|
|
if (((per.l(ad:0x40026400+0x84))&0x04)==0x04)
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "S4FCR,DMA Stream 4 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "S4FCR,DMA Stream 4 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40026400+0x84))&0x04)==0x04)
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "S4FCR,DMA Stream 4 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
rbitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "S4FCR,DMA Stream 4 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Stream 5 registers"
|
|
if (((per.l(ad:0x40026400+0x88))&0x01)==0x00)
|
|
group.long 0x88++0x0B
|
|
line.long 0x00 "S5CR,DMA Stream 5 Configuration Register"
|
|
sif (cpuis("STM32F74*")||cpuis("STM32F75*"))
|
|
sif cpuis("STM32F750V*")
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SAI1_B,,CRYP_OUT,SPI1_TX,USART1_RX,,TIM1_UP,?..."
|
|
else
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SAI1_B,SPI6_TX,CRYP_OUT,SPI1_TX,USART1_RX,,TIM1_UP,SPI5_RX"
|
|
endif
|
|
newline
|
|
elif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SAI1_B,SPI6_TX,CRYP_OUT,SPI1_TX,USART1_RX,,TIM1_UP,SPI5_RX,DFSDM1_FLT1,SPI5_RX,,SDMMC2,?..."
|
|
newline
|
|
elif (cpuis("STM32F72*")||cpuis("STM32F732*")||cpuis("STM32F732*"))
|
|
sif (cpuis("STM32F72?R*")||cpuis("STM32F73?R"))
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SAI1_B,,AES_OUT,SPI1_TX,USART1_RX,,TIM1_UP,?..."
|
|
elif (cpuis("STM32F72?V*")||cpuis("STM32F73?V*"))
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SAI1_B,,AES_OUT,SPI1_TX,USART1_RX,,TIM1_UP,?..."
|
|
else
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SAI1_B,,AES_OUT,SPI1_TX,USART1_RX,,TIM1_UP,SPI5_RX"
|
|
endif
|
|
newline
|
|
elif cpuis("STM32F730*")
|
|
sif cpuis("STM32F73?R")
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SAI1_B,,AES_OUT,SPI1_TX,USART1_RX,,TIM1_UP,?..."
|
|
elif cpuis("STM32F73?V*")
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SAI1_B,,AES_OUT,SPI1_TX,USART1_RX,,TIM1_UP,,,,,SDMMC2,?..."
|
|
else
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SAI1_B,,AES_OUT,SPI1_TX,USART1_RX,,TIM1_UP,SPI5_RX,,,,SDMMC2,?..."
|
|
endif
|
|
newline
|
|
else
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" ",,CRYP_OUT,SPI1_TX,USART1_RX,,TIM1_UP,?..."
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
newline
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
line.long 0x04 "S5NDTR,DMA Stream 5 Number Of Data Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x08 "S5PAR,DMA Stream 5 Peripheral Address Register"
|
|
else
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "S5CR,DMA Stream 5 Configuration Register"
|
|
sif (cpuis("STM32F74*")||cpuis("STM32F75*"))
|
|
sif cpuis("STM32F750V*")
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SAI1_B,,CRYP_OUT,SPI1_TX,USART1_RX,,TIM1_UP,?..."
|
|
else
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SAI1_B,SPI6_TX,CRYP_OUT,SPI1_TX,USART1_RX,,TIM1_UP,SPI5_RX"
|
|
endif
|
|
newline
|
|
elif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SAI1_B,SPI6_TX,CRYP_OUT,SPI1_TX,USART1_RX,,TIM1_UP,SPI5_RX,DFSDM1_FLT1,SPI5_RX,,SDMMC2,?..."
|
|
newline
|
|
elif (cpuis("STM32F72*")||cpuis("STM32F732*")||cpuis("STM32F732*"))
|
|
sif (cpuis("STM32F72?R*")||cpuis("STM32F73?R"))
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SAI1_B,,AES_OUT,SPI1_TX,USART1_RX,,TIM1_UP,?..."
|
|
elif (cpuis("STM32F72?V*")||cpuis("STM32F73?V*"))
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SAI1_B,,AES_OUT,SPI1_TX,USART1_RX,,TIM1_UP,?..."
|
|
else
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SAI1_B,,AES_OUT,SPI1_TX,USART1_RX,,TIM1_UP,SPI5_RX"
|
|
endif
|
|
newline
|
|
elif cpuis("STM32F730*")
|
|
sif cpuis("STM32F73?R")
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SAI1_B,,AES_OUT,SPI1_TX,USART1_RX,,TIM1_UP,?..."
|
|
elif cpuis("STM32F73?V*")
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SAI1_B,,AES_OUT,SPI1_TX,USART1_RX,,TIM1_UP,,,,,SDMMC2,?..."
|
|
else
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SAI1_B,,AES_OUT,SPI1_TX,USART1_RX,,TIM1_UP,SPI5_RX,,,,SDMMC2,?..."
|
|
endif
|
|
newline
|
|
else
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" ",,CRYP_OUT,SPI1_TX,USART1_RX,,TIM1_UP,?..."
|
|
newline
|
|
endif
|
|
newline
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
newline
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
rgroup.long 0x8C++0x07
|
|
line.long 0x00 "S5NDTR,DMA Stream 5 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S5PAR,DMA Stream 5 Peripheral Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0x88))&0x01)==0x00)||((((per.l(ad:0x40026400+0x88))&0x01)==0x01)&&(((per.l(ad:0x40026400+0x88))&0x80000)==0x80000))
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "S5M0AR,DMA Stream 5 Memory 0 Address Register"
|
|
else
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "S5M0AR,DMA Stream 5 Memory 0 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0x88))&0x01)==0x00)||((((per.l(ad:0x40026400+0x88))&0x01)==0x01)&&(((per.l(ad:0x40026400+0x88))&0x80000)==0x00))
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "S5M1AR,DMA Stream 5 Memory 1 Address Register"
|
|
else
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "S5M1AR,DMA Stream 5 Memory 1 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0x88))&0x01)==0x00)
|
|
if (((per.l(ad:0x40026400+0x9C))&0x04)==0x04)
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "S5FCR,DMA Stream 5 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "S5FCR,DMA Stream 5 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40026400+0x9C))&0x04)==0x04)
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "S5FCR,DMA Stream 5 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
rbitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "S5FCR,DMA Stream 5 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Stream 6 registers"
|
|
if (((per.l(ad:0x40026400+0xA0))&0x01)==0x00)
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "S6CR,DMA Stream 6 Configuration Register"
|
|
sif (cpuis("STM32F74*")||cpuis("STM32F75*"))
|
|
sif cpuis("STM32F750V*")
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "TIM1_CH1/TIM1_CH2/TIM1_CH3,,CRYP_IN,SAI2_B,SDMMC1,USART6_TX,TIM1_CH3,?..."
|
|
else
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "TIM1_CH1/TIM1_CH2/TIM1_CH3,SPI6_RX,CRYP_IN,SAI2_B,SDMMC1,USART6_TX,TIM1_CH3,SPI5_TX"
|
|
endif
|
|
newline
|
|
elif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "TIM1_CH1/TIM1_CH2/TIM1_CH3,SPI6_RX,CRYP_IN,SAI2_B,SDMMC1,USART6_TX,TIM1_CH3,SPI5_TX,DFSDM1_FLT2,,SAI1_A,?..."
|
|
newline
|
|
elif (cpuis("STM32F72*")||cpuis("STM32F732*")||cpuis("STM32F733*"))
|
|
sif (cpuis("STM32F72?R*")||cpuis("STM32F73?R*")||cpuis("STM32F72?V*")||cpuis("STM32F73?V*"))
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "TIM1_CH1/TIM1_CH2/TIM1_CH3,,AES_IN,SAI2_B,SDMMC1,USART6_TX,TIM1_CH3,?..."
|
|
else
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "TIM1_CH1/TIM1_CH2/TIM1_CH3,,AES_IN,SAI2_B,SDMMC1,USART6_TX,TIM1_CH3,SPI5_TX,?..."
|
|
endif
|
|
newline
|
|
elif cpuis("STM32F730*")
|
|
sif cpuis("STM32F73?R*")||cpuis("STM32F73?V*")
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "TIM1_CH1/TIM1_CH2/TIM1_CH3,,AES_IN,SAI2_B,SDMMC1,USART6_TX,TIM1_CH3,?..."
|
|
else
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "TIM1_CH1/TIM1_CH2/TIM1_CH3,,AES_IN,SAI2_B,SDMMC1,USART6_TX,TIM1_CH3,SPI5_TX,?..."
|
|
endif
|
|
newline
|
|
else
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "TIM1_CH1/2/3,,CRYP_IN,,SDIO,USART6_TX,TIM1_CH3,?..."
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
newline
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
group.long 0xA4++0x07
|
|
line.long 0x00 "S6NDTR,DMA Stream 6 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S6PAR,DMA Stream 6 Peripheral Address Register"
|
|
else
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "S6CR,DMA Stream 6 Configuration Register"
|
|
sif (cpuis("STM32F74*")||cpuis("STM32F75*"))
|
|
sif cpuis("STM32F750V*")
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "TIM1_CH1/TIM1_CH2/TIM1_CH3,,CRYP_IN,SAI2_B,SDMMC1,USART6_TX,TIM1_CH3,?..."
|
|
else
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "TIM1_CH1/TIM1_CH2/TIM1_CH3,SPI6_RX,CRYP_IN,SAI2_B,SDMMC1,USART6_TX,TIM1_CH3,SPI5_TX"
|
|
endif
|
|
newline
|
|
elif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "TIM1_CH1/TIM1_CH2/TIM1_CH3,SPI6_RX,CRYP_IN,SAI2_B,SDMMC1,USART6_TX,TIM1_CH3,SPI5_TX,DFSDM1_FLT2,,SAI1_A,?..."
|
|
newline
|
|
elif (cpuis("STM32F72*")||cpuis("STM32F732*")||cpuis("STM32F733*"))
|
|
sif (cpuis("STM32F72?R*")||cpuis("STM32F73?R*")||cpuis("STM32F72?V*")||cpuis("STM32F73?V*"))
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "TIM1_CH1/TIM1_CH2/TIM1_CH3,,AES_IN,SAI2_B,SDMMC1,USART6_TX,TIM1_CH3,?..."
|
|
else
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "TIM1_CH1/TIM1_CH2/TIM1_CH3,,AES_IN,SAI2_B,SDMMC1,USART6_TX,TIM1_CH3,SPI5_TX,?..."
|
|
endif
|
|
newline
|
|
elif cpuis("STM32F730*")
|
|
sif cpuis("STM32F73?R*")||cpuis("STM32F73?V*")
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "TIM1_CH1/TIM1_CH2/TIM1_CH3,,AES_IN,SAI2_B,SDMMC1,USART6_TX,TIM1_CH3,?..."
|
|
else
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "TIM1_CH1/TIM1_CH2/TIM1_CH3,,AES_IN,SAI2_B,SDMMC1,USART6_TX,TIM1_CH3,SPI5_TX,?..."
|
|
endif
|
|
newline
|
|
else
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "TIM1_CH1/2/3,,CRYP_IN,,SDIO,USART6_TX,TIM1_CH3,?..."
|
|
newline
|
|
endif
|
|
newline
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
newline
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
rgroup.long 0xA4++0x07
|
|
line.long 0x00 "S6NDTR,DMA Stream 6 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S6PAR,DMA Stream 6 Peripheral Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0xA0))&0x01)==0x00)||((((per.l(ad:0x40026400+0xA0))&0x01)==0x01)&&(((per.l(ad:0x40026400+0xA0))&0x80000)==0x80000))
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "S6M0AR,DMA Stream 6 Memory 0 Address Register"
|
|
else
|
|
rgroup.long 0xAC++0x03
|
|
line.long 0x00 "S6M0AR,DMA Stream 6 Memory 0 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0xA0))&0x01)==0x00)||((((per.l(ad:0x40026400+0xA0))&0x01)==0x01)&&(((per.l(ad:0x40026400+0xA0))&0x80000)==0x00))
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "S6M1AR,DMA Stream 6 Memory 1 Address Register"
|
|
else
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "S6M1AR,DMA Stream 6 Memory 1 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0xA0))&0x01)==0x00)
|
|
if (((per.l(ad:0x40026400+0xB4))&0x04)==0x04)
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "S6FCR,DMA Stream 6 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "S6FCR,DMA Stream 6 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40026400+0xB4))&0x04)==0x04)
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "S6FCR,DMA Stream 6 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
rbitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "S6FCR,DMA Stream 6 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Stream 7 registers"
|
|
if (((per.l(ad:0x40026400+0xB8))&0x01)==0x00)
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "S7CR,DMA Stream 7 Configuration Register"
|
|
sif (cpuis("STM32F74*")||cpuis("STM32F75*"))
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SAI2_B,DCMI,HASH_IN,QUADSPI,USART1_TX,USART6_TX,,TIM8_CH4/TRIG/COM"
|
|
newline
|
|
elif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SAI2_B,DCMI,HASH_IN,QUADSPI,USART1_TX,USART6_TX,,TIM8_CH4/TRIG/COM,DFSDM1_FLT3,?..."
|
|
newline
|
|
elif (cpuis("STM32F72*")||cpuis("STM32F732*")||cpuis("STM32F733*"))
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SAI2_B,,,QUADSPI,USART1_TX,USART6_TX,,TIM8_CH4/TRIG/COM"
|
|
newline
|
|
elif cpuis("STM32F730*")
|
|
bitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SAI2_B,,,QUADSPI,USART1_TX,USART6_TX,,TIM8_CH4/TRIG/COM,?..."
|
|
newline
|
|
else
|
|
bitfld.long 0x00 25.--27. " CHSEL ,Channel selection" ",,HASH_IN,,USART1_TX,USART6_TX,,TIM8_CH4/TRIG/COM"
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
newline
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
group.long 0xBC++0x07
|
|
line.long 0x00 "S7NDTR,DMA Stream 7 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S7PAR,DMA Stream 7 Peripheral Address Register"
|
|
else
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "S7CR,DMA Stream 7 Configuration Register"
|
|
sif (cpuis("STM32F74*")||cpuis("STM32F75*"))
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SAI2_B,DCMI,HASH_IN,QUADSPI,USART1_TX,USART6_TX,,TIM8_CH4/TRIG/COM"
|
|
newline
|
|
elif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SAI2_B,DCMI,HASH_IN,QUADSPI,USART1_TX,USART6_TX,,TIM8_CH4/TRIG/COM,DFSDM1_FLT3,?..."
|
|
newline
|
|
elif (cpuis("STM32F72*")||cpuis("STM32F732*")||cpuis("STM32F733*"))
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" "SAI2_B,,,QUADSPI,USART1_TX,USART6_TX,,TIM8_CH4/TRIG/COM"
|
|
newline
|
|
elif cpuis("STM32F730*")
|
|
rbitfld.long 0x00 25.--28. " CHSEL ,Channel selection" "SAI2_B,,,QUADSPI,USART1_TX,USART6_TX,,TIM8_CH4/TRIG/COM,?..."
|
|
newline
|
|
else
|
|
rbitfld.long 0x00 25.--27. " CHSEL ,Channel selection" ",,HASH_IN,,USART1_TX,USART6_TX,,TIM8_CH4/TRIG/COM"
|
|
newline
|
|
endif
|
|
newline
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
newline
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
rgroup.long 0xBC++0x07
|
|
line.long 0x00 "S7NDTR,DMA Stream 7 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S7PAR,DMA Stream 7 Peripheral Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0xB8))&0x01)==0x00)||((((per.l(ad:0x40026400+0xB8))&0x01)==0x01)&&(((per.l(ad:0x40026400+0xB8))&0x80000)==0x80000))
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "S7M0AR,DMA Stream 7 Memory 0 Address Register"
|
|
else
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "S7M0AR,DMA Stream 7 Memory 0 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0xB8))&0x01)==0x00)||((((per.l(ad:0x40026400+0xB8))&0x01)==0x01)&&(((per.l(ad:0x40026400+0xB8))&0x80000)==0x00))
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "S7M1AR,DMA Stream 7 Memory 1 Address Register"
|
|
else
|
|
rgroup.long 0xC8++0x03
|
|
line.long 0x00 "S7M1AR,DMA Stream 7 Memory 1 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0xB8))&0x01)==0x00)
|
|
if (((per.l(ad:0x40026400+0xCC))&0x04)==0x04)
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "S7FCR,DMA Stream 7 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "S7FCR,DMA Stream 7 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40026400+0xCC))&0x04)==0x04)
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "S7FCR,DMA Stream 7 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
rbitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "S7FCR,DMA Stream 7 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
endif
|
|
endif
|
|
tree.end
|
|
else
|
|
if (((per.l(ad:0x40026400+0x10))&0x01)==0x00)
|
|
if (((per.l(ad:0x40026400+0x10))&0x40000)==0x40000)
|
|
group.long 0x10++0x03 "Stream 0 Registers"
|
|
line.long 0x00 "S0CR,DMA Stream 0 Configuration Register"
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
newline
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03 "Stream 0 Registers"
|
|
line.long 0x00 "S0CR,DMA Stream 0 Configuration Register"
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
newline
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x10+0x04)++0x07
|
|
line.long 0x00 "S0NDTR,DMA Stream 0 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S0PAR,DMA Stream 0 Peripheral Address Register"
|
|
else
|
|
if (((per.l(ad:0x40026400+0x10))&0x40000)==0x40000)
|
|
group.long 0x10++0x03 "Stream 0 Registers"
|
|
line.long 0x00 "S0CR,DMA Stream 0 Configuration Register"
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
newline
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03 "Stream 0 Registers"
|
|
line.long 0x00 "S0CR,DMA Stream 0 Configuration Register"
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
newline
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
newline
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long (0x10+0x04)++0x07
|
|
line.long 0x00 "S0NDTR,DMA Stream 0 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S0PAR,DMA Stream 0 Peripheral Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0x10))&0x01)==0x00)||((((per.l(ad:0x40026400+0x10))&0x01)==0x01)&&(((per.l(ad:0x40026400+0x10))&0x80000)==0x80000))
|
|
group.long (0x10+0x0C)++0x07
|
|
line.long 0x00 "S0M0AR,DMA Stream 0 Memory 0 Address Register"
|
|
line.long 0x04 "S0M1AR,DMA Stream 0 Memory 1 Address Register"
|
|
else
|
|
rgroup.long (0x10+0x0C)++0x07
|
|
line.long 0x00 "S0M0AR,DMA Stream 0 Memory 0 Address Register"
|
|
line.long 0x04 "S0M1AR,DMA Stream 0 Memory 1 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0x10))&0x01)==0x00)
|
|
group.long (0x10+0x14)++0x03
|
|
line.long 0x00 "S0FCR,DMA Stream 0 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long (0x10+0x14)++0x03
|
|
line.long 0x00 "S0FCR,DMA Stream 0 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
rbitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0x28))&0x01)==0x00)
|
|
if (((per.l(ad:0x40026400+0x28))&0x40000)==0x40000)
|
|
group.long 0x28++0x03 "Stream 1 Registers"
|
|
line.long 0x00 "S1CR,DMA Stream 1 Configuration Register"
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
newline
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x28++0x03 "Stream 1 Registers"
|
|
line.long 0x00 "S1CR,DMA Stream 1 Configuration Register"
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
newline
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x28+0x04)++0x07
|
|
line.long 0x00 "S1NDTR,DMA Stream 1 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S1PAR,DMA Stream 1 Peripheral Address Register"
|
|
else
|
|
if (((per.l(ad:0x40026400+0x28))&0x40000)==0x40000)
|
|
group.long 0x28++0x03 "Stream 1 Registers"
|
|
line.long 0x00 "S1CR,DMA Stream 1 Configuration Register"
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
newline
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x28++0x03 "Stream 1 Registers"
|
|
line.long 0x00 "S1CR,DMA Stream 1 Configuration Register"
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
newline
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
newline
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long (0x28+0x04)++0x07
|
|
line.long 0x00 "S1NDTR,DMA Stream 1 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S1PAR,DMA Stream 1 Peripheral Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0x28))&0x01)==0x00)||((((per.l(ad:0x40026400+0x28))&0x01)==0x01)&&(((per.l(ad:0x40026400+0x28))&0x80000)==0x80000))
|
|
group.long (0x28+0x0C)++0x07
|
|
line.long 0x00 "S1M0AR,DMA Stream 1 Memory 0 Address Register"
|
|
line.long 0x04 "S1M1AR,DMA Stream 1 Memory 1 Address Register"
|
|
else
|
|
rgroup.long (0x28+0x0C)++0x07
|
|
line.long 0x00 "S1M0AR,DMA Stream 1 Memory 0 Address Register"
|
|
line.long 0x04 "S1M1AR,DMA Stream 1 Memory 1 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0x28))&0x01)==0x00)
|
|
group.long (0x28+0x14)++0x03
|
|
line.long 0x00 "S1FCR,DMA Stream 1 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long (0x28+0x14)++0x03
|
|
line.long 0x00 "S1FCR,DMA Stream 1 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
rbitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0x40))&0x01)==0x00)
|
|
if (((per.l(ad:0x40026400+0x40))&0x40000)==0x40000)
|
|
group.long 0x40++0x03 "Stream 2 Registers"
|
|
line.long 0x00 "S2CR,DMA Stream 2 Configuration Register"
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
newline
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x40++0x03 "Stream 2 Registers"
|
|
line.long 0x00 "S2CR,DMA Stream 2 Configuration Register"
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
newline
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x40+0x04)++0x07
|
|
line.long 0x00 "S2NDTR,DMA Stream 2 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S2PAR,DMA Stream 2 Peripheral Address Register"
|
|
else
|
|
if (((per.l(ad:0x40026400+0x40))&0x40000)==0x40000)
|
|
group.long 0x40++0x03 "Stream 2 Registers"
|
|
line.long 0x00 "S2CR,DMA Stream 2 Configuration Register"
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
newline
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x40++0x03 "Stream 2 Registers"
|
|
line.long 0x00 "S2CR,DMA Stream 2 Configuration Register"
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
newline
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
newline
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long (0x40+0x04)++0x07
|
|
line.long 0x00 "S2NDTR,DMA Stream 2 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S2PAR,DMA Stream 2 Peripheral Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0x40))&0x01)==0x00)||((((per.l(ad:0x40026400+0x40))&0x01)==0x01)&&(((per.l(ad:0x40026400+0x40))&0x80000)==0x80000))
|
|
group.long (0x40+0x0C)++0x07
|
|
line.long 0x00 "S2M0AR,DMA Stream 2 Memory 0 Address Register"
|
|
line.long 0x04 "S2M1AR,DMA Stream 2 Memory 1 Address Register"
|
|
else
|
|
rgroup.long (0x40+0x0C)++0x07
|
|
line.long 0x00 "S2M0AR,DMA Stream 2 Memory 0 Address Register"
|
|
line.long 0x04 "S2M1AR,DMA Stream 2 Memory 1 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0x40))&0x01)==0x00)
|
|
group.long (0x40+0x14)++0x03
|
|
line.long 0x00 "S2FCR,DMA Stream 2 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long (0x40+0x14)++0x03
|
|
line.long 0x00 "S2FCR,DMA Stream 2 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
rbitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0x58))&0x01)==0x00)
|
|
if (((per.l(ad:0x40026400+0x58))&0x40000)==0x40000)
|
|
group.long 0x58++0x03 "Stream 3 Registers"
|
|
line.long 0x00 "S3CR,DMA Stream 3 Configuration Register"
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
newline
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x58++0x03 "Stream 3 Registers"
|
|
line.long 0x00 "S3CR,DMA Stream 3 Configuration Register"
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
newline
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x58+0x04)++0x07
|
|
line.long 0x00 "S3NDTR,DMA Stream 3 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S3PAR,DMA Stream 3 Peripheral Address Register"
|
|
else
|
|
if (((per.l(ad:0x40026400+0x58))&0x40000)==0x40000)
|
|
group.long 0x58++0x03 "Stream 3 Registers"
|
|
line.long 0x00 "S3CR,DMA Stream 3 Configuration Register"
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
newline
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x58++0x03 "Stream 3 Registers"
|
|
line.long 0x00 "S3CR,DMA Stream 3 Configuration Register"
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
newline
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
newline
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long (0x58+0x04)++0x07
|
|
line.long 0x00 "S3NDTR,DMA Stream 3 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S3PAR,DMA Stream 3 Peripheral Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0x58))&0x01)==0x00)||((((per.l(ad:0x40026400+0x58))&0x01)==0x01)&&(((per.l(ad:0x40026400+0x58))&0x80000)==0x80000))
|
|
group.long (0x58+0x0C)++0x07
|
|
line.long 0x00 "S3M0AR,DMA Stream 3 Memory 0 Address Register"
|
|
line.long 0x04 "S3M1AR,DMA Stream 3 Memory 1 Address Register"
|
|
else
|
|
rgroup.long (0x58+0x0C)++0x07
|
|
line.long 0x00 "S3M0AR,DMA Stream 3 Memory 0 Address Register"
|
|
line.long 0x04 "S3M1AR,DMA Stream 3 Memory 1 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0x58))&0x01)==0x00)
|
|
group.long (0x58+0x14)++0x03
|
|
line.long 0x00 "S3FCR,DMA Stream 3 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long (0x58+0x14)++0x03
|
|
line.long 0x00 "S3FCR,DMA Stream 3 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
rbitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0x70))&0x01)==0x00)
|
|
if (((per.l(ad:0x40026400+0x70))&0x40000)==0x40000)
|
|
group.long 0x70++0x03 "Stream 4 Registers"
|
|
line.long 0x00 "S4CR,DMA Stream 4 Configuration Register"
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
newline
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x70++0x03 "Stream 4 Registers"
|
|
line.long 0x00 "S4CR,DMA Stream 4 Configuration Register"
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
newline
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x70+0x04)++0x07
|
|
line.long 0x00 "S4NDTR,DMA Stream 4 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S4PAR,DMA Stream 4 Peripheral Address Register"
|
|
else
|
|
if (((per.l(ad:0x40026400+0x70))&0x40000)==0x40000)
|
|
group.long 0x70++0x03 "Stream 4 Registers"
|
|
line.long 0x00 "S4CR,DMA Stream 4 Configuration Register"
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
newline
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x70++0x03 "Stream 4 Registers"
|
|
line.long 0x00 "S4CR,DMA Stream 4 Configuration Register"
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
newline
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
newline
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long (0x70+0x04)++0x07
|
|
line.long 0x00 "S4NDTR,DMA Stream 4 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S4PAR,DMA Stream 4 Peripheral Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0x70))&0x01)==0x00)||((((per.l(ad:0x40026400+0x70))&0x01)==0x01)&&(((per.l(ad:0x40026400+0x70))&0x80000)==0x80000))
|
|
group.long (0x70+0x0C)++0x07
|
|
line.long 0x00 "S4M0AR,DMA Stream 4 Memory 0 Address Register"
|
|
line.long 0x04 "S4M1AR,DMA Stream 4 Memory 1 Address Register"
|
|
else
|
|
rgroup.long (0x70+0x0C)++0x07
|
|
line.long 0x00 "S4M0AR,DMA Stream 4 Memory 0 Address Register"
|
|
line.long 0x04 "S4M1AR,DMA Stream 4 Memory 1 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0x70))&0x01)==0x00)
|
|
group.long (0x70+0x14)++0x03
|
|
line.long 0x00 "S4FCR,DMA Stream 4 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long (0x70+0x14)++0x03
|
|
line.long 0x00 "S4FCR,DMA Stream 4 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
rbitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0x88))&0x01)==0x00)
|
|
if (((per.l(ad:0x40026400+0x88))&0x40000)==0x40000)
|
|
group.long 0x88++0x03 "Stream 5 Registers"
|
|
line.long 0x00 "S5CR,DMA Stream 5 Configuration Register"
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
newline
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x88++0x03 "Stream 5 Registers"
|
|
line.long 0x00 "S5CR,DMA Stream 5 Configuration Register"
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
newline
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x88+0x04)++0x07
|
|
line.long 0x00 "S5NDTR,DMA Stream 5 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S5PAR,DMA Stream 5 Peripheral Address Register"
|
|
else
|
|
if (((per.l(ad:0x40026400+0x88))&0x40000)==0x40000)
|
|
group.long 0x88++0x03 "Stream 5 Registers"
|
|
line.long 0x00 "S5CR,DMA Stream 5 Configuration Register"
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
newline
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x88++0x03 "Stream 5 Registers"
|
|
line.long 0x00 "S5CR,DMA Stream 5 Configuration Register"
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
newline
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
newline
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long (0x88+0x04)++0x07
|
|
line.long 0x00 "S5NDTR,DMA Stream 5 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S5PAR,DMA Stream 5 Peripheral Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0x88))&0x01)==0x00)||((((per.l(ad:0x40026400+0x88))&0x01)==0x01)&&(((per.l(ad:0x40026400+0x88))&0x80000)==0x80000))
|
|
group.long (0x88+0x0C)++0x07
|
|
line.long 0x00 "S5M0AR,DMA Stream 5 Memory 0 Address Register"
|
|
line.long 0x04 "S5M1AR,DMA Stream 5 Memory 1 Address Register"
|
|
else
|
|
rgroup.long (0x88+0x0C)++0x07
|
|
line.long 0x00 "S5M0AR,DMA Stream 5 Memory 0 Address Register"
|
|
line.long 0x04 "S5M1AR,DMA Stream 5 Memory 1 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0x88))&0x01)==0x00)
|
|
group.long (0x88+0x14)++0x03
|
|
line.long 0x00 "S5FCR,DMA Stream 5 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long (0x88+0x14)++0x03
|
|
line.long 0x00 "S5FCR,DMA Stream 5 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
rbitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0xA0))&0x01)==0x00)
|
|
if (((per.l(ad:0x40026400+0xA0))&0x40000)==0x40000)
|
|
group.long 0xA0++0x03 "Stream 6 Registers"
|
|
line.long 0x00 "S6CR,DMA Stream 6 Configuration Register"
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
newline
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA0++0x03 "Stream 6 Registers"
|
|
line.long 0x00 "S6CR,DMA Stream 6 Configuration Register"
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
newline
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xA0+0x04)++0x07
|
|
line.long 0x00 "S6NDTR,DMA Stream 6 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S6PAR,DMA Stream 6 Peripheral Address Register"
|
|
else
|
|
if (((per.l(ad:0x40026400+0xA0))&0x40000)==0x40000)
|
|
group.long 0xA0++0x03 "Stream 6 Registers"
|
|
line.long 0x00 "S6CR,DMA Stream 6 Configuration Register"
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
newline
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xA0++0x03 "Stream 6 Registers"
|
|
line.long 0x00 "S6CR,DMA Stream 6 Configuration Register"
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
newline
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
newline
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long (0xA0+0x04)++0x07
|
|
line.long 0x00 "S6NDTR,DMA Stream 6 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S6PAR,DMA Stream 6 Peripheral Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0xA0))&0x01)==0x00)||((((per.l(ad:0x40026400+0xA0))&0x01)==0x01)&&(((per.l(ad:0x40026400+0xA0))&0x80000)==0x80000))
|
|
group.long (0xA0+0x0C)++0x07
|
|
line.long 0x00 "S6M0AR,DMA Stream 6 Memory 0 Address Register"
|
|
line.long 0x04 "S6M1AR,DMA Stream 6 Memory 1 Address Register"
|
|
else
|
|
rgroup.long (0xA0+0x0C)++0x07
|
|
line.long 0x00 "S6M0AR,DMA Stream 6 Memory 0 Address Register"
|
|
line.long 0x04 "S6M1AR,DMA Stream 6 Memory 1 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0xA0))&0x01)==0x00)
|
|
group.long (0xA0+0x14)++0x03
|
|
line.long 0x00 "S6FCR,DMA Stream 6 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long (0xA0+0x14)++0x03
|
|
line.long 0x00 "S6FCR,DMA Stream 6 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
rbitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0xB8))&0x01)==0x00)
|
|
if (((per.l(ad:0x40026400+0xB8))&0x40000)==0x40000)
|
|
group.long 0xB8++0x03 "Stream 7 Registers"
|
|
line.long 0x00 "S7CR,DMA Stream 7 Configuration Register"
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
newline
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB8++0x03 "Stream 7 Registers"
|
|
line.long 0x00 "S7CR,DMA Stream 7 Configuration Register"
|
|
bitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
bitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
newline
|
|
bitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
bitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
bitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
newline
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0xB8+0x04)++0x07
|
|
line.long 0x00 "S7NDTR,DMA Stream 7 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S7PAR,DMA Stream 7 Peripheral Address Register"
|
|
else
|
|
if (((per.l(ad:0x40026400+0xB8))&0x40000)==0x40000)
|
|
group.long 0xB8++0x03 "Stream 7 Registers"
|
|
line.long 0x00 "S7CR,DMA Stream 7 Configuration Register"
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 19. " CT ,Current target (double buffer mode)" "Memory 0,Memory 1"
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
newline
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
newline
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xB8++0x03 "Stream 7 Registers"
|
|
line.long 0x00 "S7CR,DMA Stream 7 Configuration Register"
|
|
rbitfld.long 0x00 23.--24. " MBURST ,Memory burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 21.--22. " PBURST ,Peripheral burst transfer configuration" "Single transfer,INCR4,INCR8,INCR16"
|
|
rbitfld.long 0x00 18. " DBM ,Double buffer mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--17. " PL ,Priority level" "Low,Medium,High,Very high"
|
|
newline
|
|
rbitfld.long 0x00 15. " PINCOS ,Peripheral increment offset size" "PSIZE,32-bit"
|
|
rbitfld.long 0x00 13.--14. " MSIZE ,Memory data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 11.--12. " PSIZE ,Peripheral data size" "8-bit,16-bit,32-bit,?..."
|
|
rbitfld.long 0x00 10. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 9. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6.--7. " DIR ,Data transfer direction" "Peripheral-to-memory,Memory-to-peripheral,Memory-to-memory,?..."
|
|
rbitfld.long 0x00 5. " PFCTRL ,Peripheral flow controller" "DMA,Peripheral"
|
|
newline
|
|
bitfld.long 0x00 4. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DMEIE ,Direct mode error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " EN ,Stream enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long (0xB8+0x04)++0x07
|
|
line.long 0x00 "S7NDTR,DMA Stream 7 Number Of Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data items to transfer"
|
|
line.long 0x04 "S7PAR,DMA Stream 7 Peripheral Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0xB8))&0x01)==0x00)||((((per.l(ad:0x40026400+0xB8))&0x01)==0x01)&&(((per.l(ad:0x40026400+0xB8))&0x80000)==0x80000))
|
|
group.long (0xB8+0x0C)++0x07
|
|
line.long 0x00 "S7M0AR,DMA Stream 7 Memory 0 Address Register"
|
|
line.long 0x04 "S7M1AR,DMA Stream 7 Memory 1 Address Register"
|
|
else
|
|
rgroup.long (0xB8+0x0C)++0x07
|
|
line.long 0x00 "S7M0AR,DMA Stream 7 Memory 0 Address Register"
|
|
line.long 0x04 "S7M1AR,DMA Stream 7 Memory 1 Address Register"
|
|
endif
|
|
if (((per.l(ad:0x40026400+0xB8))&0x01)==0x00)
|
|
group.long (0xB8+0x14)++0x03
|
|
line.long 0x00 "S7FCR,DMA Stream 7 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
bitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
else
|
|
group.long (0xB8+0x14)++0x03
|
|
line.long 0x00 "S7FCR,DMA Stream 7 FIFO Control Register"
|
|
bitfld.long 0x00 7. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3.--5. " FS ,FIFO status" "0 < fifo_level < 1/4,1/4 =< fifo_level < 1/2,1/2 =< fifo_level < 3/4,3/4 =< fifo_level < full,FIFO is empty,FIFO is full,?..."
|
|
rbitfld.long 0x00 2. " DMDIS ,Direct mode disable" "No,Yes"
|
|
rbitfld.long 0x00 0.--1. " FTH ,FIFO threshold selection" "1/4 full FIFO,1/2 full FIFO,3/4 full FIFO,Full FIFO"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
sif (!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
tree "DMA2D (Chrom-Art Accelerator controller)"
|
|
base ad:0x4002B000
|
|
width 11.
|
|
if (((per.l(ad:0x4002B000))&0x07)==(0x01))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,DMA2D Control Register"
|
|
sif cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32H742*")||cpuis("STM32H750*")
|
|
rbitfld.long 0x00 16.--18. " MODE ,DMA2D mode" "Memory-to-memory,Memory-to-memory with PFC,Memory-to-memory with blending,Register-to-memory,Memory-to-memory,Memory-to-memory,?..."
|
|
else
|
|
rbitfld.long 0x00 16.--17. " MODE ,DMA2D mode" "Memory-to-memory,Memory-to-memory with PFC,Memory-to-memory with blending,Register-to-memory"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 13. " CEIE ,Configuration error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " CTCIE ,CLUT transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " CAEIE ,CLUT access error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TWIE ,Transfer watermark interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32H742*")||cpuis("STM32H750*")
|
|
rbitfld.long 0x00 6. " LOM ,Line offset mode" "Expressed in pixels,Expressed in bytes"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 2. " ABORT ,Abort" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 0. " START ,Start" "Not started,Started"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,DMA2D Control Register"
|
|
sif cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32H742*")||cpuis("STM32H750*")
|
|
bitfld.long 0x00 16.--18. " MODE ,DMA2D mode" "Memory-to-memory,Memory-to-memory with PFC,Memory-to-memory with blending,Register-to-memory,Memory-to-memory,Memory-to-memory,?..."
|
|
else
|
|
bitfld.long 0x00 16.--17. " MODE ,DMA2D mode" "Memory-to-memory,Memory-to-memory with PFC,Memory-to-memory with blending,Register-to-memory"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 13. " CEIE ,Configuration error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " CTCIE ,CLUT transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " CAEIE ,CLUT access error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TWIE ,Transfer watermark interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32H742*")||cpuis("STM32H750*")
|
|
bitfld.long 0x00 6. " LOM ,Line offset mode" "Expressed in pixels,Expressed in bytes"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 2. " ABORT ,Abort" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 0. " START ,Start" "Not started,Started"
|
|
endif
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ISR,DMA2D Interrupt Status Register"
|
|
bitfld.long 0x00 5. " CEIF ,Configuration error interrupt flag" "No error,Error"
|
|
bitfld.long 0x00 4. " CTCIF ,CLUT transfer complete interrupt flag" "Not completed,Completed"
|
|
bitfld.long 0x00 3. " CAEIF ,CLUT access error interrupt flag" "No error,Error"
|
|
bitfld.long 0x00 2. " TWIF ,Transfer watermark interrupt flag" "Not transferred,Transferred"
|
|
newline
|
|
bitfld.long 0x00 1. " TCIF ,Transfer complete interrupt flag" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " TEIF ,Transfer error interrupt flag" "No error,Error"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "IFCR,DMA2D Interrupt Flag Clear Register"
|
|
eventfld.long 0x00 5. " CCEIF ,Clear configuration error interrupt flag" "No effect,Clear"
|
|
eventfld.long 0x00 4. " CCTCIF ,Clear CLUT transfer complete interrupt flag" "No effect,Clear"
|
|
eventfld.long 0x00 3. " CAECIF ,Clear CLUT access error interrupt flag" "No effect,Clear"
|
|
eventfld.long 0x00 2. " CTWIF ,Clear transfer watermark interrupt flag" "No effect,Clear"
|
|
newline
|
|
eventfld.long 0x00 1. " CTCIF ,Clear transfer complete interrupt flag" "No effect,Clear"
|
|
eventfld.long 0x00 0. " CTEIF ,Clear transfer error interrupt flag" "No effect,Clear"
|
|
if (((per.l(ad:0x4002B000))&0x07)==(0x01))
|
|
rgroup.long 0x0C++0x13
|
|
line.long 0x00 "FGMAR,DMA2D Foreground Memory Address Register"
|
|
line.long 0x04 "FGOR,DMA2D Foreground Offset Register"
|
|
sif cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32H742*")||cpuis("STM32H750*")
|
|
hexmask.long.word 0x04 0.--15. 0x01 " LO ,Line offset"
|
|
else
|
|
hexmask.long.word 0x04 0.--13. 0x01 " LO ,Line offset"
|
|
endif
|
|
line.long 0x08 "BGMAR,DMA2D Background Memory Address Register"
|
|
line.long 0x0C "BGOR,DMA2D Background Offset Register"
|
|
sif cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32H742*")||cpuis("STM32H750*")
|
|
hexmask.long.word 0x0C 0.--15. 0x01 " LO ,Line offset"
|
|
else
|
|
hexmask.long.word 0x0C 0.--13. 0x01 " LO ,Line offset"
|
|
endif
|
|
line.long 0x10 "FGPFCCR,DMA2D Foreground PFC Control Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " ALPHA ,Alpha value"
|
|
newline
|
|
sif cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32H742*")||cpuis("STM32H750*")
|
|
bitfld.long 0x10 21. " RBS ,Red blue swap" "Regular,Swap"
|
|
bitfld.long 0x10 20. " AI ,Alpha inverted" "Regular,Inverted"
|
|
bitfld.long 0x10 18.--19. " CSS ,Chroma sub-sampling" "4:4:4,4:2:2,4:2:0,?..."
|
|
newline
|
|
elif cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32L496*")||cpuis("STM32L4A6*")
|
|
bitfld.long 0x10 21. " RBS ,Red blue swap" "Regular,Swap"
|
|
bitfld.long 0x10 20. " AI ,Alpha inverted" "Regular,Inverted"
|
|
newline
|
|
endif
|
|
bitfld.long 0x10 16.--17. " AM ,Alpha mode" "No modification,ALPHA,Alpha * original,?..."
|
|
hexmask.long.byte 0x10 8.--15. 0x01 " CS ,CLUT size"
|
|
bitfld.long 0x10 5. " START ,Start" "Not started,Started"
|
|
bitfld.long 0x10 4. " CCM ,CLUT color mode" "ARGB8888,RGB888"
|
|
newline
|
|
bitfld.long 0x10 0.--3. " CM ,Color mode" "ARGB8888,RGB888,RGB565,ARGB1555,ARGB4444,L8,AL44,AL88,L4,A8,A4,YCbCr,?..."
|
|
else
|
|
group.long 0x0C++0x13
|
|
line.long 0x00 "FGMAR,DMA2D Foreground Memory Address Register"
|
|
line.long 0x04 "FGOR,DMA2D Foreground Offset Register"
|
|
sif cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32H742*")||cpuis("STM32H750*")
|
|
hexmask.long.word 0x04 0.--15. 0x01 " LO ,Line offset"
|
|
else
|
|
hexmask.long.word 0x04 0.--13. 0x01 " LO ,Line offset"
|
|
endif
|
|
line.long 0x08 "BGMAR,DMA2D Background Memory Address Register"
|
|
line.long 0x0C "BGOR,DMA2D Background Offset Register"
|
|
sif cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32H742*")||cpuis("STM32H750*")
|
|
hexmask.long.word 0x0C 0.--15. 0x01 " LO ,Line offset"
|
|
else
|
|
hexmask.long.word 0x0C 0.--13. 0x01 " LO ,Line offset"
|
|
endif
|
|
line.long 0x10 "FGPFCCR,DMA2D Foreground PFC Control Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " ALPHA ,Alpha value"
|
|
newline
|
|
sif cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32H742*")||cpuis("STM32H750*")
|
|
bitfld.long 0x10 21. " RBS ,Red blue swap" "Regular,Swap"
|
|
bitfld.long 0x10 20. " AI ,Alpha inverted" "Regular,Inverted"
|
|
bitfld.long 0x10 18.--19. " CSS ,Chroma sub-sampling" "4:4:4,4:2:2,4:2:0,?..."
|
|
newline
|
|
elif cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32L496*")||cpuis("STM32L4A6*")
|
|
bitfld.long 0x10 21. " RBS ,Red blue swap" "Regular,Swap"
|
|
bitfld.long 0x10 20. " AI ,Alpha inverted" "Regular,Inverted"
|
|
newline
|
|
endif
|
|
bitfld.long 0x10 16.--17. " AM ,Alpha mode" "No modification,ALPHA,Alpha * original,?..."
|
|
hexmask.long.byte 0x10 8.--15. 1. " CS ,CLUT size"
|
|
bitfld.long 0x10 5. " START ,Start" "Not started,Started"
|
|
bitfld.long 0x10 4. " CCM ,CLUT color mode" "ARGB8888,RGB888"
|
|
newline
|
|
bitfld.long 0x10 0.--3. " CM ,Color mode" "ARGB8888,RGB888,RGB565,ARGB1555,ARGB4444,L8,AL44,AL88,L4,A8,A4,YCbCr,?..."
|
|
endif
|
|
if (((per.l(ad:0x4002B000))&0x07)==(0x01))
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "FGCOLR,DMA2D Foreground Color Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED ,Red value"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN ,Green value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE ,Blue value"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "BGPFCCR,DMA2D Background PFC Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA ,Alpha value"
|
|
newline
|
|
sif cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32L496*")||cpuis("STM32L4A6*")||cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32H742*")||cpuis("STM32H750*")
|
|
rbitfld.long 0x00 21. " RBS ,Red blue swap" "Regular,Swap"
|
|
rbitfld.long 0x00 20. " AI ,Alpha inverted" "Regular,Inverted"
|
|
newline
|
|
endif
|
|
rbitfld.long 0x00 16.--17. " AM ,Alpha mode" "No modification,ALPHA,Alpha * original,?..."
|
|
hexmask.long.byte 0x00 8.--15. 1. " CS ,CLUT size"
|
|
eventfld.long 0x00 5. " START ,Start" "Not started,Started"
|
|
rbitfld.long 0x00 4. " CCM ,CLUT color mode" "ARGB8888,RGB888"
|
|
newline
|
|
rbitfld.long 0x00 0.--3. " CM ,Color mode" "ARGB8888,RGB888,RGB565,ARGB1555,ARGB4444,L8,AL44,AL88,L4,A8,A4,?..."
|
|
else
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "FGCOLR,DMA2D Foreground Color Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED ,Red value"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN ,Green value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE ,Blue value"
|
|
line.long 0x04 "BGPFCCR,DMA2D Background PFC Control Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " ALPHA ,Alpha value"
|
|
newline
|
|
sif cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32L496*")||cpuis("STM32L4A6*")||cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32H742*")||cpuis("STM32H750*")
|
|
bitfld.long 0x04 21. " RBS ,Red blue swap" "Regular,Swap"
|
|
bitfld.long 0x04 20. " AI ,Alpha inverted" "Regular,Inverted"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 16.--17. " AM ,Alpha mode" "No modification,ALPHA,Alpha * original,?..."
|
|
hexmask.long.byte 0x04 8.--15. 1. " CS ,CLUT size"
|
|
eventfld.long 0x04 5. " START ,Start" "Not started,Started"
|
|
bitfld.long 0x04 4. " CCM ,CLUT color mode" "ARGB8888,RGB888"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " CM ,Color mode" "ARGB8888,RGB888,RGB565,ARGB1555,ARGB4444,L8,AL44,AL88,L4,A8,A4,?..."
|
|
endif
|
|
if (((per.l(ad:0x4002B000))&0x07)==(0x01))
|
|
rgroup.long 0x28++0x0F
|
|
line.long 0x00 "BGCOLR,DMA2D Background Color Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED ,Red value"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN ,Green value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE ,Blue value"
|
|
line.long 0x04 "FGCMAR,DMA2D Foreground CLUT Memory Address Register"
|
|
line.long 0x08 "BGCMAR,DMA2D Background CLUT Memory Address Register"
|
|
line.long 0x0C "OPFCCR,DMA2D Output PFC Control Register"
|
|
sif cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32H742*")||cpuis("STM32H750*")
|
|
bitfld.long 0x0C 21. " RBS ,Red blue swap" "Regular,Swap"
|
|
bitfld.long 0x0C 20. " AI ,Alpha inverted" "Regular,Inverted"
|
|
bitfld.long 0x0C 8. " SB ,Swap bytes" "Regular,Swapped"
|
|
newline
|
|
elif cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32L496*")||cpuis("STM32L4A6*")
|
|
bitfld.long 0x0C 21. " RBS ,Red blue swap" "Regular,Swap"
|
|
bitfld.long 0x0C 20. " AI ,Alpha inverted" "Regular,Inverted"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0C 0.--2. " CM ,Color mode" "ARGB8888,RGB888,RGB565,ARGB1555,ARGB4444,?..."
|
|
if (((per.l((ad:0x4002B000+0x34))&0x07))==0x00)
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "OCOLR,DMA2D Output Color Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA ,Alpha value"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED ,Red value"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN ,Green value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE ,Blue value"
|
|
elif (((per.l((ad:0x4002B000+0x34))&0x07))==0x01)
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "OCOLR,DMA2D Output Color Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED ,Red value"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN ,Green value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE ,Blue value"
|
|
elif (((per.l((ad:0x4002B000+0x34))&0x07))==0x02)
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "OCOLR,DMA2D Output Color Register"
|
|
bitfld.long 0x00 11.--15. " RED ,Red value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--10. " GREEN ,Green value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--4. " BLUE ,Blue value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
elif (((per.l((ad:0x4002B000+0x34))&0x07))==0x03)
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "OCOLR,DMA2D Output Color Register"
|
|
bitfld.long 0x00 15. " ALPHA ,Alpha value" "0,1"
|
|
bitfld.long 0x00 10.--14. " RED ,Red value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " GREEN ,Green value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " BLUE ,Blue value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
elif (((per.l((ad:0x4002B000+0x34))&0x07))==0x04)
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "OCOLR,DMA2D Output Color Register"
|
|
bitfld.long 0x00 12.--15. " ALPHA ,Alpha value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " RED ,Red value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " GREEN ,Green value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " BLUE ,Blue value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "OCOLR,DMA2D Output Color Register"
|
|
endif
|
|
rgroup.long 0x3C++0x0F
|
|
line.long 0x00 "OMAR,DMA2D Output Memory Address Register"
|
|
line.long 0x04 "OOR,DMA2D Output Offset Register"
|
|
hexmask.long.word 0x04 0.--13. 0x01 " LO ,Line offset"
|
|
line.long 0x08 "NLR,DMA2D Number Of Line Register"
|
|
hexmask.long.word 0x08 16.--29. 1. " PL ,Pixel per lines"
|
|
hexmask.long.word 0x08 0.--15. 1. " NL ,Number of lines"
|
|
line.long 0x0C "LWR,DMA2D Line Watermark Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " LW ,Line watermark"
|
|
else
|
|
group.long 0x28++0x0F
|
|
line.long 0x00 "BGCOLR,DMA2D Background Color Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED ,Red value"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN ,Green value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE ,Blue value"
|
|
line.long 0x04 "FGCMAR,DMA2D Foreground CLUT Memory Address Register"
|
|
line.long 0x08 "BGCMAR,DMA2D Background CLUT Memory Address Register"
|
|
line.long 0x0C "OPFCCR,DMA2D Output PFC Control Register"
|
|
sif cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32H742*")||cpuis("STM32H750*")
|
|
bitfld.long 0x0C 21. " RBS ,Red blue swap" "Regular,Swap"
|
|
bitfld.long 0x0C 20. " AI ,Alpha inverted" "Regular,Inverted"
|
|
bitfld.long 0x0C 8. " SB ,Swap bytes" "Regular,Swapped"
|
|
newline
|
|
elif cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32L496*")||cpuis("STM32L4A6*")
|
|
bitfld.long 0x0C 21. " RBS ,Red blue swap" "Regular,Swap"
|
|
bitfld.long 0x0C 20. " AI ,Alpha inverted" "Regular,Inverted"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0C 0.--2. " CM ,Color mode" "ARGB8888,RGB888,RGB565,ARGB1555,ARGB4444,?..."
|
|
if (((per.l((ad:0x4002B000+0x34))&0x07))==0x00)
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "OCOLR,DMA2D Output Color Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA ,Alpha value"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED ,Red value"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN ,Green value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE ,Blue value"
|
|
elif (((per.l((ad:0x4002B000+0x34))&0x07))==0x01)
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "OCOLR,DMA2D Output Color Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED ,Red value"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN ,Green value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE ,Blue value"
|
|
elif (((per.l((ad:0x4002B000+0x34))&0x07))==0x02)
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "OCOLR,DMA2D Output Color Register"
|
|
bitfld.long 0x00 11.--15. " RED ,Red value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--10. " GREEN ,Green value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--4. " BLUE ,Blue value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
elif (((per.l((ad:0x4002B000+0x34))&0x07))==0x03)
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "OCOLR,DMA2D Output Color Register"
|
|
bitfld.long 0x00 15. " ALPHA ,Alpha value" "0,1"
|
|
bitfld.long 0x00 10.--14. " RED ,Red value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. " GREEN ,Green value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " BLUE ,Blue value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
elif (((per.l((ad:0x4002B000+0x34))&0x07))==0x04)
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "OCOLR,DMA2D Output Color Register"
|
|
bitfld.long 0x00 12.--15. " ALPHA ,Alpha value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " RED ,Red value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " GREEN ,Green value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " BLUE ,Blue value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "OCOLR,DMA2D Output Color Register"
|
|
endif
|
|
group.long 0x3C++0x0F
|
|
line.long 0x00 "OMAR,DMA2D Output Memory Address Register"
|
|
line.long 0x04 "OOR,DMA2D Output Offset Register"
|
|
hexmask.long.word 0x04 0.--13. 0x01 " LO ,Line offset"
|
|
line.long 0x08 "NLR,DMA2D Number Of Line Register"
|
|
hexmask.long.word 0x08 16.--29. 1. " PL ,Pixel per lines"
|
|
hexmask.long.word 0x08 0.--15. 1. " NL ,Number of lines"
|
|
line.long 0x0C "LWR,DMA2D Line Watermark Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " LW ,Line watermark"
|
|
endif
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "AMTCR,DMA2D AHB Master Timer Configuration Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DT ,Dead time"
|
|
bitfld.long 0x00 0. " EN ,Enable dead time functionality" "Disabled,Enabled"
|
|
sif cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32H742*")||cpuis("STM32H750*")
|
|
tree "DMA2D Foreground CLUT"
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "FGCLUT0 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA0 ,Alpha0 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED0 ,Red0 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN0 ,Green0 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE0 ,Blue0 "
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "FGCLUT1 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA1 ,Alpha1 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED1 ,Red1 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN1 ,Green1 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE1 ,Blue1 "
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "FGCLUT2 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA2 ,Alpha2 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED2 ,Red2 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN2 ,Green2 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE2 ,Blue2 "
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "FGCLUT3 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA3 ,Alpha3 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED3 ,Red3 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN3 ,Green3 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE3 ,Blue3 "
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "FGCLUT4 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA4 ,Alpha4 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED4 ,Red4 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN4 ,Green4 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE4 ,Blue4 "
|
|
group.long 0x414++0x03
|
|
line.long 0x00 "FGCLUT5 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA5 ,Alpha5 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED5 ,Red5 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN5 ,Green5 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE5 ,Blue5 "
|
|
group.long 0x418++0x03
|
|
line.long 0x00 "FGCLUT6 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA6 ,Alpha6 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED6 ,Red6 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN6 ,Green6 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE6 ,Blue6 "
|
|
group.long 0x41C++0x03
|
|
line.long 0x00 "FGCLUT7 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA7 ,Alpha7 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED7 ,Red7 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN7 ,Green7 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE7 ,Blue7 "
|
|
group.long 0x420++0x03
|
|
line.long 0x00 "FGCLUT8 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA8 ,Alpha8 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED8 ,Red8 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN8 ,Green8 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE8 ,Blue8 "
|
|
group.long 0x424++0x03
|
|
line.long 0x00 "FGCLUT9 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA9 ,Alpha9 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED9 ,Red9 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN9 ,Green9 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE9 ,Blue9 "
|
|
group.long 0x428++0x03
|
|
line.long 0x00 "FGCLUT10 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA10 ,Alpha10 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED10 ,Red10 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN10 ,Green10 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE10 ,Blue10 "
|
|
group.long 0x42C++0x03
|
|
line.long 0x00 "FGCLUT11 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA11 ,Alpha11 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED11 ,Red11 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN11 ,Green11 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE11 ,Blue11 "
|
|
group.long 0x430++0x03
|
|
line.long 0x00 "FGCLUT12 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA12 ,Alpha12 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED12 ,Red12 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN12 ,Green12 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE12 ,Blue12 "
|
|
group.long 0x434++0x03
|
|
line.long 0x00 "FGCLUT13 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA13 ,Alpha13 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED13 ,Red13 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN13 ,Green13 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE13 ,Blue13 "
|
|
group.long 0x438++0x03
|
|
line.long 0x00 "FGCLUT14 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA14 ,Alpha14 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED14 ,Red14 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN14 ,Green14 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE14 ,Blue14 "
|
|
group.long 0x43C++0x03
|
|
line.long 0x00 "FGCLUT15 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA15 ,Alpha15 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED15 ,Red15 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN15 ,Green15 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE15 ,Blue15 "
|
|
group.long 0x440++0x03
|
|
line.long 0x00 "FGCLUT16 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA16 ,Alpha16 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED16 ,Red16 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN16 ,Green16 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE16 ,Blue16 "
|
|
group.long 0x444++0x03
|
|
line.long 0x00 "FGCLUT17 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA17 ,Alpha17 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED17 ,Red17 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN17 ,Green17 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE17 ,Blue17 "
|
|
group.long 0x448++0x03
|
|
line.long 0x00 "FGCLUT18 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA18 ,Alpha18 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED18 ,Red18 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN18 ,Green18 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE18 ,Blue18 "
|
|
group.long 0x44C++0x03
|
|
line.long 0x00 "FGCLUT19 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA19 ,Alpha19 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED19 ,Red19 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN19 ,Green19 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE19 ,Blue19 "
|
|
group.long 0x450++0x03
|
|
line.long 0x00 "FGCLUT20 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA20 ,Alpha20 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED20 ,Red20 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN20 ,Green20 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE20 ,Blue20 "
|
|
group.long 0x454++0x03
|
|
line.long 0x00 "FGCLUT21 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA21 ,Alpha21 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED21 ,Red21 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN21 ,Green21 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE21 ,Blue21 "
|
|
group.long 0x458++0x03
|
|
line.long 0x00 "FGCLUT22 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA22 ,Alpha22 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED22 ,Red22 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN22 ,Green22 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE22 ,Blue22 "
|
|
group.long 0x45C++0x03
|
|
line.long 0x00 "FGCLUT23 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA23 ,Alpha23 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED23 ,Red23 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN23 ,Green23 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE23 ,Blue23 "
|
|
group.long 0x460++0x03
|
|
line.long 0x00 "FGCLUT24 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA24 ,Alpha24 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED24 ,Red24 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN24 ,Green24 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE24 ,Blue24 "
|
|
group.long 0x464++0x03
|
|
line.long 0x00 "FGCLUT25 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA25 ,Alpha25 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED25 ,Red25 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN25 ,Green25 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE25 ,Blue25 "
|
|
group.long 0x468++0x03
|
|
line.long 0x00 "FGCLUT26 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA26 ,Alpha26 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED26 ,Red26 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN26 ,Green26 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE26 ,Blue26 "
|
|
group.long 0x46C++0x03
|
|
line.long 0x00 "FGCLUT27 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA27 ,Alpha27 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED27 ,Red27 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN27 ,Green27 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE27 ,Blue27 "
|
|
group.long 0x470++0x03
|
|
line.long 0x00 "FGCLUT28 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA28 ,Alpha28 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED28 ,Red28 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN28 ,Green28 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE28 ,Blue28 "
|
|
group.long 0x474++0x03
|
|
line.long 0x00 "FGCLUT29 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA29 ,Alpha29 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED29 ,Red29 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN29 ,Green29 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE29 ,Blue29 "
|
|
group.long 0x478++0x03
|
|
line.long 0x00 "FGCLUT30 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA30 ,Alpha30 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED30 ,Red30 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN30 ,Green30 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE30 ,Blue30 "
|
|
group.long 0x47C++0x03
|
|
line.long 0x00 "FGCLUT31 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA31 ,Alpha31 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED31 ,Red31 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN31 ,Green31 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE31 ,Blue31 "
|
|
group.long 0x480++0x03
|
|
line.long 0x00 "FGCLUT32 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA32 ,Alpha32 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED32 ,Red32 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN32 ,Green32 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE32 ,Blue32 "
|
|
group.long 0x484++0x03
|
|
line.long 0x00 "FGCLUT33 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA33 ,Alpha33 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED33 ,Red33 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN33 ,Green33 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE33 ,Blue33 "
|
|
group.long 0x488++0x03
|
|
line.long 0x00 "FGCLUT34 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA34 ,Alpha34 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED34 ,Red34 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN34 ,Green34 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE34 ,Blue34 "
|
|
group.long 0x48C++0x03
|
|
line.long 0x00 "FGCLUT35 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA35 ,Alpha35 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED35 ,Red35 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN35 ,Green35 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE35 ,Blue35 "
|
|
group.long 0x490++0x03
|
|
line.long 0x00 "FGCLUT36 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA36 ,Alpha36 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED36 ,Red36 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN36 ,Green36 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE36 ,Blue36 "
|
|
group.long 0x494++0x03
|
|
line.long 0x00 "FGCLUT37 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA37 ,Alpha37 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED37 ,Red37 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN37 ,Green37 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE37 ,Blue37 "
|
|
group.long 0x498++0x03
|
|
line.long 0x00 "FGCLUT38 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA38 ,Alpha38 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED38 ,Red38 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN38 ,Green38 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE38 ,Blue38 "
|
|
group.long 0x49C++0x03
|
|
line.long 0x00 "FGCLUT39 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA39 ,Alpha39 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED39 ,Red39 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN39 ,Green39 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE39 ,Blue39 "
|
|
group.long 0x4A0++0x03
|
|
line.long 0x00 "FGCLUT40 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA40 ,Alpha40 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED40 ,Red40 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN40 ,Green40 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE40 ,Blue40 "
|
|
group.long 0x4A4++0x03
|
|
line.long 0x00 "FGCLUT41 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA41 ,Alpha41 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED41 ,Red41 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN41 ,Green41 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE41 ,Blue41 "
|
|
group.long 0x4A8++0x03
|
|
line.long 0x00 "FGCLUT42 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA42 ,Alpha42 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED42 ,Red42 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN42 ,Green42 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE42 ,Blue42 "
|
|
group.long 0x4AC++0x03
|
|
line.long 0x00 "FGCLUT43 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA43 ,Alpha43 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED43 ,Red43 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN43 ,Green43 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE43 ,Blue43 "
|
|
group.long 0x4B0++0x03
|
|
line.long 0x00 "FGCLUT44 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA44 ,Alpha44 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED44 ,Red44 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN44 ,Green44 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE44 ,Blue44 "
|
|
group.long 0x4B4++0x03
|
|
line.long 0x00 "FGCLUT45 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA45 ,Alpha45 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED45 ,Red45 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN45 ,Green45 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE45 ,Blue45 "
|
|
group.long 0x4B8++0x03
|
|
line.long 0x00 "FGCLUT46 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA46 ,Alpha46 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED46 ,Red46 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN46 ,Green46 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE46 ,Blue46 "
|
|
group.long 0x4BC++0x03
|
|
line.long 0x00 "FGCLUT47 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA47 ,Alpha47 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED47 ,Red47 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN47 ,Green47 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE47 ,Blue47 "
|
|
group.long 0x4C0++0x03
|
|
line.long 0x00 "FGCLUT48 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA48 ,Alpha48 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED48 ,Red48 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN48 ,Green48 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE48 ,Blue48 "
|
|
group.long 0x4C4++0x03
|
|
line.long 0x00 "FGCLUT49 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA49 ,Alpha49 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED49 ,Red49 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN49 ,Green49 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE49 ,Blue49 "
|
|
group.long 0x4C8++0x03
|
|
line.long 0x00 "FGCLUT50 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA50 ,Alpha50 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED50 ,Red50 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN50 ,Green50 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE50 ,Blue50 "
|
|
group.long 0x4CC++0x03
|
|
line.long 0x00 "FGCLUT51 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA51 ,Alpha51 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED51 ,Red51 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN51 ,Green51 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE51 ,Blue51 "
|
|
group.long 0x4D0++0x03
|
|
line.long 0x00 "FGCLUT52 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA52 ,Alpha52 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED52 ,Red52 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN52 ,Green52 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE52 ,Blue52 "
|
|
group.long 0x4D4++0x03
|
|
line.long 0x00 "FGCLUT53 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA53 ,Alpha53 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED53 ,Red53 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN53 ,Green53 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE53 ,Blue53 "
|
|
group.long 0x4D8++0x03
|
|
line.long 0x00 "FGCLUT54 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA54 ,Alpha54 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED54 ,Red54 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN54 ,Green54 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE54 ,Blue54 "
|
|
group.long 0x4DC++0x03
|
|
line.long 0x00 "FGCLUT55 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA55 ,Alpha55 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED55 ,Red55 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN55 ,Green55 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE55 ,Blue55 "
|
|
group.long 0x4E0++0x03
|
|
line.long 0x00 "FGCLUT56 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA56 ,Alpha56 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED56 ,Red56 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN56 ,Green56 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE56 ,Blue56 "
|
|
group.long 0x4E4++0x03
|
|
line.long 0x00 "FGCLUT57 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA57 ,Alpha57 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED57 ,Red57 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN57 ,Green57 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE57 ,Blue57 "
|
|
group.long 0x4E8++0x03
|
|
line.long 0x00 "FGCLUT58 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA58 ,Alpha58 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED58 ,Red58 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN58 ,Green58 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE58 ,Blue58 "
|
|
group.long 0x4EC++0x03
|
|
line.long 0x00 "FGCLUT59 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA59 ,Alpha59 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED59 ,Red59 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN59 ,Green59 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE59 ,Blue59 "
|
|
group.long 0x4F0++0x03
|
|
line.long 0x00 "FGCLUT60 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA60 ,Alpha60 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED60 ,Red60 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN60 ,Green60 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE60 ,Blue60 "
|
|
group.long 0x4F4++0x03
|
|
line.long 0x00 "FGCLUT61 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA61 ,Alpha61 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED61 ,Red61 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN61 ,Green61 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE61 ,Blue61 "
|
|
group.long 0x4F8++0x03
|
|
line.long 0x00 "FGCLUT62 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA62 ,Alpha62 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED62 ,Red62 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN62 ,Green62 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE62 ,Blue62 "
|
|
group.long 0x4FC++0x03
|
|
line.long 0x00 "FGCLUT63 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA63 ,Alpha63 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED63 ,Red63 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN63 ,Green63 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE63 ,Blue63 "
|
|
group.long 0x500++0x03
|
|
line.long 0x00 "FGCLUT64 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA64 ,Alpha64 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED64 ,Red64 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN64 ,Green64 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE64 ,Blue64 "
|
|
group.long 0x504++0x03
|
|
line.long 0x00 "FGCLUT65 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA65 ,Alpha65 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED65 ,Red65 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN65 ,Green65 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE65 ,Blue65 "
|
|
group.long 0x508++0x03
|
|
line.long 0x00 "FGCLUT66 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA66 ,Alpha66 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED66 ,Red66 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN66 ,Green66 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE66 ,Blue66 "
|
|
group.long 0x50C++0x03
|
|
line.long 0x00 "FGCLUT67 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA67 ,Alpha67 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED67 ,Red67 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN67 ,Green67 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE67 ,Blue67 "
|
|
group.long 0x510++0x03
|
|
line.long 0x00 "FGCLUT68 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA68 ,Alpha68 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED68 ,Red68 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN68 ,Green68 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE68 ,Blue68 "
|
|
group.long 0x514++0x03
|
|
line.long 0x00 "FGCLUT69 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA69 ,Alpha69 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED69 ,Red69 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN69 ,Green69 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE69 ,Blue69 "
|
|
group.long 0x518++0x03
|
|
line.long 0x00 "FGCLUT70 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA70 ,Alpha70 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED70 ,Red70 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN70 ,Green70 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE70 ,Blue70 "
|
|
group.long 0x51C++0x03
|
|
line.long 0x00 "FGCLUT71 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA71 ,Alpha71 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED71 ,Red71 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN71 ,Green71 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE71 ,Blue71 "
|
|
group.long 0x520++0x03
|
|
line.long 0x00 "FGCLUT72 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA72 ,Alpha72 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED72 ,Red72 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN72 ,Green72 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE72 ,Blue72 "
|
|
group.long 0x524++0x03
|
|
line.long 0x00 "FGCLUT73 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA73 ,Alpha73 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED73 ,Red73 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN73 ,Green73 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE73 ,Blue73 "
|
|
group.long 0x528++0x03
|
|
line.long 0x00 "FGCLUT74 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA74 ,Alpha74 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED74 ,Red74 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN74 ,Green74 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE74 ,Blue74 "
|
|
group.long 0x52C++0x03
|
|
line.long 0x00 "FGCLUT75 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA75 ,Alpha75 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED75 ,Red75 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN75 ,Green75 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE75 ,Blue75 "
|
|
group.long 0x530++0x03
|
|
line.long 0x00 "FGCLUT76 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA76 ,Alpha76 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED76 ,Red76 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN76 ,Green76 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE76 ,Blue76 "
|
|
group.long 0x534++0x03
|
|
line.long 0x00 "FGCLUT77 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA77 ,Alpha77 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED77 ,Red77 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN77 ,Green77 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE77 ,Blue77 "
|
|
group.long 0x538++0x03
|
|
line.long 0x00 "FGCLUT78 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA78 ,Alpha78 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED78 ,Red78 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN78 ,Green78 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE78 ,Blue78 "
|
|
group.long 0x53C++0x03
|
|
line.long 0x00 "FGCLUT79 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA79 ,Alpha79 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED79 ,Red79 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN79 ,Green79 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE79 ,Blue79 "
|
|
group.long 0x540++0x03
|
|
line.long 0x00 "FGCLUT80 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA80 ,Alpha80 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED80 ,Red80 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN80 ,Green80 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE80 ,Blue80 "
|
|
group.long 0x544++0x03
|
|
line.long 0x00 "FGCLUT81 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA81 ,Alpha81 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED81 ,Red81 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN81 ,Green81 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE81 ,Blue81 "
|
|
group.long 0x548++0x03
|
|
line.long 0x00 "FGCLUT82 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA82 ,Alpha82 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED82 ,Red82 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN82 ,Green82 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE82 ,Blue82 "
|
|
group.long 0x54C++0x03
|
|
line.long 0x00 "FGCLUT83 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA83 ,Alpha83 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED83 ,Red83 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN83 ,Green83 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE83 ,Blue83 "
|
|
group.long 0x550++0x03
|
|
line.long 0x00 "FGCLUT84 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA84 ,Alpha84 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED84 ,Red84 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN84 ,Green84 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE84 ,Blue84 "
|
|
group.long 0x554++0x03
|
|
line.long 0x00 "FGCLUT85 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA85 ,Alpha85 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED85 ,Red85 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN85 ,Green85 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE85 ,Blue85 "
|
|
group.long 0x558++0x03
|
|
line.long 0x00 "FGCLUT86 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA86 ,Alpha86 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED86 ,Red86 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN86 ,Green86 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE86 ,Blue86 "
|
|
group.long 0x55C++0x03
|
|
line.long 0x00 "FGCLUT87 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA87 ,Alpha87 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED87 ,Red87 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN87 ,Green87 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE87 ,Blue87 "
|
|
group.long 0x560++0x03
|
|
line.long 0x00 "FGCLUT88 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA88 ,Alpha88 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED88 ,Red88 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN88 ,Green88 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE88 ,Blue88 "
|
|
group.long 0x564++0x03
|
|
line.long 0x00 "FGCLUT89 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA89 ,Alpha89 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED89 ,Red89 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN89 ,Green89 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE89 ,Blue89 "
|
|
group.long 0x568++0x03
|
|
line.long 0x00 "FGCLUT90 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA90 ,Alpha90 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED90 ,Red90 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN90 ,Green90 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE90 ,Blue90 "
|
|
group.long 0x56C++0x03
|
|
line.long 0x00 "FGCLUT91 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA91 ,Alpha91 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED91 ,Red91 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN91 ,Green91 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE91 ,Blue91 "
|
|
group.long 0x570++0x03
|
|
line.long 0x00 "FGCLUT92 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA92 ,Alpha92 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED92 ,Red92 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN92 ,Green92 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE92 ,Blue92 "
|
|
group.long 0x574++0x03
|
|
line.long 0x00 "FGCLUT93 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA93 ,Alpha93 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED93 ,Red93 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN93 ,Green93 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE93 ,Blue93 "
|
|
group.long 0x578++0x03
|
|
line.long 0x00 "FGCLUT94 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA94 ,Alpha94 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED94 ,Red94 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN94 ,Green94 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE94 ,Blue94 "
|
|
group.long 0x57C++0x03
|
|
line.long 0x00 "FGCLUT95 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA95 ,Alpha95 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED95 ,Red95 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN95 ,Green95 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE95 ,Blue95 "
|
|
group.long 0x580++0x03
|
|
line.long 0x00 "FGCLUT96 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA96 ,Alpha96 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED96 ,Red96 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN96 ,Green96 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE96 ,Blue96 "
|
|
group.long 0x584++0x03
|
|
line.long 0x00 "FGCLUT97 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA97 ,Alpha97 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED97 ,Red97 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN97 ,Green97 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE97 ,Blue97 "
|
|
group.long 0x588++0x03
|
|
line.long 0x00 "FGCLUT98 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA98 ,Alpha98 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED98 ,Red98 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN98 ,Green98 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE98 ,Blue98 "
|
|
group.long 0x58C++0x03
|
|
line.long 0x00 "FGCLUT99 ,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA99 ,Alpha99 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED99 ,Red99 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN99 ,Green99 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE99 ,Blue99 "
|
|
group.long 0x590++0x03
|
|
line.long 0x00 "FGCLUT100,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA100 ,Alpha100"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED100 ,Red100"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN100 ,Green100"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE100 ,Blue100"
|
|
group.long 0x594++0x03
|
|
line.long 0x00 "FGCLUT101,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA101 ,Alpha101"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED101 ,Red101"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN101 ,Green101"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE101 ,Blue101"
|
|
group.long 0x598++0x03
|
|
line.long 0x00 "FGCLUT102,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA102 ,Alpha102"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED102 ,Red102"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN102 ,Green102"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE102 ,Blue102"
|
|
group.long 0x59C++0x03
|
|
line.long 0x00 "FGCLUT103,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA103 ,Alpha103"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED103 ,Red103"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN103 ,Green103"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE103 ,Blue103"
|
|
group.long 0x5A0++0x03
|
|
line.long 0x00 "FGCLUT104,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA104 ,Alpha104"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED104 ,Red104"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN104 ,Green104"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE104 ,Blue104"
|
|
group.long 0x5A4++0x03
|
|
line.long 0x00 "FGCLUT105,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA105 ,Alpha105"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED105 ,Red105"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN105 ,Green105"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE105 ,Blue105"
|
|
group.long 0x5A8++0x03
|
|
line.long 0x00 "FGCLUT106,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA106 ,Alpha106"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED106 ,Red106"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN106 ,Green106"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE106 ,Blue106"
|
|
group.long 0x5AC++0x03
|
|
line.long 0x00 "FGCLUT107,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA107 ,Alpha107"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED107 ,Red107"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN107 ,Green107"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE107 ,Blue107"
|
|
group.long 0x5B0++0x03
|
|
line.long 0x00 "FGCLUT108,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA108 ,Alpha108"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED108 ,Red108"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN108 ,Green108"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE108 ,Blue108"
|
|
group.long 0x5B4++0x03
|
|
line.long 0x00 "FGCLUT109,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA109 ,Alpha109"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED109 ,Red109"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN109 ,Green109"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE109 ,Blue109"
|
|
group.long 0x5B8++0x03
|
|
line.long 0x00 "FGCLUT110,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA110 ,Alpha110"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED110 ,Red110"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN110 ,Green110"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE110 ,Blue110"
|
|
group.long 0x5BC++0x03
|
|
line.long 0x00 "FGCLUT111,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA111 ,Alpha111"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED111 ,Red111"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN111 ,Green111"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE111 ,Blue111"
|
|
group.long 0x5C0++0x03
|
|
line.long 0x00 "FGCLUT112,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA112 ,Alpha112"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED112 ,Red112"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN112 ,Green112"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE112 ,Blue112"
|
|
group.long 0x5C4++0x03
|
|
line.long 0x00 "FGCLUT113,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA113 ,Alpha113"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED113 ,Red113"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN113 ,Green113"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE113 ,Blue113"
|
|
group.long 0x5C8++0x03
|
|
line.long 0x00 "FGCLUT114,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA114 ,Alpha114"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED114 ,Red114"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN114 ,Green114"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE114 ,Blue114"
|
|
group.long 0x5CC++0x03
|
|
line.long 0x00 "FGCLUT115,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA115 ,Alpha115"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED115 ,Red115"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN115 ,Green115"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE115 ,Blue115"
|
|
group.long 0x5D0++0x03
|
|
line.long 0x00 "FGCLUT116,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA116 ,Alpha116"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED116 ,Red116"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN116 ,Green116"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE116 ,Blue116"
|
|
group.long 0x5D4++0x03
|
|
line.long 0x00 "FGCLUT117,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA117 ,Alpha117"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED117 ,Red117"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN117 ,Green117"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE117 ,Blue117"
|
|
group.long 0x5D8++0x03
|
|
line.long 0x00 "FGCLUT118,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA118 ,Alpha118"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED118 ,Red118"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN118 ,Green118"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE118 ,Blue118"
|
|
group.long 0x5DC++0x03
|
|
line.long 0x00 "FGCLUT119,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA119 ,Alpha119"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED119 ,Red119"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN119 ,Green119"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE119 ,Blue119"
|
|
group.long 0x5E0++0x03
|
|
line.long 0x00 "FGCLUT120,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA120 ,Alpha120"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED120 ,Red120"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN120 ,Green120"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE120 ,Blue120"
|
|
group.long 0x5E4++0x03
|
|
line.long 0x00 "FGCLUT121,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA121 ,Alpha121"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED121 ,Red121"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN121 ,Green121"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE121 ,Blue121"
|
|
group.long 0x5E8++0x03
|
|
line.long 0x00 "FGCLUT122,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA122 ,Alpha122"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED122 ,Red122"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN122 ,Green122"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE122 ,Blue122"
|
|
group.long 0x5EC++0x03
|
|
line.long 0x00 "FGCLUT123,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA123 ,Alpha123"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED123 ,Red123"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN123 ,Green123"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE123 ,Blue123"
|
|
group.long 0x5F0++0x03
|
|
line.long 0x00 "FGCLUT124,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA124 ,Alpha124"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED124 ,Red124"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN124 ,Green124"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE124 ,Blue124"
|
|
group.long 0x5F4++0x03
|
|
line.long 0x00 "FGCLUT125,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA125 ,Alpha125"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED125 ,Red125"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN125 ,Green125"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE125 ,Blue125"
|
|
group.long 0x5F8++0x03
|
|
line.long 0x00 "FGCLUT126,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA126 ,Alpha126"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED126 ,Red126"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN126 ,Green126"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE126 ,Blue126"
|
|
group.long 0x5FC++0x03
|
|
line.long 0x00 "FGCLUT127,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA127 ,Alpha127"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED127 ,Red127"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN127 ,Green127"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE127 ,Blue127"
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "FGCLUT128,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA128 ,Alpha128"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED128 ,Red128"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN128 ,Green128"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE128 ,Blue128"
|
|
group.long 0x604++0x03
|
|
line.long 0x00 "FGCLUT129,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA129 ,Alpha129"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED129 ,Red129"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN129 ,Green129"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE129 ,Blue129"
|
|
group.long 0x608++0x03
|
|
line.long 0x00 "FGCLUT130,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA130 ,Alpha130"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED130 ,Red130"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN130 ,Green130"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE130 ,Blue130"
|
|
group.long 0x60C++0x03
|
|
line.long 0x00 "FGCLUT131,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA131 ,Alpha131"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED131 ,Red131"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN131 ,Green131"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE131 ,Blue131"
|
|
group.long 0x610++0x03
|
|
line.long 0x00 "FGCLUT132,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA132 ,Alpha132"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED132 ,Red132"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN132 ,Green132"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE132 ,Blue132"
|
|
group.long 0x614++0x03
|
|
line.long 0x00 "FGCLUT133,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA133 ,Alpha133"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED133 ,Red133"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN133 ,Green133"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE133 ,Blue133"
|
|
group.long 0x618++0x03
|
|
line.long 0x00 "FGCLUT134,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA134 ,Alpha134"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED134 ,Red134"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN134 ,Green134"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE134 ,Blue134"
|
|
group.long 0x61C++0x03
|
|
line.long 0x00 "FGCLUT135,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA135 ,Alpha135"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED135 ,Red135"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN135 ,Green135"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE135 ,Blue135"
|
|
group.long 0x620++0x03
|
|
line.long 0x00 "FGCLUT136,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA136 ,Alpha136"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED136 ,Red136"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN136 ,Green136"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE136 ,Blue136"
|
|
group.long 0x624++0x03
|
|
line.long 0x00 "FGCLUT137,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA137 ,Alpha137"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED137 ,Red137"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN137 ,Green137"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE137 ,Blue137"
|
|
group.long 0x628++0x03
|
|
line.long 0x00 "FGCLUT138,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA138 ,Alpha138"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED138 ,Red138"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN138 ,Green138"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE138 ,Blue138"
|
|
group.long 0x62C++0x03
|
|
line.long 0x00 "FGCLUT139,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA139 ,Alpha139"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED139 ,Red139"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN139 ,Green139"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE139 ,Blue139"
|
|
group.long 0x630++0x03
|
|
line.long 0x00 "FGCLUT140,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA140 ,Alpha140"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED140 ,Red140"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN140 ,Green140"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE140 ,Blue140"
|
|
group.long 0x634++0x03
|
|
line.long 0x00 "FGCLUT141,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA141 ,Alpha141"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED141 ,Red141"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN141 ,Green141"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE141 ,Blue141"
|
|
group.long 0x638++0x03
|
|
line.long 0x00 "FGCLUT142,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA142 ,Alpha142"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED142 ,Red142"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN142 ,Green142"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE142 ,Blue142"
|
|
group.long 0x63C++0x03
|
|
line.long 0x00 "FGCLUT143,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA143 ,Alpha143"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED143 ,Red143"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN143 ,Green143"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE143 ,Blue143"
|
|
group.long 0x640++0x03
|
|
line.long 0x00 "FGCLUT144,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA144 ,Alpha144"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED144 ,Red144"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN144 ,Green144"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE144 ,Blue144"
|
|
group.long 0x644++0x03
|
|
line.long 0x00 "FGCLUT145,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA145 ,Alpha145"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED145 ,Red145"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN145 ,Green145"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE145 ,Blue145"
|
|
group.long 0x648++0x03
|
|
line.long 0x00 "FGCLUT146,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA146 ,Alpha146"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED146 ,Red146"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN146 ,Green146"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE146 ,Blue146"
|
|
group.long 0x64C++0x03
|
|
line.long 0x00 "FGCLUT147,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA147 ,Alpha147"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED147 ,Red147"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN147 ,Green147"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE147 ,Blue147"
|
|
group.long 0x650++0x03
|
|
line.long 0x00 "FGCLUT148,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA148 ,Alpha148"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED148 ,Red148"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN148 ,Green148"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE148 ,Blue148"
|
|
group.long 0x654++0x03
|
|
line.long 0x00 "FGCLUT149,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA149 ,Alpha149"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED149 ,Red149"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN149 ,Green149"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE149 ,Blue149"
|
|
group.long 0x658++0x03
|
|
line.long 0x00 "FGCLUT150,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA150 ,Alpha150"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED150 ,Red150"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN150 ,Green150"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE150 ,Blue150"
|
|
group.long 0x65C++0x03
|
|
line.long 0x00 "FGCLUT151,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA151 ,Alpha151"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED151 ,Red151"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN151 ,Green151"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE151 ,Blue151"
|
|
group.long 0x660++0x03
|
|
line.long 0x00 "FGCLUT152,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA152 ,Alpha152"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED152 ,Red152"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN152 ,Green152"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE152 ,Blue152"
|
|
group.long 0x664++0x03
|
|
line.long 0x00 "FGCLUT153,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA153 ,Alpha153"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED153 ,Red153"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN153 ,Green153"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE153 ,Blue153"
|
|
group.long 0x668++0x03
|
|
line.long 0x00 "FGCLUT154,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA154 ,Alpha154"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED154 ,Red154"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN154 ,Green154"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE154 ,Blue154"
|
|
group.long 0x66C++0x03
|
|
line.long 0x00 "FGCLUT155,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA155 ,Alpha155"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED155 ,Red155"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN155 ,Green155"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE155 ,Blue155"
|
|
group.long 0x670++0x03
|
|
line.long 0x00 "FGCLUT156,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA156 ,Alpha156"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED156 ,Red156"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN156 ,Green156"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE156 ,Blue156"
|
|
group.long 0x674++0x03
|
|
line.long 0x00 "FGCLUT157,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA157 ,Alpha157"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED157 ,Red157"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN157 ,Green157"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE157 ,Blue157"
|
|
group.long 0x678++0x03
|
|
line.long 0x00 "FGCLUT158,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA158 ,Alpha158"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED158 ,Red158"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN158 ,Green158"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE158 ,Blue158"
|
|
group.long 0x67C++0x03
|
|
line.long 0x00 "FGCLUT159,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA159 ,Alpha159"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED159 ,Red159"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN159 ,Green159"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE159 ,Blue159"
|
|
group.long 0x680++0x03
|
|
line.long 0x00 "FGCLUT160,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA160 ,Alpha160"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED160 ,Red160"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN160 ,Green160"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE160 ,Blue160"
|
|
group.long 0x684++0x03
|
|
line.long 0x00 "FGCLUT161,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA161 ,Alpha161"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED161 ,Red161"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN161 ,Green161"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE161 ,Blue161"
|
|
group.long 0x688++0x03
|
|
line.long 0x00 "FGCLUT162,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA162 ,Alpha162"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED162 ,Red162"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN162 ,Green162"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE162 ,Blue162"
|
|
group.long 0x68C++0x03
|
|
line.long 0x00 "FGCLUT163,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA163 ,Alpha163"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED163 ,Red163"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN163 ,Green163"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE163 ,Blue163"
|
|
group.long 0x690++0x03
|
|
line.long 0x00 "FGCLUT164,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA164 ,Alpha164"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED164 ,Red164"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN164 ,Green164"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE164 ,Blue164"
|
|
group.long 0x694++0x03
|
|
line.long 0x00 "FGCLUT165,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA165 ,Alpha165"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED165 ,Red165"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN165 ,Green165"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE165 ,Blue165"
|
|
group.long 0x698++0x03
|
|
line.long 0x00 "FGCLUT166,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA166 ,Alpha166"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED166 ,Red166"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN166 ,Green166"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE166 ,Blue166"
|
|
group.long 0x69C++0x03
|
|
line.long 0x00 "FGCLUT167,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA167 ,Alpha167"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED167 ,Red167"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN167 ,Green167"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE167 ,Blue167"
|
|
group.long 0x6A0++0x03
|
|
line.long 0x00 "FGCLUT168,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA168 ,Alpha168"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED168 ,Red168"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN168 ,Green168"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE168 ,Blue168"
|
|
group.long 0x6A4++0x03
|
|
line.long 0x00 "FGCLUT169,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA169 ,Alpha169"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED169 ,Red169"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN169 ,Green169"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE169 ,Blue169"
|
|
group.long 0x6A8++0x03
|
|
line.long 0x00 "FGCLUT170,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA170 ,Alpha170"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED170 ,Red170"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN170 ,Green170"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE170 ,Blue170"
|
|
group.long 0x6AC++0x03
|
|
line.long 0x00 "FGCLUT171,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA171 ,Alpha171"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED171 ,Red171"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN171 ,Green171"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE171 ,Blue171"
|
|
group.long 0x6B0++0x03
|
|
line.long 0x00 "FGCLUT172,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA172 ,Alpha172"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED172 ,Red172"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN172 ,Green172"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE172 ,Blue172"
|
|
group.long 0x6B4++0x03
|
|
line.long 0x00 "FGCLUT173,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA173 ,Alpha173"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED173 ,Red173"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN173 ,Green173"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE173 ,Blue173"
|
|
group.long 0x6B8++0x03
|
|
line.long 0x00 "FGCLUT174,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA174 ,Alpha174"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED174 ,Red174"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN174 ,Green174"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE174 ,Blue174"
|
|
group.long 0x6BC++0x03
|
|
line.long 0x00 "FGCLUT175,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA175 ,Alpha175"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED175 ,Red175"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN175 ,Green175"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE175 ,Blue175"
|
|
group.long 0x6C0++0x03
|
|
line.long 0x00 "FGCLUT176,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA176 ,Alpha176"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED176 ,Red176"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN176 ,Green176"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE176 ,Blue176"
|
|
group.long 0x6C4++0x03
|
|
line.long 0x00 "FGCLUT177,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA177 ,Alpha177"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED177 ,Red177"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN177 ,Green177"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE177 ,Blue177"
|
|
group.long 0x6C8++0x03
|
|
line.long 0x00 "FGCLUT178,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA178 ,Alpha178"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED178 ,Red178"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN178 ,Green178"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE178 ,Blue178"
|
|
group.long 0x6CC++0x03
|
|
line.long 0x00 "FGCLUT179,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA179 ,Alpha179"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED179 ,Red179"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN179 ,Green179"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE179 ,Blue179"
|
|
group.long 0x6D0++0x03
|
|
line.long 0x00 "FGCLUT180,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA180 ,Alpha180"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED180 ,Red180"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN180 ,Green180"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE180 ,Blue180"
|
|
group.long 0x6D4++0x03
|
|
line.long 0x00 "FGCLUT181,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA181 ,Alpha181"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED181 ,Red181"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN181 ,Green181"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE181 ,Blue181"
|
|
group.long 0x6D8++0x03
|
|
line.long 0x00 "FGCLUT182,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA182 ,Alpha182"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED182 ,Red182"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN182 ,Green182"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE182 ,Blue182"
|
|
group.long 0x6DC++0x03
|
|
line.long 0x00 "FGCLUT183,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA183 ,Alpha183"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED183 ,Red183"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN183 ,Green183"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE183 ,Blue183"
|
|
group.long 0x6E0++0x03
|
|
line.long 0x00 "FGCLUT184,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA184 ,Alpha184"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED184 ,Red184"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN184 ,Green184"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE184 ,Blue184"
|
|
group.long 0x6E4++0x03
|
|
line.long 0x00 "FGCLUT185,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA185 ,Alpha185"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED185 ,Red185"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN185 ,Green185"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE185 ,Blue185"
|
|
group.long 0x6E8++0x03
|
|
line.long 0x00 "FGCLUT186,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA186 ,Alpha186"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED186 ,Red186"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN186 ,Green186"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE186 ,Blue186"
|
|
group.long 0x6EC++0x03
|
|
line.long 0x00 "FGCLUT187,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA187 ,Alpha187"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED187 ,Red187"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN187 ,Green187"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE187 ,Blue187"
|
|
group.long 0x6F0++0x03
|
|
line.long 0x00 "FGCLUT188,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA188 ,Alpha188"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED188 ,Red188"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN188 ,Green188"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE188 ,Blue188"
|
|
group.long 0x6F4++0x03
|
|
line.long 0x00 "FGCLUT189,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA189 ,Alpha189"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED189 ,Red189"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN189 ,Green189"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE189 ,Blue189"
|
|
group.long 0x6F8++0x03
|
|
line.long 0x00 "FGCLUT190,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA190 ,Alpha190"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED190 ,Red190"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN190 ,Green190"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE190 ,Blue190"
|
|
group.long 0x6FC++0x03
|
|
line.long 0x00 "FGCLUT191,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA191 ,Alpha191"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED191 ,Red191"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN191 ,Green191"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE191 ,Blue191"
|
|
group.long 0x700++0x03
|
|
line.long 0x00 "FGCLUT192,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA192 ,Alpha192"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED192 ,Red192"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN192 ,Green192"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE192 ,Blue192"
|
|
group.long 0x704++0x03
|
|
line.long 0x00 "FGCLUT193,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA193 ,Alpha193"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED193 ,Red193"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN193 ,Green193"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE193 ,Blue193"
|
|
group.long 0x708++0x03
|
|
line.long 0x00 "FGCLUT194,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA194 ,Alpha194"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED194 ,Red194"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN194 ,Green194"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE194 ,Blue194"
|
|
group.long 0x70C++0x03
|
|
line.long 0x00 "FGCLUT195,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA195 ,Alpha195"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED195 ,Red195"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN195 ,Green195"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE195 ,Blue195"
|
|
group.long 0x710++0x03
|
|
line.long 0x00 "FGCLUT196,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA196 ,Alpha196"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED196 ,Red196"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN196 ,Green196"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE196 ,Blue196"
|
|
group.long 0x714++0x03
|
|
line.long 0x00 "FGCLUT197,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA197 ,Alpha197"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED197 ,Red197"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN197 ,Green197"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE197 ,Blue197"
|
|
group.long 0x718++0x03
|
|
line.long 0x00 "FGCLUT198,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA198 ,Alpha198"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED198 ,Red198"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN198 ,Green198"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE198 ,Blue198"
|
|
group.long 0x71C++0x03
|
|
line.long 0x00 "FGCLUT199,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA199 ,Alpha199"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED199 ,Red199"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN199 ,Green199"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE199 ,Blue199"
|
|
group.long 0x720++0x03
|
|
line.long 0x00 "FGCLUT200,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA200 ,Alpha200"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED200 ,Red200"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN200 ,Green200"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE200 ,Blue200"
|
|
group.long 0x724++0x03
|
|
line.long 0x00 "FGCLUT201,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA201 ,Alpha201"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED201 ,Red201"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN201 ,Green201"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE201 ,Blue201"
|
|
group.long 0x728++0x03
|
|
line.long 0x00 "FGCLUT202,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA202 ,Alpha202"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED202 ,Red202"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN202 ,Green202"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE202 ,Blue202"
|
|
group.long 0x72C++0x03
|
|
line.long 0x00 "FGCLUT203,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA203 ,Alpha203"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED203 ,Red203"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN203 ,Green203"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE203 ,Blue203"
|
|
group.long 0x730++0x03
|
|
line.long 0x00 "FGCLUT204,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA204 ,Alpha204"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED204 ,Red204"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN204 ,Green204"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE204 ,Blue204"
|
|
group.long 0x734++0x03
|
|
line.long 0x00 "FGCLUT205,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA205 ,Alpha205"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED205 ,Red205"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN205 ,Green205"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE205 ,Blue205"
|
|
group.long 0x738++0x03
|
|
line.long 0x00 "FGCLUT206,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA206 ,Alpha206"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED206 ,Red206"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN206 ,Green206"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE206 ,Blue206"
|
|
group.long 0x73C++0x03
|
|
line.long 0x00 "FGCLUT207,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA207 ,Alpha207"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED207 ,Red207"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN207 ,Green207"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE207 ,Blue207"
|
|
group.long 0x740++0x03
|
|
line.long 0x00 "FGCLUT208,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA208 ,Alpha208"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED208 ,Red208"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN208 ,Green208"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE208 ,Blue208"
|
|
group.long 0x744++0x03
|
|
line.long 0x00 "FGCLUT209,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA209 ,Alpha209"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED209 ,Red209"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN209 ,Green209"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE209 ,Blue209"
|
|
group.long 0x748++0x03
|
|
line.long 0x00 "FGCLUT210,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA210 ,Alpha210"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED210 ,Red210"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN210 ,Green210"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE210 ,Blue210"
|
|
group.long 0x74C++0x03
|
|
line.long 0x00 "FGCLUT211,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA211 ,Alpha211"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED211 ,Red211"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN211 ,Green211"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE211 ,Blue211"
|
|
group.long 0x750++0x03
|
|
line.long 0x00 "FGCLUT212,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA212 ,Alpha212"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED212 ,Red212"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN212 ,Green212"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE212 ,Blue212"
|
|
group.long 0x754++0x03
|
|
line.long 0x00 "FGCLUT213,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA213 ,Alpha213"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED213 ,Red213"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN213 ,Green213"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE213 ,Blue213"
|
|
group.long 0x758++0x03
|
|
line.long 0x00 "FGCLUT214,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA214 ,Alpha214"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED214 ,Red214"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN214 ,Green214"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE214 ,Blue214"
|
|
group.long 0x75C++0x03
|
|
line.long 0x00 "FGCLUT215,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA215 ,Alpha215"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED215 ,Red215"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN215 ,Green215"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE215 ,Blue215"
|
|
group.long 0x760++0x03
|
|
line.long 0x00 "FGCLUT216,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA216 ,Alpha216"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED216 ,Red216"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN216 ,Green216"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE216 ,Blue216"
|
|
group.long 0x764++0x03
|
|
line.long 0x00 "FGCLUT217,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA217 ,Alpha217"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED217 ,Red217"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN217 ,Green217"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE217 ,Blue217"
|
|
group.long 0x768++0x03
|
|
line.long 0x00 "FGCLUT218,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA218 ,Alpha218"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED218 ,Red218"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN218 ,Green218"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE218 ,Blue218"
|
|
group.long 0x76C++0x03
|
|
line.long 0x00 "FGCLUT219,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA219 ,Alpha219"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED219 ,Red219"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN219 ,Green219"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE219 ,Blue219"
|
|
group.long 0x770++0x03
|
|
line.long 0x00 "FGCLUT220,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA220 ,Alpha220"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED220 ,Red220"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN220 ,Green220"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE220 ,Blue220"
|
|
group.long 0x774++0x03
|
|
line.long 0x00 "FGCLUT221,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA221 ,Alpha221"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED221 ,Red221"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN221 ,Green221"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE221 ,Blue221"
|
|
group.long 0x778++0x03
|
|
line.long 0x00 "FGCLUT222,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA222 ,Alpha222"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED222 ,Red222"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN222 ,Green222"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE222 ,Blue222"
|
|
group.long 0x77C++0x03
|
|
line.long 0x00 "FGCLUT223,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA223 ,Alpha223"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED223 ,Red223"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN223 ,Green223"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE223 ,Blue223"
|
|
group.long 0x780++0x03
|
|
line.long 0x00 "FGCLUT224,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA224 ,Alpha224"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED224 ,Red224"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN224 ,Green224"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE224 ,Blue224"
|
|
group.long 0x784++0x03
|
|
line.long 0x00 "FGCLUT225,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA225 ,Alpha225"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED225 ,Red225"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN225 ,Green225"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE225 ,Blue225"
|
|
group.long 0x788++0x03
|
|
line.long 0x00 "FGCLUT226,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA226 ,Alpha226"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED226 ,Red226"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN226 ,Green226"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE226 ,Blue226"
|
|
group.long 0x78C++0x03
|
|
line.long 0x00 "FGCLUT227,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA227 ,Alpha227"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED227 ,Red227"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN227 ,Green227"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE227 ,Blue227"
|
|
group.long 0x790++0x03
|
|
line.long 0x00 "FGCLUT228,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA228 ,Alpha228"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED228 ,Red228"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN228 ,Green228"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE228 ,Blue228"
|
|
group.long 0x794++0x03
|
|
line.long 0x00 "FGCLUT229,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA229 ,Alpha229"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED229 ,Red229"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN229 ,Green229"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE229 ,Blue229"
|
|
group.long 0x798++0x03
|
|
line.long 0x00 "FGCLUT230,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA230 ,Alpha230"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED230 ,Red230"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN230 ,Green230"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE230 ,Blue230"
|
|
group.long 0x79C++0x03
|
|
line.long 0x00 "FGCLUT231,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA231 ,Alpha231"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED231 ,Red231"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN231 ,Green231"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE231 ,Blue231"
|
|
group.long 0x7A0++0x03
|
|
line.long 0x00 "FGCLUT232,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA232 ,Alpha232"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED232 ,Red232"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN232 ,Green232"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE232 ,Blue232"
|
|
group.long 0x7A4++0x03
|
|
line.long 0x00 "FGCLUT233,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA233 ,Alpha233"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED233 ,Red233"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN233 ,Green233"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE233 ,Blue233"
|
|
group.long 0x7A8++0x03
|
|
line.long 0x00 "FGCLUT234,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA234 ,Alpha234"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED234 ,Red234"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN234 ,Green234"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE234 ,Blue234"
|
|
group.long 0x7AC++0x03
|
|
line.long 0x00 "FGCLUT235,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA235 ,Alpha235"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED235 ,Red235"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN235 ,Green235"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE235 ,Blue235"
|
|
group.long 0x7B0++0x03
|
|
line.long 0x00 "FGCLUT236,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA236 ,Alpha236"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED236 ,Red236"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN236 ,Green236"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE236 ,Blue236"
|
|
group.long 0x7B4++0x03
|
|
line.long 0x00 "FGCLUT237,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA237 ,Alpha237"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED237 ,Red237"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN237 ,Green237"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE237 ,Blue237"
|
|
group.long 0x7B8++0x03
|
|
line.long 0x00 "FGCLUT238,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA238 ,Alpha238"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED238 ,Red238"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN238 ,Green238"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE238 ,Blue238"
|
|
group.long 0x7BC++0x03
|
|
line.long 0x00 "FGCLUT239,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA239 ,Alpha239"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED239 ,Red239"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN239 ,Green239"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE239 ,Blue239"
|
|
group.long 0x7C0++0x03
|
|
line.long 0x00 "FGCLUT240,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA240 ,Alpha240"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED240 ,Red240"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN240 ,Green240"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE240 ,Blue240"
|
|
group.long 0x7C4++0x03
|
|
line.long 0x00 "FGCLUT241,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA241 ,Alpha241"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED241 ,Red241"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN241 ,Green241"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE241 ,Blue241"
|
|
group.long 0x7C8++0x03
|
|
line.long 0x00 "FGCLUT242,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA242 ,Alpha242"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED242 ,Red242"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN242 ,Green242"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE242 ,Blue242"
|
|
group.long 0x7CC++0x03
|
|
line.long 0x00 "FGCLUT243,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA243 ,Alpha243"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED243 ,Red243"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN243 ,Green243"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE243 ,Blue243"
|
|
group.long 0x7D0++0x03
|
|
line.long 0x00 "FGCLUT244,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA244 ,Alpha244"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED244 ,Red244"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN244 ,Green244"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE244 ,Blue244"
|
|
group.long 0x7D4++0x03
|
|
line.long 0x00 "FGCLUT245,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA245 ,Alpha245"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED245 ,Red245"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN245 ,Green245"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE245 ,Blue245"
|
|
group.long 0x7D8++0x03
|
|
line.long 0x00 "FGCLUT246,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA246 ,Alpha246"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED246 ,Red246"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN246 ,Green246"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE246 ,Blue246"
|
|
group.long 0x7DC++0x03
|
|
line.long 0x00 "FGCLUT247,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA247 ,Alpha247"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED247 ,Red247"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN247 ,Green247"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE247 ,Blue247"
|
|
group.long 0x7E0++0x03
|
|
line.long 0x00 "FGCLUT248,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA248 ,Alpha248"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED248 ,Red248"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN248 ,Green248"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE248 ,Blue248"
|
|
group.long 0x7E4++0x03
|
|
line.long 0x00 "FGCLUT249,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA249 ,Alpha249"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED249 ,Red249"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN249 ,Green249"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE249 ,Blue249"
|
|
group.long 0x7E8++0x03
|
|
line.long 0x00 "FGCLUT250,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA250 ,Alpha250"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED250 ,Red250"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN250 ,Green250"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE250 ,Blue250"
|
|
group.long 0x7EC++0x03
|
|
line.long 0x00 "FGCLUT251,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA251 ,Alpha251"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED251 ,Red251"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN251 ,Green251"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE251 ,Blue251"
|
|
group.long 0x7F0++0x03
|
|
line.long 0x00 "FGCLUT252,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA252 ,Alpha252"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED252 ,Red252"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN252 ,Green252"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE252 ,Blue252"
|
|
group.long 0x7F4++0x03
|
|
line.long 0x00 "FGCLUT253,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA253 ,Alpha253"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED253 ,Red253"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN253 ,Green253"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE253 ,Blue253"
|
|
group.long 0x7F8++0x03
|
|
line.long 0x00 "FGCLUT254,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA254 ,Alpha254"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED254 ,Red254"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN254 ,Green254"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE254 ,Blue254"
|
|
group.long 0x7FC++0x03
|
|
line.long 0x00 "FGCLUT255,DMA2D Foreground CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA255 ,Alpha255"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED255 ,Red255"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN255 ,Green255"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE255 ,Blue255"
|
|
tree.end
|
|
tree "DMA2D Background CLUT"
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "BGCLUT0 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA0 ,Alpha0 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED0 ,Red0 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN0 ,Green0 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE0 ,Blue0 "
|
|
group.long 0x804++0x03
|
|
line.long 0x00 "BGCLUT1 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA1 ,Alpha1 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED1 ,Red1 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN1 ,Green1 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE1 ,Blue1 "
|
|
group.long 0x808++0x03
|
|
line.long 0x00 "BGCLUT2 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA2 ,Alpha2 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED2 ,Red2 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN2 ,Green2 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE2 ,Blue2 "
|
|
group.long 0x80C++0x03
|
|
line.long 0x00 "BGCLUT3 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA3 ,Alpha3 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED3 ,Red3 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN3 ,Green3 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE3 ,Blue3 "
|
|
group.long 0x810++0x03
|
|
line.long 0x00 "BGCLUT4 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA4 ,Alpha4 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED4 ,Red4 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN4 ,Green4 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE4 ,Blue4 "
|
|
group.long 0x814++0x03
|
|
line.long 0x00 "BGCLUT5 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA5 ,Alpha5 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED5 ,Red5 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN5 ,Green5 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE5 ,Blue5 "
|
|
group.long 0x818++0x03
|
|
line.long 0x00 "BGCLUT6 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA6 ,Alpha6 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED6 ,Red6 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN6 ,Green6 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE6 ,Blue6 "
|
|
group.long 0x81C++0x03
|
|
line.long 0x00 "BGCLUT7 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA7 ,Alpha7 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED7 ,Red7 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN7 ,Green7 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE7 ,Blue7 "
|
|
group.long 0x820++0x03
|
|
line.long 0x00 "BGCLUT8 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA8 ,Alpha8 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED8 ,Red8 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN8 ,Green8 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE8 ,Blue8 "
|
|
group.long 0x824++0x03
|
|
line.long 0x00 "BGCLUT9 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA9 ,Alpha9 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED9 ,Red9 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN9 ,Green9 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE9 ,Blue9 "
|
|
group.long 0x828++0x03
|
|
line.long 0x00 "BGCLUT10 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA10 ,Alpha10 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED10 ,Red10 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN10 ,Green10 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE10 ,Blue10 "
|
|
group.long 0x82C++0x03
|
|
line.long 0x00 "BGCLUT11 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA11 ,Alpha11 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED11 ,Red11 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN11 ,Green11 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE11 ,Blue11 "
|
|
group.long 0x830++0x03
|
|
line.long 0x00 "BGCLUT12 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA12 ,Alpha12 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED12 ,Red12 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN12 ,Green12 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE12 ,Blue12 "
|
|
group.long 0x834++0x03
|
|
line.long 0x00 "BGCLUT13 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA13 ,Alpha13 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED13 ,Red13 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN13 ,Green13 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE13 ,Blue13 "
|
|
group.long 0x838++0x03
|
|
line.long 0x00 "BGCLUT14 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA14 ,Alpha14 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED14 ,Red14 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN14 ,Green14 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE14 ,Blue14 "
|
|
group.long 0x83C++0x03
|
|
line.long 0x00 "BGCLUT15 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA15 ,Alpha15 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED15 ,Red15 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN15 ,Green15 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE15 ,Blue15 "
|
|
group.long 0x840++0x03
|
|
line.long 0x00 "BGCLUT16 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA16 ,Alpha16 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED16 ,Red16 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN16 ,Green16 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE16 ,Blue16 "
|
|
group.long 0x844++0x03
|
|
line.long 0x00 "BGCLUT17 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA17 ,Alpha17 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED17 ,Red17 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN17 ,Green17 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE17 ,Blue17 "
|
|
group.long 0x848++0x03
|
|
line.long 0x00 "BGCLUT18 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA18 ,Alpha18 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED18 ,Red18 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN18 ,Green18 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE18 ,Blue18 "
|
|
group.long 0x84C++0x03
|
|
line.long 0x00 "BGCLUT19 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA19 ,Alpha19 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED19 ,Red19 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN19 ,Green19 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE19 ,Blue19 "
|
|
group.long 0x850++0x03
|
|
line.long 0x00 "BGCLUT20 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA20 ,Alpha20 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED20 ,Red20 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN20 ,Green20 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE20 ,Blue20 "
|
|
group.long 0x854++0x03
|
|
line.long 0x00 "BGCLUT21 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA21 ,Alpha21 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED21 ,Red21 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN21 ,Green21 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE21 ,Blue21 "
|
|
group.long 0x858++0x03
|
|
line.long 0x00 "BGCLUT22 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA22 ,Alpha22 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED22 ,Red22 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN22 ,Green22 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE22 ,Blue22 "
|
|
group.long 0x85C++0x03
|
|
line.long 0x00 "BGCLUT23 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA23 ,Alpha23 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED23 ,Red23 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN23 ,Green23 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE23 ,Blue23 "
|
|
group.long 0x860++0x03
|
|
line.long 0x00 "BGCLUT24 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA24 ,Alpha24 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED24 ,Red24 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN24 ,Green24 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE24 ,Blue24 "
|
|
group.long 0x864++0x03
|
|
line.long 0x00 "BGCLUT25 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA25 ,Alpha25 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED25 ,Red25 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN25 ,Green25 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE25 ,Blue25 "
|
|
group.long 0x868++0x03
|
|
line.long 0x00 "BGCLUT26 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA26 ,Alpha26 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED26 ,Red26 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN26 ,Green26 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE26 ,Blue26 "
|
|
group.long 0x86C++0x03
|
|
line.long 0x00 "BGCLUT27 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA27 ,Alpha27 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED27 ,Red27 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN27 ,Green27 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE27 ,Blue27 "
|
|
group.long 0x870++0x03
|
|
line.long 0x00 "BGCLUT28 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA28 ,Alpha28 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED28 ,Red28 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN28 ,Green28 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE28 ,Blue28 "
|
|
group.long 0x874++0x03
|
|
line.long 0x00 "BGCLUT29 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA29 ,Alpha29 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED29 ,Red29 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN29 ,Green29 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE29 ,Blue29 "
|
|
group.long 0x878++0x03
|
|
line.long 0x00 "BGCLUT30 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA30 ,Alpha30 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED30 ,Red30 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN30 ,Green30 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE30 ,Blue30 "
|
|
group.long 0x87C++0x03
|
|
line.long 0x00 "BGCLUT31 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA31 ,Alpha31 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED31 ,Red31 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN31 ,Green31 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE31 ,Blue31 "
|
|
group.long 0x880++0x03
|
|
line.long 0x00 "BGCLUT32 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA32 ,Alpha32 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED32 ,Red32 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN32 ,Green32 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE32 ,Blue32 "
|
|
group.long 0x884++0x03
|
|
line.long 0x00 "BGCLUT33 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA33 ,Alpha33 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED33 ,Red33 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN33 ,Green33 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE33 ,Blue33 "
|
|
group.long 0x888++0x03
|
|
line.long 0x00 "BGCLUT34 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA34 ,Alpha34 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED34 ,Red34 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN34 ,Green34 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE34 ,Blue34 "
|
|
group.long 0x88C++0x03
|
|
line.long 0x00 "BGCLUT35 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA35 ,Alpha35 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED35 ,Red35 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN35 ,Green35 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE35 ,Blue35 "
|
|
group.long 0x890++0x03
|
|
line.long 0x00 "BGCLUT36 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA36 ,Alpha36 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED36 ,Red36 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN36 ,Green36 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE36 ,Blue36 "
|
|
group.long 0x894++0x03
|
|
line.long 0x00 "BGCLUT37 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA37 ,Alpha37 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED37 ,Red37 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN37 ,Green37 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE37 ,Blue37 "
|
|
group.long 0x898++0x03
|
|
line.long 0x00 "BGCLUT38 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA38 ,Alpha38 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED38 ,Red38 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN38 ,Green38 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE38 ,Blue38 "
|
|
group.long 0x89C++0x03
|
|
line.long 0x00 "BGCLUT39 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA39 ,Alpha39 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED39 ,Red39 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN39 ,Green39 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE39 ,Blue39 "
|
|
group.long 0x8A0++0x03
|
|
line.long 0x00 "BGCLUT40 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA40 ,Alpha40 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED40 ,Red40 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN40 ,Green40 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE40 ,Blue40 "
|
|
group.long 0x8A4++0x03
|
|
line.long 0x00 "BGCLUT41 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA41 ,Alpha41 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED41 ,Red41 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN41 ,Green41 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE41 ,Blue41 "
|
|
group.long 0x8A8++0x03
|
|
line.long 0x00 "BGCLUT42 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA42 ,Alpha42 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED42 ,Red42 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN42 ,Green42 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE42 ,Blue42 "
|
|
group.long 0x8AC++0x03
|
|
line.long 0x00 "BGCLUT43 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA43 ,Alpha43 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED43 ,Red43 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN43 ,Green43 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE43 ,Blue43 "
|
|
group.long 0x8B0++0x03
|
|
line.long 0x00 "BGCLUT44 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA44 ,Alpha44 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED44 ,Red44 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN44 ,Green44 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE44 ,Blue44 "
|
|
group.long 0x8B4++0x03
|
|
line.long 0x00 "BGCLUT45 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA45 ,Alpha45 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED45 ,Red45 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN45 ,Green45 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE45 ,Blue45 "
|
|
group.long 0x8B8++0x03
|
|
line.long 0x00 "BGCLUT46 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA46 ,Alpha46 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED46 ,Red46 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN46 ,Green46 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE46 ,Blue46 "
|
|
group.long 0x8BC++0x03
|
|
line.long 0x00 "BGCLUT47 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA47 ,Alpha47 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED47 ,Red47 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN47 ,Green47 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE47 ,Blue47 "
|
|
group.long 0x8C0++0x03
|
|
line.long 0x00 "BGCLUT48 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA48 ,Alpha48 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED48 ,Red48 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN48 ,Green48 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE48 ,Blue48 "
|
|
group.long 0x8C4++0x03
|
|
line.long 0x00 "BGCLUT49 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA49 ,Alpha49 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED49 ,Red49 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN49 ,Green49 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE49 ,Blue49 "
|
|
group.long 0x8C8++0x03
|
|
line.long 0x00 "BGCLUT50 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA50 ,Alpha50 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED50 ,Red50 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN50 ,Green50 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE50 ,Blue50 "
|
|
group.long 0x8CC++0x03
|
|
line.long 0x00 "BGCLUT51 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA51 ,Alpha51 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED51 ,Red51 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN51 ,Green51 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE51 ,Blue51 "
|
|
group.long 0x8D0++0x03
|
|
line.long 0x00 "BGCLUT52 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA52 ,Alpha52 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED52 ,Red52 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN52 ,Green52 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE52 ,Blue52 "
|
|
group.long 0x8D4++0x03
|
|
line.long 0x00 "BGCLUT53 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA53 ,Alpha53 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED53 ,Red53 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN53 ,Green53 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE53 ,Blue53 "
|
|
group.long 0x8D8++0x03
|
|
line.long 0x00 "BGCLUT54 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA54 ,Alpha54 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED54 ,Red54 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN54 ,Green54 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE54 ,Blue54 "
|
|
group.long 0x8DC++0x03
|
|
line.long 0x00 "BGCLUT55 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA55 ,Alpha55 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED55 ,Red55 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN55 ,Green55 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE55 ,Blue55 "
|
|
group.long 0x8E0++0x03
|
|
line.long 0x00 "BGCLUT56 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA56 ,Alpha56 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED56 ,Red56 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN56 ,Green56 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE56 ,Blue56 "
|
|
group.long 0x8E4++0x03
|
|
line.long 0x00 "BGCLUT57 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA57 ,Alpha57 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED57 ,Red57 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN57 ,Green57 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE57 ,Blue57 "
|
|
group.long 0x8E8++0x03
|
|
line.long 0x00 "BGCLUT58 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA58 ,Alpha58 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED58 ,Red58 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN58 ,Green58 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE58 ,Blue58 "
|
|
group.long 0x8EC++0x03
|
|
line.long 0x00 "BGCLUT59 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA59 ,Alpha59 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED59 ,Red59 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN59 ,Green59 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE59 ,Blue59 "
|
|
group.long 0x8F0++0x03
|
|
line.long 0x00 "BGCLUT60 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA60 ,Alpha60 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED60 ,Red60 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN60 ,Green60 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE60 ,Blue60 "
|
|
group.long 0x8F4++0x03
|
|
line.long 0x00 "BGCLUT61 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA61 ,Alpha61 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED61 ,Red61 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN61 ,Green61 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE61 ,Blue61 "
|
|
group.long 0x8F8++0x03
|
|
line.long 0x00 "BGCLUT62 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA62 ,Alpha62 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED62 ,Red62 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN62 ,Green62 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE62 ,Blue62 "
|
|
group.long 0x8FC++0x03
|
|
line.long 0x00 "BGCLUT63 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA63 ,Alpha63 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED63 ,Red63 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN63 ,Green63 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE63 ,Blue63 "
|
|
group.long 0x900++0x03
|
|
line.long 0x00 "BGCLUT64 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA64 ,Alpha64 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED64 ,Red64 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN64 ,Green64 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE64 ,Blue64 "
|
|
group.long 0x904++0x03
|
|
line.long 0x00 "BGCLUT65 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA65 ,Alpha65 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED65 ,Red65 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN65 ,Green65 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE65 ,Blue65 "
|
|
group.long 0x908++0x03
|
|
line.long 0x00 "BGCLUT66 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA66 ,Alpha66 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED66 ,Red66 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN66 ,Green66 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE66 ,Blue66 "
|
|
group.long 0x90C++0x03
|
|
line.long 0x00 "BGCLUT67 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA67 ,Alpha67 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED67 ,Red67 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN67 ,Green67 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE67 ,Blue67 "
|
|
group.long 0x910++0x03
|
|
line.long 0x00 "BGCLUT68 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA68 ,Alpha68 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED68 ,Red68 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN68 ,Green68 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE68 ,Blue68 "
|
|
group.long 0x914++0x03
|
|
line.long 0x00 "BGCLUT69 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA69 ,Alpha69 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED69 ,Red69 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN69 ,Green69 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE69 ,Blue69 "
|
|
group.long 0x918++0x03
|
|
line.long 0x00 "BGCLUT70 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA70 ,Alpha70 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED70 ,Red70 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN70 ,Green70 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE70 ,Blue70 "
|
|
group.long 0x91C++0x03
|
|
line.long 0x00 "BGCLUT71 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA71 ,Alpha71 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED71 ,Red71 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN71 ,Green71 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE71 ,Blue71 "
|
|
group.long 0x920++0x03
|
|
line.long 0x00 "BGCLUT72 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA72 ,Alpha72 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED72 ,Red72 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN72 ,Green72 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE72 ,Blue72 "
|
|
group.long 0x924++0x03
|
|
line.long 0x00 "BGCLUT73 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA73 ,Alpha73 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED73 ,Red73 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN73 ,Green73 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE73 ,Blue73 "
|
|
group.long 0x928++0x03
|
|
line.long 0x00 "BGCLUT74 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA74 ,Alpha74 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED74 ,Red74 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN74 ,Green74 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE74 ,Blue74 "
|
|
group.long 0x92C++0x03
|
|
line.long 0x00 "BGCLUT75 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA75 ,Alpha75 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED75 ,Red75 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN75 ,Green75 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE75 ,Blue75 "
|
|
group.long 0x930++0x03
|
|
line.long 0x00 "BGCLUT76 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA76 ,Alpha76 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED76 ,Red76 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN76 ,Green76 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE76 ,Blue76 "
|
|
group.long 0x934++0x03
|
|
line.long 0x00 "BGCLUT77 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA77 ,Alpha77 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED77 ,Red77 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN77 ,Green77 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE77 ,Blue77 "
|
|
group.long 0x938++0x03
|
|
line.long 0x00 "BGCLUT78 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA78 ,Alpha78 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED78 ,Red78 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN78 ,Green78 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE78 ,Blue78 "
|
|
group.long 0x93C++0x03
|
|
line.long 0x00 "BGCLUT79 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA79 ,Alpha79 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED79 ,Red79 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN79 ,Green79 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE79 ,Blue79 "
|
|
group.long 0x940++0x03
|
|
line.long 0x00 "BGCLUT80 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA80 ,Alpha80 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED80 ,Red80 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN80 ,Green80 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE80 ,Blue80 "
|
|
group.long 0x944++0x03
|
|
line.long 0x00 "BGCLUT81 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA81 ,Alpha81 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED81 ,Red81 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN81 ,Green81 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE81 ,Blue81 "
|
|
group.long 0x948++0x03
|
|
line.long 0x00 "BGCLUT82 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA82 ,Alpha82 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED82 ,Red82 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN82 ,Green82 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE82 ,Blue82 "
|
|
group.long 0x94C++0x03
|
|
line.long 0x00 "BGCLUT83 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA83 ,Alpha83 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED83 ,Red83 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN83 ,Green83 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE83 ,Blue83 "
|
|
group.long 0x950++0x03
|
|
line.long 0x00 "BGCLUT84 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA84 ,Alpha84 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED84 ,Red84 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN84 ,Green84 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE84 ,Blue84 "
|
|
group.long 0x954++0x03
|
|
line.long 0x00 "BGCLUT85 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA85 ,Alpha85 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED85 ,Red85 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN85 ,Green85 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE85 ,Blue85 "
|
|
group.long 0x958++0x03
|
|
line.long 0x00 "BGCLUT86 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA86 ,Alpha86 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED86 ,Red86 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN86 ,Green86 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE86 ,Blue86 "
|
|
group.long 0x95C++0x03
|
|
line.long 0x00 "BGCLUT87 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA87 ,Alpha87 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED87 ,Red87 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN87 ,Green87 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE87 ,Blue87 "
|
|
group.long 0x960++0x03
|
|
line.long 0x00 "BGCLUT88 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA88 ,Alpha88 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED88 ,Red88 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN88 ,Green88 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE88 ,Blue88 "
|
|
group.long 0x964++0x03
|
|
line.long 0x00 "BGCLUT89 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA89 ,Alpha89 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED89 ,Red89 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN89 ,Green89 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE89 ,Blue89 "
|
|
group.long 0x968++0x03
|
|
line.long 0x00 "BGCLUT90 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA90 ,Alpha90 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED90 ,Red90 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN90 ,Green90 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE90 ,Blue90 "
|
|
group.long 0x96C++0x03
|
|
line.long 0x00 "BGCLUT91 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA91 ,Alpha91 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED91 ,Red91 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN91 ,Green91 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE91 ,Blue91 "
|
|
group.long 0x970++0x03
|
|
line.long 0x00 "BGCLUT92 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA92 ,Alpha92 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED92 ,Red92 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN92 ,Green92 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE92 ,Blue92 "
|
|
group.long 0x974++0x03
|
|
line.long 0x00 "BGCLUT93 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA93 ,Alpha93 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED93 ,Red93 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN93 ,Green93 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE93 ,Blue93 "
|
|
group.long 0x978++0x03
|
|
line.long 0x00 "BGCLUT94 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA94 ,Alpha94 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED94 ,Red94 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN94 ,Green94 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE94 ,Blue94 "
|
|
group.long 0x97C++0x03
|
|
line.long 0x00 "BGCLUT95 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA95 ,Alpha95 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED95 ,Red95 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN95 ,Green95 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE95 ,Blue95 "
|
|
group.long 0x980++0x03
|
|
line.long 0x00 "BGCLUT96 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA96 ,Alpha96 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED96 ,Red96 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN96 ,Green96 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE96 ,Blue96 "
|
|
group.long 0x984++0x03
|
|
line.long 0x00 "BGCLUT97 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA97 ,Alpha97 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED97 ,Red97 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN97 ,Green97 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE97 ,Blue97 "
|
|
group.long 0x988++0x03
|
|
line.long 0x00 "BGCLUT98 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA98 ,Alpha98 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED98 ,Red98 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN98 ,Green98 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE98 ,Blue98 "
|
|
group.long 0x98C++0x03
|
|
line.long 0x00 "BGCLUT99 ,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA99 ,Alpha99 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED99 ,Red99 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN99 ,Green99 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE99 ,Blue99 "
|
|
group.long 0x990++0x03
|
|
line.long 0x00 "BGCLUT100,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA100 ,Alpha100"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED100 ,Red100"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN100 ,Green100"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE100 ,Blue100"
|
|
group.long 0x994++0x03
|
|
line.long 0x00 "BGCLUT101,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA101 ,Alpha101"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED101 ,Red101"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN101 ,Green101"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE101 ,Blue101"
|
|
group.long 0x998++0x03
|
|
line.long 0x00 "BGCLUT102,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA102 ,Alpha102"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED102 ,Red102"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN102 ,Green102"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE102 ,Blue102"
|
|
group.long 0x99C++0x03
|
|
line.long 0x00 "BGCLUT103,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA103 ,Alpha103"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED103 ,Red103"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN103 ,Green103"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE103 ,Blue103"
|
|
group.long 0x9A0++0x03
|
|
line.long 0x00 "BGCLUT104,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA104 ,Alpha104"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED104 ,Red104"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN104 ,Green104"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE104 ,Blue104"
|
|
group.long 0x9A4++0x03
|
|
line.long 0x00 "BGCLUT105,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA105 ,Alpha105"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED105 ,Red105"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN105 ,Green105"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE105 ,Blue105"
|
|
group.long 0x9A8++0x03
|
|
line.long 0x00 "BGCLUT106,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA106 ,Alpha106"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED106 ,Red106"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN106 ,Green106"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE106 ,Blue106"
|
|
group.long 0x9AC++0x03
|
|
line.long 0x00 "BGCLUT107,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA107 ,Alpha107"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED107 ,Red107"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN107 ,Green107"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE107 ,Blue107"
|
|
group.long 0x9B0++0x03
|
|
line.long 0x00 "BGCLUT108,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA108 ,Alpha108"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED108 ,Red108"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN108 ,Green108"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE108 ,Blue108"
|
|
group.long 0x9B4++0x03
|
|
line.long 0x00 "BGCLUT109,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA109 ,Alpha109"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED109 ,Red109"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN109 ,Green109"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE109 ,Blue109"
|
|
group.long 0x9B8++0x03
|
|
line.long 0x00 "BGCLUT110,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA110 ,Alpha110"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED110 ,Red110"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN110 ,Green110"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE110 ,Blue110"
|
|
group.long 0x9BC++0x03
|
|
line.long 0x00 "BGCLUT111,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA111 ,Alpha111"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED111 ,Red111"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN111 ,Green111"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE111 ,Blue111"
|
|
group.long 0x9C0++0x03
|
|
line.long 0x00 "BGCLUT112,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA112 ,Alpha112"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED112 ,Red112"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN112 ,Green112"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE112 ,Blue112"
|
|
group.long 0x9C4++0x03
|
|
line.long 0x00 "BGCLUT113,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA113 ,Alpha113"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED113 ,Red113"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN113 ,Green113"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE113 ,Blue113"
|
|
group.long 0x9C8++0x03
|
|
line.long 0x00 "BGCLUT114,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA114 ,Alpha114"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED114 ,Red114"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN114 ,Green114"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE114 ,Blue114"
|
|
group.long 0x9CC++0x03
|
|
line.long 0x00 "BGCLUT115,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA115 ,Alpha115"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED115 ,Red115"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN115 ,Green115"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE115 ,Blue115"
|
|
group.long 0x9D0++0x03
|
|
line.long 0x00 "BGCLUT116,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA116 ,Alpha116"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED116 ,Red116"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN116 ,Green116"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE116 ,Blue116"
|
|
group.long 0x9D4++0x03
|
|
line.long 0x00 "BGCLUT117,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA117 ,Alpha117"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED117 ,Red117"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN117 ,Green117"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE117 ,Blue117"
|
|
group.long 0x9D8++0x03
|
|
line.long 0x00 "BGCLUT118,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA118 ,Alpha118"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED118 ,Red118"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN118 ,Green118"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE118 ,Blue118"
|
|
group.long 0x9DC++0x03
|
|
line.long 0x00 "BGCLUT119,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA119 ,Alpha119"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED119 ,Red119"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN119 ,Green119"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE119 ,Blue119"
|
|
group.long 0x9E0++0x03
|
|
line.long 0x00 "BGCLUT120,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA120 ,Alpha120"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED120 ,Red120"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN120 ,Green120"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE120 ,Blue120"
|
|
group.long 0x9E4++0x03
|
|
line.long 0x00 "BGCLUT121,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA121 ,Alpha121"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED121 ,Red121"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN121 ,Green121"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE121 ,Blue121"
|
|
group.long 0x9E8++0x03
|
|
line.long 0x00 "BGCLUT122,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA122 ,Alpha122"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED122 ,Red122"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN122 ,Green122"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE122 ,Blue122"
|
|
group.long 0x9EC++0x03
|
|
line.long 0x00 "BGCLUT123,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA123 ,Alpha123"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED123 ,Red123"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN123 ,Green123"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE123 ,Blue123"
|
|
group.long 0x9F0++0x03
|
|
line.long 0x00 "BGCLUT124,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA124 ,Alpha124"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED124 ,Red124"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN124 ,Green124"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE124 ,Blue124"
|
|
group.long 0x9F4++0x03
|
|
line.long 0x00 "BGCLUT125,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA125 ,Alpha125"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED125 ,Red125"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN125 ,Green125"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE125 ,Blue125"
|
|
group.long 0x9F8++0x03
|
|
line.long 0x00 "BGCLUT126,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA126 ,Alpha126"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED126 ,Red126"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN126 ,Green126"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE126 ,Blue126"
|
|
group.long 0x9FC++0x03
|
|
line.long 0x00 "BGCLUT127,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA127 ,Alpha127"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED127 ,Red127"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN127 ,Green127"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE127 ,Blue127"
|
|
group.long 0xA00++0x03
|
|
line.long 0x00 "BGCLUT128,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA128 ,Alpha128"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED128 ,Red128"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN128 ,Green128"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE128 ,Blue128"
|
|
group.long 0xA04++0x03
|
|
line.long 0x00 "BGCLUT129,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA129 ,Alpha129"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED129 ,Red129"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN129 ,Green129"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE129 ,Blue129"
|
|
group.long 0xA08++0x03
|
|
line.long 0x00 "BGCLUT130,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA130 ,Alpha130"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED130 ,Red130"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN130 ,Green130"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE130 ,Blue130"
|
|
group.long 0xA0C++0x03
|
|
line.long 0x00 "BGCLUT131,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA131 ,Alpha131"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED131 ,Red131"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN131 ,Green131"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE131 ,Blue131"
|
|
group.long 0xA10++0x03
|
|
line.long 0x00 "BGCLUT132,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA132 ,Alpha132"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED132 ,Red132"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN132 ,Green132"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE132 ,Blue132"
|
|
group.long 0xA14++0x03
|
|
line.long 0x00 "BGCLUT133,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA133 ,Alpha133"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED133 ,Red133"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN133 ,Green133"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE133 ,Blue133"
|
|
group.long 0xA18++0x03
|
|
line.long 0x00 "BGCLUT134,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA134 ,Alpha134"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED134 ,Red134"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN134 ,Green134"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE134 ,Blue134"
|
|
group.long 0xA1C++0x03
|
|
line.long 0x00 "BGCLUT135,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA135 ,Alpha135"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED135 ,Red135"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN135 ,Green135"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE135 ,Blue135"
|
|
group.long 0xA20++0x03
|
|
line.long 0x00 "BGCLUT136,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA136 ,Alpha136"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED136 ,Red136"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN136 ,Green136"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE136 ,Blue136"
|
|
group.long 0xA24++0x03
|
|
line.long 0x00 "BGCLUT137,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA137 ,Alpha137"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED137 ,Red137"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN137 ,Green137"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE137 ,Blue137"
|
|
group.long 0xA28++0x03
|
|
line.long 0x00 "BGCLUT138,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA138 ,Alpha138"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED138 ,Red138"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN138 ,Green138"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE138 ,Blue138"
|
|
group.long 0xA2C++0x03
|
|
line.long 0x00 "BGCLUT139,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA139 ,Alpha139"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED139 ,Red139"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN139 ,Green139"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE139 ,Blue139"
|
|
group.long 0xA30++0x03
|
|
line.long 0x00 "BGCLUT140,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA140 ,Alpha140"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED140 ,Red140"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN140 ,Green140"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE140 ,Blue140"
|
|
group.long 0xA34++0x03
|
|
line.long 0x00 "BGCLUT141,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA141 ,Alpha141"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED141 ,Red141"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN141 ,Green141"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE141 ,Blue141"
|
|
group.long 0xA38++0x03
|
|
line.long 0x00 "BGCLUT142,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA142 ,Alpha142"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED142 ,Red142"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN142 ,Green142"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE142 ,Blue142"
|
|
group.long 0xA3C++0x03
|
|
line.long 0x00 "BGCLUT143,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA143 ,Alpha143"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED143 ,Red143"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN143 ,Green143"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE143 ,Blue143"
|
|
group.long 0xA40++0x03
|
|
line.long 0x00 "BGCLUT144,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA144 ,Alpha144"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED144 ,Red144"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN144 ,Green144"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE144 ,Blue144"
|
|
group.long 0xA44++0x03
|
|
line.long 0x00 "BGCLUT145,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA145 ,Alpha145"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED145 ,Red145"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN145 ,Green145"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE145 ,Blue145"
|
|
group.long 0xA48++0x03
|
|
line.long 0x00 "BGCLUT146,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA146 ,Alpha146"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED146 ,Red146"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN146 ,Green146"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE146 ,Blue146"
|
|
group.long 0xA4C++0x03
|
|
line.long 0x00 "BGCLUT147,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA147 ,Alpha147"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED147 ,Red147"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN147 ,Green147"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE147 ,Blue147"
|
|
group.long 0xA50++0x03
|
|
line.long 0x00 "BGCLUT148,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA148 ,Alpha148"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED148 ,Red148"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN148 ,Green148"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE148 ,Blue148"
|
|
group.long 0xA54++0x03
|
|
line.long 0x00 "BGCLUT149,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA149 ,Alpha149"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED149 ,Red149"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN149 ,Green149"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE149 ,Blue149"
|
|
group.long 0xA58++0x03
|
|
line.long 0x00 "BGCLUT150,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA150 ,Alpha150"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED150 ,Red150"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN150 ,Green150"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE150 ,Blue150"
|
|
group.long 0xA5C++0x03
|
|
line.long 0x00 "BGCLUT151,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA151 ,Alpha151"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED151 ,Red151"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN151 ,Green151"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE151 ,Blue151"
|
|
group.long 0xA60++0x03
|
|
line.long 0x00 "BGCLUT152,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA152 ,Alpha152"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED152 ,Red152"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN152 ,Green152"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE152 ,Blue152"
|
|
group.long 0xA64++0x03
|
|
line.long 0x00 "BGCLUT153,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA153 ,Alpha153"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED153 ,Red153"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN153 ,Green153"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE153 ,Blue153"
|
|
group.long 0xA68++0x03
|
|
line.long 0x00 "BGCLUT154,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA154 ,Alpha154"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED154 ,Red154"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN154 ,Green154"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE154 ,Blue154"
|
|
group.long 0xA6C++0x03
|
|
line.long 0x00 "BGCLUT155,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA155 ,Alpha155"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED155 ,Red155"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN155 ,Green155"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE155 ,Blue155"
|
|
group.long 0xA70++0x03
|
|
line.long 0x00 "BGCLUT156,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA156 ,Alpha156"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED156 ,Red156"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN156 ,Green156"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE156 ,Blue156"
|
|
group.long 0xA74++0x03
|
|
line.long 0x00 "BGCLUT157,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA157 ,Alpha157"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED157 ,Red157"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN157 ,Green157"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE157 ,Blue157"
|
|
group.long 0xA78++0x03
|
|
line.long 0x00 "BGCLUT158,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA158 ,Alpha158"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED158 ,Red158"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN158 ,Green158"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE158 ,Blue158"
|
|
group.long 0xA7C++0x03
|
|
line.long 0x00 "BGCLUT159,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA159 ,Alpha159"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED159 ,Red159"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN159 ,Green159"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE159 ,Blue159"
|
|
group.long 0xA80++0x03
|
|
line.long 0x00 "BGCLUT160,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA160 ,Alpha160"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED160 ,Red160"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN160 ,Green160"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE160 ,Blue160"
|
|
group.long 0xA84++0x03
|
|
line.long 0x00 "BGCLUT161,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA161 ,Alpha161"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED161 ,Red161"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN161 ,Green161"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE161 ,Blue161"
|
|
group.long 0xA88++0x03
|
|
line.long 0x00 "BGCLUT162,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA162 ,Alpha162"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED162 ,Red162"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN162 ,Green162"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE162 ,Blue162"
|
|
group.long 0xA8C++0x03
|
|
line.long 0x00 "BGCLUT163,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA163 ,Alpha163"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED163 ,Red163"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN163 ,Green163"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE163 ,Blue163"
|
|
group.long 0xA90++0x03
|
|
line.long 0x00 "BGCLUT164,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA164 ,Alpha164"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED164 ,Red164"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN164 ,Green164"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE164 ,Blue164"
|
|
group.long 0xA94++0x03
|
|
line.long 0x00 "BGCLUT165,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA165 ,Alpha165"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED165 ,Red165"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN165 ,Green165"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE165 ,Blue165"
|
|
group.long 0xA98++0x03
|
|
line.long 0x00 "BGCLUT166,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA166 ,Alpha166"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED166 ,Red166"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN166 ,Green166"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE166 ,Blue166"
|
|
group.long 0xA9C++0x03
|
|
line.long 0x00 "BGCLUT167,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA167 ,Alpha167"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED167 ,Red167"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN167 ,Green167"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE167 ,Blue167"
|
|
group.long 0xAA0++0x03
|
|
line.long 0x00 "BGCLUT168,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA168 ,Alpha168"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED168 ,Red168"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN168 ,Green168"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE168 ,Blue168"
|
|
group.long 0xAA4++0x03
|
|
line.long 0x00 "BGCLUT169,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA169 ,Alpha169"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED169 ,Red169"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN169 ,Green169"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE169 ,Blue169"
|
|
group.long 0xAA8++0x03
|
|
line.long 0x00 "BGCLUT170,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA170 ,Alpha170"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED170 ,Red170"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN170 ,Green170"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE170 ,Blue170"
|
|
group.long 0xAAC++0x03
|
|
line.long 0x00 "BGCLUT171,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA171 ,Alpha171"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED171 ,Red171"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN171 ,Green171"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE171 ,Blue171"
|
|
group.long 0xAB0++0x03
|
|
line.long 0x00 "BGCLUT172,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA172 ,Alpha172"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED172 ,Red172"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN172 ,Green172"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE172 ,Blue172"
|
|
group.long 0xAB4++0x03
|
|
line.long 0x00 "BGCLUT173,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA173 ,Alpha173"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED173 ,Red173"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN173 ,Green173"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE173 ,Blue173"
|
|
group.long 0xAB8++0x03
|
|
line.long 0x00 "BGCLUT174,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA174 ,Alpha174"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED174 ,Red174"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN174 ,Green174"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE174 ,Blue174"
|
|
group.long 0xABC++0x03
|
|
line.long 0x00 "BGCLUT175,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA175 ,Alpha175"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED175 ,Red175"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN175 ,Green175"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE175 ,Blue175"
|
|
group.long 0xAC0++0x03
|
|
line.long 0x00 "BGCLUT176,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA176 ,Alpha176"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED176 ,Red176"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN176 ,Green176"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE176 ,Blue176"
|
|
group.long 0xAC4++0x03
|
|
line.long 0x00 "BGCLUT177,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA177 ,Alpha177"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED177 ,Red177"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN177 ,Green177"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE177 ,Blue177"
|
|
group.long 0xAC8++0x03
|
|
line.long 0x00 "BGCLUT178,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA178 ,Alpha178"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED178 ,Red178"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN178 ,Green178"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE178 ,Blue178"
|
|
group.long 0xACC++0x03
|
|
line.long 0x00 "BGCLUT179,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA179 ,Alpha179"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED179 ,Red179"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN179 ,Green179"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE179 ,Blue179"
|
|
group.long 0xAD0++0x03
|
|
line.long 0x00 "BGCLUT180,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA180 ,Alpha180"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED180 ,Red180"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN180 ,Green180"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE180 ,Blue180"
|
|
group.long 0xAD4++0x03
|
|
line.long 0x00 "BGCLUT181,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA181 ,Alpha181"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED181 ,Red181"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN181 ,Green181"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE181 ,Blue181"
|
|
group.long 0xAD8++0x03
|
|
line.long 0x00 "BGCLUT182,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA182 ,Alpha182"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED182 ,Red182"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN182 ,Green182"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE182 ,Blue182"
|
|
group.long 0xADC++0x03
|
|
line.long 0x00 "BGCLUT183,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA183 ,Alpha183"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED183 ,Red183"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN183 ,Green183"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE183 ,Blue183"
|
|
group.long 0xAE0++0x03
|
|
line.long 0x00 "BGCLUT184,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA184 ,Alpha184"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED184 ,Red184"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN184 ,Green184"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE184 ,Blue184"
|
|
group.long 0xAE4++0x03
|
|
line.long 0x00 "BGCLUT185,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA185 ,Alpha185"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED185 ,Red185"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN185 ,Green185"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE185 ,Blue185"
|
|
group.long 0xAE8++0x03
|
|
line.long 0x00 "BGCLUT186,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA186 ,Alpha186"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED186 ,Red186"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN186 ,Green186"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE186 ,Blue186"
|
|
group.long 0xAEC++0x03
|
|
line.long 0x00 "BGCLUT187,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA187 ,Alpha187"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED187 ,Red187"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN187 ,Green187"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE187 ,Blue187"
|
|
group.long 0xAF0++0x03
|
|
line.long 0x00 "BGCLUT188,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA188 ,Alpha188"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED188 ,Red188"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN188 ,Green188"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE188 ,Blue188"
|
|
group.long 0xAF4++0x03
|
|
line.long 0x00 "BGCLUT189,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA189 ,Alpha189"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED189 ,Red189"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN189 ,Green189"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE189 ,Blue189"
|
|
group.long 0xAF8++0x03
|
|
line.long 0x00 "BGCLUT190,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA190 ,Alpha190"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED190 ,Red190"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN190 ,Green190"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE190 ,Blue190"
|
|
group.long 0xAFC++0x03
|
|
line.long 0x00 "BGCLUT191,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA191 ,Alpha191"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED191 ,Red191"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN191 ,Green191"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE191 ,Blue191"
|
|
group.long 0xB00++0x03
|
|
line.long 0x00 "BGCLUT192,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA192 ,Alpha192"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED192 ,Red192"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN192 ,Green192"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE192 ,Blue192"
|
|
group.long 0xB04++0x03
|
|
line.long 0x00 "BGCLUT193,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA193 ,Alpha193"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED193 ,Red193"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN193 ,Green193"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE193 ,Blue193"
|
|
group.long 0xB08++0x03
|
|
line.long 0x00 "BGCLUT194,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA194 ,Alpha194"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED194 ,Red194"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN194 ,Green194"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE194 ,Blue194"
|
|
group.long 0xB0C++0x03
|
|
line.long 0x00 "BGCLUT195,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA195 ,Alpha195"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED195 ,Red195"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN195 ,Green195"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE195 ,Blue195"
|
|
group.long 0xB10++0x03
|
|
line.long 0x00 "BGCLUT196,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA196 ,Alpha196"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED196 ,Red196"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN196 ,Green196"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE196 ,Blue196"
|
|
group.long 0xB14++0x03
|
|
line.long 0x00 "BGCLUT197,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA197 ,Alpha197"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED197 ,Red197"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN197 ,Green197"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE197 ,Blue197"
|
|
group.long 0xB18++0x03
|
|
line.long 0x00 "BGCLUT198,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA198 ,Alpha198"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED198 ,Red198"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN198 ,Green198"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE198 ,Blue198"
|
|
group.long 0xB1C++0x03
|
|
line.long 0x00 "BGCLUT199,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA199 ,Alpha199"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED199 ,Red199"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN199 ,Green199"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE199 ,Blue199"
|
|
group.long 0xB20++0x03
|
|
line.long 0x00 "BGCLUT200,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA200 ,Alpha200"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED200 ,Red200"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN200 ,Green200"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE200 ,Blue200"
|
|
group.long 0xB24++0x03
|
|
line.long 0x00 "BGCLUT201,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA201 ,Alpha201"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED201 ,Red201"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN201 ,Green201"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE201 ,Blue201"
|
|
group.long 0xB28++0x03
|
|
line.long 0x00 "BGCLUT202,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA202 ,Alpha202"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED202 ,Red202"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN202 ,Green202"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE202 ,Blue202"
|
|
group.long 0xB2C++0x03
|
|
line.long 0x00 "BGCLUT203,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA203 ,Alpha203"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED203 ,Red203"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN203 ,Green203"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE203 ,Blue203"
|
|
group.long 0xB30++0x03
|
|
line.long 0x00 "BGCLUT204,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA204 ,Alpha204"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED204 ,Red204"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN204 ,Green204"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE204 ,Blue204"
|
|
group.long 0xB34++0x03
|
|
line.long 0x00 "BGCLUT205,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA205 ,Alpha205"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED205 ,Red205"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN205 ,Green205"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE205 ,Blue205"
|
|
group.long 0xB38++0x03
|
|
line.long 0x00 "BGCLUT206,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA206 ,Alpha206"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED206 ,Red206"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN206 ,Green206"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE206 ,Blue206"
|
|
group.long 0xB3C++0x03
|
|
line.long 0x00 "BGCLUT207,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA207 ,Alpha207"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED207 ,Red207"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN207 ,Green207"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE207 ,Blue207"
|
|
group.long 0xB40++0x03
|
|
line.long 0x00 "BGCLUT208,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA208 ,Alpha208"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED208 ,Red208"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN208 ,Green208"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE208 ,Blue208"
|
|
group.long 0xB44++0x03
|
|
line.long 0x00 "BGCLUT209,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA209 ,Alpha209"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED209 ,Red209"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN209 ,Green209"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE209 ,Blue209"
|
|
group.long 0xB48++0x03
|
|
line.long 0x00 "BGCLUT210,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA210 ,Alpha210"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED210 ,Red210"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN210 ,Green210"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE210 ,Blue210"
|
|
group.long 0xB4C++0x03
|
|
line.long 0x00 "BGCLUT211,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA211 ,Alpha211"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED211 ,Red211"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN211 ,Green211"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE211 ,Blue211"
|
|
group.long 0xB50++0x03
|
|
line.long 0x00 "BGCLUT212,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA212 ,Alpha212"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED212 ,Red212"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN212 ,Green212"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE212 ,Blue212"
|
|
group.long 0xB54++0x03
|
|
line.long 0x00 "BGCLUT213,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA213 ,Alpha213"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED213 ,Red213"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN213 ,Green213"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE213 ,Blue213"
|
|
group.long 0xB58++0x03
|
|
line.long 0x00 "BGCLUT214,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA214 ,Alpha214"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED214 ,Red214"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN214 ,Green214"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE214 ,Blue214"
|
|
group.long 0xB5C++0x03
|
|
line.long 0x00 "BGCLUT215,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA215 ,Alpha215"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED215 ,Red215"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN215 ,Green215"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE215 ,Blue215"
|
|
group.long 0xB60++0x03
|
|
line.long 0x00 "BGCLUT216,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA216 ,Alpha216"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED216 ,Red216"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN216 ,Green216"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE216 ,Blue216"
|
|
group.long 0xB64++0x03
|
|
line.long 0x00 "BGCLUT217,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA217 ,Alpha217"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED217 ,Red217"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN217 ,Green217"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE217 ,Blue217"
|
|
group.long 0xB68++0x03
|
|
line.long 0x00 "BGCLUT218,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA218 ,Alpha218"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED218 ,Red218"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN218 ,Green218"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE218 ,Blue218"
|
|
group.long 0xB6C++0x03
|
|
line.long 0x00 "BGCLUT219,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA219 ,Alpha219"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED219 ,Red219"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN219 ,Green219"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE219 ,Blue219"
|
|
group.long 0xB70++0x03
|
|
line.long 0x00 "BGCLUT220,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA220 ,Alpha220"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED220 ,Red220"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN220 ,Green220"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE220 ,Blue220"
|
|
group.long 0xB74++0x03
|
|
line.long 0x00 "BGCLUT221,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA221 ,Alpha221"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED221 ,Red221"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN221 ,Green221"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE221 ,Blue221"
|
|
group.long 0xB78++0x03
|
|
line.long 0x00 "BGCLUT222,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA222 ,Alpha222"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED222 ,Red222"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN222 ,Green222"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE222 ,Blue222"
|
|
group.long 0xB7C++0x03
|
|
line.long 0x00 "BGCLUT223,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA223 ,Alpha223"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED223 ,Red223"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN223 ,Green223"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE223 ,Blue223"
|
|
group.long 0xB80++0x03
|
|
line.long 0x00 "BGCLUT224,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA224 ,Alpha224"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED224 ,Red224"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN224 ,Green224"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE224 ,Blue224"
|
|
group.long 0xB84++0x03
|
|
line.long 0x00 "BGCLUT225,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA225 ,Alpha225"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED225 ,Red225"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN225 ,Green225"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE225 ,Blue225"
|
|
group.long 0xB88++0x03
|
|
line.long 0x00 "BGCLUT226,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA226 ,Alpha226"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED226 ,Red226"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN226 ,Green226"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE226 ,Blue226"
|
|
group.long 0xB8C++0x03
|
|
line.long 0x00 "BGCLUT227,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA227 ,Alpha227"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED227 ,Red227"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN227 ,Green227"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE227 ,Blue227"
|
|
group.long 0xB90++0x03
|
|
line.long 0x00 "BGCLUT228,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA228 ,Alpha228"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED228 ,Red228"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN228 ,Green228"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE228 ,Blue228"
|
|
group.long 0xB94++0x03
|
|
line.long 0x00 "BGCLUT229,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA229 ,Alpha229"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED229 ,Red229"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN229 ,Green229"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE229 ,Blue229"
|
|
group.long 0xB98++0x03
|
|
line.long 0x00 "BGCLUT230,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA230 ,Alpha230"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED230 ,Red230"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN230 ,Green230"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE230 ,Blue230"
|
|
group.long 0xB9C++0x03
|
|
line.long 0x00 "BGCLUT231,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA231 ,Alpha231"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED231 ,Red231"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN231 ,Green231"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE231 ,Blue231"
|
|
group.long 0xBA0++0x03
|
|
line.long 0x00 "BGCLUT232,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA232 ,Alpha232"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED232 ,Red232"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN232 ,Green232"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE232 ,Blue232"
|
|
group.long 0xBA4++0x03
|
|
line.long 0x00 "BGCLUT233,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA233 ,Alpha233"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED233 ,Red233"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN233 ,Green233"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE233 ,Blue233"
|
|
group.long 0xBA8++0x03
|
|
line.long 0x00 "BGCLUT234,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA234 ,Alpha234"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED234 ,Red234"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN234 ,Green234"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE234 ,Blue234"
|
|
group.long 0xBAC++0x03
|
|
line.long 0x00 "BGCLUT235,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA235 ,Alpha235"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED235 ,Red235"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN235 ,Green235"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE235 ,Blue235"
|
|
group.long 0xBB0++0x03
|
|
line.long 0x00 "BGCLUT236,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA236 ,Alpha236"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED236 ,Red236"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN236 ,Green236"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE236 ,Blue236"
|
|
group.long 0xBB4++0x03
|
|
line.long 0x00 "BGCLUT237,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA237 ,Alpha237"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED237 ,Red237"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN237 ,Green237"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE237 ,Blue237"
|
|
group.long 0xBB8++0x03
|
|
line.long 0x00 "BGCLUT238,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA238 ,Alpha238"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED238 ,Red238"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN238 ,Green238"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE238 ,Blue238"
|
|
group.long 0xBBC++0x03
|
|
line.long 0x00 "BGCLUT239,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA239 ,Alpha239"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED239 ,Red239"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN239 ,Green239"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE239 ,Blue239"
|
|
group.long 0xBC0++0x03
|
|
line.long 0x00 "BGCLUT240,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA240 ,Alpha240"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED240 ,Red240"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN240 ,Green240"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE240 ,Blue240"
|
|
group.long 0xBC4++0x03
|
|
line.long 0x00 "BGCLUT241,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA241 ,Alpha241"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED241 ,Red241"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN241 ,Green241"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE241 ,Blue241"
|
|
group.long 0xBC8++0x03
|
|
line.long 0x00 "BGCLUT242,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA242 ,Alpha242"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED242 ,Red242"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN242 ,Green242"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE242 ,Blue242"
|
|
group.long 0xBCC++0x03
|
|
line.long 0x00 "BGCLUT243,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA243 ,Alpha243"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED243 ,Red243"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN243 ,Green243"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE243 ,Blue243"
|
|
group.long 0xBD0++0x03
|
|
line.long 0x00 "BGCLUT244,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA244 ,Alpha244"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED244 ,Red244"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN244 ,Green244"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE244 ,Blue244"
|
|
group.long 0xBD4++0x03
|
|
line.long 0x00 "BGCLUT245,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA245 ,Alpha245"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED245 ,Red245"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN245 ,Green245"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE245 ,Blue245"
|
|
group.long 0xBD8++0x03
|
|
line.long 0x00 "BGCLUT246,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA246 ,Alpha246"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED246 ,Red246"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN246 ,Green246"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE246 ,Blue246"
|
|
group.long 0xBDC++0x03
|
|
line.long 0x00 "BGCLUT247,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA247 ,Alpha247"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED247 ,Red247"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN247 ,Green247"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE247 ,Blue247"
|
|
group.long 0xBE0++0x03
|
|
line.long 0x00 "BGCLUT248,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA248 ,Alpha248"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED248 ,Red248"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN248 ,Green248"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE248 ,Blue248"
|
|
group.long 0xBE4++0x03
|
|
line.long 0x00 "BGCLUT249,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA249 ,Alpha249"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED249 ,Red249"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN249 ,Green249"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE249 ,Blue249"
|
|
group.long 0xBE8++0x03
|
|
line.long 0x00 "BGCLUT250,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA250 ,Alpha250"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED250 ,Red250"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN250 ,Green250"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE250 ,Blue250"
|
|
group.long 0xBEC++0x03
|
|
line.long 0x00 "BGCLUT251,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA251 ,Alpha251"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED251 ,Red251"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN251 ,Green251"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE251 ,Blue251"
|
|
group.long 0xBF0++0x03
|
|
line.long 0x00 "BGCLUT252,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA252 ,Alpha252"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED252 ,Red252"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN252 ,Green252"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE252 ,Blue252"
|
|
group.long 0xBF4++0x03
|
|
line.long 0x00 "BGCLUT253,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA253 ,Alpha253"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED253 ,Red253"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN253 ,Green253"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE253 ,Blue253"
|
|
group.long 0xBF8++0x03
|
|
line.long 0x00 "BGCLUT254,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA254 ,Alpha254"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED254 ,Red254"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN254 ,Green254"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE254 ,Blue254"
|
|
group.long 0xBFC++0x03
|
|
line.long 0x00 "BGCLUT255,DMA2D Background CLUT"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA255 ,Alpha255"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED255 ,Red255"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN255 ,Green255"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE255 ,Blue255"
|
|
tree.end
|
|
endif
|
|
sif cpuis("STM32L496*")||cpuis("STM32L4A6*")
|
|
rgroup.long 0x3F4++0x0B
|
|
line.long 0x00 "VERR,DMA2D IP Version Register"
|
|
bitfld.long 0x00 4.--7. " MAJREV ,Major revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " MINREV ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "IPIDR,DMA2D IP Identification Register"
|
|
line.long 0x08 "SIDR,DMA2D IP Size Identification Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "EXTI (External interrupt/event controller)"
|
|
base ad:0x40013C00
|
|
width 7.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "IMR,EXTI Interrupt Mask Register"
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32F72*"))
|
|
bitfld.long 0x00 24. " IM24 ,Interrupt mask on line 24" "Masked,Not masked"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32F7*")||cpuis("STM32L15??C-A")||cpuis("STM32L15??C")||cpuis("STM32L162?C-A")||cpuis("STM32L162?C")||cpuis("STM32L15??E")||cpuis("STM32L162?E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC"))
|
|
sif (!cpuis("STM32F730R*"))
|
|
bitfld.long 0x00 23. " IM23 ,Interrupt mask on line 23" "Masked,Not masked"
|
|
newline
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 22. " IM22 ,Interrupt mask on line 22" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " IM21 ,Interrupt mask on line 21" "Masked,Not masked"
|
|
newline
|
|
sif (!cpuis("STM32F411*")&&!cpuis("STM32F401*"))
|
|
bitfld.long 0x00 20. " IM20 ,Interrupt mask on line 20" "Masked,Not masked"
|
|
newline
|
|
sif (!cpuis("STM32F769A*")&&!cpuis("STM32F778A*")&&!cpuis("STM32F779A*")&&!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
bitfld.long 0x00 19. " IM19 ,Interrupt mask on line 19" "Masked,Not masked"
|
|
newline
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 18. " IM18 ,Interrupt mask on line 18" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " IM17 ,Interrupt mask on line 17" "Masked,Not masked"
|
|
bitfld.long 0x00 16. " IM16 ,Interrupt mask on line 16" "Masked,Not masked"
|
|
bitfld.long 0x00 15. " IM15 ,Interrupt mask on line 15" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 14. " IM14 ,Interrupt mask on line 14" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " IM13 ,Interrupt mask on line 13" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " IM12 ,Interrupt mask on line 12" "Masked,Not masked"
|
|
bitfld.long 0x00 11. " IM11 ,Interrupt mask on line 11" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 10. " IM10 ,Interrupt mask on line 10" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " IM9 ,Interrupt mask on line 9" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " IM8 ,Interrupt mask on line 8" "Masked,Not masked"
|
|
bitfld.long 0x00 7. " IM7 ,Interrupt mask on line 7" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 6. " IM6 ,Interrupt mask on line 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " IM5 ,Interrupt mask on line 5" "Masked,Not masked"
|
|
bitfld.long 0x00 4. " IM4 ,Interrupt mask on line 4" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " IM3 ,Interrupt mask on line 3" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 2. " IM2 ,Interrupt mask on line 2" "Masked,Not masked"
|
|
bitfld.long 0x00 1. " IM1 ,Interrupt mask on line 1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " IM0 ,Interrupt mask on line 0" "Masked,Not masked"
|
|
line.long 0x04 "EMR,EXTI Event Mask Register"
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32F72*"))
|
|
bitfld.long 0x04 24. " EM24 ,Event mask on line 24" "Masked,Not masked"
|
|
newline
|
|
endif
|
|
sif cpuis("STM32F7*")||cpuis("STM32L15??C-A")||cpuis("STM32L15??C")||cpuis("STM32L162?C-A")||cpuis("STM32L162?C")||cpuis("STM32L15??E")||cpuis("STM32L162?E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
sif (!cpuis("STM32F730R*"))
|
|
bitfld.long 0x04 23. " EM23 ,Event mask on line 23" "Masked,Not masked"
|
|
newline
|
|
endif
|
|
endif
|
|
bitfld.long 0x04 22. " EM22 ,Event mask on line 22" "Masked,Not masked"
|
|
bitfld.long 0x04 21. " EM21 ,Event mask on line 21" "Masked,Not masked"
|
|
newline
|
|
sif (!cpuis("STM32F411*")&&!cpuis("STM32F401*"))
|
|
bitfld.long 0x04 20. " EM20 ,Event mask on line 20" "Masked,Not masked"
|
|
newline
|
|
sif (!cpuis("STM32F769A*")&&!cpuis("STM32F778A*")&&!cpuis("STM32F779A*")&&!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
bitfld.long 0x04 19. " EM19 ,Event mask on line 19" "Masked,Not masked"
|
|
endif
|
|
endif
|
|
newline
|
|
bitfld.long 0x04 18. " EM18 ,Event mask on line 18" "Masked,Not masked"
|
|
bitfld.long 0x04 17. " EM17 ,Event mask on line 17" "Masked,Not masked"
|
|
bitfld.long 0x04 16. " EM16 ,Event mask on line 16" "Masked,Not masked"
|
|
bitfld.long 0x04 15. " EM15 ,Event mask on line 15" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x04 14. " EM14 ,Event mask on line 14" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " EM13 ,Event mask on line 13" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " EM12 ,Event mask on line 12" "Masked,Not masked"
|
|
bitfld.long 0x04 11. " EM11 ,Event mask on line 11" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x04 10. " EM10 ,Event mask on line 10" "Masked,Not masked"
|
|
bitfld.long 0x04 9. " EM9 ,Event mask on line 9" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " EM8 ,Event mask on line 8" "Masked,Not masked"
|
|
bitfld.long 0x04 7. " EM7 ,Event mask on line 7" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x04 6. " EM6 ,Event mask on line 6" "Masked,Not masked"
|
|
bitfld.long 0x04 5. " EM5 ,Event mask on line 5" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " EM4 ,Event mask on line 4" "Masked,Not masked"
|
|
bitfld.long 0x04 3. " EM3 ,Event mask on line 3" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x04 2. " EM2 ,Event mask on line 2" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " EM1 ,Event mask on line 1" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " EM0 ,Event mask on line 0" "Masked,Not masked"
|
|
line.long 0x08 "RTSR,EXTI Rising Edge Trigger Selection Register"
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32F72*"))
|
|
bitfld.long 0x08 24. " TR24 ,Rising edge trigger event configuration bit of line 24" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32F7*")||cpuis("STM32L15??C-A")||cpuis("STM32L15??C")||cpuis("STM32L162?C-A")||cpuis("STM32L162?C")||cpuis("STM32L15??E")||cpuis("STM32L162?E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC"))
|
|
sif (!cpuis("STM32F730R*"))
|
|
bitfld.long 0x08 23. " TR23 ,Rising edge trigger event configuration bit of line 23" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
endif
|
|
bitfld.long 0x08 22. " TR22 ,Rising edge trigger event configuration bit of line 22" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " TR21 ,Rising edge trigger event configuration bit of line 21" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*"))
|
|
bitfld.long 0x08 20. " TR20 ,Rising edge trigger event configuration bit of line 20" "Disabled,Enabled"
|
|
newline
|
|
elif (!cpuis("STM32F411*")&&!cpuis("STM32F401*"))
|
|
bitfld.long 0x08 20. " TR20 ,Rising edge trigger event configuration bit of line 20" "Disabled,Enabled"
|
|
newline
|
|
sif (!cpuis("STM32F769A*")&&!cpuis("STM32F778A*")&&!cpuis("STM32F779A*")&&!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
bitfld.long 0x08 19. " TR19 ,Rising edge trigger event configuration bit of line 19" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
endif
|
|
bitfld.long 0x08 18. " TR18 ,Rising edge trigger event configuration bit of line 18" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " TR17 ,Rising edge trigger event configuration bit of line 17" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " TR16 ,Rising edge trigger event configuration bit of line 16" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " TR15 ,Rising edge trigger event configuration bit of line 15" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 14. " TR14 ,Rising edge trigger event configuration bit of line 14" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " TR13 ,Rising edge trigger event configuration bit of line 13" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " TR12 ,Rising edge trigger event configuration bit of line 12" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " TR11 ,Rising edge trigger event configuration bit of line 11" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 10. " TR10 ,Rising edge trigger event configuration bit of line 10" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " TR9 ,Rising edge trigger event configuration bit of line 9" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " TR8 ,Rising edge trigger event configuration bit of line 8" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " TR7 ,Rising edge trigger event configuration bit of line 7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 6. " TR6 ,Rising edge trigger event configuration bit of line 6" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " TR5 ,Rising edge trigger event configuration bit of line 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TR4 ,Rising edge trigger event configuration bit of line 4" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " TR3 ,Rising edge trigger event configuration bit of line 3" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 2. " TR2 ,Rising edge trigger event configuration bit of line 2" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " TR1 ,Rising edge trigger event configuration bit of line 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " TR0 ,Rising edge trigger event configuration bit of line 0" "Disabled,Enabled"
|
|
line.long 0x0C "FTSR,Falling Edge Trigger Selection Register"
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32F72*"))
|
|
bitfld.long 0x0C 24. " TR24 ,Falling edge trigger event configuration bit of line 24" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
sif cpuis("STM32F7*")||cpuis("STM32L15??C-A")||cpuis("STM32L15??C")||cpuis("STM32L162?C-A")||cpuis("STM32L162?C")||cpuis("STM32L15??E")||cpuis("STM32L162?E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
sif (!cpuis("STM32F730R*"))
|
|
bitfld.long 0x0C 23. " TR23 ,Falling edge trigger event configuration bit of line 23" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
endif
|
|
bitfld.long 0x0C 22. " TR22 ,Falling edge trigger event configuration bit of line 22" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " TR21 ,Falling edge trigger event configuration bit of line 21" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
bitfld.long 0x0C 20. " TR20 ,Falling edge trigger event configuration bit of line 20" "Disabled,Enabled"
|
|
newline
|
|
elif (!cpuis("STM32F411*")&&!cpuis("STM32F401*"))
|
|
bitfld.long 0x0C 20. " TR20 ,Falling edge trigger event configuration bit of line 20" "Disabled,Enabled"
|
|
newline
|
|
sif (!cpuis("STM32F769A*")&&!cpuis("STM32F778A*")&&!cpuis("STM32F779A*")&&!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
bitfld.long 0x0C 19. " TR19 ,Falling edge trigger event configuration bit of line 19" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
endif
|
|
bitfld.long 0x0C 18. " TR18 ,Falling edge trigger event configuration bit of line 18" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " TR17 ,Falling edge trigger event configuration bit of line 17" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " TR16 ,Falling edge trigger event configuration bit of line 16" "Disabled,Enabled"
|
|
bitfld.long 0x0C 15. " TR15 ,Falling edge trigger event configuration bit of line 15" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 14. " TR14 ,Falling edge trigger event configuration bit of line 14" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " TR13 ,Falling edge trigger event configuration bit of line 13" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " TR12 ,Falling edge trigger event configuration bit of line 12" "Disabled,Enabled"
|
|
bitfld.long 0x0C 11. " TR11 ,Falling edge trigger event configuration bit of line 11" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 10. " TR10 ,Falling edge trigger event configuration bit of line 10" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " TR9 ,Falling edge trigger event configuration bit of line 9" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " TR8 ,Falling edge trigger event configuration bit of line 8" "Disabled,Enabled"
|
|
bitfld.long 0x0C 7. " TR7 ,Falling edge trigger event configuration bit of line 7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 6. " TR6 ,Falling edge trigger event configuration bit of line 6" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " TR5 ,Falling edge trigger event configuration bit of line 5" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TR4 ,Falling edge trigger event configuration bit of line 4" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " TR3 ,Falling edge trigger event configuration bit of line 3" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 2. " TR2 ,Falling edge trigger event configuration bit of line 2" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " TR1 ,Falling edge trigger event configuration bit of line 1" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " TR0 ,Falling edge trigger event configuration bit of line 0" "Disabled,Enabled"
|
|
line.long 0x10 "SWIER,EXTI Software Interrupt Event Register"
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32F72*"))
|
|
bitfld.long 0x10 24. " SWIER24 ,Software interrupt on line 24" "No interrupt,Interrupt"
|
|
newline
|
|
endif
|
|
sif cpuis("STM32F7*")||cpuis("STM32L15??C-A")||cpuis("STM32L15??C")||cpuis("STM32L162?C-A")||cpuis("STM32L162?C")||cpuis("STM32L15??E")||cpuis("STM32L162?E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
sif (!cpuis("STM32F730R*"))
|
|
bitfld.long 0x10 23. " SWIER23 ,Software interrupt on line 23" "No interrupt,Interrupt"
|
|
newline
|
|
endif
|
|
endif
|
|
bitfld.long 0x10 22. " SWIER22 ,Software interrupt on line 22" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 21. " SWIER21 ,Software interrupt on line 21" "No interrupt,Interrupt"
|
|
newline
|
|
sif (!cpuis("STM32F411*")&&!cpuis("STM32F401*"))
|
|
bitfld.long 0x10 20. " SWIER20 ,Software interrupt on line 20" "No interrupt,Interrupt"
|
|
newline
|
|
sif (!cpuis("STM32F769A*")&&!cpuis("STM32F778A*")&&!cpuis("STM32F779A*")&&!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
bitfld.long 0x10 19. " SWIER19 ,Software interrupt on line 19" "No interrupt,Interrupt"
|
|
newline
|
|
endif
|
|
endif
|
|
bitfld.long 0x10 18. " SWIER18 ,Software interrupt on line 18" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 17. " SWIER17 ,Software interrupt on line 17" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16. " SWIER16 ,Software interrupt on line 16" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 15. " SWIER15 ,Software interrupt on line 15" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x10 14. " SWIER14 ,Software interrupt on line 14" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 13. " SWIER13 ,Software interrupt on line 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 12. " SWIER12 ,Software interrupt on line 12" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 11. " SWIER11 ,Software interrupt on line 11" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x10 10. " SWIER10 ,Software interrupt on line 10" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 9. " SWIER9 ,Software interrupt on line 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 8. " SWIER8 ,Software interrupt on line 8" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 7. " SWIER7 ,Software interrupt on line 7" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x10 6. " SWIER6 ,Software interrupt on line 6" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 5. " SWIER5 ,Software interrupt on line 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 4. " SWIER4 ,Software interrupt on line 4" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 3. " SWIER3 ,Software interrupt on line 3" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x10 2. " SWIER2 ,Software interrupt on line 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 1. " SWIER1 ,Software interrupt on line 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 0. " SWIER0 ,Software interrupt on line 0" "No interrupt,Interrupt"
|
|
line.long 0x14 "PR,EXTI Pending Register"
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
eventfld.long 0x14 24. " PR24 ,Pending bit 24" "Not pending,Pending"
|
|
newline
|
|
endif
|
|
sif cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")||cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100RC")
|
|
sif cpuis("STM32L15??C-A")||cpuis("STM32L15??C")||cpuis("STM32L162?C-A")||cpuis("STM32L162?C")||cpuis("STM32L15??E")||cpuis("STM32L162?E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100RC")
|
|
eventfld.long 0x14 23. " PR23 ,Pending bit 23" "Not pending,Pending"
|
|
newline
|
|
endif
|
|
eventfld.long 0x14 22. " PR22 ,Pending bit 22" "Not pending,Pending"
|
|
eventfld.long 0x14 21. " PR21 ,Pending bit 21" "Not pending,Pending"
|
|
eventfld.long 0x14 20. " PR20 ,Pending bit 20" "Not pending,Pending"
|
|
newline
|
|
else
|
|
sif (cpuis("STM32F7*"))
|
|
sif (!cpuis("STM32F730R*"))
|
|
eventfld.long 0x14 23. " PR23 ,Pending bit 23" "Not pending,Pending"
|
|
newline
|
|
endif
|
|
endif
|
|
eventfld.long 0x14 22. " PR22 ,Pending bit 22" "Not pending,Pending"
|
|
eventfld.long 0x14 21. " PR21 ,Pending bit 21" "Not pending,Pending"
|
|
newline
|
|
sif (!cpuis("STM32F411*")&&!cpuis("STM32F401*"))
|
|
eventfld.long 0x14 20. " PR20 ,Pending bit 20" "Not pending,Pending"
|
|
newline
|
|
sif (!cpuis("STM32F769A*")&&!cpuis("STM32F778A*")&&!cpuis("STM32F779A*")&&!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
eventfld.long 0x14 19. " PR19 ,Pending bit 19" "Not pending,Pending"
|
|
newline
|
|
endif
|
|
endif
|
|
endif
|
|
eventfld.long 0x14 18. " PR18 ,Pending bit 18" "Not pending,Pending"
|
|
eventfld.long 0x14 17. " PR17 ,Pending bit 17" "Not pending,Pending"
|
|
eventfld.long 0x14 16. " PR16 ,Pending bit 16" "Not pending,Pending"
|
|
eventfld.long 0x14 15. " PR15 ,Pending bit 15" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x14 14. " PR14 ,Pending bit 14" "Not pending,Pending"
|
|
eventfld.long 0x14 13. " PR13 ,Pending bit 13" "Not pending,Pending"
|
|
eventfld.long 0x14 12. " PR12 ,Pending bit 12" "Not pending,Pending"
|
|
eventfld.long 0x14 11. " PR11 ,Pending bit 11" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x14 10. " PR10 ,Pending bit 10" "Not pending,Pending"
|
|
eventfld.long 0x14 9. " PR9 ,Pending bit 9" "Not pending,Pending"
|
|
eventfld.long 0x14 8. " PR8 ,Pending bit 8" "Not pending,Pending"
|
|
eventfld.long 0x14 7. " PR7 ,Pending bit 7" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x14 6. " PR6 ,Pending bit 6" "Not pending,Pending"
|
|
eventfld.long 0x14 5. " PR5 ,Pending bit 5" "Not pending,Pending"
|
|
eventfld.long 0x14 4. " PR4 ,Pending bit 4" "Not pending,Pending"
|
|
eventfld.long 0x14 3. " PR3 ,Pending bit 3" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x14 2. " PR2 ,Pending bit 2" "Not pending,Pending"
|
|
eventfld.long 0x14 1. " PR1 ,Pending bit 1" "Not pending,Pending"
|
|
eventfld.long 0x14 0. " PR0 ,Pending bit 0" "Not pending,Pending"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CRC (Cyclic Redundancy Check)"
|
|
base ad:0x40023000
|
|
width 6.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DR,Data Register"
|
|
line.long 0x04 "IDR,Independent Data Register"
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*")&&!cpuis("STM32H742*")&&!cpuis("STM32H750*"))
|
|
hexmask.long.byte 0x04 0.--7. 1. " IDR ,General-purpose 8-bit data register bits"
|
|
endif
|
|
line.long 0x08 "CR,Control Register"
|
|
bitfld.long 0x08 7. " REV_OUT ,Reverse output data" "Not reversed,Reversed"
|
|
bitfld.long 0x08 5.--6. " REV_IN ,Reverse input data" "Not reversed,By byte,By half-word,By word"
|
|
bitfld.long 0x08 3.--4. " POLYSIZE ,Polynomial size" "32-bit,16-bit,8-bit,7-bit"
|
|
bitfld.long 0x08 0. " RESET ,Reset CRC bit" "No reset,Reset"
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "INIT,Initial CRC Value"
|
|
line.long 0x04 "POL,CRC Polynomial"
|
|
width 0x0B
|
|
tree.end
|
|
sif (!cpuis("STM32F72?R*")&&!cpuis("STM32F73?R*"))
|
|
sif (cpuis("STM32F750V8")&&cpuis("STM32F730V8"))
|
|
tree "FMC (Flexible Memory Controller)"
|
|
base ad:0xA0000000
|
|
width 7.
|
|
tree "NOR/PSRAM Controller Registers"
|
|
group.long 0x0++0x07
|
|
line.long 0x00 "BCR1,SRAM/NOR-Flash Chip-select Control Register 1"
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*"))
|
|
bitfld.long 0x00 21. " WFDIS ,Write FIFO disable" "No,Yes"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 20. " CCLKEN ,Continuous clock enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " CBURSTRW ,Write burst enable" "Asynchronous,Synchronous"
|
|
sif (cpuis("STM32F4*")||cpuis("STM32F7*"))
|
|
newline
|
|
bitfld.long 0x00 16.--18. " CPSIZE ,CRAM page size" "No burst,128 bytes,256 bytes,512 bytes,1024 bytes,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 15. " ASYNCWAIT ,Wait signal during asynchronous transfers" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " EXTMOD ,Extended mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " WAITEN ,Wait enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WREN ,Write enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " WAITCFG ,Wait timing configuration" "One clock cycle,During wait state"
|
|
sif (cpuis("STM32F427*")||cpuis("STM32F429*")||cpuis("STM32F437*")||cpuis("STM32F439*"))
|
|
newline
|
|
bitfld.long 0x00 10. " WRAPMOD ,Wrapped burst mode support" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 9. " WAITPOL ,Wait signal polarity bit" "Active low,Active high"
|
|
bitfld.long 0x00 8. " BURSTEN ,Burst enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " FACCEN ,Flash access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MWID ,Memory data bus width" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 2.--3. " MTYP ,Memory type" "SRAM,PSRAM,NOR/OneNAND,?..."
|
|
newline
|
|
bitfld.long 0x00 1. " MUXEN ,Address/data multiplexing enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MBKEN ,Memory bank enable bit" "Disabled,Enabled"
|
|
line.long 0x04 "BTR1,SRAM/NOR-Flash Chip-select Timing Register 1"
|
|
bitfld.long 0x04 28.--29. " ACCMOD ,Access mode" "A,B,C,D"
|
|
bitfld.long 0x04 24.--27. " DATLAT ,Data latency" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17"
|
|
bitfld.long 0x04 20.--23. " CLKDIV ,Clock divide ratio" ",HCLK*2,HCLK*3,,,,,,,,,,,,,HCLK*16"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " BUSTURN ,Bus turnaround phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATAST ,Data-phase duration"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " ADDHLD ,Address-hold phase duration" ",HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
bitfld.long 0x04 0.--3. " ADDSET ,Address setup phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
group.long (0x0+0x104)++0x03
|
|
line.long 0x00 "BWTR1,SRAM/NOR-Flash Write Timing Register 1"
|
|
bitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "A,B,C,D"
|
|
bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
tree.end
|
|
width 7.
|
|
tree "NAND Flash/PC Card Controller Registers"
|
|
sif (cpuis("STM32F7*"))
|
|
group.long 0x80++0x0F
|
|
line.long 0x00 "PCR,PC Card/NAND Flash Control Register"
|
|
bitfld.long 0x00 17.--19. " ECCPS ,ECC page size" "256 bytes,512 bytes,1024 bytes,2048 bytes,4096 bytes,8192 bytes,?..."
|
|
bitfld.long 0x00 13.--16. " TAR ,ALE to RE delay" "1 HCLK,2 HCLK,3 HCLK,4 HCLK,5 HCLK,6 HCLK,7 HCLK,8 HCLK,9 HCLK,10 HCLK,11 HCLK,12 HCLK,13 HCLK,14 HCLK,15 HCLK,16 HCLK"
|
|
newline
|
|
bitfld.long 0x00 9.--12. " TCLR ,CLE to RE delay" "1 HCLK,2 HCLK,3 HCLK,4 HCLK,5 HCLK,6 HCLK,7 HCLK,8 HCLK,9 HCLK,10 HCLK,11 HCLK,12 HCLK,13 HCLK,14 HCLK,15 HCLK,16 HCLK"
|
|
bitfld.long 0x00 6. " ECCEN ,ECC computation logic enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " PWID ,Data bus width" "8 bits,16 bits,?..."
|
|
bitfld.long 0x00 3. " PTYP ,Memory type" ",NAND Flash"
|
|
newline
|
|
bitfld.long 0x00 2. " PBKEN ,PC card/NAND flash memory bank enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PWAITEN ,Wait feature enable bit" "Disabled,Enabled"
|
|
line.long 0x04 "SR,FIFO Status And Interrupt Register"
|
|
rbitfld.long 0x04 6. " FEMPT ,FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x04 5. " IFEN ,Interrupt falling edge detection enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 4. " ILEN ,Interrupt high-level detection enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " IREN ,Interrupt rising edge detection enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 2. " IFS ,Interrupt falling edge status" "Not occurred,Occurred"
|
|
bitfld.long 0x04 1. " ILS ,Interrupt high-level status" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x04 0. " IRS ,Interrupt rising edge status" "Not occurred,Occurred"
|
|
newline
|
|
line.long 0x08 "PMEM,Common Memory Space Timing Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " MEMHIZ ,Common memory data bus Hi-Z time"
|
|
hexmask.long.byte 0x08 16.--23. 1. " MEMHOLD ,Common memory hold time"
|
|
newline
|
|
hexmask.long.byte 0x08 8.--15. 1. " MEMWAIT ,Common memory wait time"
|
|
hexmask.long.byte 0x08 0.--7. 1. " MEMSET ,Common memory setup time"
|
|
line.long 0x0C "PATT,Attribute Memory Space Timing Register"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " ATTHIZ ,Attribute memory data bus Hi-Z time"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " ATTHOLD ,Attribute memory hold time"
|
|
newline
|
|
hexmask.long.byte 0x0C 8.--15. 1. " ATTWAIT ,Attribute memory wait time"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " ATTSET ,Attribute memory setup time"
|
|
if (((per.l((ad:0xA0000000+0x80)))&0xE0000)==0x00)
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "ECCR,ECC Result Register"
|
|
hexmask.long.tbyte 0x00 0.--21. 1. " ECC ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x80)))&0xE0000)==0x20000)
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "ECCR,ECC Result Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECC ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x80)))&0xE0000)==0x40000)
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "ECCR,ECC Result Register"
|
|
hexmask.long 0x00 0.--25. 1. " ECC ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x80)))&0xE0000)==0x60000)
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "ECCR,ECC Result Register"
|
|
hexmask.long 0x00 0.--27. 1. " ECC ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x80)))&0xE0000)==0x80000)
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "ECCR,ECC Result Register"
|
|
hexmask.long 0x00 0.--29. 1. " ECC ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x80)))&0xE0000)==0xA0000)
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "ECCR,ECC Result Register"
|
|
else
|
|
hgroup.long 0x94++0x03
|
|
hide.long 0x00 "ECCR,ECC Result Register"
|
|
endif
|
|
else
|
|
group.long 0x60++0x0F
|
|
line.long 0x00 "PCR2,PC Card/NAND Flash Control Registers 2"
|
|
bitfld.long 0x00 17.--19. " ECCPS ,ECC page size" "256 bytes,512 bytes,1024 bytes,2048 bytes,4096 bytes,8192 bytes,?..."
|
|
bitfld.long 0x00 13.--16. " TAR ,ALE to RE delay" "1 HCLK,2 HCLK,3 HCLK,4 HCLK,5 HCLK,6 HCLK,7 HCLK,8 HCLK,9 HCLK,10 HCLK,11 HCLK,12 HCLK,13 HCLK,14 HCLK,15 HCLK,16 HCLK"
|
|
newline
|
|
bitfld.long 0x00 9.--12. " TCLR ,CLE to RE delay" "1 HCLK,2 HCLK,3 HCLK,4 HCLK,5 HCLK,6 HCLK,7 HCLK,8 HCLK,9 HCLK,10 HCLK,11 HCLK,12 HCLK,13 HCLK,14 HCLK,15 HCLK,16 HCLK"
|
|
bitfld.long 0x00 6. " ECCEN ,ECC computation logic enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " PWID ,Databus width" "8 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " PTYP ,Memory type" "PC Card/CompactFlash/CF+/PCMCIA,NAND Flash"
|
|
newline
|
|
bitfld.long 0x00 2. " PBKEN ,PC card/NAND flash memory bank enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PWAITEN ,Wait feature enable bit" "Disabled,Enabled"
|
|
line.long 0x04 "SR2,FIFO Status And Interrupt Register 2"
|
|
rbitfld.long 0x04 6. " FEMPT ,FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x04 5. " IFEN ,Interrupt falling edge detection enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 4. " ILEN ,Interrupt high-level detection enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " IREN ,Interrupt rising edge detection enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 2. " IFS ,Interrupt falling edge status" "Not occurred,Occurred"
|
|
bitfld.long 0x04 1. " ILS ,Interrupt high-level status" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x04 0. " IRS ,Interrupt rising edge status" "Not occurred,Occurred"
|
|
line.long 0x08 "PMEM2,Common Memory Space Timing Register 2"
|
|
hexmask.long.byte 0x08 24.--31. 1. " MEMHIZ2 ,Common memory 2 data bus HiZ time"
|
|
hexmask.long.byte 0x08 16.--23. 1. " MEMHOLD2 ,Common memory 2 hold time"
|
|
newline
|
|
hexmask.long.byte 0x08 8.--15. 1. " MEMWAIT2 ,Common memory 2 wait time"
|
|
hexmask.long.byte 0x08 0.--7. 1. " MEMSET2 ,Common memory 2 setup time"
|
|
line.long 0x0C "PATT2,Attribute Memory Space Timing Register 2"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " ATTHIZ2 ,Attribute memory 2 databus HiZ time"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " ATTHOLD2 ,Attribute memory 2 hold time"
|
|
newline
|
|
hexmask.long.byte 0x0C 8.--15. 1. " ATTWAIT2 ,Attribute memory 2 wait time"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " ATTSET2 ,Attribute memory 2 setup time"
|
|
sif (!cpuis("STM32F7*"))
|
|
endif
|
|
if (((per.l((ad:0xA0000000+0x60)))&0xE0000)==0x00)
|
|
rgroup.long (0x60+0x14)++0x03
|
|
line.long 0x00 "ECCR2,ECC Result Register 2"
|
|
hexmask.long.tbyte 0x00 0.--21. 1. " ECC2 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x60)))&0xE0000)==0x20000)
|
|
rgroup.long (0x60+0x14)++0x03
|
|
line.long 0x00 "ECCR2,ECC Result Register 2"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECC2 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x60)))&0xE0000)==0x40000)
|
|
rgroup.long (0x60+0x14)++0x03
|
|
line.long 0x00 "ECCR2,ECC Result Register 2"
|
|
hexmask.long 0x00 0.--25. 1. " ECC2 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x60)))&0xE0000)==0x60000)
|
|
rgroup.long (0x60+0x14)++0x03
|
|
line.long 0x00 "ECCR2,ECC Result Register 2"
|
|
hexmask.long 0x00 0.--27. 1. " ECC2 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x60)))&0xE0000)==0x80000)
|
|
rgroup.long (0x60+0x14)++0x03
|
|
line.long 0x00 "ECCR2,ECC Result Register 2"
|
|
hexmask.long 0x00 0.--29. 1. " ECC2 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x60)))&0xE0000)==0xA0000)
|
|
rgroup.long (0x60+0x14)++0x03
|
|
line.long 0x00 "ECCR2,ECC Result Register 2"
|
|
else
|
|
hgroup.long (0x60+0x14)++0x03
|
|
hide.long 0x00 "ECCR2,ECC Result Register 2"
|
|
endif
|
|
group.long 0x80++0x0F
|
|
line.long 0x00 "PCR3,PC Card/NAND Flash Control Registers 3"
|
|
bitfld.long 0x00 17.--19. " ECCPS ,ECC page size" "256 bytes,512 bytes,1024 bytes,2048 bytes,4096 bytes,8192 bytes,?..."
|
|
bitfld.long 0x00 13.--16. " TAR ,ALE to RE delay" "1 HCLK,2 HCLK,3 HCLK,4 HCLK,5 HCLK,6 HCLK,7 HCLK,8 HCLK,9 HCLK,10 HCLK,11 HCLK,12 HCLK,13 HCLK,14 HCLK,15 HCLK,16 HCLK"
|
|
newline
|
|
bitfld.long 0x00 9.--12. " TCLR ,CLE to RE delay" "1 HCLK,2 HCLK,3 HCLK,4 HCLK,5 HCLK,6 HCLK,7 HCLK,8 HCLK,9 HCLK,10 HCLK,11 HCLK,12 HCLK,13 HCLK,14 HCLK,15 HCLK,16 HCLK"
|
|
bitfld.long 0x00 6. " ECCEN ,ECC computation logic enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " PWID ,Databus width" "8 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " PTYP ,Memory type" "PC Card/CompactFlash/CF+/PCMCIA,NAND Flash"
|
|
newline
|
|
bitfld.long 0x00 2. " PBKEN ,PC card/NAND flash memory bank enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PWAITEN ,Wait feature enable bit" "Disabled,Enabled"
|
|
line.long 0x04 "SR3,FIFO Status And Interrupt Register 3"
|
|
rbitfld.long 0x04 6. " FEMPT ,FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x04 5. " IFEN ,Interrupt falling edge detection enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 4. " ILEN ,Interrupt high-level detection enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " IREN ,Interrupt rising edge detection enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 2. " IFS ,Interrupt falling edge status" "Not occurred,Occurred"
|
|
bitfld.long 0x04 1. " ILS ,Interrupt high-level status" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x04 0. " IRS ,Interrupt rising edge status" "Not occurred,Occurred"
|
|
line.long 0x08 "PMEM3,Common Memory Space Timing Register 3"
|
|
hexmask.long.byte 0x08 24.--31. 1. " MEMHIZ3 ,Common memory 3 data bus HiZ time"
|
|
hexmask.long.byte 0x08 16.--23. 1. " MEMHOLD3 ,Common memory 3 hold time"
|
|
newline
|
|
hexmask.long.byte 0x08 8.--15. 1. " MEMWAIT3 ,Common memory 3 wait time"
|
|
hexmask.long.byte 0x08 0.--7. 1. " MEMSET3 ,Common memory 3 setup time"
|
|
line.long 0x0C "PATT3,Attribute Memory Space Timing Register 3"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " ATTHIZ3 ,Attribute memory 3 databus HiZ time"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " ATTHOLD3 ,Attribute memory 3 hold time"
|
|
newline
|
|
hexmask.long.byte 0x0C 8.--15. 1. " ATTWAIT3 ,Attribute memory 3 wait time"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " ATTSET3 ,Attribute memory 3 setup time"
|
|
sif (!cpuis("STM32F7*"))
|
|
endif
|
|
if (((per.l((ad:0xA0000000+0x80)))&0xE0000)==0x00)
|
|
rgroup.long (0x80+0x14)++0x03
|
|
line.long 0x00 "ECCR3,ECC Result Register 3"
|
|
hexmask.long.tbyte 0x00 0.--21. 1. " ECC3 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x80)))&0xE0000)==0x20000)
|
|
rgroup.long (0x80+0x14)++0x03
|
|
line.long 0x00 "ECCR3,ECC Result Register 3"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECC3 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x80)))&0xE0000)==0x40000)
|
|
rgroup.long (0x80+0x14)++0x03
|
|
line.long 0x00 "ECCR3,ECC Result Register 3"
|
|
hexmask.long 0x00 0.--25. 1. " ECC3 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x80)))&0xE0000)==0x60000)
|
|
rgroup.long (0x80+0x14)++0x03
|
|
line.long 0x00 "ECCR3,ECC Result Register 3"
|
|
hexmask.long 0x00 0.--27. 1. " ECC3 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x80)))&0xE0000)==0x80000)
|
|
rgroup.long (0x80+0x14)++0x03
|
|
line.long 0x00 "ECCR3,ECC Result Register 3"
|
|
hexmask.long 0x00 0.--29. 1. " ECC3 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x80)))&0xE0000)==0xA0000)
|
|
rgroup.long (0x80+0x14)++0x03
|
|
line.long 0x00 "ECCR3,ECC Result Register 3"
|
|
else
|
|
hgroup.long (0x80+0x14)++0x03
|
|
hide.long 0x00 "ECCR3,ECC Result Register 3"
|
|
endif
|
|
group.long 0xA0++0x0F
|
|
line.long 0x00 "PCR4,PC Card/NAND Flash Control Registers 4"
|
|
bitfld.long 0x00 17.--19. " ECCPS ,ECC page size" "256 bytes,512 bytes,1024 bytes,2048 bytes,4096 bytes,8192 bytes,?..."
|
|
bitfld.long 0x00 13.--16. " TAR ,ALE to RE delay" "1 HCLK,2 HCLK,3 HCLK,4 HCLK,5 HCLK,6 HCLK,7 HCLK,8 HCLK,9 HCLK,10 HCLK,11 HCLK,12 HCLK,13 HCLK,14 HCLK,15 HCLK,16 HCLK"
|
|
newline
|
|
bitfld.long 0x00 9.--12. " TCLR ,CLE to RE delay" "1 HCLK,2 HCLK,3 HCLK,4 HCLK,5 HCLK,6 HCLK,7 HCLK,8 HCLK,9 HCLK,10 HCLK,11 HCLK,12 HCLK,13 HCLK,14 HCLK,15 HCLK,16 HCLK"
|
|
bitfld.long 0x00 6. " ECCEN ,ECC computation logic enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " PWID ,Databus width" "8 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " PTYP ,Memory type" "PC Card/CompactFlash/CF+/PCMCIA,NAND Flash"
|
|
newline
|
|
bitfld.long 0x00 2. " PBKEN ,PC card/NAND flash memory bank enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PWAITEN ,Wait feature enable bit" "Disabled,Enabled"
|
|
line.long 0x04 "SR4,FIFO Status And Interrupt Register 4"
|
|
rbitfld.long 0x04 6. " FEMPT ,FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x04 5. " IFEN ,Interrupt falling edge detection enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 4. " ILEN ,Interrupt high-level detection enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " IREN ,Interrupt rising edge detection enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 2. " IFS ,Interrupt falling edge status" "Not occurred,Occurred"
|
|
bitfld.long 0x04 1. " ILS ,Interrupt high-level status" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x04 0. " IRS ,Interrupt rising edge status" "Not occurred,Occurred"
|
|
line.long 0x08 "PMEM4,Common Memory Space Timing Register 4"
|
|
hexmask.long.byte 0x08 24.--31. 1. " MEMHIZ4 ,Common memory 4 data bus HiZ time"
|
|
hexmask.long.byte 0x08 16.--23. 1. " MEMHOLD4 ,Common memory 4 hold time"
|
|
newline
|
|
hexmask.long.byte 0x08 8.--15. 1. " MEMWAIT4 ,Common memory 4 wait time"
|
|
hexmask.long.byte 0x08 0.--7. 1. " MEMSET4 ,Common memory 4 setup time"
|
|
line.long 0x0C "PATT4,Attribute Memory Space Timing Register 4"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " ATTHIZ4 ,Attribute memory 4 databus HiZ time"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " ATTHOLD4 ,Attribute memory 4 hold time"
|
|
newline
|
|
hexmask.long.byte 0x0C 8.--15. 1. " ATTWAIT4 ,Attribute memory 4 wait time"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " ATTSET4 ,Attribute memory 4 setup time"
|
|
sif (!cpuis("STM32F7*"))
|
|
group.long (0xA0+0x10)++0x03
|
|
line.long 0x00 "PIO4,I/O Space Timing Register 4"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IOHIZ4 ,I/O 4 data bus HiZ time"
|
|
hexmask.long.byte 0x00 16.--23. 1. " IOHOLD4 ,I/O 4 hold time"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " IOWAIT4 ,I/O 4 wait time"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IOSET4 ,I/O 4 setup time"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "SDRAM Controller Registers"
|
|
group.long 0x140++0x17
|
|
line.long 0x00 "SDCR1,SDRAM Control Register 1"
|
|
bitfld.long 0x00 13.--14. " RPIPE ,Read pipe" "No delay,1 cycle,2 cycles,?..."
|
|
bitfld.long 0x00 12. " RBURST ,Burst read" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SDCLK ,SDRAM clock configuration" "Disabled,,2*HCLK,3*HCLK"
|
|
newline
|
|
bitfld.long 0x00 9. " WP ,Write protection" "Disabled,Enabled"
|
|
bitfld.long 0x00 7.--8. " CAS ,CAS latency" ",1 cycle,2 cycles,3 cycles"
|
|
bitfld.long 0x00 6. " NB ,Number of internal banks" "2,4"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " MWID ,Memory data bus width" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 2.--3. " NR ,Number of row address bits" "11 bits,12 bits,13 bits,?..."
|
|
bitfld.long 0x00 0.--1. " NC ,Number of column address bits" "8 bits,9 bits,10 bits,11 bits"
|
|
line.long 0x04 "SDCR2,SDRAM Control Register 2"
|
|
rbitfld.long 0x04 13.--14. " RPIPE ,Read pipe" "No delay,1 cycle,2 cycles,?..."
|
|
bitfld.long 0x04 12. " RBURST ,Burst read" "Disabled,Enabled"
|
|
bitfld.long 0x04 10.--11. " SDCLK ,SDRAM clock configuration" "Disabled,,2*HCLK,3*HCLK"
|
|
newline
|
|
bitfld.long 0x04 9. " WP ,Write protection" "Disabled,Enabled"
|
|
bitfld.long 0x04 7.--8. " CAS ,CAS latency" ",1 cycle,2 cycles,3 cycles"
|
|
bitfld.long 0x04 6. " NB ,Number of internal banks" "2,4"
|
|
newline
|
|
bitfld.long 0x04 4.--5. " MWID ,Memory data bus width" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x04 2.--3. " NR ,Number of row address bits" "11 bits,12 bits,13 bits,?..."
|
|
bitfld.long 0x04 0.--1. " NC ,Number of column address bits" "8 bits,9 bits,10 bits,11 bits"
|
|
line.long 0x08 "SDTR1,SDRAM Timing Register 1"
|
|
bitfld.long 0x08 24.--27. " TRCD ,Row to column delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
bitfld.long 0x08 20.--23. " TRP ,Row precharge delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
bitfld.long 0x08 16.--19. " TWR ,Recovery delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
newline
|
|
bitfld.long 0x08 12.--15. " TRC ,Row cycle delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
bitfld.long 0x08 8.--11. " TRAS ,Self refresh time" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
bitfld.long 0x08 4.--7. " TXSR ,Exit self-refresh delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
newline
|
|
bitfld.long 0x08 0.--3. " TMRD ,Load mode register to active" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
line.long 0x0C "SDTR2,SDRAM Timing Register 2"
|
|
bitfld.long 0x0C 24.--27. " TRCD ,Row to column delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
rbitfld.long 0x0C 20.--23. " TRP ,Row precharge delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
bitfld.long 0x0C 16.--19. " TWR ,Recovery delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
newline
|
|
bitfld.long 0x0C 12.--15. " TRC ,Row cycle delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
bitfld.long 0x0C 8.--11. " TRAS ,Self refresh time" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
bitfld.long 0x0C 4.--7. " TXSR ,Exit self-refresh delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
newline
|
|
bitfld.long 0x0C 0.--3. " TMRD ,Load mode register to active" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
line.long 0x10 "SDCMR,SDRAM Command Mode Register"
|
|
hexmask.long.word 0x10 9.--21. 1. " MRD ,Mode register definition"
|
|
sif (cpuis("STM32F7*")||cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*"))
|
|
newline
|
|
bitfld.long 0x10 5.--8. " NRFS ,Number of auto-refresh" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
else
|
|
newline
|
|
bitfld.long 0x10 5.--8. " NRFS ,Number of auto-refresh" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x10 4. " CTB1 ,Command target bank 1" "Not issued,Issued"
|
|
sif (!cpuis("STM32F7??V?"))
|
|
newline
|
|
bitfld.long 0x10 3. " CTB2 ,Command target bank 2" "Not issued,Issued"
|
|
endif
|
|
bitfld.long 0x10 0.--2. " MODE ,Command mode" "Normal,Clock Configuration Enable,PALL,Auto-refresh,Load Mode Register,Self-refresh,Power-down,?..."
|
|
line.long 0x14 "SDRTR,SDRAM Refresh Timer Register"
|
|
bitfld.long 0x14 14. " REIE ,RES interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x14 1.--13. 1. " COUNT ,Refresh timer count"
|
|
bitfld.long 0x14 0. " CRE ,Clear refresh error flag" "No effect,Clear"
|
|
rgroup.long 0x158++0x03
|
|
line.long 0x00 "SDSR,SDRAM Status Register"
|
|
bitfld.long 0x00 5. " BUSY ,Busy status" "Idle,Busy"
|
|
bitfld.long 0x00 3.--4. " MODES2 ,Status mode for bank 2" "Normal,Self-refresh,Power-down,?..."
|
|
newline
|
|
bitfld.long 0x00 1.--2. " MODES1 ,Status mode for bank 1" "Normal,Self-refresh,Power-down,?..."
|
|
bitfld.long 0x00 0. " RE ,Refresh error flag" "No error,Error"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
tree "FMC (Flexible Memory Controller)"
|
|
base ad:0xA0000000
|
|
width 7.
|
|
tree "NOR/PSRAM Controller Registers"
|
|
group.long 0x0++0x07
|
|
line.long 0x00 "BCR1,SRAM/NOR-Flash Chip-select Control Register 1"
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*"))
|
|
bitfld.long 0x00 21. " WFDIS ,Write FIFO disable" "No,Yes"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 20. " CCLKEN ,Continuous clock enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " CBURSTRW ,Write burst enable" "Asynchronous,Synchronous"
|
|
sif (cpuis("STM32F4*")||cpuis("STM32F7*"))
|
|
newline
|
|
bitfld.long 0x00 16.--18. " CPSIZE ,CRAM page size" "No burst,128 bytes,256 bytes,512 bytes,1024 bytes,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 15. " ASYNCWAIT ,Wait signal during asynchronous transfers" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " EXTMOD ,Extended mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " WAITEN ,Wait enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WREN ,Write enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " WAITCFG ,Wait timing configuration" "One clock cycle,During wait state"
|
|
sif (cpuis("STM32F427*")||cpuis("STM32F429*")||cpuis("STM32F437*")||cpuis("STM32F439*"))
|
|
newline
|
|
bitfld.long 0x00 10. " WRAPMOD ,Wrapped burst mode support" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 9. " WAITPOL ,Wait signal polarity bit" "Active low,Active high"
|
|
bitfld.long 0x00 8. " BURSTEN ,Burst enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " FACCEN ,Flash access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MWID ,Memory data bus width" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 2.--3. " MTYP ,Memory type" "SRAM,PSRAM,NOR/OneNAND,?..."
|
|
newline
|
|
bitfld.long 0x00 1. " MUXEN ,Address/data multiplexing enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MBKEN ,Memory bank enable bit" "Disabled,Enabled"
|
|
line.long 0x04 "BTR1,SRAM/NOR-Flash Chip-select Timing Register 1"
|
|
bitfld.long 0x04 28.--29. " ACCMOD ,Access mode" "A,B,C,D"
|
|
bitfld.long 0x04 24.--27. " DATLAT ,Data latency" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17"
|
|
bitfld.long 0x04 20.--23. " CLKDIV ,Clock divide ratio" ",HCLK*2,HCLK*3,,,,,,,,,,,,,HCLK*16"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " BUSTURN ,Bus turnaround phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATAST ,Data-phase duration"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " ADDHLD ,Address-hold phase duration" ",HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
bitfld.long 0x04 0.--3. " ADDSET ,Address setup phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
group.long (0x0+0x104)++0x03
|
|
line.long 0x00 "BWTR1,SRAM/NOR-Flash Write Timing Register 1"
|
|
bitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "A,B,C,D"
|
|
bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
group.long 0x8++0x07
|
|
line.long 0x00 "BCR2,SRAM/NOR-Flash Chip-select Control Register 2"
|
|
bitfld.long 0x00 19. " CBURSTRW ,Write burst enable" "Asynchronous,Synchronous"
|
|
sif (cpuis("STM32F4*")||cpuis("STM32F7*"))
|
|
newline
|
|
bitfld.long 0x00 16.--18. " CPSIZE ,CRAM page size" "No burst,128 bytes,256 bytes,512 bytes,1024 bytes,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 15. " ASYNCWAIT ,Wait signal during asynchronous transfers" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " EXTMOD ,Extended mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " WAITEN ,Wait enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WREN ,Write enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " WAITCFG ,Wait timing configuration" "One clock cycle,During wait state"
|
|
sif (cpuis("STM32F427*")||cpuis("STM32F429*")||cpuis("STM32F437*")||cpuis("STM32F439*"))
|
|
newline
|
|
bitfld.long 0x00 10. " WRAPMOD ,Wrapped burst mode support" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 9. " WAITPOL ,Wait signal polarity bit" "Active low,Active high"
|
|
bitfld.long 0x00 8. " BURSTEN ,Burst enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " FACCEN ,Flash access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MWID ,Memory data bus width" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 2.--3. " MTYP ,Memory type" "SRAM,PSRAM,NOR/OneNAND,?..."
|
|
newline
|
|
bitfld.long 0x00 1. " MUXEN ,Address/data multiplexing enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MBKEN ,Memory bank enable bit" "Disabled,Enabled"
|
|
line.long 0x04 "BTR2,SRAM/NOR-Flash Chip-select Timing Register 2"
|
|
bitfld.long 0x04 28.--29. " ACCMOD ,Access mode" "A,B,C,D"
|
|
bitfld.long 0x04 24.--27. " DATLAT ,Data latency" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17"
|
|
bitfld.long 0x04 20.--23. " CLKDIV ,Clock divide ratio" ",HCLK*2,HCLK*3,,,,,,,,,,,,,HCLK*16"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " BUSTURN ,Bus turnaround phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATAST ,Data-phase duration"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " ADDHLD ,Address-hold phase duration" ",HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
bitfld.long 0x04 0.--3. " ADDSET ,Address setup phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
group.long (0x8+0x104)++0x03
|
|
line.long 0x00 "BWTR2,SRAM/NOR-Flash Write Timing Register 2"
|
|
bitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "A,B,C,D"
|
|
bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "BCR3,SRAM/NOR-Flash Chip-select Control Register 3"
|
|
bitfld.long 0x00 19. " CBURSTRW ,Write burst enable" "Asynchronous,Synchronous"
|
|
sif (cpuis("STM32F4*")||cpuis("STM32F7*"))
|
|
newline
|
|
bitfld.long 0x00 16.--18. " CPSIZE ,CRAM page size" "No burst,128 bytes,256 bytes,512 bytes,1024 bytes,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 15. " ASYNCWAIT ,Wait signal during asynchronous transfers" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " EXTMOD ,Extended mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " WAITEN ,Wait enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WREN ,Write enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " WAITCFG ,Wait timing configuration" "One clock cycle,During wait state"
|
|
sif (cpuis("STM32F427*")||cpuis("STM32F429*")||cpuis("STM32F437*")||cpuis("STM32F439*"))
|
|
newline
|
|
bitfld.long 0x00 10. " WRAPMOD ,Wrapped burst mode support" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 9. " WAITPOL ,Wait signal polarity bit" "Active low,Active high"
|
|
bitfld.long 0x00 8. " BURSTEN ,Burst enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " FACCEN ,Flash access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MWID ,Memory data bus width" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 2.--3. " MTYP ,Memory type" "SRAM,PSRAM,NOR/OneNAND,?..."
|
|
newline
|
|
bitfld.long 0x00 1. " MUXEN ,Address/data multiplexing enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MBKEN ,Memory bank enable bit" "Disabled,Enabled"
|
|
line.long 0x04 "BTR3,SRAM/NOR-Flash Chip-select Timing Register 3"
|
|
bitfld.long 0x04 28.--29. " ACCMOD ,Access mode" "A,B,C,D"
|
|
bitfld.long 0x04 24.--27. " DATLAT ,Data latency" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17"
|
|
bitfld.long 0x04 20.--23. " CLKDIV ,Clock divide ratio" ",HCLK*2,HCLK*3,,,,,,,,,,,,,HCLK*16"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " BUSTURN ,Bus turnaround phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATAST ,Data-phase duration"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " ADDHLD ,Address-hold phase duration" ",HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
bitfld.long 0x04 0.--3. " ADDSET ,Address setup phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
group.long (0x10+0x104)++0x03
|
|
line.long 0x00 "BWTR3,SRAM/NOR-Flash Write Timing Register 3"
|
|
bitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "A,B,C,D"
|
|
bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
group.long 0x18++0x07
|
|
line.long 0x00 "BCR4,SRAM/NOR-Flash Chip-select Control Register 4"
|
|
bitfld.long 0x00 19. " CBURSTRW ,Write burst enable" "Asynchronous,Synchronous"
|
|
sif (cpuis("STM32F4*")||cpuis("STM32F7*"))
|
|
newline
|
|
bitfld.long 0x00 16.--18. " CPSIZE ,CRAM page size" "No burst,128 bytes,256 bytes,512 bytes,1024 bytes,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 15. " ASYNCWAIT ,Wait signal during asynchronous transfers" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " EXTMOD ,Extended mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " WAITEN ,Wait enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WREN ,Write enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " WAITCFG ,Wait timing configuration" "One clock cycle,During wait state"
|
|
sif (cpuis("STM32F427*")||cpuis("STM32F429*")||cpuis("STM32F437*")||cpuis("STM32F439*"))
|
|
newline
|
|
bitfld.long 0x00 10. " WRAPMOD ,Wrapped burst mode support" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 9. " WAITPOL ,Wait signal polarity bit" "Active low,Active high"
|
|
bitfld.long 0x00 8. " BURSTEN ,Burst enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " FACCEN ,Flash access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MWID ,Memory data bus width" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 2.--3. " MTYP ,Memory type" "SRAM,PSRAM,NOR/OneNAND,?..."
|
|
newline
|
|
bitfld.long 0x00 1. " MUXEN ,Address/data multiplexing enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MBKEN ,Memory bank enable bit" "Disabled,Enabled"
|
|
line.long 0x04 "BTR4,SRAM/NOR-Flash Chip-select Timing Register 4"
|
|
bitfld.long 0x04 28.--29. " ACCMOD ,Access mode" "A,B,C,D"
|
|
bitfld.long 0x04 24.--27. " DATLAT ,Data latency" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17"
|
|
bitfld.long 0x04 20.--23. " CLKDIV ,Clock divide ratio" ",HCLK*2,HCLK*3,,,,,,,,,,,,,HCLK*16"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " BUSTURN ,Bus turnaround phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATAST ,Data-phase duration"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " ADDHLD ,Address-hold phase duration" ",HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
bitfld.long 0x04 0.--3. " ADDSET ,Address setup phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
group.long (0x18+0x104)++0x03
|
|
line.long 0x00 "BWTR4,SRAM/NOR-Flash Write Timing Register 4"
|
|
bitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "A,B,C,D"
|
|
bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
tree.end
|
|
width 7.
|
|
tree "NAND Flash/PC Card Controller Registers"
|
|
sif (cpuis("STM32F7*"))
|
|
group.long 0x80++0x0F
|
|
line.long 0x00 "PCR,PC Card/NAND Flash Control Register"
|
|
bitfld.long 0x00 17.--19. " ECCPS ,ECC page size" "256 bytes,512 bytes,1024 bytes,2048 bytes,4096 bytes,8192 bytes,?..."
|
|
bitfld.long 0x00 13.--16. " TAR ,ALE to RE delay" "1 HCLK,2 HCLK,3 HCLK,4 HCLK,5 HCLK,6 HCLK,7 HCLK,8 HCLK,9 HCLK,10 HCLK,11 HCLK,12 HCLK,13 HCLK,14 HCLK,15 HCLK,16 HCLK"
|
|
newline
|
|
bitfld.long 0x00 9.--12. " TCLR ,CLE to RE delay" "1 HCLK,2 HCLK,3 HCLK,4 HCLK,5 HCLK,6 HCLK,7 HCLK,8 HCLK,9 HCLK,10 HCLK,11 HCLK,12 HCLK,13 HCLK,14 HCLK,15 HCLK,16 HCLK"
|
|
bitfld.long 0x00 6. " ECCEN ,ECC computation logic enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " PWID ,Data bus width" "8 bits,16 bits,?..."
|
|
bitfld.long 0x00 3. " PTYP ,Memory type" ",NAND Flash"
|
|
newline
|
|
bitfld.long 0x00 2. " PBKEN ,PC card/NAND flash memory bank enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PWAITEN ,Wait feature enable bit" "Disabled,Enabled"
|
|
line.long 0x04 "SR,FIFO Status And Interrupt Register"
|
|
rbitfld.long 0x04 6. " FEMPT ,FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x04 5. " IFEN ,Interrupt falling edge detection enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 4. " ILEN ,Interrupt high-level detection enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " IREN ,Interrupt rising edge detection enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 2. " IFS ,Interrupt falling edge status" "Not occurred,Occurred"
|
|
bitfld.long 0x04 1. " ILS ,Interrupt high-level status" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x04 0. " IRS ,Interrupt rising edge status" "Not occurred,Occurred"
|
|
newline
|
|
line.long 0x08 "PMEM,Common Memory Space Timing Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " MEMHIZ ,Common memory data bus Hi-Z time"
|
|
hexmask.long.byte 0x08 16.--23. 1. " MEMHOLD ,Common memory hold time"
|
|
newline
|
|
hexmask.long.byte 0x08 8.--15. 1. " MEMWAIT ,Common memory wait time"
|
|
hexmask.long.byte 0x08 0.--7. 1. " MEMSET ,Common memory setup time"
|
|
line.long 0x0C "PATT,Attribute Memory Space Timing Register"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " ATTHIZ ,Attribute memory data bus Hi-Z time"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " ATTHOLD ,Attribute memory hold time"
|
|
newline
|
|
hexmask.long.byte 0x0C 8.--15. 1. " ATTWAIT ,Attribute memory wait time"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " ATTSET ,Attribute memory setup time"
|
|
if (((per.l((ad:0xA0000000+0x80)))&0xE0000)==0x00)
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "ECCR,ECC Result Register"
|
|
hexmask.long.tbyte 0x00 0.--21. 1. " ECC ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x80)))&0xE0000)==0x20000)
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "ECCR,ECC Result Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECC ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x80)))&0xE0000)==0x40000)
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "ECCR,ECC Result Register"
|
|
hexmask.long 0x00 0.--25. 1. " ECC ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x80)))&0xE0000)==0x60000)
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "ECCR,ECC Result Register"
|
|
hexmask.long 0x00 0.--27. 1. " ECC ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x80)))&0xE0000)==0x80000)
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "ECCR,ECC Result Register"
|
|
hexmask.long 0x00 0.--29. 1. " ECC ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x80)))&0xE0000)==0xA0000)
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "ECCR,ECC Result Register"
|
|
else
|
|
hgroup.long 0x94++0x03
|
|
hide.long 0x00 "ECCR,ECC Result Register"
|
|
endif
|
|
else
|
|
group.long 0x60++0x0F
|
|
line.long 0x00 "PCR2,PC Card/NAND Flash Control Registers 2"
|
|
bitfld.long 0x00 17.--19. " ECCPS ,ECC page size" "256 bytes,512 bytes,1024 bytes,2048 bytes,4096 bytes,8192 bytes,?..."
|
|
bitfld.long 0x00 13.--16. " TAR ,ALE to RE delay" "1 HCLK,2 HCLK,3 HCLK,4 HCLK,5 HCLK,6 HCLK,7 HCLK,8 HCLK,9 HCLK,10 HCLK,11 HCLK,12 HCLK,13 HCLK,14 HCLK,15 HCLK,16 HCLK"
|
|
newline
|
|
bitfld.long 0x00 9.--12. " TCLR ,CLE to RE delay" "1 HCLK,2 HCLK,3 HCLK,4 HCLK,5 HCLK,6 HCLK,7 HCLK,8 HCLK,9 HCLK,10 HCLK,11 HCLK,12 HCLK,13 HCLK,14 HCLK,15 HCLK,16 HCLK"
|
|
bitfld.long 0x00 6. " ECCEN ,ECC computation logic enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " PWID ,Databus width" "8 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " PTYP ,Memory type" "PC Card/CompactFlash/CF+/PCMCIA,NAND Flash"
|
|
newline
|
|
bitfld.long 0x00 2. " PBKEN ,PC card/NAND flash memory bank enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PWAITEN ,Wait feature enable bit" "Disabled,Enabled"
|
|
line.long 0x04 "SR2,FIFO Status And Interrupt Register 2"
|
|
rbitfld.long 0x04 6. " FEMPT ,FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x04 5. " IFEN ,Interrupt falling edge detection enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 4. " ILEN ,Interrupt high-level detection enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " IREN ,Interrupt rising edge detection enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 2. " IFS ,Interrupt falling edge status" "Not occurred,Occurred"
|
|
bitfld.long 0x04 1. " ILS ,Interrupt high-level status" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x04 0. " IRS ,Interrupt rising edge status" "Not occurred,Occurred"
|
|
line.long 0x08 "PMEM2,Common Memory Space Timing Register 2"
|
|
hexmask.long.byte 0x08 24.--31. 1. " MEMHIZ2 ,Common memory 2 data bus HiZ time"
|
|
hexmask.long.byte 0x08 16.--23. 1. " MEMHOLD2 ,Common memory 2 hold time"
|
|
newline
|
|
hexmask.long.byte 0x08 8.--15. 1. " MEMWAIT2 ,Common memory 2 wait time"
|
|
hexmask.long.byte 0x08 0.--7. 1. " MEMSET2 ,Common memory 2 setup time"
|
|
line.long 0x0C "PATT2,Attribute Memory Space Timing Register 2"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " ATTHIZ2 ,Attribute memory 2 databus HiZ time"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " ATTHOLD2 ,Attribute memory 2 hold time"
|
|
newline
|
|
hexmask.long.byte 0x0C 8.--15. 1. " ATTWAIT2 ,Attribute memory 2 wait time"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " ATTSET2 ,Attribute memory 2 setup time"
|
|
sif (!cpuis("STM32F7*"))
|
|
endif
|
|
if (((per.l((ad:0xA0000000+0x60)))&0xE0000)==0x00)
|
|
rgroup.long (0x60+0x14)++0x03
|
|
line.long 0x00 "ECCR2,ECC Result Register 2"
|
|
hexmask.long.tbyte 0x00 0.--21. 1. " ECC2 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x60)))&0xE0000)==0x20000)
|
|
rgroup.long (0x60+0x14)++0x03
|
|
line.long 0x00 "ECCR2,ECC Result Register 2"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECC2 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x60)))&0xE0000)==0x40000)
|
|
rgroup.long (0x60+0x14)++0x03
|
|
line.long 0x00 "ECCR2,ECC Result Register 2"
|
|
hexmask.long 0x00 0.--25. 1. " ECC2 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x60)))&0xE0000)==0x60000)
|
|
rgroup.long (0x60+0x14)++0x03
|
|
line.long 0x00 "ECCR2,ECC Result Register 2"
|
|
hexmask.long 0x00 0.--27. 1. " ECC2 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x60)))&0xE0000)==0x80000)
|
|
rgroup.long (0x60+0x14)++0x03
|
|
line.long 0x00 "ECCR2,ECC Result Register 2"
|
|
hexmask.long 0x00 0.--29. 1. " ECC2 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x60)))&0xE0000)==0xA0000)
|
|
rgroup.long (0x60+0x14)++0x03
|
|
line.long 0x00 "ECCR2,ECC Result Register 2"
|
|
else
|
|
hgroup.long (0x60+0x14)++0x03
|
|
hide.long 0x00 "ECCR2,ECC Result Register 2"
|
|
endif
|
|
group.long 0x80++0x0F
|
|
line.long 0x00 "PCR3,PC Card/NAND Flash Control Registers 3"
|
|
bitfld.long 0x00 17.--19. " ECCPS ,ECC page size" "256 bytes,512 bytes,1024 bytes,2048 bytes,4096 bytes,8192 bytes,?..."
|
|
bitfld.long 0x00 13.--16. " TAR ,ALE to RE delay" "1 HCLK,2 HCLK,3 HCLK,4 HCLK,5 HCLK,6 HCLK,7 HCLK,8 HCLK,9 HCLK,10 HCLK,11 HCLK,12 HCLK,13 HCLK,14 HCLK,15 HCLK,16 HCLK"
|
|
newline
|
|
bitfld.long 0x00 9.--12. " TCLR ,CLE to RE delay" "1 HCLK,2 HCLK,3 HCLK,4 HCLK,5 HCLK,6 HCLK,7 HCLK,8 HCLK,9 HCLK,10 HCLK,11 HCLK,12 HCLK,13 HCLK,14 HCLK,15 HCLK,16 HCLK"
|
|
bitfld.long 0x00 6. " ECCEN ,ECC computation logic enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " PWID ,Databus width" "8 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " PTYP ,Memory type" "PC Card/CompactFlash/CF+/PCMCIA,NAND Flash"
|
|
newline
|
|
bitfld.long 0x00 2. " PBKEN ,PC card/NAND flash memory bank enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PWAITEN ,Wait feature enable bit" "Disabled,Enabled"
|
|
line.long 0x04 "SR3,FIFO Status And Interrupt Register 3"
|
|
rbitfld.long 0x04 6. " FEMPT ,FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x04 5. " IFEN ,Interrupt falling edge detection enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 4. " ILEN ,Interrupt high-level detection enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " IREN ,Interrupt rising edge detection enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 2. " IFS ,Interrupt falling edge status" "Not occurred,Occurred"
|
|
bitfld.long 0x04 1. " ILS ,Interrupt high-level status" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x04 0. " IRS ,Interrupt rising edge status" "Not occurred,Occurred"
|
|
line.long 0x08 "PMEM3,Common Memory Space Timing Register 3"
|
|
hexmask.long.byte 0x08 24.--31. 1. " MEMHIZ3 ,Common memory 3 data bus HiZ time"
|
|
hexmask.long.byte 0x08 16.--23. 1. " MEMHOLD3 ,Common memory 3 hold time"
|
|
newline
|
|
hexmask.long.byte 0x08 8.--15. 1. " MEMWAIT3 ,Common memory 3 wait time"
|
|
hexmask.long.byte 0x08 0.--7. 1. " MEMSET3 ,Common memory 3 setup time"
|
|
line.long 0x0C "PATT3,Attribute Memory Space Timing Register 3"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " ATTHIZ3 ,Attribute memory 3 databus HiZ time"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " ATTHOLD3 ,Attribute memory 3 hold time"
|
|
newline
|
|
hexmask.long.byte 0x0C 8.--15. 1. " ATTWAIT3 ,Attribute memory 3 wait time"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " ATTSET3 ,Attribute memory 3 setup time"
|
|
sif (!cpuis("STM32F7*"))
|
|
endif
|
|
if (((per.l((ad:0xA0000000+0x80)))&0xE0000)==0x00)
|
|
rgroup.long (0x80+0x14)++0x03
|
|
line.long 0x00 "ECCR3,ECC Result Register 3"
|
|
hexmask.long.tbyte 0x00 0.--21. 1. " ECC3 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x80)))&0xE0000)==0x20000)
|
|
rgroup.long (0x80+0x14)++0x03
|
|
line.long 0x00 "ECCR3,ECC Result Register 3"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECC3 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x80)))&0xE0000)==0x40000)
|
|
rgroup.long (0x80+0x14)++0x03
|
|
line.long 0x00 "ECCR3,ECC Result Register 3"
|
|
hexmask.long 0x00 0.--25. 1. " ECC3 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x80)))&0xE0000)==0x60000)
|
|
rgroup.long (0x80+0x14)++0x03
|
|
line.long 0x00 "ECCR3,ECC Result Register 3"
|
|
hexmask.long 0x00 0.--27. 1. " ECC3 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x80)))&0xE0000)==0x80000)
|
|
rgroup.long (0x80+0x14)++0x03
|
|
line.long 0x00 "ECCR3,ECC Result Register 3"
|
|
hexmask.long 0x00 0.--29. 1. " ECC3 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x80)))&0xE0000)==0xA0000)
|
|
rgroup.long (0x80+0x14)++0x03
|
|
line.long 0x00 "ECCR3,ECC Result Register 3"
|
|
else
|
|
hgroup.long (0x80+0x14)++0x03
|
|
hide.long 0x00 "ECCR3,ECC Result Register 3"
|
|
endif
|
|
group.long 0xA0++0x0F
|
|
line.long 0x00 "PCR4,PC Card/NAND Flash Control Registers 4"
|
|
bitfld.long 0x00 17.--19. " ECCPS ,ECC page size" "256 bytes,512 bytes,1024 bytes,2048 bytes,4096 bytes,8192 bytes,?..."
|
|
bitfld.long 0x00 13.--16. " TAR ,ALE to RE delay" "1 HCLK,2 HCLK,3 HCLK,4 HCLK,5 HCLK,6 HCLK,7 HCLK,8 HCLK,9 HCLK,10 HCLK,11 HCLK,12 HCLK,13 HCLK,14 HCLK,15 HCLK,16 HCLK"
|
|
newline
|
|
bitfld.long 0x00 9.--12. " TCLR ,CLE to RE delay" "1 HCLK,2 HCLK,3 HCLK,4 HCLK,5 HCLK,6 HCLK,7 HCLK,8 HCLK,9 HCLK,10 HCLK,11 HCLK,12 HCLK,13 HCLK,14 HCLK,15 HCLK,16 HCLK"
|
|
bitfld.long 0x00 6. " ECCEN ,ECC computation logic enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " PWID ,Databus width" "8 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " PTYP ,Memory type" "PC Card/CompactFlash/CF+/PCMCIA,NAND Flash"
|
|
newline
|
|
bitfld.long 0x00 2. " PBKEN ,PC card/NAND flash memory bank enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PWAITEN ,Wait feature enable bit" "Disabled,Enabled"
|
|
line.long 0x04 "SR4,FIFO Status And Interrupt Register 4"
|
|
rbitfld.long 0x04 6. " FEMPT ,FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x04 5. " IFEN ,Interrupt falling edge detection enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 4. " ILEN ,Interrupt high-level detection enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " IREN ,Interrupt rising edge detection enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 2. " IFS ,Interrupt falling edge status" "Not occurred,Occurred"
|
|
bitfld.long 0x04 1. " ILS ,Interrupt high-level status" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x04 0. " IRS ,Interrupt rising edge status" "Not occurred,Occurred"
|
|
line.long 0x08 "PMEM4,Common Memory Space Timing Register 4"
|
|
hexmask.long.byte 0x08 24.--31. 1. " MEMHIZ4 ,Common memory 4 data bus HiZ time"
|
|
hexmask.long.byte 0x08 16.--23. 1. " MEMHOLD4 ,Common memory 4 hold time"
|
|
newline
|
|
hexmask.long.byte 0x08 8.--15. 1. " MEMWAIT4 ,Common memory 4 wait time"
|
|
hexmask.long.byte 0x08 0.--7. 1. " MEMSET4 ,Common memory 4 setup time"
|
|
line.long 0x0C "PATT4,Attribute Memory Space Timing Register 4"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " ATTHIZ4 ,Attribute memory 4 databus HiZ time"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " ATTHOLD4 ,Attribute memory 4 hold time"
|
|
newline
|
|
hexmask.long.byte 0x0C 8.--15. 1. " ATTWAIT4 ,Attribute memory 4 wait time"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " ATTSET4 ,Attribute memory 4 setup time"
|
|
sif (!cpuis("STM32F7*"))
|
|
group.long (0xA0+0x10)++0x03
|
|
line.long 0x00 "PIO4,I/O Space Timing Register 4"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IOHIZ4 ,I/O 4 data bus HiZ time"
|
|
hexmask.long.byte 0x00 16.--23. 1. " IOHOLD4 ,I/O 4 hold time"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " IOWAIT4 ,I/O 4 wait time"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IOSET4 ,I/O 4 setup time"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "SDRAM Controller Registers"
|
|
group.long 0x140++0x17
|
|
line.long 0x00 "SDCR1,SDRAM Control Register 1"
|
|
bitfld.long 0x00 13.--14. " RPIPE ,Read pipe" "No delay,1 cycle,2 cycles,?..."
|
|
bitfld.long 0x00 12. " RBURST ,Burst read" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SDCLK ,SDRAM clock configuration" "Disabled,,2*HCLK,3*HCLK"
|
|
newline
|
|
bitfld.long 0x00 9. " WP ,Write protection" "Disabled,Enabled"
|
|
bitfld.long 0x00 7.--8. " CAS ,CAS latency" ",1 cycle,2 cycles,3 cycles"
|
|
bitfld.long 0x00 6. " NB ,Number of internal banks" "2,4"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " MWID ,Memory data bus width" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 2.--3. " NR ,Number of row address bits" "11 bits,12 bits,13 bits,?..."
|
|
bitfld.long 0x00 0.--1. " NC ,Number of column address bits" "8 bits,9 bits,10 bits,11 bits"
|
|
line.long 0x04 "SDCR2,SDRAM Control Register 2"
|
|
rbitfld.long 0x04 13.--14. " RPIPE ,Read pipe" "No delay,1 cycle,2 cycles,?..."
|
|
bitfld.long 0x04 12. " RBURST ,Burst read" "Disabled,Enabled"
|
|
bitfld.long 0x04 10.--11. " SDCLK ,SDRAM clock configuration" "Disabled,,2*HCLK,3*HCLK"
|
|
newline
|
|
bitfld.long 0x04 9. " WP ,Write protection" "Disabled,Enabled"
|
|
bitfld.long 0x04 7.--8. " CAS ,CAS latency" ",1 cycle,2 cycles,3 cycles"
|
|
bitfld.long 0x04 6. " NB ,Number of internal banks" "2,4"
|
|
newline
|
|
bitfld.long 0x04 4.--5. " MWID ,Memory data bus width" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x04 2.--3. " NR ,Number of row address bits" "11 bits,12 bits,13 bits,?..."
|
|
bitfld.long 0x04 0.--1. " NC ,Number of column address bits" "8 bits,9 bits,10 bits,11 bits"
|
|
line.long 0x08 "SDTR1,SDRAM Timing Register 1"
|
|
bitfld.long 0x08 24.--27. " TRCD ,Row to column delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
bitfld.long 0x08 20.--23. " TRP ,Row precharge delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
bitfld.long 0x08 16.--19. " TWR ,Recovery delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
newline
|
|
bitfld.long 0x08 12.--15. " TRC ,Row cycle delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
bitfld.long 0x08 8.--11. " TRAS ,Self refresh time" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
bitfld.long 0x08 4.--7. " TXSR ,Exit self-refresh delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
newline
|
|
bitfld.long 0x08 0.--3. " TMRD ,Load mode register to active" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
line.long 0x0C "SDTR2,SDRAM Timing Register 2"
|
|
bitfld.long 0x0C 24.--27. " TRCD ,Row to column delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
rbitfld.long 0x0C 20.--23. " TRP ,Row precharge delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
bitfld.long 0x0C 16.--19. " TWR ,Recovery delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
newline
|
|
bitfld.long 0x0C 12.--15. " TRC ,Row cycle delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
bitfld.long 0x0C 8.--11. " TRAS ,Self refresh time" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
bitfld.long 0x0C 4.--7. " TXSR ,Exit self-refresh delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
newline
|
|
bitfld.long 0x0C 0.--3. " TMRD ,Load mode register to active" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
line.long 0x10 "SDCMR,SDRAM Command Mode Register"
|
|
hexmask.long.word 0x10 9.--21. 1. " MRD ,Mode register definition"
|
|
sif (cpuis("STM32F7*")||cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*"))
|
|
newline
|
|
bitfld.long 0x10 5.--8. " NRFS ,Number of auto-refresh" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles"
|
|
else
|
|
newline
|
|
bitfld.long 0x10 5.--8. " NRFS ,Number of auto-refresh" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x10 4. " CTB1 ,Command target bank 1" "Not issued,Issued"
|
|
sif (!cpuis("STM32F7??V?"))
|
|
newline
|
|
bitfld.long 0x10 3. " CTB2 ,Command target bank 2" "Not issued,Issued"
|
|
endif
|
|
bitfld.long 0x10 0.--2. " MODE ,Command mode" "Normal,Clock Configuration Enable,PALL,Auto-refresh,Load Mode Register,Self-refresh,Power-down,?..."
|
|
line.long 0x14 "SDRTR,SDRAM Refresh Timer Register"
|
|
bitfld.long 0x14 14. " REIE ,RES interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x14 1.--13. 1. " COUNT ,Refresh timer count"
|
|
bitfld.long 0x14 0. " CRE ,Clear refresh error flag" "No effect,Clear"
|
|
rgroup.long 0x158++0x03
|
|
line.long 0x00 "SDSR,SDRAM Status Register"
|
|
bitfld.long 0x00 5. " BUSY ,Busy status" "Idle,Busy"
|
|
bitfld.long 0x00 3.--4. " MODES2 ,Status mode for bank 2" "Normal,Self-refresh,Power-down,?..."
|
|
newline
|
|
bitfld.long 0x00 1.--2. " MODES1 ,Status mode for bank 1" "Normal,Self-refresh,Power-down,?..."
|
|
bitfld.long 0x00 0. " RE ,Refresh error flag" "No error,Error"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
endif
|
|
tree "QUADSPI (QuadSPI)"
|
|
base ad:0xA0001000
|
|
width 7.
|
|
if ((((per.l(ad:0xA0001014))&0xC000000)==0x00)&&(((per.l(ad:0xA0001008))&0x20)==0x00))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,QUADSPI Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESCALER ,Clock prescaler"
|
|
bitfld.long 0x00 23. " PMM ,Polling match mode" "AND mode,OR mode"
|
|
bitfld.long 0x00 22. " APMS ,Automatic poll mode stop" "Running,Stopped"
|
|
bitfld.long 0x00 20. " TOIE ,TimeOut interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " SMIE ,Status match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " FTIE ,FIFO threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
bitfld.long 0x00 8.--12. " FTHRES ,FIFO threshold level" "Free>=1,Free>=2,Free>=3,Free>=4,Free>=5,Free>=6,Free>=7,Free>=8,Free>=9,Free>=10,Free>=11,Free>=12,Free>=13,Free>=14,Free>=15,Free>=16,Free>=17,Free>=18,Free>=19,Free>=20,Free>=21,Free>=22,Free>=23,Free>=24,Free>=25,Free>=26,Free>=27,Free>=28,Free>=29,Free>=30,Free>=31,Free>=32"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 8.--11. " FTHRES ,FIFO threshold level" "Free>=1,Free>=2,Free>=3,Free>=4,Free>=5,Free>=6,Free>=7,Free>=8,Free>=9,Free>=10,Free>=11,Free>=12,Free>=13,Free>=14,Free>=15,Free>=16"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
bitfld.long 0x00 7. " FSEL ,Flash memory selection" "FLASH 1,FLASH 2"
|
|
bitfld.long 0x00 6. " DFM ,Dual-flash mode enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 4. " SSHIFT ,Sample shift" "No shift,1/2 cycle shift"
|
|
newline
|
|
sif !cpuis("STM32H743*")&&!cpuis("STM32H753*")
|
|
bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " ABORT ,Abort request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " EN ,Enable the QUADSPI" "Disabled,Enabled"
|
|
elif ((((per.l(ad:0xA0001014))&0xC000000)==0x00)&&(((per.l(ad:0xA0001008))&0x20)==0x20))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,QUADSPI Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESCALER ,Clock prescaler"
|
|
rbitfld.long 0x00 23. " PMM ,Polling match mode" "AND mode,OR mode"
|
|
rbitfld.long 0x00 22. " APMS ,Automatic poll mode stop" "Running,Stopped"
|
|
bitfld.long 0x00 20. " TOIE ,TimeOut interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " SMIE ,Status match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " FTIE ,FIFO threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
bitfld.long 0x00 8.--12. " FTHRES ,FIFO threshold level" "Free>=1,Free>=2,Free>=3,Free>=4,Free>=5,Free>=6,Free>=7,Free>=8,Free>=9,Free>=10,Free>=11,Free>=12,Free>=13,Free>=14,Free>=15,Free>=16,Free>=17,Free>=18,Free>=19,Free>=20,Free>=21,Free>=22,Free>=23,Free>=24,Free>=25,Free>=26,Free>=27,Free>=28,Free>=29,Free>=30,Free>=31,Free>=32"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 8.--11. " FTHRES ,FIFO threshold level" "Free>=1,Free>=2,Free>=3,Free>=4,Free>=5,Free>=6,Free>=7,Free>=8,Free>=9,Free>=10,Free>=11,Free>=12,Free>=13,Free>=14,Free>=15,Free>=16"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
rbitfld.long 0x00 7. " FSEL ,Flash memory selection" "FLASH 1,FLASH 2"
|
|
rbitfld.long 0x00 6. " DFM ,Dual-flash mode enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
rbitfld.long 0x00 4. " SSHIFT ,Sample shift" "No shift,1/2 cycle shift"
|
|
newline
|
|
sif !cpuis("STM32H743*")&&!cpuis("STM32H753*")
|
|
bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " ABORT ,Abort request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " EN ,Enable the QUADSPI" "Disabled,Enabled"
|
|
elif ((((per.l(ad:0xA0001014))&0xC000000)==0x4000000)&&(((per.l(ad:0xA0001008))&0x20)==0x00))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,QUADSPI Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESCALER ,Clock prescaler"
|
|
bitfld.long 0x00 23. " PMM ,Polling match mode" "AND mode,OR mode"
|
|
bitfld.long 0x00 22. " APMS ,Automatic poll mode stop" "Running,Stopped"
|
|
bitfld.long 0x00 20. " TOIE ,TimeOut interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " SMIE ,Status match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " FTIE ,FIFO threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
bitfld.long 0x00 8.--12. " FTHRES ,FIFO threshold level" "Valid>=1,Valid>=2,Valid>=3,Valid>=4,Valid>=5,Valid>=6,Valid>=7,Valid>=8,Valid>=9,Valid>=10,Valid>=11,Valid>=12,Valid>=13,Valid>=14,Valid>=15,Valid>=16,Valid>=17,Valid>=18,Valid>=19,Valid>=20,Valid>=21,Valid>=22,Valid>=23,Valid>=24,Valid>=25,Valid>=26,Valid>=27,Valid>=28,Valid>=29,Valid>=30,Valid>=31,Valid>=32"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 8.--11. " FTHRES ,FIFO threshold level" "Valid>=1,Valid>=2,Valid>=3,Valid>=4,Valid>=5,Valid>=6,Valid>=7,Valid>=8,Valid>=9,Valid>=10,Valid>=11,Valid>=12,Valid>=13,Valid>=14,Valid>=15,Valid>=16"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
bitfld.long 0x00 7. " FSEL ,Flash memory selection" "FLASH 1,FLASH 2"
|
|
bitfld.long 0x00 6. " DFM ,Dual-flash mode enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 4. " SSHIFT ,Sample shift" "No shift,1/2 cycle shift"
|
|
newline
|
|
sif !cpuis("STM32H743*")&&!cpuis("STM32H753*")
|
|
bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " ABORT ,Abort request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " EN ,Enable the QUADSPI" "Disabled,Enabled"
|
|
elif ((((per.l(ad:0xA0001014))&0xC000000)==0x4000000)&&(((per.l(ad:0xA0001008))&0x20)==0x20))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,QUADSPI Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESCALER ,Clock prescaler"
|
|
rbitfld.long 0x00 23. " PMM ,Polling match mode" "AND mode,OR mode"
|
|
rbitfld.long 0x00 22. " APMS ,Automatic poll mode stop" "Running,Stopped"
|
|
bitfld.long 0x00 20. " TOIE ,TimeOut interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " SMIE ,Status match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " FTIE ,FIFO threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
bitfld.long 0x00 8.--12. " FTHRES ,FIFO threshold level" "Valid>=1,Valid>=2,Valid>=3,Valid>=4,Valid>=5,Valid>=6,Valid>=7,Valid>=8,Valid>=9,Valid>=10,Valid>=11,Valid>=12,Valid>=13,Valid>=14,Valid>=15,Valid>=16,Valid>=17,Valid>=18,Valid>=19,Valid>=20,Valid>=21,Valid>=22,Valid>=23,Valid>=24,Valid>=25,Valid>=26,Valid>=27,Valid>=28,Valid>=29,Valid>=30,Valid>=31,Valid>=32"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 8.--11. " FTHRES ,FIFO threshold level" "Valid>=1,Valid>=2,Valid>=3,Valid>=4,Valid>=5,Valid>=6,Valid>=7,Valid>=8,Valid>=9,Valid>=10,Valid>=11,Valid>=12,Valid>=13,Valid>=14,Valid>=15,Valid>=16"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
rbitfld.long 0x00 7. " FSEL ,Flash memory selection" "FLASH 1,FLASH 2"
|
|
rbitfld.long 0x00 6. " DFM ,Dual-flash mode enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
rbitfld.long 0x00 4. " SSHIFT ,Sample shift" "No shift,1/2 cycle shift"
|
|
newline
|
|
sif !cpuis("STM32H743*")&&!cpuis("STM32H753*")
|
|
bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " ABORT ,Abort request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " EN ,Enable the QUADSPI" "Disabled,Enabled"
|
|
elif ((((per.l(ad:0xA0001014))&0xC000000)==0xC000000)&&(((per.l(ad:0xA0001008))&0x20)==0x00))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,QUADSPI Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESCALER ,Clock prescaler"
|
|
bitfld.long 0x00 23. " PMM ,Polling match mode" "AND mode,OR mode"
|
|
bitfld.long 0x00 22. " APMS ,Automatic poll mode stop" "Running,Stopped"
|
|
bitfld.long 0x00 20. " TOIE ,TimeOut interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " SMIE ,Status match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " FTIE ,FIFO threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
bitfld.long 0x00 7. " FSEL ,Flash memory selection" "FLASH 1,FLASH 2"
|
|
bitfld.long 0x00 6. " DFM ,Dual-flash mode enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 4. " SSHIFT ,Sample shift" "No shift,1/2 cycle shift"
|
|
bitfld.long 0x00 3. " TCEN ,Timeout counter enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("STM32H743*")&&!cpuis("STM32H753*")
|
|
bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " ABORT ,Abort request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 0. " EN ,Enable the QUADSPI" "Disabled,Enabled"
|
|
elif ((((per.l(ad:0xA0001014))&0xC000000)==0xC000000)&&(((per.l(ad:0xA0001008))&0x20)==0x20))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,QUADSPI Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESCALER ,Clock prescaler"
|
|
rbitfld.long 0x00 23. " PMM ,Polling match mode" "AND mode,OR mode"
|
|
rbitfld.long 0x00 22. " APMS ,Automatic poll mode stop" "Running,Stopped"
|
|
bitfld.long 0x00 20. " TOIE ,TimeOut interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " SMIE ,Status match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " FTIE ,FIFO threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
rbitfld.long 0x00 7. " FSEL ,Flash memory selection" "FLASH 1,FLASH 2"
|
|
rbitfld.long 0x00 6. " DFM ,Dual-flash mode enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
rbitfld.long 0x00 4. " SSHIFT ,Sample shift" "No shift,1/2 cycle shift"
|
|
rbitfld.long 0x00 3. " TCEN ,Timeout counter enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("STM32H743*")&&!cpuis("STM32H753*")
|
|
bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " ABORT ,Abort request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 0. " EN ,Enable the QUADSPI" "Disabled,Enabled"
|
|
elif ((((per.l(ad:0xA0001014))&0xC000000)==0x8000000)&&(((per.l(ad:0xA0001008))&0x20)==0x00))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,QUADSPI Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESCALER ,Clock prescaler"
|
|
bitfld.long 0x00 23. " PMM ,Polling match mode" "AND mode,OR mode"
|
|
bitfld.long 0x00 22. " APMS ,Automatic poll mode stop" "Running,Stopped"
|
|
bitfld.long 0x00 20. " TOIE ,TimeOut interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " SMIE ,Status match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " FTIE ,FIFO threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
bitfld.long 0x00 7. " FSEL ,Flash memory selection" "FLASH 1,FLASH 2"
|
|
bitfld.long 0x00 6. " DFM ,Dual-flash mode enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 4. " SSHIFT ,Sample shift" "No shift,1/2 cycle shift"
|
|
newline
|
|
sif !cpuis("STM32H743*")&&!cpuis("STM32H753*")
|
|
bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " ABORT ,Abort request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " EN ,Enable the QUADSPI" "Disabled,Enabled"
|
|
elif ((((per.l(ad:0xA0001014))&0xC000000)==0x8000000)&&(((per.l(ad:0xA0001008))&0x20)==0x20))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,QUADSPI Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRESCALER ,Clock prescaler"
|
|
rbitfld.long 0x00 23. " PMM ,Polling match mode" "AND mode,OR mode"
|
|
rbitfld.long 0x00 22. " APMS ,Automatic poll mode stop" "Running,Stopped"
|
|
bitfld.long 0x00 20. " TOIE ,TimeOut interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " SMIE ,Status match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " FTIE ,FIFO threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
rbitfld.long 0x00 7. " FSEL ,Flash memory selection" "FLASH 1,FLASH 2"
|
|
rbitfld.long 0x00 6. " DFM ,Dual-flash mode enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
rbitfld.long 0x00 4. " SSHIFT ,Sample shift" "No shift,1/2 cycle shift"
|
|
newline
|
|
sif !cpuis("STM32H743*")&&!cpuis("STM32H753*")
|
|
bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " ABORT ,Abort request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " EN ,Enable the QUADSPI" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
if (((per.l(ad:0xA0001008))&0x20)==0x00)
|
|
if (((per.l(ad:0xA0001014))&0xC000000)==0x4000000||((per.l(ad:0xA0001014))&0xC000000)==0x00||((per.l(ad:0xA0001014))&0xC000000)==0x8000000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DCR,QUADSPI Device Configuration Register"
|
|
bitfld.long 0x00 16.--20. " FSIZE ,FLASH memory size" "2B,4B,8B,16B,32B,64B,128B,256B,512B,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
newline
|
|
sif cpuis("STM32H743*")||cpuis("STM32H753*")
|
|
bitfld.long 0x00 8.--10. " CSHT ,Chip select high time" "High>=1,High>=2,High>=3,High>=4,High>=5,High>=6,High>=7,High>=8"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 8.--10. " CSHT ,Chip select high time" ">=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 0. " CKMODE ,Mode 0 / mode 3" "Mode0,Mode3"
|
|
elif (((per.l(ad:0xA0001014))&0xC000000)==0xC000000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DCR,QUADSPI Device Configuration Register"
|
|
bitfld.long 0x00 16.--20. " FSIZE ,FLASH memory size" "2B,4B,8B,16B,32B,64B,128B,256B,512B,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,?..."
|
|
bitfld.long 0x00 8.--10. " CSHT ,Chip select high time" "High>=1,High>=2,High>=3,High>=4,High>=5,High>=6,High>=7,High>=8"
|
|
bitfld.long 0x00 0. " CKMODE ,Mode 0 / mode 3" "Mode0,Mode3"
|
|
endif
|
|
elif (((per.l(ad:0xA0001008))&0x20)==0x20)
|
|
if (((per.l(ad:0xA0001014))&0xC000000)==0x4000000||((per.l(ad:0xA0001014))&0xC000000)==0x00||((per.l(ad:0xA0001014))&0xC000000)==0x8000000)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "DCR,QUADSPI Device Configuration Register"
|
|
bitfld.long 0x00 16.--20. " FSIZE ,FLASH memory size" "2B,4B,8B,16B,32B,64B,128B,256B,512B,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
newline
|
|
sif cpuis("STM32H743*")||cpuis("STM32H753*")
|
|
bitfld.long 0x00 8.--10. " CSHT ,Chip select high time" "High>=1,High>=2,High>=3,High>=4,High>=5,High>=6,High>=7,High>=8"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 8.--10. " CSHT ,Chip select high time" ">=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 0. " CKMODE ,Mode 0 / mode 3" "Mode0,Mode3"
|
|
elif (((per.l(ad:0xA0001014))&0xC000000)==0xC000000)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "DCR,QUADSPI Device Configuration Register"
|
|
bitfld.long 0x00 16.--20. " FSIZE ,FLASH memory size" "2B,4B,8B,16B,32B,64B,128B,256B,512B,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,?..."
|
|
bitfld.long 0x00 8.--10. " CSHT ,Chip select high time" "High>=1,High>=2,High>=3,High>=4,High>=5,High>=6,High>=7,High>=8"
|
|
bitfld.long 0x00 0. " CKMODE ,Mode 0 / mode 3" "Mode0,Mode3"
|
|
endif
|
|
endif
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SR,QUADSPI Status Register"
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
bitfld.long 0x00 8.--13. " FLEVEL ,FIFO level" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,Full,?..."
|
|
newline
|
|
else
|
|
bitfld.long 0x00 8.--12. " FLEVEL ,FIFO level" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,Full,?..."
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " BUSY ,This bit is set when an operation is on going" "Idle,Busy"
|
|
bitfld.long 0x00 4. " TOF ,Timeout flag" "No timeout,Timeout"
|
|
newline
|
|
sif !cpuis("STM32H743*")&&!cpuis("STM32H753*")
|
|
bitfld.long 0x00 3. " SMF ,Status match flag" "No match,Match"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 2. " FTF ,FIFO threshold flag" "Not reached,Reached"
|
|
bitfld.long 0x00 1. " TCF ,Transfer complete flag" "Not transferred,Transferred"
|
|
bitfld.long 0x00 0. " TEF ,Transfer error flag" "No error,Error"
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "FCR,QUADSPI Flag Clear Register"
|
|
bitfld.long 0x00 4. " CTOF ,Clear timeout flag" "No effect,Clear"
|
|
bitfld.long 0x00 3. " CSMF ,Clear status match flag" "No effect,Clear"
|
|
bitfld.long 0x00 1. " CTCF ,Clear transfer complete flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CTEF ,Clear transfer error flag" "No effect,Clear"
|
|
if (((per.l(ad:0xA0001008))&0x20)==0x00)
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "DLR,QUADSPI Data Length Register"
|
|
line.long 0x04 "CCR,QUADSPI Communication Configuration Register"
|
|
bitfld.long 0x04 31. " DDRM ,Double data rate mode" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
bitfld.long 0x04 30. " DHHC ,DDR hold half cycle" "Analog delay,1/2 system clk"
|
|
newline
|
|
endif
|
|
sif cpuis("STM32H743*")||cpuis("STM32H753*")
|
|
bitfld.long 0x04 29. " FRCM ,Free running clock mode" "Normal,Free running"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 28. " SIOO ,Send instruction only once mode" "Every transaction,Only first command"
|
|
bitfld.long 0x04 26.--27. " FMODE ,Functional mode" "Indirect write,Indirect read,Automatic polling,Memory-mapped"
|
|
bitfld.long 0x04 24.--25. " DMODE ,Data mode" "No data,Single line,Two lines,Four lines"
|
|
bitfld.long 0x04 18.--22. " DCYC ,Number of dummy cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x04 16.--17. " ABSIZE ,Alternate bytes size" "8b,16b,24b,32b"
|
|
bitfld.long 0x04 14.--15. " ABMODE ,Alternate bytes mode" "No bytes,Single line,Two lines,Four lines"
|
|
bitfld.long 0x04 12.--13. " ADSIZE ,Address size" "8b,16b,24b,32b"
|
|
bitfld.long 0x04 10.--11. " ADMODE ,Address mode" "No address,Single line,Two lines,Four lines"
|
|
newline
|
|
bitfld.long 0x04 8.--9. " IMODE ,Instruction mode" "No instruction,Single line,Two lines,Four lines"
|
|
hexmask.long.byte 0x04 0.--7. 1. " INSTRUCTION ,Instruction to be send to the external SPI device"
|
|
else
|
|
rgroup.long 0x10++0x07
|
|
line.long 0x00 "DLR,QUADSPI Data Length Register"
|
|
line.long 0x04 "CCR,QUADSPI Communication Configuration Register"
|
|
bitfld.long 0x04 31. " DDRM ,Double data rate mode" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
bitfld.long 0x04 30. " DHHC ,DDR hold half cycle" "Analog delay,1/2 system clk"
|
|
newline
|
|
endif
|
|
sif cpuis("STM32H743*")||cpuis("STM32H753*")
|
|
bitfld.long 0x04 29. " FRCM ,Free running clock mode" "Normal,Free running"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 28. " SIOO ,Send instruction only once mode" "Every transaction,Only first command"
|
|
bitfld.long 0x04 26.--27. " FMODE ,Functional mode" "Indirect write,Indirect read,Automatic polling,Memory-mapped"
|
|
bitfld.long 0x04 24.--25. " DMODE ,Data mode" "No data,Single line,Two lines,Four lines"
|
|
bitfld.long 0x04 18.--22. " DCYC ,Number of dummy cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x04 16.--17. " ABSIZE ,Alternate bytes size" "8b,16b,24b,32b"
|
|
bitfld.long 0x04 14.--15. " ABMODE ,Alternate bytes mode" "No bytes,Single line,Two lines,Four lines"
|
|
bitfld.long 0x04 12.--13. " ADSIZE ,Address size" "8b,16b,24b,32b"
|
|
bitfld.long 0x04 10.--11. " ADMODE ,Address mode" "No address,Single line,Two lines,Four lines"
|
|
newline
|
|
bitfld.long 0x04 8.--9. " IMODE ,Instruction mode" "No instruction,Single line,Two lines,Four lines"
|
|
hexmask.long.byte 0x04 0.--7. 1. " INSTRUCTION ,Instruction to be send to the external SPI device"
|
|
endif
|
|
if (((per.l(ad:0xA0001008))&0x20)==0x00||((per.l(ad:0xA0001014))&0xC000000)==0xC000000)
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "AR,QUADSPI Address Register"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "AR,QUADSPI Address Register"
|
|
endif
|
|
if (((per.l(ad:0xA0001008))&0x20)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ABR,QUADSPI Alternate Bytes Register"
|
|
else
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ABR,QUADSPI Alternate Bytes Register"
|
|
endif
|
|
newline
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "DR,QUADSPI Data Register"
|
|
in
|
|
newline
|
|
if (((per.l(ad:0xA0001008))&0x20)==0x00)
|
|
group.long 0x24++0x0F
|
|
line.long 0x00 "PSMKR,QUADSPI Polling Status Mask Register"
|
|
bitfld.long 0x00 31. " MASK[31] ,Status mask bit 31" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " [30] ,Status mask bit 30" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " [29] ,Status mask bit 29" "Masked,Not masked"
|
|
bitfld.long 0x00 28. " [28] ,Status mask bit 28" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Status mask bit 27" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " [26] ,Status mask bit 26" "Masked,Not masked"
|
|
bitfld.long 0x00 25. " [25] ,Status mask bit 25" "Masked,Not masked"
|
|
bitfld.long 0x00 24. " [24] ,Status mask bit 24" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Status mask bit 23" "Masked,Not masked"
|
|
bitfld.long 0x00 22. " [22] ,Status mask bit 22" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " [21] ,Status mask bit 21" "Masked,Not masked"
|
|
bitfld.long 0x00 20. " [20] ,Status mask bit 20" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Status mask bit 19" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " [18] ,Status mask bit 18" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " [17] ,Status mask bit 17" "Masked,Not masked"
|
|
bitfld.long 0x00 16. " [16] ,Status mask bit 16" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Status mask bit 15" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " [14] ,Status mask bit 14" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " [13] ,Status mask bit 13" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " [12] ,Status mask bit 12" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Status mask bit 11" "Masked,Not masked"
|
|
bitfld.long 0x00 10. " [10] ,Status mask bit 10" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " [9] ,Status mask bit 9" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " [8] ,Status mask bit 8" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Status mask bit 7" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " [6] ,Status mask bit 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " [5] ,Status mask bit 5" "Masked,Not masked"
|
|
bitfld.long 0x00 4. " [4] ,Status mask bit 4" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Status mask bit 3" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " [2] ,Status mask bit 2" "Masked,Not masked"
|
|
bitfld.long 0x00 1. " [1] ,Status mask bit 1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " [0] ,Status mask bit 0" "Masked,Not masked"
|
|
line.long 0x04 "PSMAR,QUADSPI Polling Status Match Register"
|
|
line.long 0x08 "PIR,QUADSPI Polling Interval Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " INTERVAL ,Polling interval"
|
|
line.long 0x0C "LPTR,QUADSPI Low-power Timeout Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TIMEOUT ,Timeout period"
|
|
else
|
|
rgroup.long 0x24++0x0F
|
|
line.long 0x00 "PSMKR,QUADSPI Polling Status Mask Register"
|
|
bitfld.long 0x00 31. " MASK[31] ,Status mask bit 31" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " [30] ,Status mask bit 30" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " [29] ,Status mask bit 29" "Masked,Not masked"
|
|
bitfld.long 0x00 28. " [28] ,Status mask bit 28" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Status mask bit 27" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " [26] ,Status mask bit 26" "Masked,Not masked"
|
|
bitfld.long 0x00 25. " [25] ,Status mask bit 25" "Masked,Not masked"
|
|
bitfld.long 0x00 24. " [24] ,Status mask bit 24" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Status mask bit 23" "Masked,Not masked"
|
|
bitfld.long 0x00 22. " [22] ,Status mask bit 22" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " [21] ,Status mask bit 21" "Masked,Not masked"
|
|
bitfld.long 0x00 20. " [20] ,Status mask bit 20" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Status mask bit 19" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " [18] ,Status mask bit 18" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " [17] ,Status mask bit 17" "Masked,Not masked"
|
|
bitfld.long 0x00 16. " [16] ,Status mask bit 16" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Status mask bit 15" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " [14] ,Status mask bit 14" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " [13] ,Status mask bit 13" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " [12] ,Status mask bit 12" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Status mask bit 11" "Masked,Not masked"
|
|
bitfld.long 0x00 10. " [10] ,Status mask bit 10" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " [9] ,Status mask bit 9" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " [8] ,Status mask bit 8" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Status mask bit 7" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " [6] ,Status mask bit 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " [5] ,Status mask bit 5" "Masked,Not masked"
|
|
bitfld.long 0x00 4. " [4] ,Status mask bit 4" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Status mask bit 3" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " [2] ,Status mask bit 2" "Masked,Not masked"
|
|
bitfld.long 0x00 1. " [1] ,Status mask bit 1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " [0] ,Status mask bit 0" "Masked,Not masked"
|
|
line.long 0x04 "PSMAR,QUADSPI Polling Status Match Register"
|
|
line.long 0x08 "PIR,QUADSPI Polling Interval Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " INTERVAL ,Polling interval"
|
|
line.long 0x0C "LPTR,QUADSPI Low-Power Timeout Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TIMEOUT ,Timeout period"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "ADC (Analog-to-Digital Converter)"
|
|
tree "Common Registers"
|
|
base ad:0x40012300
|
|
width 7.
|
|
sif (cpuis("STM32F411R?")||cpuis("STM32F411V?")||cpuis("STM32F411C?")||cpuis("STM32F401?D")||cpuis("STM32F401?E"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CCR,ADC Common Control Register"
|
|
bitfld.long 0x00 23. " TSVREFE ,Temperature sensor and VREFINT enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " VBATE ,VBAT enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " ADCPRE ,ADC prescaler" "PCLK2/2,PCLK2/4,PCLK2/6,PCLK2/8"
|
|
else
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CSR,ADC Common Status Register"
|
|
sif (!cpuis("STM32F446M?")&&!cpuis("STM32F446R?")&&!cpuis("STM32F446V?"))
|
|
bitfld.long 0x00 21. " OVR3 ,Overrun flag of ADC3" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " STRT3 ,Regular channel start flag of ADC3" "Not started,Started"
|
|
bitfld.long 0x00 19. " JSTRT3 ,Injected channel start flag of ADC3" "Not started,Started"
|
|
bitfld.long 0x00 18. " JEOC3 ,Injected channel end of conversion of ADC3" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x00 17. " EOC3 ,End of conversion of ADC3" "Not completed,Completed"
|
|
bitfld.long 0x00 16. " AWD3 ,Analog watchdog flag of ADC3" "Not occurred,Occurred"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 13. " OVR2 ,Overrun flag of ADC2" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " STRT2 ,Regular channel start flag of ADC2" "Not started,Started"
|
|
bitfld.long 0x00 11. " JSTRT2 ,Injected channel start flag of ADC2" "Not started,Started"
|
|
bitfld.long 0x00 10. " JEOC2 ,Injected channel end of conversion of ADC2" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x00 9. " EOC2 ,End of conversion of ADC2" "Not completed,Completed"
|
|
bitfld.long 0x00 8. " AWD2 ,Analog watchdog flag of ADC2" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " OVR1 ,Overrun flag of ADC1" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " STRT1 ,Regular channel start flag of ADC1" "Not started,Started"
|
|
newline
|
|
bitfld.long 0x00 3. " JSTRT1 ,Injected channel start flag of ADC1" "Not started,Started"
|
|
bitfld.long 0x00 2. " JEOC1 ,Injected channel end of conversion of ADC1" "Not completed,Completed"
|
|
bitfld.long 0x00 1. " EOC1 ,End of conversion of ADC1" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " AWD1 ,Analog watchdog flag of ADC1" "Not occurred,Occurred"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CCR,ADC Common Control Register"
|
|
bitfld.long 0x00 23. " TSVREFE ,Temperature sensor and VREFINT enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " VBATE ,VBAT enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " ADCPRE ,ADC prescaler" "PCLK2/2,PCLK2/4,PCLK2/6,PCLK2/8"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " DMA ,Direct memory access mode for multi ADC mode" "Disabled,Mode 1,Mode 2,Mode 3"
|
|
bitfld.long 0x00 13. " DDS ,DMA disable selection (for multi-ADC mode)" "Last transfer finished,Conversion finished"
|
|
bitfld.long 0x00 8.--11. " DELAY ,Delay between 2 sampling phases" "5 * TADCCLK,6 * TADCCLK,7 * TADCCLK,8 * TADCCLK,9 * TADCCLK,10 * TADCCLK,11 * TADCCLK,12 * TADCCLK,13 * TADCCLK,14 * TADCCLK,15 * TADCCLK,16 * TADCCLK,17 * TADCCLK,18 * TADCCLK,19 * TADCCLK,20 * TADCCLK"
|
|
newline
|
|
bitfld.long 0x00 0.--4. " MULTI ,Multi ADC mode selection" "Independent mode,Dual mode/combined regular simultaneous + injected simultaneous mode,Dual mode/combined regular simultaneous + alternate trigger mode,,,Dual mode/injected simultaneous mode only,Dual mode/regular simultaneous mode only,Dual mode/interleaved mode only,,Dual mode/alternate trigger mode only,,,,,,,,Triple mode/combined regular simultaneous + injected simultaneous mode,Triple mode/combined regular simultaneous + alternate trigger mode,,,Triple mode/injected simultaneous mode only,Triple mode/regular simultaneous mode only,Triple mode/interleaved mode only,,Triple mode/alternate trigger mode only,?..."
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "CDR,ADC Common Regular Data Register For Dual And Triple Modes"
|
|
hexmask.long.word 0x00 16.--31. 1. " DATA2 ,2nd data item of a pair of regular conversions"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA1 ,1st data item of a pair of regular conversions"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "ADC 1"
|
|
base ad:0x40012000
|
|
width 7.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "SR,ADC Status Register"
|
|
bitfld.long 0x00 5. " OVR ,Overrun" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " STRT ,Regular channel start flag" "Not started,Started"
|
|
bitfld.long 0x00 3. " JSTRT ,Injected channel start flag" "Not started,Started"
|
|
bitfld.long 0x00 2. " JEOC ,Injected channel end of conversion" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x00 1. " EOC ,Regular channel end of conversion" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " AWD ,Analog watchdog flag" "Not occurred,Occurred"
|
|
line.long 0x04 "CR1,ADC Control Register 1"
|
|
bitfld.long 0x04 26. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24.--25. " RES ,Resolution" "12-bit,10-bit,8-bit,6-bit"
|
|
bitfld.long 0x04 23. " AWDEN ,Analog watchdog enable on regular channels" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " JAWDEN ,Analog watchdog enable on injected channels" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 13.--15. " DISCNUM ,Discontinuous mode channel count" "1CH,2CH,3CH,4CH,5CH,6CH,7CH,8CH"
|
|
bitfld.long 0x04 12. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " DISCEN ,Discontinuous mode on regular channels" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " JAUTO ,Automatic injected group conversion" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 9. " AWDSGL ,Enable the watchdog on a single channel in scan mode" "All,Single"
|
|
bitfld.long 0x04 8. " SCAN ,Scan mode" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " JEOCIE ,Interrupt enable for injected channels" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 5. " EOCIE ,Interrupt enable for EOC" "Disabled,Enabled"
|
|
sif (cpuis("STM32F411C?")||cpuis("STM32F401C?"))
|
|
newline
|
|
bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,?..."
|
|
elif (cpuis("STM32F405O*")||cpuis("STM32F415O*"))
|
|
newline
|
|
bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,?..."
|
|
elif (cpuis("STM32F446M?")||cpuis("STM32F469V*")||cpuis("STM32F479V*"))
|
|
newline
|
|
bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,?..."
|
|
elif (cpuis("STM32F4??R*")||cpuis("STM32F4??V*")||cpuis("STM32F469I*")||cpuis("STM32F20?R*")||cpuis("STM32F21?R*")||cpuis("STM32F205V*")||cpuis("STM32F207V*")||cpuis("STM32F215V*")||cpuis("STM32F7??V?")||cpuis("STM32F7?2R?")||cpuis("STM32F730R8"))
|
|
newline
|
|
bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_IN15,?..."
|
|
elif (cpuis("STM32F469Z*")||cpuis("STM32F479Z*"))
|
|
newline
|
|
bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_IN15,ADC_IN16,ADC_IN17,ADC_IN18,ADC_IN19,?..."
|
|
else
|
|
newline
|
|
bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_IN15,ADC_IN16,ADC_IN17,ADC_IN18,ADC_IN19,ADC_IN20,ADC_IN21,ADC_IN22,ADC_IN23,?..."
|
|
endif
|
|
if (((per.l(ad:0x40012000+0x08))&0x01)==0x01)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR2,ADC Control Register 2"
|
|
bitfld.long 0x00 30. " SWSTART ,Start conversion of regular channels" "Reset,Start"
|
|
bitfld.long 0x00 28.--29. " EXTEN ,External trigger enable for regular channels" "Disabled,Rising edge,Falling edge,Both"
|
|
sif cpuis("STM32F411*")||cpuis("STM32F401*")
|
|
newline
|
|
bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM1_CC1,TIM1_CC2,TIM1_CC3,TIM2_CC2,TIM2_CC3,TIM2_CC4,TIM2_TRGO,TIM3_CC1,TIM3_TRGO,TIM4_CC4,TIM5_CC1,TIM5_CC2,TIM5_CC3,,,EXTI11"
|
|
elif cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F75*")||cpuis("STM32F767BI")
|
|
newline
|
|
bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM1_CH1,TIM1_CH2,TIM1_CH3,TIM2_CH2,TIM5_TRGO,TIM4_CH4,TIM3_CH4,TIM8_TRGO,TIM8_TRGO2,TIM1_TRGO,TIM1_TRGO2,TIM2_TRGO,TIM4_TRGO,TIM6_TRGO,,EXTI11"
|
|
else
|
|
newline
|
|
bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM1_CC1,TIM1_CC2,TIM1_CC3,TIM2_CC2,TIM5_TRGO,TIM4_CCM3,TIM3_CCM4,TIM8_TRGO2,TIM8_TRGO2,TIM1_TRGO,TIM1_TRGO2,TIM2_TRGO,TIM4_TRGO,TIM6_TRGO,,EXTI11"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 22. " JSWSTART ,Start conversion of injected channels" "Reset,Start"
|
|
bitfld.long 0x00 20.--21. " JEXTEN ,External trigger enable for injected channels" "Disabled,Rising edge,Falling edge,Both"
|
|
newline
|
|
sif cpuis("STM32F411*")||cpuis("STM32F401*")
|
|
bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM1_CC4,TIM1_TRGO,TIM2_CC1,TIM2_TRGO2,TIM3_CC2,TIM3_CC4,TIM4_CC1,TIM4_CC2,TIM4_CC3,TIM4_TRGO,TIM5_CC4,TIM5_TRGO,,,,EXTI15"
|
|
elif cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis(" STM32F75*")||cpuis("STM32F767BI")
|
|
bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM1_TRGO,TIM1_CH4,TIM2_TRGO,TIM2_CH1,TIM3_CH4,TIM4_TRGO,,TIM8_CH4,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_CH3,TIM5_TRGO,TIM3_CH1,TIM6_TRGO,?..."
|
|
else
|
|
bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM1_TRGO,TIM1_CH4,TIM2_TRGO,TIM2_CH1,TIM3_CH4,TIM4_TRGO,,TIM8_CH4,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_CH3,TIM5_TRGO,TIM3_CH1,TIM6_TRGO,EXTI15"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 11. " ALIGN ,Data alignment" "Right,Left"
|
|
bitfld.long 0x00 10. " EOCS ,End of conversion selection" "Sequence,Conversion"
|
|
bitfld.long 0x00 9. " DDS ,DMA disable selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DMA ,Direct memory access mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " CONT ,Continuous conversion" "Single,Continuous"
|
|
bitfld.long 0x00 0. " ADON ,A/D converter ON / OFF" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR2,ADC Control Register 2"
|
|
rbitfld.long 0x00 30. " SWSTART ,Start conversion of regular channels" "Reset,Start"
|
|
bitfld.long 0x00 28.--29. " EXTEN ,External trigger enable for regular channels" "Disabled,Rising edge,Falling edge,Both"
|
|
newline
|
|
sif cpuis("STM32F411*")||cpuis("STM32F401*")
|
|
bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM1_CC1,TIM1_CC2,TIM1_CC3,TIM2_CC2,TIM5_TRGO,TIM4_CCM3,TIM3_CCM4,TIM8_TRGO2,TIM8_TRGO2,TIM1_TRGO,TIM1_TRGO2,TIM2_TRGO,TIM4_TRGO,TIM6_TRGO,,EXTI11"
|
|
elif cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F75*")||cpuis("STM32F767BI")
|
|
bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM1_CH1,TIM1_CH2,TIM1_CH3,TIM2_CH2,TIM5_TRGO,TIM4_CH4,TIM3_CH4,TIM8_TRGO,TIM8_TRGO2,TIM1_TRGO,TIM1_TRGO2,TIM2_TRGO,TIM4_TRGO,TIM6_TRGO,,EXTI11"
|
|
else
|
|
bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM1_CC1,TIM1_CC2,TIM1_CC3,TIM2_CC2,TIM2_CC3,TIM2_CC4,TIM2_TRGO,TIM3_CC1,TIM3_TRGO,TIM4_CC4,TIM5_CC1,TIM5_CC2,TIM5_CC3,TIM8_CC1,TIM8_TRGO,EXTI11"
|
|
endif
|
|
newline
|
|
rbitfld.long 0x00 22. " JSWSTART ,Start conversion of injected channels" "Reset,Start"
|
|
bitfld.long 0x00 20.--21. " JEXTEN ,External trigger enable for injected channels" "Disabled,Rising edge,Falling edge,Both"
|
|
newline
|
|
sif cpuis("STM32F411*")||cpuis("STM32F401*")
|
|
bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM1_CC4,TIM1_TRGO,TIM2_CC1,TIM2_TRGO2,TIM3_CC2,TIM3_CC4,TIM4_CC1,TIM4_CC2,TIM4_CC3,TIM4_TRGO,TIM5_CC4,TIM5_TRGO,,,,EXTI15"
|
|
elif (cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F767BI"))
|
|
bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM1_TRGO,TIM1_CH4,TIM2_TRGO,TIM2_CH1,TIM3_CH4,TIM4_TRGO,,TIM8_CH4,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_CH3,TIM5_TRGO,TIM3_CH1,TIM6_TRGO,?..."
|
|
else
|
|
bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM1_TRGO,TIM1_CC4,TIM2_TRGO,TIM2_CC1,TIM3_CC4,TIM4_TRGO,,TIM8_CC4,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_CC3,TIM5_TRGO,TIM3_CC1,TIM6_TRGO,EXTI15"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 11. " ALIGN ,Data alignment" "Right,Left"
|
|
bitfld.long 0x00 10. " EOCS ,End of conversion selection" "Sequence,Conversion"
|
|
bitfld.long 0x00 9. " DDS ,DMA disable selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DMA ,Direct memory access mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " CONT ,Continuous conversion" "Single,Continuous"
|
|
bitfld.long 0x00 0. " ADON ,A/D converter ON / OFF" "Disabled,Enabled"
|
|
endif
|
|
sif (!cpuis("STM32F411C?")&&!cpuis("STM32F401C?"))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SMPR1,ADC Sample Time Register 1"
|
|
sif (cpuis("STM32F4??R*")||cpuis("STM32F4??V*")||cpuis("STM32F469I*")||cpuis("STM32F7??V?")||cpuis("STM32F7??R?"))
|
|
bitfld.long 0x00 15.--17. " SMP15 ,Channel 15 sample time selection" "3,15,28,56,84,112,144,480"
|
|
newline
|
|
elif cpuis("STM32F20?R*")||cpuis("STM32F21?R*")||cpuis("STM32F205V*")||cpuis("STM32F207V*")||cpuis("STM32F215V*")
|
|
bitfld.long 0x00 18.--20. " SMP16 ,Channel 16 sample time selection" "3,15,28,56,84,112,144,480"
|
|
bitfld.long 0x00 15.--17. " SMP15 ,Channel 15 sample time selection" "3,15,28,56,84,112,144,480"
|
|
newline
|
|
elif (!cpuis("STM32F405OE")&&!cpuis("STM32F405OG")&&!cpuis("STM32F415OG")&&!cpuis("STM32F446M?"))
|
|
bitfld.long 0x00 24.--26. " SMP18 ,Channel 18 sample time selection" "3,15,28,56,84,112,144,480"
|
|
bitfld.long 0x00 21.--23. " SMP17 ,Channel 17 sample time selection" "3,15,28,56,84,112,144,480"
|
|
bitfld.long 0x00 18.--20. " SMP16 ,Channel 16 sample time selection" "3,15,28,56,84,112,144,480"
|
|
bitfld.long 0x00 15.--17. " SMP15 ,Channel 15 sample time selection" "3,15,28,56,84,112,144,480"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 12.--14. " SMP14 ,Channel 14 sample time selection" "3,15,28,56,84,112,144,480"
|
|
bitfld.long 0x00 9.--11. " SMP13 ,Channel 13 sample time selection" "3,15,28,56,84,112,144,480"
|
|
bitfld.long 0x00 6.--8. " SMP12 ,Channel 12 sample time selection" "3,15,28,56,84,112,144,480"
|
|
bitfld.long 0x00 3.--5. " SMP11 ,Channel 11 sample time selection" "3,15,28,56,84,112,144,480"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " SMP10 ,Channel 10 sample time selection" "3,15,28,56,84,112,144,480"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SMPR2,ADC Sample Time Register 2"
|
|
bitfld.long 0x00 27.--29. " SMP9 ,Channel 9 sample time selection" "3,15,28,56,84,112,144,480"
|
|
bitfld.long 0x00 24.--26. " SMP8 ,Channel 8 sample time selection" "3,15,28,56,84,112,144,480"
|
|
bitfld.long 0x00 21.--23. " SMP7 ,Channel 7 sample time selection" "3,15,28,56,84,112,144,480"
|
|
bitfld.long 0x00 18.--20. " SMP6 ,Channel 6 sample time selection" "3,15,28,56,84,112,144,480"
|
|
newline
|
|
bitfld.long 0x00 15.--17. " SMP5 ,Channel 5 sample time selection" "3,15,28,56,84,112,144,480"
|
|
bitfld.long 0x00 12.--14. " SMP4 ,Channel 4 sample time selection" "3,15,28,56,84,112,144,480"
|
|
bitfld.long 0x00 9.--11. " SMP3 ,Channel 3 sample time selection" "3,15,28,56,84,112,144,480"
|
|
bitfld.long 0x00 6.--8. " SMP2 ,Channel 2 sample time selection" "3,15,28,56,84,112,144,480"
|
|
newline
|
|
bitfld.long 0x00 3.--5. " SMP1 ,Channel 1 sample time selection" "3,15,28,56,84,112,144,480"
|
|
bitfld.long 0x00 0.--2. " SMP0 ,Channel 0 sample time selection" "3,15,28,56,84,112,144,480"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "JOFR1,ADC Injected Channel Data Offset Register 1"
|
|
hexmask.long.word 0x00 0.--11. 0x01 " JOFFSET1 ,Data offset for injected channel 1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "JOFR2,ADC Injected Channel Data Offset Register 2"
|
|
hexmask.long.word 0x00 0.--11. 0x01 " JOFFSET2 ,Data offset for injected channel 2"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "JOFR3,ADC Injected Channel Data Offset Register 3"
|
|
hexmask.long.word 0x00 0.--11. 0x01 " JOFFSET3 ,Data offset for injected channel 3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "JOFR4,ADC Injected Channel Data Offset Register 4"
|
|
hexmask.long.word 0x00 0.--11. 0x01 " JOFFSET4 ,Data offset for injected channel 4"
|
|
group.long 0x24++0x07
|
|
line.long 0x00 "HTR,ADC Watchdog High Threshold Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " HT ,Analog watchdog higher threshold"
|
|
line.long 0x04 "LTR,ADC Watchdog Low Threshold Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " LT ,Analog watchdog lower threshold"
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F411R?")||cpuis("STM32F411V?")||cpuis("STM32F411C?")||cpuis("STM32F401R?")||cpuis("STM32F401V?")||cpuis("STM32F401C?"))
|
|
group.long 0x2C++0x0F
|
|
line.long 0x00 "SQR1,ADC Regular Sequence Register 1"
|
|
bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x04 "SQR2,ADC Regular Sequence Register 2"
|
|
bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
newline
|
|
bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x08 "SQR3,ADC Regular Sequence Register 3"
|
|
bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 10.--14. " SQ3 ,3th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
newline
|
|
bitfld.long 0x08 5.--9. " SQ2 ,2th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 0.--4. " SQ1 ,1th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x0C "JSQR,ADC Injected Sequence Register"
|
|
bitfld.long 0x0C 20.--21. " JL ,Injected sequence length" "1,2,3,4"
|
|
bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x0C 10.--14. " JSQ3 ,3th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x0C 5.--9. " JSQ2 ,2th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
newline
|
|
bitfld.long 0x0C 0.--4. " JSQ1 ,1th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
elif (cpuis("STM32F427A*")||cpuis("STM32F429Z*")||cpuis("STM32F429N*")||cpuis("STM32F429I*")||cpuis("STM32F429B*")||cpuis("STM32F429A*")||cpuis("STM32F437AI")||cpuis("STM32F439AI"))
|
|
group.long 0x2C++0x0F
|
|
line.long 0x00 "SQR1,ADC Regular Sequence Register 1"
|
|
bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
line.long 0x04 "SQR2,ADC Regular Sequence Register 2"
|
|
bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
newline
|
|
bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
line.long 0x08 "SQR3,ADC Regular Sequence Register 3"
|
|
bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x08 10.--14. " SQ3 ,3th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
newline
|
|
bitfld.long 0x08 5.--9. " SQ2 ,2th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x08 0.--4. " SQ1 ,1th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
line.long 0x0C "JSQR,ADC Injected Sequence Register"
|
|
bitfld.long 0x0C 20.--21. " JL ,Injected sequence length" "1,2,3,4"
|
|
bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x0C 10.--14. " JSQ3 ,3th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x0C 5.--9. " JSQ2 ,2th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
newline
|
|
bitfld.long 0x0C 0.--4. " JSQ1 ,1th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
elif (cpuis("STM32F20?R*")||cpuis("STM32F21?R*")||cpuis("STM32F205V*")||cpuis("STM32F207V*")||cpuis("STM32F215V*")||cpuis("STM32F4??R*")||cpuis("STM32F4??V*")||cpuis("STM32F469I*"))
|
|
group.long 0x2C++0x0F
|
|
line.long 0x00 "SQR1,ADC Regular Sequence Register 1"
|
|
bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
line.long 0x04 "SQR2,ADC Regular Sequence Register 2"
|
|
bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
newline
|
|
bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
line.long 0x08 "SQR3,ADC Regular Sequence Register 3"
|
|
bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x08 10.--14. " SQ3 ,3th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
newline
|
|
bitfld.long 0x08 5.--9. " SQ2 ,2th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x08 0.--4. " SQ1 ,1th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
line.long 0x0C "JSQR,ADC Injected Sequence Register"
|
|
bitfld.long 0x0C 20.--21. " JL ,Injected sequence length" "1,2,3,4"
|
|
bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x0C 10.--14. " JSQ3 ,3th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x0C 5.--9. " JSQ2 ,2th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
newline
|
|
bitfld.long 0x0C 0.--4. " JSQ1 ,1th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
elif (cpuis("STM32F405O*")||cpuis("STM32F415O*"))
|
|
group.long 0x2C++0x0F
|
|
line.long 0x00 "SQR1,ADC Regular Sequence Register 1"
|
|
bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
line.long 0x04 "SQR2,ADC Regular Sequence Register 2"
|
|
bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
newline
|
|
bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
line.long 0x08 "SQR3,ADC Regular Sequence Register 3"
|
|
bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
bitfld.long 0x08 10.--14. " SQ3 ,3th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
newline
|
|
bitfld.long 0x08 5.--9. " SQ2 ,2th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
bitfld.long 0x08 0.--4. " SQ1 ,1th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
line.long 0x0C "JSQR,ADC Injected Sequence Register"
|
|
bitfld.long 0x0C 20.--21. " JL ,Injected sequence length" "1,2,3,4"
|
|
bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
bitfld.long 0x0C 10.--14. " JSQ3 ,3th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
bitfld.long 0x0C 5.--9. " JSQ2 ,2th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
newline
|
|
bitfld.long 0x0C 0.--4. " JSQ1 ,1th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
else
|
|
group.long 0x2C++0x0F
|
|
line.long 0x00 "SQR1,ADC Regular Sequence Register 1"
|
|
bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x04 "SQR2,ADC Regular Sequence Register 2"
|
|
bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
newline
|
|
bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x08 "SQR3,ADC Regular Sequence Register 3"
|
|
bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 10.--14. " SQ3 ,3th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
newline
|
|
bitfld.long 0x08 5.--9. " SQ2 ,2th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 0.--4. " SQ1 ,1th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x0C "JSQR,ADC Injected Sequence Register"
|
|
bitfld.long 0x0C 20.--21. " JL ,Injected sequence length" "1,2,3,4"
|
|
bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x0C 10.--14. " JSQ3 ,3th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x0C 5.--9. " JSQ2 ,2th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
newline
|
|
bitfld.long 0x0C 0.--4. " JSQ1 ,1th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
endif
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "JDR1,ADC Injected Data Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "JDR2,ADC Injected Data Register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "JDR3,ADC Injected Data Register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "JDR4,ADC Injected Data Register 4"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DR,ADC Regular Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Regular data"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ADC 2"
|
|
base ad:0x40012100
|
|
width 7.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "SR,ADC Status Register"
|
|
bitfld.long 0x00 5. " OVR ,Overrun" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " STRT ,Regular channel start flag" "Not started,Started"
|
|
bitfld.long 0x00 3. " JSTRT ,Injected channel start flag" "Not started,Started"
|
|
bitfld.long 0x00 2. " JEOC ,Injected channel end of conversion" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x00 1. " EOC ,Regular channel end of conversion" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " AWD ,Analog watchdog flag" "Not occurred,Occurred"
|
|
line.long 0x04 "CR1,ADC Control Register 1"
|
|
bitfld.long 0x04 26. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24.--25. " RES ,Resolution" "12-bit,10-bit,8-bit,6-bit"
|
|
bitfld.long 0x04 23. " AWDEN ,Analog watchdog enable on regular channels" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " JAWDEN ,Analog watchdog enable on injected channels" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 13.--15. " DISCNUM ,Discontinuous mode channel count" "1CH,2CH,3CH,4CH,5CH,6CH,7CH,8CH"
|
|
bitfld.long 0x04 12. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " DISCEN ,Discontinuous mode on regular channels" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " JAUTO ,Automatic injected group conversion" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 9. " AWDSGL ,Enable the watchdog on a single channel in scan mode" "All,Single"
|
|
bitfld.long 0x04 8. " SCAN ,Scan mode" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " JEOCIE ,Interrupt enable for injected channels" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 5. " EOCIE ,Interrupt enable for EOC" "Disabled,Enabled"
|
|
sif (cpuis("STM32F411C?")||cpuis("STM32F401C?"))
|
|
newline
|
|
bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,?..."
|
|
elif (cpuis("STM32F405O*")||cpuis("STM32F415O*"))
|
|
newline
|
|
bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,?..."
|
|
elif (cpuis("STM32F446M?")||cpuis("STM32F469V*")||cpuis("STM32F479V*"))
|
|
newline
|
|
bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,?..."
|
|
elif (cpuis("STM32F4??R*")||cpuis("STM32F4??V*")||cpuis("STM32F469I*")||cpuis("STM32F20?R*")||cpuis("STM32F21?R*")||cpuis("STM32F205V*")||cpuis("STM32F207V*")||cpuis("STM32F215V*")||cpuis("STM32F7??V?")||cpuis("STM32F7?2R?")||cpuis("STM32F730R8"))
|
|
newline
|
|
bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_IN15,?..."
|
|
elif (cpuis("STM32F469Z*")||cpuis("STM32F479Z*"))
|
|
newline
|
|
bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_IN15,ADC_IN16,ADC_IN17,ADC_IN18,ADC_IN19,?..."
|
|
else
|
|
newline
|
|
bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_IN15,ADC_IN16,ADC_IN17,ADC_IN18,ADC_IN19,ADC_IN20,ADC_IN21,ADC_IN22,ADC_IN23,?..."
|
|
endif
|
|
if (((per.l(ad:0x40012100+0x08))&0x01)==0x01)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR2,ADC Control Register 2"
|
|
bitfld.long 0x00 30. " SWSTART ,Start conversion of regular channels" "Reset,Start"
|
|
bitfld.long 0x00 28.--29. " EXTEN ,External trigger enable for regular channels" "Disabled,Rising edge,Falling edge,Both"
|
|
sif cpuis("STM32F411*")||cpuis("STM32F401*")
|
|
newline
|
|
bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM1_CC1,TIM1_CC2,TIM1_CC3,TIM2_CC2,TIM2_CC3,TIM2_CC4,TIM2_TRGO,TIM3_CC1,TIM3_TRGO,TIM4_CC4,TIM5_CC1,TIM5_CC2,TIM5_CC3,,,EXTI11"
|
|
elif cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F75*")||cpuis("STM32F767BI")
|
|
newline
|
|
bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM1_CH1,TIM1_CH2,TIM1_CH3,TIM2_CH2,TIM5_TRGO,TIM4_CH4,TIM3_CH4,TIM8_TRGO,TIM8_TRGO2,TIM1_TRGO,TIM1_TRGO2,TIM2_TRGO,TIM4_TRGO,TIM6_TRGO,,EXTI11"
|
|
else
|
|
newline
|
|
bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM1_CC1,TIM1_CC2,TIM1_CC3,TIM2_CC2,TIM5_TRGO,TIM4_CCM3,TIM3_CCM4,TIM8_TRGO2,TIM8_TRGO2,TIM1_TRGO,TIM1_TRGO2,TIM2_TRGO,TIM4_TRGO,TIM6_TRGO,,EXTI11"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 22. " JSWSTART ,Start conversion of injected channels" "Reset,Start"
|
|
bitfld.long 0x00 20.--21. " JEXTEN ,External trigger enable for injected channels" "Disabled,Rising edge,Falling edge,Both"
|
|
newline
|
|
sif cpuis("STM32F411*")||cpuis("STM32F401*")
|
|
bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM1_CC4,TIM1_TRGO,TIM2_CC1,TIM2_TRGO2,TIM3_CC2,TIM3_CC4,TIM4_CC1,TIM4_CC2,TIM4_CC3,TIM4_TRGO,TIM5_CC4,TIM5_TRGO,,,,EXTI15"
|
|
elif cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis(" STM32F75*")||cpuis("STM32F767BI")
|
|
bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM1_TRGO,TIM1_CH4,TIM2_TRGO,TIM2_CH1,TIM3_CH4,TIM4_TRGO,,TIM8_CH4,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_CH3,TIM5_TRGO,TIM3_CH1,TIM6_TRGO,?..."
|
|
else
|
|
bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM1_TRGO,TIM1_CH4,TIM2_TRGO,TIM2_CH1,TIM3_CH4,TIM4_TRGO,,TIM8_CH4,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_CH3,TIM5_TRGO,TIM3_CH1,TIM6_TRGO,EXTI15"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 11. " ALIGN ,Data alignment" "Right,Left"
|
|
bitfld.long 0x00 10. " EOCS ,End of conversion selection" "Sequence,Conversion"
|
|
bitfld.long 0x00 9. " DDS ,DMA disable selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DMA ,Direct memory access mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " CONT ,Continuous conversion" "Single,Continuous"
|
|
bitfld.long 0x00 0. " ADON ,A/D converter ON / OFF" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR2,ADC Control Register 2"
|
|
rbitfld.long 0x00 30. " SWSTART ,Start conversion of regular channels" "Reset,Start"
|
|
bitfld.long 0x00 28.--29. " EXTEN ,External trigger enable for regular channels" "Disabled,Rising edge,Falling edge,Both"
|
|
newline
|
|
sif cpuis("STM32F411*")||cpuis("STM32F401*")
|
|
bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM1_CC1,TIM1_CC2,TIM1_CC3,TIM2_CC2,TIM5_TRGO,TIM4_CCM3,TIM3_CCM4,TIM8_TRGO2,TIM8_TRGO2,TIM1_TRGO,TIM1_TRGO2,TIM2_TRGO,TIM4_TRGO,TIM6_TRGO,,EXTI11"
|
|
elif cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F75*")||cpuis("STM32F767BI")
|
|
bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM1_CH1,TIM1_CH2,TIM1_CH3,TIM2_CH2,TIM5_TRGO,TIM4_CH4,TIM3_CH4,TIM8_TRGO,TIM8_TRGO2,TIM1_TRGO,TIM1_TRGO2,TIM2_TRGO,TIM4_TRGO,TIM6_TRGO,,EXTI11"
|
|
else
|
|
bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM1_CC1,TIM1_CC2,TIM1_CC3,TIM2_CC2,TIM2_CC3,TIM2_CC4,TIM2_TRGO,TIM3_CC1,TIM3_TRGO,TIM4_CC4,TIM5_CC1,TIM5_CC2,TIM5_CC3,TIM8_CC1,TIM8_TRGO,EXTI11"
|
|
endif
|
|
newline
|
|
rbitfld.long 0x00 22. " JSWSTART ,Start conversion of injected channels" "Reset,Start"
|
|
bitfld.long 0x00 20.--21. " JEXTEN ,External trigger enable for injected channels" "Disabled,Rising edge,Falling edge,Both"
|
|
newline
|
|
sif cpuis("STM32F411*")||cpuis("STM32F401*")
|
|
bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM1_CC4,TIM1_TRGO,TIM2_CC1,TIM2_TRGO2,TIM3_CC2,TIM3_CC4,TIM4_CC1,TIM4_CC2,TIM4_CC3,TIM4_TRGO,TIM5_CC4,TIM5_TRGO,,,,EXTI15"
|
|
elif (cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F767BI"))
|
|
bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM1_TRGO,TIM1_CH4,TIM2_TRGO,TIM2_CH1,TIM3_CH4,TIM4_TRGO,,TIM8_CH4,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_CH3,TIM5_TRGO,TIM3_CH1,TIM6_TRGO,?..."
|
|
else
|
|
bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM1_TRGO,TIM1_CC4,TIM2_TRGO,TIM2_CC1,TIM3_CC4,TIM4_TRGO,,TIM8_CC4,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_CC3,TIM5_TRGO,TIM3_CC1,TIM6_TRGO,EXTI15"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 11. " ALIGN ,Data alignment" "Right,Left"
|
|
bitfld.long 0x00 10. " EOCS ,End of conversion selection" "Sequence,Conversion"
|
|
bitfld.long 0x00 9. " DDS ,DMA disable selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DMA ,Direct memory access mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " CONT ,Continuous conversion" "Single,Continuous"
|
|
bitfld.long 0x00 0. " ADON ,A/D converter ON / OFF" "Disabled,Enabled"
|
|
endif
|
|
sif (!cpuis("STM32F411C?")&&!cpuis("STM32F401C?"))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SMPR1,ADC Sample Time Register 1"
|
|
sif (cpuis("STM32F4??R*")||cpuis("STM32F4??V*")||cpuis("STM32F469I*")||cpuis("STM32F7??V?")||cpuis("STM32F7??R?"))
|
|
bitfld.long 0x00 15.--17. " SMP15 ,Channel 15 sample time selection" "3,15,28,56,84,112,144,480"
|
|
newline
|
|
elif cpuis("STM32F20?R*")||cpuis("STM32F21?R*")||cpuis("STM32F205V*")||cpuis("STM32F207V*")||cpuis("STM32F215V*")
|
|
bitfld.long 0x00 18.--20. " SMP16 ,Channel 16 sample time selection" "3,15,28,56,84,112,144,480"
|
|
bitfld.long 0x00 15.--17. " SMP15 ,Channel 15 sample time selection" "3,15,28,56,84,112,144,480"
|
|
newline
|
|
elif (!cpuis("STM32F405OE")&&!cpuis("STM32F405OG")&&!cpuis("STM32F415OG")&&!cpuis("STM32F446M?"))
|
|
bitfld.long 0x00 24.--26. " SMP18 ,Channel 18 sample time selection" "3,15,28,56,84,112,144,480"
|
|
bitfld.long 0x00 21.--23. " SMP17 ,Channel 17 sample time selection" "3,15,28,56,84,112,144,480"
|
|
bitfld.long 0x00 18.--20. " SMP16 ,Channel 16 sample time selection" "3,15,28,56,84,112,144,480"
|
|
bitfld.long 0x00 15.--17. " SMP15 ,Channel 15 sample time selection" "3,15,28,56,84,112,144,480"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 12.--14. " SMP14 ,Channel 14 sample time selection" "3,15,28,56,84,112,144,480"
|
|
bitfld.long 0x00 9.--11. " SMP13 ,Channel 13 sample time selection" "3,15,28,56,84,112,144,480"
|
|
bitfld.long 0x00 6.--8. " SMP12 ,Channel 12 sample time selection" "3,15,28,56,84,112,144,480"
|
|
bitfld.long 0x00 3.--5. " SMP11 ,Channel 11 sample time selection" "3,15,28,56,84,112,144,480"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " SMP10 ,Channel 10 sample time selection" "3,15,28,56,84,112,144,480"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SMPR2,ADC Sample Time Register 2"
|
|
bitfld.long 0x00 27.--29. " SMP9 ,Channel 9 sample time selection" "3,15,28,56,84,112,144,480"
|
|
bitfld.long 0x00 24.--26. " SMP8 ,Channel 8 sample time selection" "3,15,28,56,84,112,144,480"
|
|
bitfld.long 0x00 21.--23. " SMP7 ,Channel 7 sample time selection" "3,15,28,56,84,112,144,480"
|
|
bitfld.long 0x00 18.--20. " SMP6 ,Channel 6 sample time selection" "3,15,28,56,84,112,144,480"
|
|
newline
|
|
bitfld.long 0x00 15.--17. " SMP5 ,Channel 5 sample time selection" "3,15,28,56,84,112,144,480"
|
|
bitfld.long 0x00 12.--14. " SMP4 ,Channel 4 sample time selection" "3,15,28,56,84,112,144,480"
|
|
bitfld.long 0x00 9.--11. " SMP3 ,Channel 3 sample time selection" "3,15,28,56,84,112,144,480"
|
|
bitfld.long 0x00 6.--8. " SMP2 ,Channel 2 sample time selection" "3,15,28,56,84,112,144,480"
|
|
newline
|
|
bitfld.long 0x00 3.--5. " SMP1 ,Channel 1 sample time selection" "3,15,28,56,84,112,144,480"
|
|
bitfld.long 0x00 0.--2. " SMP0 ,Channel 0 sample time selection" "3,15,28,56,84,112,144,480"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "JOFR1,ADC Injected Channel Data Offset Register 1"
|
|
hexmask.long.word 0x00 0.--11. 0x01 " JOFFSET1 ,Data offset for injected channel 1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "JOFR2,ADC Injected Channel Data Offset Register 2"
|
|
hexmask.long.word 0x00 0.--11. 0x01 " JOFFSET2 ,Data offset for injected channel 2"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "JOFR3,ADC Injected Channel Data Offset Register 3"
|
|
hexmask.long.word 0x00 0.--11. 0x01 " JOFFSET3 ,Data offset for injected channel 3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "JOFR4,ADC Injected Channel Data Offset Register 4"
|
|
hexmask.long.word 0x00 0.--11. 0x01 " JOFFSET4 ,Data offset for injected channel 4"
|
|
group.long 0x24++0x07
|
|
line.long 0x00 "HTR,ADC Watchdog High Threshold Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " HT ,Analog watchdog higher threshold"
|
|
line.long 0x04 "LTR,ADC Watchdog Low Threshold Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " LT ,Analog watchdog lower threshold"
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F411R?")||cpuis("STM32F411V?")||cpuis("STM32F411C?")||cpuis("STM32F401R?")||cpuis("STM32F401V?")||cpuis("STM32F401C?"))
|
|
group.long 0x2C++0x0F
|
|
line.long 0x00 "SQR1,ADC Regular Sequence Register 1"
|
|
bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x04 "SQR2,ADC Regular Sequence Register 2"
|
|
bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
newline
|
|
bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x08 "SQR3,ADC Regular Sequence Register 3"
|
|
bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 10.--14. " SQ3 ,3th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
newline
|
|
bitfld.long 0x08 5.--9. " SQ2 ,2th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 0.--4. " SQ1 ,1th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x0C "JSQR,ADC Injected Sequence Register"
|
|
bitfld.long 0x0C 20.--21. " JL ,Injected sequence length" "1,2,3,4"
|
|
bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x0C 10.--14. " JSQ3 ,3th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x0C 5.--9. " JSQ2 ,2th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
newline
|
|
bitfld.long 0x0C 0.--4. " JSQ1 ,1th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
elif (cpuis("STM32F427A*")||cpuis("STM32F429Z*")||cpuis("STM32F429N*")||cpuis("STM32F429I*")||cpuis("STM32F429B*")||cpuis("STM32F429A*")||cpuis("STM32F437AI")||cpuis("STM32F439AI"))
|
|
group.long 0x2C++0x0F
|
|
line.long 0x00 "SQR1,ADC Regular Sequence Register 1"
|
|
bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
line.long 0x04 "SQR2,ADC Regular Sequence Register 2"
|
|
bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
newline
|
|
bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
line.long 0x08 "SQR3,ADC Regular Sequence Register 3"
|
|
bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x08 10.--14. " SQ3 ,3th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
newline
|
|
bitfld.long 0x08 5.--9. " SQ2 ,2th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x08 0.--4. " SQ1 ,1th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
line.long 0x0C "JSQR,ADC Injected Sequence Register"
|
|
bitfld.long 0x0C 20.--21. " JL ,Injected sequence length" "1,2,3,4"
|
|
bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x0C 10.--14. " JSQ3 ,3th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x0C 5.--9. " JSQ2 ,2th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
newline
|
|
bitfld.long 0x0C 0.--4. " JSQ1 ,1th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
elif (cpuis("STM32F20?R*")||cpuis("STM32F21?R*")||cpuis("STM32F205V*")||cpuis("STM32F207V*")||cpuis("STM32F215V*")||cpuis("STM32F4??R*")||cpuis("STM32F4??V*")||cpuis("STM32F469I*"))
|
|
group.long 0x2C++0x0F
|
|
line.long 0x00 "SQR1,ADC Regular Sequence Register 1"
|
|
bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
line.long 0x04 "SQR2,ADC Regular Sequence Register 2"
|
|
bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
newline
|
|
bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
line.long 0x08 "SQR3,ADC Regular Sequence Register 3"
|
|
bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x08 10.--14. " SQ3 ,3th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
newline
|
|
bitfld.long 0x08 5.--9. " SQ2 ,2th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x08 0.--4. " SQ1 ,1th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
line.long 0x0C "JSQR,ADC Injected Sequence Register"
|
|
bitfld.long 0x0C 20.--21. " JL ,Injected sequence length" "1,2,3,4"
|
|
bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x0C 10.--14. " JSQ3 ,3th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x0C 5.--9. " JSQ2 ,2th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
newline
|
|
bitfld.long 0x0C 0.--4. " JSQ1 ,1th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
elif (cpuis("STM32F405O*")||cpuis("STM32F415O*"))
|
|
group.long 0x2C++0x0F
|
|
line.long 0x00 "SQR1,ADC Regular Sequence Register 1"
|
|
bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
line.long 0x04 "SQR2,ADC Regular Sequence Register 2"
|
|
bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
newline
|
|
bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
line.long 0x08 "SQR3,ADC Regular Sequence Register 3"
|
|
bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
bitfld.long 0x08 10.--14. " SQ3 ,3th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
newline
|
|
bitfld.long 0x08 5.--9. " SQ2 ,2th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
bitfld.long 0x08 0.--4. " SQ1 ,1th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
line.long 0x0C "JSQR,ADC Injected Sequence Register"
|
|
bitfld.long 0x0C 20.--21. " JL ,Injected sequence length" "1,2,3,4"
|
|
bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
bitfld.long 0x0C 10.--14. " JSQ3 ,3th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
bitfld.long 0x0C 5.--9. " JSQ2 ,2th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
newline
|
|
bitfld.long 0x0C 0.--4. " JSQ1 ,1th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
else
|
|
group.long 0x2C++0x0F
|
|
line.long 0x00 "SQR1,ADC Regular Sequence Register 1"
|
|
bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x04 "SQR2,ADC Regular Sequence Register 2"
|
|
bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
newline
|
|
bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x08 "SQR3,ADC Regular Sequence Register 3"
|
|
bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 10.--14. " SQ3 ,3th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
newline
|
|
bitfld.long 0x08 5.--9. " SQ2 ,2th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 0.--4. " SQ1 ,1th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x0C "JSQR,ADC Injected Sequence Register"
|
|
bitfld.long 0x0C 20.--21. " JL ,Injected sequence length" "1,2,3,4"
|
|
bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x0C 10.--14. " JSQ3 ,3th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x0C 5.--9. " JSQ2 ,2th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
newline
|
|
bitfld.long 0x0C 0.--4. " JSQ1 ,1th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
endif
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "JDR1,ADC Injected Data Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "JDR2,ADC Injected Data Register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "JDR3,ADC Injected Data Register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "JDR4,ADC Injected Data Register 4"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DR,ADC Regular Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Regular data"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ADC 3"
|
|
base ad:0x40012200
|
|
width 7.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "SR,ADC Status Register"
|
|
bitfld.long 0x00 5. " OVR ,Overrun" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " STRT ,Regular channel start flag" "Not started,Started"
|
|
bitfld.long 0x00 3. " JSTRT ,Injected channel start flag" "Not started,Started"
|
|
bitfld.long 0x00 2. " JEOC ,Injected channel end of conversion" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x00 1. " EOC ,Regular channel end of conversion" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " AWD ,Analog watchdog flag" "Not occurred,Occurred"
|
|
line.long 0x04 "CR1,ADC Control Register 1"
|
|
bitfld.long 0x04 26. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24.--25. " RES ,Resolution" "12-bit,10-bit,8-bit,6-bit"
|
|
bitfld.long 0x04 23. " AWDEN ,Analog watchdog enable on regular channels" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " JAWDEN ,Analog watchdog enable on injected channels" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 13.--15. " DISCNUM ,Discontinuous mode channel count" "1CH,2CH,3CH,4CH,5CH,6CH,7CH,8CH"
|
|
bitfld.long 0x04 12. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " DISCEN ,Discontinuous mode on regular channels" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " JAUTO ,Automatic injected group conversion" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 9. " AWDSGL ,Enable the watchdog on a single channel in scan mode" "All,Single"
|
|
bitfld.long 0x04 8. " SCAN ,Scan mode" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " JEOCIE ,Interrupt enable for injected channels" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 5. " EOCIE ,Interrupt enable for EOC" "Disabled,Enabled"
|
|
sif (cpuis("STM32F411C?")||cpuis("STM32F401C?"))
|
|
newline
|
|
bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,?..."
|
|
elif (cpuis("STM32F405O*")||cpuis("STM32F415O*"))
|
|
newline
|
|
bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,?..."
|
|
elif (cpuis("STM32F446M?")||cpuis("STM32F469V*")||cpuis("STM32F479V*"))
|
|
newline
|
|
bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,?..."
|
|
elif (cpuis("STM32F4??R*")||cpuis("STM32F4??V*")||cpuis("STM32F469I*")||cpuis("STM32F20?R*")||cpuis("STM32F21?R*")||cpuis("STM32F205V*")||cpuis("STM32F207V*")||cpuis("STM32F215V*")||cpuis("STM32F7??V?")||cpuis("STM32F7?2R?")||cpuis("STM32F730R8"))
|
|
newline
|
|
bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_IN15,?..."
|
|
elif (cpuis("STM32F469Z*")||cpuis("STM32F479Z*"))
|
|
newline
|
|
bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_IN15,ADC_IN16,ADC_IN17,ADC_IN18,ADC_IN19,?..."
|
|
else
|
|
newline
|
|
bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_IN15,ADC_IN16,ADC_IN17,ADC_IN18,ADC_IN19,ADC_IN20,ADC_IN21,ADC_IN22,ADC_IN23,?..."
|
|
endif
|
|
if (((per.l(ad:0x40012200+0x08))&0x01)==0x01)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR2,ADC Control Register 2"
|
|
bitfld.long 0x00 30. " SWSTART ,Start conversion of regular channels" "Reset,Start"
|
|
bitfld.long 0x00 28.--29. " EXTEN ,External trigger enable for regular channels" "Disabled,Rising edge,Falling edge,Both"
|
|
sif cpuis("STM32F411*")||cpuis("STM32F401*")
|
|
newline
|
|
bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM1_CC1,TIM1_CC2,TIM1_CC3,TIM2_CC2,TIM2_CC3,TIM2_CC4,TIM2_TRGO,TIM3_CC1,TIM3_TRGO,TIM4_CC4,TIM5_CC1,TIM5_CC2,TIM5_CC3,,,EXTI11"
|
|
elif cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F75*")||cpuis("STM32F767BI")
|
|
newline
|
|
bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM1_CH1,TIM1_CH2,TIM1_CH3,TIM2_CH2,TIM5_TRGO,TIM4_CH4,TIM3_CH4,TIM8_TRGO,TIM8_TRGO2,TIM1_TRGO,TIM1_TRGO2,TIM2_TRGO,TIM4_TRGO,TIM6_TRGO,,EXTI11"
|
|
else
|
|
newline
|
|
bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM1_CC1,TIM1_CC2,TIM1_CC3,TIM2_CC2,TIM5_TRGO,TIM4_CCM3,TIM3_CCM4,TIM8_TRGO2,TIM8_TRGO2,TIM1_TRGO,TIM1_TRGO2,TIM2_TRGO,TIM4_TRGO,TIM6_TRGO,,EXTI11"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 22. " JSWSTART ,Start conversion of injected channels" "Reset,Start"
|
|
bitfld.long 0x00 20.--21. " JEXTEN ,External trigger enable for injected channels" "Disabled,Rising edge,Falling edge,Both"
|
|
newline
|
|
sif cpuis("STM32F411*")||cpuis("STM32F401*")
|
|
bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM1_CC4,TIM1_TRGO,TIM2_CC1,TIM2_TRGO2,TIM3_CC2,TIM3_CC4,TIM4_CC1,TIM4_CC2,TIM4_CC3,TIM4_TRGO,TIM5_CC4,TIM5_TRGO,,,,EXTI15"
|
|
elif cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis(" STM32F75*")||cpuis("STM32F767BI")
|
|
bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM1_TRGO,TIM1_CH4,TIM2_TRGO,TIM2_CH1,TIM3_CH4,TIM4_TRGO,,TIM8_CH4,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_CH3,TIM5_TRGO,TIM3_CH1,TIM6_TRGO,?..."
|
|
else
|
|
bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM1_TRGO,TIM1_CH4,TIM2_TRGO,TIM2_CH1,TIM3_CH4,TIM4_TRGO,,TIM8_CH4,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_CH3,TIM5_TRGO,TIM3_CH1,TIM6_TRGO,EXTI15"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 11. " ALIGN ,Data alignment" "Right,Left"
|
|
bitfld.long 0x00 10. " EOCS ,End of conversion selection" "Sequence,Conversion"
|
|
bitfld.long 0x00 9. " DDS ,DMA disable selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DMA ,Direct memory access mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " CONT ,Continuous conversion" "Single,Continuous"
|
|
bitfld.long 0x00 0. " ADON ,A/D converter ON / OFF" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR2,ADC Control Register 2"
|
|
rbitfld.long 0x00 30. " SWSTART ,Start conversion of regular channels" "Reset,Start"
|
|
bitfld.long 0x00 28.--29. " EXTEN ,External trigger enable for regular channels" "Disabled,Rising edge,Falling edge,Both"
|
|
newline
|
|
sif cpuis("STM32F411*")||cpuis("STM32F401*")
|
|
bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM1_CC1,TIM1_CC2,TIM1_CC3,TIM2_CC2,TIM5_TRGO,TIM4_CCM3,TIM3_CCM4,TIM8_TRGO2,TIM8_TRGO2,TIM1_TRGO,TIM1_TRGO2,TIM2_TRGO,TIM4_TRGO,TIM6_TRGO,,EXTI11"
|
|
elif cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F75*")||cpuis("STM32F767BI")
|
|
bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM1_CH1,TIM1_CH2,TIM1_CH3,TIM2_CH2,TIM5_TRGO,TIM4_CH4,TIM3_CH4,TIM8_TRGO,TIM8_TRGO2,TIM1_TRGO,TIM1_TRGO2,TIM2_TRGO,TIM4_TRGO,TIM6_TRGO,,EXTI11"
|
|
else
|
|
bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM1_CC1,TIM1_CC2,TIM1_CC3,TIM2_CC2,TIM2_CC3,TIM2_CC4,TIM2_TRGO,TIM3_CC1,TIM3_TRGO,TIM4_CC4,TIM5_CC1,TIM5_CC2,TIM5_CC3,TIM8_CC1,TIM8_TRGO,EXTI11"
|
|
endif
|
|
newline
|
|
rbitfld.long 0x00 22. " JSWSTART ,Start conversion of injected channels" "Reset,Start"
|
|
bitfld.long 0x00 20.--21. " JEXTEN ,External trigger enable for injected channels" "Disabled,Rising edge,Falling edge,Both"
|
|
newline
|
|
sif cpuis("STM32F411*")||cpuis("STM32F401*")
|
|
bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM1_CC4,TIM1_TRGO,TIM2_CC1,TIM2_TRGO2,TIM3_CC2,TIM3_CC4,TIM4_CC1,TIM4_CC2,TIM4_CC3,TIM4_TRGO,TIM5_CC4,TIM5_TRGO,,,,EXTI15"
|
|
elif (cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F767BI"))
|
|
bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM1_TRGO,TIM1_CH4,TIM2_TRGO,TIM2_CH1,TIM3_CH4,TIM4_TRGO,,TIM8_CH4,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_CH3,TIM5_TRGO,TIM3_CH1,TIM6_TRGO,?..."
|
|
else
|
|
bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM1_TRGO,TIM1_CC4,TIM2_TRGO,TIM2_CC1,TIM3_CC4,TIM4_TRGO,,TIM8_CC4,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_CC3,TIM5_TRGO,TIM3_CC1,TIM6_TRGO,EXTI15"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 11. " ALIGN ,Data alignment" "Right,Left"
|
|
bitfld.long 0x00 10. " EOCS ,End of conversion selection" "Sequence,Conversion"
|
|
bitfld.long 0x00 9. " DDS ,DMA disable selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DMA ,Direct memory access mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " CONT ,Continuous conversion" "Single,Continuous"
|
|
bitfld.long 0x00 0. " ADON ,A/D converter ON / OFF" "Disabled,Enabled"
|
|
endif
|
|
sif (!cpuis("STM32F411C?")&&!cpuis("STM32F401C?"))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SMPR1,ADC Sample Time Register 1"
|
|
sif (cpuis("STM32F4??R*")||cpuis("STM32F4??V*")||cpuis("STM32F469I*")||cpuis("STM32F7??V?")||cpuis("STM32F7??R?"))
|
|
bitfld.long 0x00 15.--17. " SMP15 ,Channel 15 sample time selection" "3,15,28,56,84,112,144,480"
|
|
newline
|
|
elif cpuis("STM32F20?R*")||cpuis("STM32F21?R*")||cpuis("STM32F205V*")||cpuis("STM32F207V*")||cpuis("STM32F215V*")
|
|
bitfld.long 0x00 18.--20. " SMP16 ,Channel 16 sample time selection" "3,15,28,56,84,112,144,480"
|
|
bitfld.long 0x00 15.--17. " SMP15 ,Channel 15 sample time selection" "3,15,28,56,84,112,144,480"
|
|
newline
|
|
elif (!cpuis("STM32F405OE")&&!cpuis("STM32F405OG")&&!cpuis("STM32F415OG")&&!cpuis("STM32F446M?"))
|
|
bitfld.long 0x00 24.--26. " SMP18 ,Channel 18 sample time selection" "3,15,28,56,84,112,144,480"
|
|
bitfld.long 0x00 21.--23. " SMP17 ,Channel 17 sample time selection" "3,15,28,56,84,112,144,480"
|
|
bitfld.long 0x00 18.--20. " SMP16 ,Channel 16 sample time selection" "3,15,28,56,84,112,144,480"
|
|
bitfld.long 0x00 15.--17. " SMP15 ,Channel 15 sample time selection" "3,15,28,56,84,112,144,480"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 12.--14. " SMP14 ,Channel 14 sample time selection" "3,15,28,56,84,112,144,480"
|
|
bitfld.long 0x00 9.--11. " SMP13 ,Channel 13 sample time selection" "3,15,28,56,84,112,144,480"
|
|
bitfld.long 0x00 6.--8. " SMP12 ,Channel 12 sample time selection" "3,15,28,56,84,112,144,480"
|
|
bitfld.long 0x00 3.--5. " SMP11 ,Channel 11 sample time selection" "3,15,28,56,84,112,144,480"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " SMP10 ,Channel 10 sample time selection" "3,15,28,56,84,112,144,480"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SMPR2,ADC Sample Time Register 2"
|
|
bitfld.long 0x00 27.--29. " SMP9 ,Channel 9 sample time selection" "3,15,28,56,84,112,144,480"
|
|
bitfld.long 0x00 24.--26. " SMP8 ,Channel 8 sample time selection" "3,15,28,56,84,112,144,480"
|
|
bitfld.long 0x00 21.--23. " SMP7 ,Channel 7 sample time selection" "3,15,28,56,84,112,144,480"
|
|
bitfld.long 0x00 18.--20. " SMP6 ,Channel 6 sample time selection" "3,15,28,56,84,112,144,480"
|
|
newline
|
|
bitfld.long 0x00 15.--17. " SMP5 ,Channel 5 sample time selection" "3,15,28,56,84,112,144,480"
|
|
bitfld.long 0x00 12.--14. " SMP4 ,Channel 4 sample time selection" "3,15,28,56,84,112,144,480"
|
|
bitfld.long 0x00 9.--11. " SMP3 ,Channel 3 sample time selection" "3,15,28,56,84,112,144,480"
|
|
bitfld.long 0x00 6.--8. " SMP2 ,Channel 2 sample time selection" "3,15,28,56,84,112,144,480"
|
|
newline
|
|
bitfld.long 0x00 3.--5. " SMP1 ,Channel 1 sample time selection" "3,15,28,56,84,112,144,480"
|
|
bitfld.long 0x00 0.--2. " SMP0 ,Channel 0 sample time selection" "3,15,28,56,84,112,144,480"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "JOFR1,ADC Injected Channel Data Offset Register 1"
|
|
hexmask.long.word 0x00 0.--11. 0x01 " JOFFSET1 ,Data offset for injected channel 1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "JOFR2,ADC Injected Channel Data Offset Register 2"
|
|
hexmask.long.word 0x00 0.--11. 0x01 " JOFFSET2 ,Data offset for injected channel 2"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "JOFR3,ADC Injected Channel Data Offset Register 3"
|
|
hexmask.long.word 0x00 0.--11. 0x01 " JOFFSET3 ,Data offset for injected channel 3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "JOFR4,ADC Injected Channel Data Offset Register 4"
|
|
hexmask.long.word 0x00 0.--11. 0x01 " JOFFSET4 ,Data offset for injected channel 4"
|
|
group.long 0x24++0x07
|
|
line.long 0x00 "HTR,ADC Watchdog High Threshold Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " HT ,Analog watchdog higher threshold"
|
|
line.long 0x04 "LTR,ADC Watchdog Low Threshold Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " LT ,Analog watchdog lower threshold"
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F411R?")||cpuis("STM32F411V?")||cpuis("STM32F411C?")||cpuis("STM32F401R?")||cpuis("STM32F401V?")||cpuis("STM32F401C?"))
|
|
group.long 0x2C++0x0F
|
|
line.long 0x00 "SQR1,ADC Regular Sequence Register 1"
|
|
bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x04 "SQR2,ADC Regular Sequence Register 2"
|
|
bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
newline
|
|
bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x08 "SQR3,ADC Regular Sequence Register 3"
|
|
bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 10.--14. " SQ3 ,3th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
newline
|
|
bitfld.long 0x08 5.--9. " SQ2 ,2th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 0.--4. " SQ1 ,1th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x0C "JSQR,ADC Injected Sequence Register"
|
|
bitfld.long 0x0C 20.--21. " JL ,Injected sequence length" "1,2,3,4"
|
|
bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x0C 10.--14. " JSQ3 ,3th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x0C 5.--9. " JSQ2 ,2th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
newline
|
|
bitfld.long 0x0C 0.--4. " JSQ1 ,1th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
elif (cpuis("STM32F427A*")||cpuis("STM32F429Z*")||cpuis("STM32F429N*")||cpuis("STM32F429I*")||cpuis("STM32F429B*")||cpuis("STM32F429A*")||cpuis("STM32F437AI")||cpuis("STM32F439AI"))
|
|
group.long 0x2C++0x0F
|
|
line.long 0x00 "SQR1,ADC Regular Sequence Register 1"
|
|
bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
line.long 0x04 "SQR2,ADC Regular Sequence Register 2"
|
|
bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
newline
|
|
bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
line.long 0x08 "SQR3,ADC Regular Sequence Register 3"
|
|
bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x08 10.--14. " SQ3 ,3th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
newline
|
|
bitfld.long 0x08 5.--9. " SQ2 ,2th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x08 0.--4. " SQ1 ,1th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
line.long 0x0C "JSQR,ADC Injected Sequence Register"
|
|
bitfld.long 0x0C 20.--21. " JL ,Injected sequence length" "1,2,3,4"
|
|
bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x0C 10.--14. " JSQ3 ,3th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
bitfld.long 0x0C 5.--9. " JSQ2 ,2th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
newline
|
|
bitfld.long 0x0C 0.--4. " JSQ1 ,1th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..."
|
|
elif (cpuis("STM32F20?R*")||cpuis("STM32F21?R*")||cpuis("STM32F205V*")||cpuis("STM32F207V*")||cpuis("STM32F215V*")||cpuis("STM32F4??R*")||cpuis("STM32F4??V*")||cpuis("STM32F469I*"))
|
|
group.long 0x2C++0x0F
|
|
line.long 0x00 "SQR1,ADC Regular Sequence Register 1"
|
|
bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
line.long 0x04 "SQR2,ADC Regular Sequence Register 2"
|
|
bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
newline
|
|
bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
line.long 0x08 "SQR3,ADC Regular Sequence Register 3"
|
|
bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x08 10.--14. " SQ3 ,3th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
newline
|
|
bitfld.long 0x08 5.--9. " SQ2 ,2th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x08 0.--4. " SQ1 ,1th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
line.long 0x0C "JSQR,ADC Injected Sequence Register"
|
|
bitfld.long 0x0C 20.--21. " JL ,Injected sequence length" "1,2,3,4"
|
|
bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x0C 10.--14. " JSQ3 ,3th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x0C 5.--9. " JSQ2 ,2th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
newline
|
|
bitfld.long 0x0C 0.--4. " JSQ1 ,1th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
elif (cpuis("STM32F405O*")||cpuis("STM32F415O*"))
|
|
group.long 0x2C++0x0F
|
|
line.long 0x00 "SQR1,ADC Regular Sequence Register 1"
|
|
bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
line.long 0x04 "SQR2,ADC Regular Sequence Register 2"
|
|
bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
newline
|
|
bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
line.long 0x08 "SQR3,ADC Regular Sequence Register 3"
|
|
bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
bitfld.long 0x08 10.--14. " SQ3 ,3th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
newline
|
|
bitfld.long 0x08 5.--9. " SQ2 ,2th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
bitfld.long 0x08 0.--4. " SQ1 ,1th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
line.long 0x0C "JSQR,ADC Injected Sequence Register"
|
|
bitfld.long 0x0C 20.--21. " JL ,Injected sequence length" "1,2,3,4"
|
|
bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
bitfld.long 0x0C 10.--14. " JSQ3 ,3th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
bitfld.long 0x0C 5.--9. " JSQ2 ,2th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
newline
|
|
bitfld.long 0x0C 0.--4. " JSQ1 ,1th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
else
|
|
group.long 0x2C++0x0F
|
|
line.long 0x00 "SQR1,ADC Regular Sequence Register 1"
|
|
bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x04 "SQR2,ADC Regular Sequence Register 2"
|
|
bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
newline
|
|
bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x08 "SQR3,ADC Regular Sequence Register 3"
|
|
bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 10.--14. " SQ3 ,3th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
newline
|
|
bitfld.long 0x08 5.--9. " SQ2 ,2th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 0.--4. " SQ1 ,1th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x0C "JSQR,ADC Injected Sequence Register"
|
|
bitfld.long 0x0C 20.--21. " JL ,Injected sequence length" "1,2,3,4"
|
|
bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x0C 10.--14. " JSQ3 ,3th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x0C 5.--9. " JSQ2 ,2th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
newline
|
|
bitfld.long 0x0C 0.--4. " JSQ1 ,1th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
endif
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "JDR1,ADC Injected Data Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "JDR2,ADC Injected Data Register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "JDR3,ADC Injected Data Register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "JDR4,ADC Injected Data Register 4"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DR,ADC Regular Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Regular data"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "DAC (Digital-to-Analog Converter)"
|
|
base ad:0x40007400
|
|
width 9.
|
|
if ((per.l(ad:0x40007400)&0x40004)==0x40004)
|
|
if ((per.l(ad:0x40007400)&0xC000C0)==(0xC000C0||0xC00080||0x8000C0||0x800080))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,DAC Control Register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,DAC channel 2 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel 2 mask/amplitude selector" "1,3,7,15,31,63,127,255,511,1023,2047,4095,4095,4095,4095,4095"
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
newline
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel 2 trigger selection" "Timer 6 TRGO,Timer 8 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel 1 mask/amplitude selector" "1,3,7,15,31,63,127,255,511,1023,2047,4095,4095,4095,4095,4095"
|
|
bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel1 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
newline
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel 1 trigger selection" "Timer 6 TRGO,Timer 8 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40007400)&0xC000C0)==(0xC00040||0x800040))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,DAC Control Register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,DAC channel 2 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel 2 mask/amplitude selector" "1,3,7,15,31,63,127,255,511,1023,2047,4095,4095,4095,4095,4095"
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
newline
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel 2 trigger selection" "Timer 6 TRGO,Timer 8 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel 1 mask/amplitude selector" "0,[1:0],[2:0],[3:0],[4:0],[5:0],[6:0],[7:0],[8:0],[9:0],[10:0],[11:0],[11:0],[11:0],[11:0],[11:0]"
|
|
bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel1 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
newline
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel 1 trigger selection" "Timer 6 TRGO,Timer 8 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40007400)&0xC000C0)==(0xC00000||0x800000))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,DAC Control Register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,DAC channel 2 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel 2 mask/amplitude selector" "1,3,7,15,31,63,127,255,511,1023,2047,4095,4095,4095,4095,4095"
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
newline
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel 2 trigger selection" "Timer 6 TRGO,Timer 8 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
textfld " "
|
|
bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel1 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
newline
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel 1 trigger selection" "Timer 6 TRGO,Timer 8 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40007400)&0xC000C0)==(0x4000C0||0x400080))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,DAC Control Register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,DAC channel 2 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel 2 mask/amplitude selector" "0,[1:0],[2:0],[3:0],[4:0],[5:0],[6:0],[7:0],[8:0],[9:0],[10:0],[11:0],[11:0],[11:0],[11:0],[11:0]"
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
newline
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel 2 trigger selection" "Timer 6 TRGO,Timer 8 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel 1 mask/amplitude selector" "1,3,7,15,31,63,127,255,511,1023,2047,4095,4095,4095,4095,4095"
|
|
bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel1 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
newline
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel 1 trigger selection" "Timer 6 TRGO,Timer 8 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40007400)&0xC000C0)==(0x400040))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,DAC Control Register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,DAC channel 2 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel 2 mask/amplitude selector" "0,[1:0],[2:0],[3:0],[4:0],[5:0],[6:0],[7:0],[8:0],[9:0],[10:0],[11:0],[11:0],[11:0],[11:0],[11:0]"
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
newline
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel 2 trigger selection" "Timer 6 TRGO,Timer 8 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel 1 mask/amplitude selector" "0,[1:0],[2:0],[3:0],[4:0],[5:0],[6:0],[7:0],[8:0],[9:0],[10:0],[11:0],[11:0],[11:0],[11:0],[11:0]"
|
|
bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel1 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
newline
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel 1 trigger selection" "Timer 6 TRGO,Timer 8 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40007400)&0xC000C0)==(0x400000))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,DAC Control Register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,DAC channel 2 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel 2 mask/amplitude selector" "0,[1:0],[2:0],[3:0],[4:0],[5:0],[6:0],[7:0],[8:0],[9:0],[10:0],[11:0],[11:0],[11:0],[11:0],[11:0]"
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
newline
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel 2 trigger selection" "Timer 6 TRGO,Timer 8 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
textfld " "
|
|
bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel1 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
newline
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel 1 trigger selection" "Timer 6 TRGO,Timer 8 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40007400)&0xC000C0)==(0xC0||0x80))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,DAC Control Register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,DAC channel 2 DMA enable" "Disabled,Enabled"
|
|
textfld " "
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
newline
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel 2 trigger selection" "Timer 6 TRGO,Timer 8 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel 1 mask/amplitude selector" "1,3,7,15,31,63,127,255,511,1023,2047,4095,4095,4095,4095,4095"
|
|
bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel1 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
newline
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel 1 trigger selection" "Timer 6 TRGO,Timer 8 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40007400)&0xC000C0)==(0x40))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,DAC Control Register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,DAC channel 2 DMA enable" "Disabled,Enabled"
|
|
textfld " "
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
newline
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel 2 trigger selection" "Timer 6 TRGO,Timer 8 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel 1 mask/amplitude selector" "0,[1:0],[2:0],[3:0],[4:0],[5:0],[6:0],[7:0],[8:0],[9:0],[10:0],[11:0],[11:0],[11:0],[11:0],[11:0]"
|
|
bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel1 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
newline
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel 1 trigger selection" "Timer 6 TRGO,Timer 8 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,DAC Control Register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,DAC channel 2 DMA enable" "Disabled,Enabled"
|
|
textfld " "
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
newline
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel 2 trigger selection" "Timer 6 TRGO,Timer 8 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
textfld " "
|
|
bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel1 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
newline
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel 1 trigger selection" "Timer 6 TRGO,Timer 8 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40007400)&0x40004)==0x40000)
|
|
if ((per.l(ad:0x40007400)&0xC00000)==(0xC00000||0x800000))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,DAC Control Register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,DAC channel 2 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel 2 mask/amplitude selector" "1,3,7,15,31,63,127,255,511,1023,2047,4095,4095,4095,4095,4095"
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
newline
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel 2 trigger selection" "Timer 6 TRGO,Timer 8 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40007400)&0xC00000)==(0x400000))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,DAC Control Register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,DAC channel 2 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel 2 mask/amplitude selector" "0,[1:0],[2:0],[3:0],[4:0],[5:0],[6:0],[7:0],[8:0],[9:0],[10:0],[11:0],[11:0],[11:0],[11:0],[11:0]"
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
newline
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel 2 trigger selection" "Timer 6 TRGO,Timer 8 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,DAC Control Register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,DAC channel 2 DMA enable" "Disabled,Enabled"
|
|
textfld " "
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
newline
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel 2 trigger selection" "Timer 6 TRGO,Timer 8 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40007400)&0x40004)==0x04)
|
|
if ((per.l(ad:0x40007400)&0xC0)==(0xC0||0x80))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,DAC Control Register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,DAC channel 2 DMA enable" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel 1 mask/amplitude selector" "1,3,7,15,31,63,127,255,511,1023,2047,4095,4095,4095,4095,4095"
|
|
bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel1 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
newline
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel 1 trigger selection" "Timer 6 TRGO,Timer 8 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40007400)&0xC0)==(0x40))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,DAC Control Register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,DAC channel 2 DMA enable" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel 1 mask/amplitude selector" "0,[1:0],[2:0],[3:0],[4:0],[5:0],[6:0],[7:0],[8:0],[9:0],[10:0],[11:0],[11:0],[11:0],[11:0],[11:0]"
|
|
bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel1 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
newline
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel 1 trigger selection" "Timer 6 TRGO,Timer 8 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,DAC Control Register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,DAC channel 2 DMA enable" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
textfld " "
|
|
bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel1 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
newline
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel 1 trigger selection" "Timer 6 TRGO,Timer 8 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,DAC Control Register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,DAC channel 2 DMA enable" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "SWTRIGR,DAC Software Trigger Register"
|
|
bitfld.long 0x00 1. " SWTRIG2 ,Channel 2 software trigger" "Disable,Enable"
|
|
bitfld.long 0x00 0. " SWTRIG1 ,Channel 1 software trigger" "Disable,Enable"
|
|
group.long 0x08++0x23
|
|
line.long 0x00 "DHR12R1,DAC Channel 1 12-bit Right Aligned Data Holding Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DACC1DHR ,DAC channel 1 12-bit right aligned data"
|
|
line.long 0x04 "DHR12L1,DAC Channel 1 12-bit Left Aligned Data Holding Register"
|
|
hexmask.long.word 0x04 4.--15. 1. " DACC1DHR ,DAC channel 1 12-bit left aligned data"
|
|
line.long 0x08 "DHR8R1,DAC Channel 1 8-bit Right Aligned Data Holding Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DACC1DHR ,DAC channel 1 8-bit right aligned data"
|
|
line.long 0x0C "DHR12R2,Channel 2 12-bit Right Aligned Data Holding Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " DACC2DHR ,Channel 2 12-bit right-aligned data"
|
|
line.long 0x10 "DHR12L2,Channel 2 12-bit Left Aligned Data Holding Register"
|
|
hexmask.long.word 0x10 4.--15. 1. " DACC2DHR ,Channel 2 12-bit left-aligned data"
|
|
line.long 0x14 "DHR8R2,Channel 2 8-bit Right-aligned Data Holding Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " DACC2DHR ,Channel 2 8-bit right-aligned data"
|
|
line.long 0x18 "DHR12RD,Dual 12-bit Right Aligned Data Holding Register"
|
|
hexmask.long.word 0x18 16.--27. 1. " DACC2DHR ,Channel 2 12-bit right-aligned data"
|
|
hexmask.long.word 0x18 0.--11. 1. " DACC1DHR ,Channel 1 12-bit right-aligned data"
|
|
line.long 0x1C "DHR12LD,DUAL 12-bit Left Aligned Data Holding Register"
|
|
hexmask.long.word 0x1C 20.--31. 1. " DACC2DHR ,Channel 2 12-bit left-aligned data"
|
|
hexmask.long.word 0x1C 4.--15. 1. " DACC1DHR ,Channel 1 12-bit left-aligned data"
|
|
line.long 0x20 "DHR8RD,DUAL 8-bit Right Aligned Data Holding Register"
|
|
hexmask.long.byte 0x20 8.--15. 1. " DACC2DHR ,Channel 2 8-bit right-aligned data"
|
|
hexmask.long.byte 0x20 0.--7. 1. " DACC1DHR ,Channel 1 8-bit right-aligned data"
|
|
rgroup.long 0x2C++0x07
|
|
line.long 0x00 "DOR1,DAC Channel 1 Data Output Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DACC1DOR ,Channel 1 data output"
|
|
line.long 0x04 "DOR2,DAC Channel 2 Data Output Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " DACC2DOR ,Channel 2 data output"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
eventfld.long 0x00 29. " DMAUDR2 ,DAC channel 2 DMA underrun flag" "No error,Error"
|
|
eventfld.long 0x00 13. " DMAUDR1 ,DAC channel 1 DMA underrun flag" "No error,Error"
|
|
width 0x0B
|
|
tree.end
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
tree.open "DFSDM1 (Digital filter for sigma delta modulators)"
|
|
base ad:0x40017400
|
|
width 20.
|
|
tree "Channel 0"
|
|
if (((per.l(ad:0x40017400+0x0))&0x80)==0x00)
|
|
if (((per.l(ad:0x40017400))&0x80000000)==0x00)
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "DFSDM_CH0CFGR1,DFSDM Channel 0 Configuration Register"
|
|
bitfld.long 0x00 31. " DFSDMEN ,Global enable for DFSDM interface" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CKOUTSRC ,Output serial clock source selection" "SysClock,AudioClock"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CKOUTDIV ,Output serial clock divider"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN0R register" "Standard,Interleaved,Dual,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 0" "Ext serial inputs,,Internal DFSDM_CHDATIN0R,?..."
|
|
bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(0+1) mod 8 channel"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHEN ,Channel 0 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 0" "Ext DFSDM_CKIN0(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 0" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)"
|
|
else
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "DFSDM_CH0CFGR1,DFSDM Channel 0 Configuration Register"
|
|
bitfld.long 0x00 31. " DFSDMEN ,Global enable for DFSDM interface" "Disabled,Enabled"
|
|
rbitfld.long 0x00 30. " CKOUTSRC ,Output serial clock source selection" "SysClock,AudioClock"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CKOUTDIV ,Output serial clock divider"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN0R register" "Standard,Interleaved,Dual,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 0" "Ext serial inputs,,Internal DFSDM_CHDATIN0R,?..."
|
|
bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(0+1) mod 8 channel"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHEN ,Channel 0 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 0" "Ext DFSDM_CKIN0(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 0" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40017400))&0x80000000)==0x00)
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "DFSDM_CH0CFGR1,DFSDM Channel 0 Configuration Register"
|
|
bitfld.long 0x00 31. " DFSDMEN ,Global enable for DFSDM interface" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CKOUTSRC ,Output serial clock source selection" "SysClock,AudioClock"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CKOUTDIV ,Output serial clock divider"
|
|
textline " "
|
|
rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN0R register" "Standard,Interleaved,Dual,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 0" "Ext serial inputs,,Internal DFSDM_CHDATIN0R,?..."
|
|
rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(0+1) mod 8 channel"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHEN ,Channel 0 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 0" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 0" "Ext DFSDM_CKIN0(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)"
|
|
textline " "
|
|
rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 0" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)"
|
|
else
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "DFSDM_CH0CFGR1,DFSDM Channel 0 Configuration Register"
|
|
bitfld.long 0x00 31. " DFSDMEN ,Global enable for DFSDM interface" "Disabled,Enabled"
|
|
rbitfld.long 0x00 30. " CKOUTSRC ,Output serial clock source selection" "SysClock,AudioClock"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CKOUTDIV ,Output serial clock divider"
|
|
textline " "
|
|
rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN0R register" "Standard,Interleaved,Dual,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 0" "Ext serial inputs,,Internal DFSDM_CHDATIN0R,?..."
|
|
rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(0+1) mod 8 channel"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHEN ,Channel 0 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 0" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 0" "Ext DFSDM_CKIN0(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)"
|
|
textline " "
|
|
rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 0" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40017400+0x0))&0x80)==0x0)
|
|
group.long (0x0+0x04)++0x07
|
|
line.long 0x00 "DFSDM_CH0CFGR2,DFSDM Channel 0 Configuration Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 0"
|
|
bitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "DFSDM_CH0AWSCDR,DFSDM Channel 0 Analog Watchdog And Short-circuit Detector Register"
|
|
bitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 0" "FastSinc,Sinc1,Sinc2,Sinc3"
|
|
bitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 15. " BKSCD3 ,Break signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned"
|
|
bitfld.long 0x04 14. " BKSCD2 ,Break signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned"
|
|
textline " "
|
|
bitfld.long 0x04 13. " BKSCD1 ,Break signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned"
|
|
bitfld.long 0x04 12. " BKSCD0 ,Break signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 0"
|
|
else
|
|
group.long (0x0+0x04)++0x07
|
|
line.long 0x00 "DFSDM_CH0CFGR2,DFSDM Channel 0 Configuration Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 0"
|
|
rbitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "DFSDM_CH0AWSCDR,DFSDM Channel 0 Analog Watchdog And Short-circuit Detector Register"
|
|
rbitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 0" "FastSinc,Sinc1,Sinc2,Sinc3"
|
|
rbitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 15. " BKSCD3 ,Break 3 signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned"
|
|
bitfld.long 0x04 14. " BKSCD2 ,Break 2 signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned"
|
|
textline " "
|
|
bitfld.long 0x04 13. " BKSCD1 ,Break 1 signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned"
|
|
bitfld.long 0x04 12. " BKSCD0 ,Break 0 signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 0"
|
|
endif
|
|
rgroup.long (0x0+0x0C)++0x03
|
|
line.long 0x00 "DFSDM_CH0WDATR,DFSDM Channel 0 Watchdog Filter Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " WDATA ,Input channel 0 watchdog data"
|
|
if (((per.l(ad:0x40017400+0x0))&0x3000)==0x2000)
|
|
if (((per.l(ad:0x40017400+0x0))&0xC000)==0x00)
|
|
group.long (0x0+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH0DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 0"
|
|
elif (((per.l(ad:0x40017400+0x0))&0xC000)==0x4000)
|
|
group.long (0x0+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH0DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 0"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 0"
|
|
else
|
|
group.long (0x0+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH0DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 0+1"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 0"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40017400+0x0))&0xC000)==0x00)
|
|
rgroup.long (0x0+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH0DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 0"
|
|
elif (((per.l(ad:0x40017400+0x0))&0xC000)==0x4000)
|
|
rgroup.long (0x0+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH0DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 0"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 0"
|
|
else
|
|
rgroup.long (0x0+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH0DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 0+1"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 0"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Channel 1"
|
|
if (((per.l(ad:0x40017400+0x20))&0x80)==0x00)
|
|
if (((per.l(ad:0x40017400))&0x80000000)==0x00)
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "DFSDM_CH1CFGR1,DFSDM Channel 1 Configuration Register"
|
|
bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN1R register" "Standard,Interleaved,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 1" "Ext serial inputs,,Internal DFSDM_CHDATIN1R,?..."
|
|
bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(1+1) mod 8 channel"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHEN ,Channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 1" "Ext DFSDM_CKIN1(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 1" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)"
|
|
else
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "DFSDM_CH1CFGR1,DFSDM Channel 1 Configuration Register"
|
|
bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN1R register" "Standard,Interleaved,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 1" "Ext serial inputs,,Internal DFSDM_CHDATIN1R,?..."
|
|
bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(1+1) mod 8 channel"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHEN ,Channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 1" "Ext DFSDM_CKIN1(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 1" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40017400))&0x80000000)==0x00)
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "DFSDM_CH1CFGR1,DFSDM Channel 1 Configuration Register"
|
|
rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN1R register" "Standard,Interleaved,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 1" "Ext serial inputs,,Internal DFSDM_CHDATIN1R,?..."
|
|
rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(1+1) mod 8 channel"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHEN ,Channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 1" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 1" "Ext DFSDM_CKIN1(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)"
|
|
textline " "
|
|
rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 1" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)"
|
|
else
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "DFSDM_CH1CFGR1,DFSDM Channel 1 Configuration Register"
|
|
rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN1R register" "Standard,Interleaved,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 1" "Ext serial inputs,,Internal DFSDM_CHDATIN1R,?..."
|
|
rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(1+1) mod 8 channel"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHEN ,Channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 1" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 1" "Ext DFSDM_CKIN1(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)"
|
|
textline " "
|
|
rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 1" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40017400+0x20))&0x80)==0x0)
|
|
group.long (0x20+0x04)++0x07
|
|
line.long 0x00 "DFSDM_CH1CFGR2,DFSDM Channel 1 Configuration Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 1"
|
|
bitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "DFSDM_CH1AWSCDR,DFSDM Channel 1 Analog Watchdog And Short-circuit Detector Register"
|
|
bitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 1" "FastSinc,Sinc1,Sinc2,Sinc3"
|
|
bitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 15. " BKSCD3 ,Break signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned"
|
|
bitfld.long 0x04 14. " BKSCD2 ,Break signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned"
|
|
textline " "
|
|
bitfld.long 0x04 13. " BKSCD1 ,Break signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned"
|
|
bitfld.long 0x04 12. " BKSCD0 ,Break signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 1"
|
|
else
|
|
group.long (0x20+0x04)++0x07
|
|
line.long 0x00 "DFSDM_CH1CFGR2,DFSDM Channel 1 Configuration Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 1"
|
|
rbitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "DFSDM_CH1AWSCDR,DFSDM Channel 1 Analog Watchdog And Short-circuit Detector Register"
|
|
rbitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 1" "FastSinc,Sinc1,Sinc2,Sinc3"
|
|
rbitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 15. " BKSCD3 ,Break 3 signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned"
|
|
bitfld.long 0x04 14. " BKSCD2 ,Break 2 signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned"
|
|
textline " "
|
|
bitfld.long 0x04 13. " BKSCD1 ,Break 1 signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned"
|
|
bitfld.long 0x04 12. " BKSCD0 ,Break 0 signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 1"
|
|
endif
|
|
rgroup.long (0x20+0x0C)++0x03
|
|
line.long 0x00 "DFSDM_CH1WDATR,DFSDM Channel 1 Watchdog Filter Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " WDATA ,Input channel 1 watchdog data"
|
|
if (((per.l(ad:0x40017400+0x20))&0x3000)==0x2000)
|
|
if (((per.l(ad:0x40017400+0x20))&0xC000)==0x00)
|
|
group.long (0x20+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH1DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 1"
|
|
elif (((per.l(ad:0x40017400+0x20))&0xC000)==0x4000)
|
|
group.long (0x20+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH1DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 1"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 1"
|
|
else
|
|
group.long (0x20+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH1DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 1"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40017400+0x20))&0xC000)==0x00)
|
|
rgroup.long (0x20+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH1DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 1"
|
|
elif (((per.l(ad:0x40017400+0x20))&0xC000)==0x4000)
|
|
rgroup.long (0x20+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH1DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 1"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 1"
|
|
else
|
|
rgroup.long (0x20+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH1DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 1"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Channel 2"
|
|
if (((per.l(ad:0x40017400+0x40))&0x80)==0x00)
|
|
if (((per.l(ad:0x40017400))&0x80000000)==0x00)
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "DFSDM_CH2CFGR1,DFSDM Channel 2 Configuration Register"
|
|
bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN2R register" "Standard,Interleaved,Dual,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 2" "Ext serial inputs,,Internal DFSDM_CHDATIN2R,?..."
|
|
bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(2+1) mod 8 channel"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHEN ,Channel 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 2" "Ext DFSDM_CKIN2(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 2" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)"
|
|
else
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "DFSDM_CH2CFGR1,DFSDM Channel 2 Configuration Register"
|
|
bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN2R register" "Standard,Interleaved,Dual,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 2" "Ext serial inputs,,Internal DFSDM_CHDATIN2R,?..."
|
|
bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(2+1) mod 8 channel"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHEN ,Channel 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 2" "Ext DFSDM_CKIN2(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 2" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40017400))&0x80000000)==0x00)
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "DFSDM_CH2CFGR1,DFSDM Channel 2 Configuration Register"
|
|
rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN2R register" "Standard,Interleaved,Dual,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 2" "Ext serial inputs,,Internal DFSDM_CHDATIN2R,?..."
|
|
rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(2+1) mod 8 channel"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHEN ,Channel 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 2" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 2" "Ext DFSDM_CKIN2(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)"
|
|
textline " "
|
|
rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 2" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)"
|
|
else
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "DFSDM_CH2CFGR1,DFSDM Channel 2 Configuration Register"
|
|
rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN2R register" "Standard,Interleaved,Dual,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 2" "Ext serial inputs,,Internal DFSDM_CHDATIN2R,?..."
|
|
rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(2+1) mod 8 channel"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHEN ,Channel 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 2" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 2" "Ext DFSDM_CKIN2(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)"
|
|
textline " "
|
|
rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 2" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40017400+0x40))&0x80)==0x0)
|
|
group.long (0x40+0x04)++0x07
|
|
line.long 0x00 "DFSDM_CH2CFGR2,DFSDM Channel 2 Configuration Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 2"
|
|
bitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "DFSDM_CH2AWSCDR,DFSDM Channel 2 Analog Watchdog And Short-circuit Detector Register"
|
|
bitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 2" "FastSinc,Sinc1,Sinc2,Sinc3"
|
|
bitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 15. " BKSCD3 ,Break signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned"
|
|
bitfld.long 0x04 14. " BKSCD2 ,Break signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned"
|
|
textline " "
|
|
bitfld.long 0x04 13. " BKSCD1 ,Break signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned"
|
|
bitfld.long 0x04 12. " BKSCD0 ,Break signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 2"
|
|
else
|
|
group.long (0x40+0x04)++0x07
|
|
line.long 0x00 "DFSDM_CH2CFGR2,DFSDM Channel 2 Configuration Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 2"
|
|
rbitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "DFSDM_CH2AWSCDR,DFSDM Channel 2 Analog Watchdog And Short-circuit Detector Register"
|
|
rbitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 2" "FastSinc,Sinc1,Sinc2,Sinc3"
|
|
rbitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 15. " BKSCD3 ,Break 3 signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned"
|
|
bitfld.long 0x04 14. " BKSCD2 ,Break 2 signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned"
|
|
textline " "
|
|
bitfld.long 0x04 13. " BKSCD1 ,Break 1 signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned"
|
|
bitfld.long 0x04 12. " BKSCD0 ,Break 0 signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 2"
|
|
endif
|
|
rgroup.long (0x40+0x0C)++0x03
|
|
line.long 0x00 "DFSDM_CH2WDATR,DFSDM Channel 2 Watchdog Filter Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " WDATA ,Input channel 2 watchdog data"
|
|
if (((per.l(ad:0x40017400+0x40))&0x3000)==0x2000)
|
|
if (((per.l(ad:0x40017400+0x40))&0xC000)==0x00)
|
|
group.long (0x40+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH2DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 2"
|
|
elif (((per.l(ad:0x40017400+0x40))&0xC000)==0x4000)
|
|
group.long (0x40+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH2DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 2"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 2"
|
|
else
|
|
group.long (0x40+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH2DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 2+1"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 2"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40017400+0x40))&0xC000)==0x00)
|
|
rgroup.long (0x40+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH2DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 2"
|
|
elif (((per.l(ad:0x40017400+0x40))&0xC000)==0x4000)
|
|
rgroup.long (0x40+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH2DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 2"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 2"
|
|
else
|
|
rgroup.long (0x40+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH2DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 2+1"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 2"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Channel 3"
|
|
if (((per.l(ad:0x40017400+0x60))&0x80)==0x00)
|
|
if (((per.l(ad:0x40017400))&0x80000000)==0x00)
|
|
group.long 0x60++0x3
|
|
line.long 0x00 "DFSDM_CH3CFGR1,DFSDM Channel 3 Configuration Register"
|
|
bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN3R register" "Standard,Interleaved,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 3" "Ext serial inputs,,Internal DFSDM_CHDATIN3R,?..."
|
|
bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(3+1) mod 8 channel"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHEN ,Channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 3" "Ext DFSDM_CKIN3(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 3" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)"
|
|
else
|
|
group.long 0x60++0x3
|
|
line.long 0x00 "DFSDM_CH3CFGR1,DFSDM Channel 3 Configuration Register"
|
|
bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN3R register" "Standard,Interleaved,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 3" "Ext serial inputs,,Internal DFSDM_CHDATIN3R,?..."
|
|
bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(3+1) mod 8 channel"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHEN ,Channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 3" "Ext DFSDM_CKIN3(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 3" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40017400))&0x80000000)==0x00)
|
|
group.long 0x60++0x3
|
|
line.long 0x00 "DFSDM_CH3CFGR1,DFSDM Channel 3 Configuration Register"
|
|
rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN3R register" "Standard,Interleaved,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 3" "Ext serial inputs,,Internal DFSDM_CHDATIN3R,?..."
|
|
rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(3+1) mod 8 channel"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHEN ,Channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 3" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 3" "Ext DFSDM_CKIN3(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)"
|
|
textline " "
|
|
rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 3" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)"
|
|
else
|
|
group.long 0x60++0x3
|
|
line.long 0x00 "DFSDM_CH3CFGR1,DFSDM Channel 3 Configuration Register"
|
|
rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN3R register" "Standard,Interleaved,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 3" "Ext serial inputs,,Internal DFSDM_CHDATIN3R,?..."
|
|
rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(3+1) mod 8 channel"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHEN ,Channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 3" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 3" "Ext DFSDM_CKIN3(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)"
|
|
textline " "
|
|
rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 3" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40017400+0x60))&0x80)==0x0)
|
|
group.long (0x60+0x04)++0x07
|
|
line.long 0x00 "DFSDM_CH3CFGR2,DFSDM Channel 3 Configuration Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 3"
|
|
bitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "DFSDM_CH3AWSCDR,DFSDM Channel 3 Analog Watchdog And Short-circuit Detector Register"
|
|
bitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 3" "FastSinc,Sinc1,Sinc2,Sinc3"
|
|
bitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 15. " BKSCD3 ,Break signal assignment for short-circuit detector on channel 3" "Not assigned,Assigned"
|
|
bitfld.long 0x04 14. " BKSCD2 ,Break signal assignment for short-circuit detector on channel 3" "Not assigned,Assigned"
|
|
textline " "
|
|
bitfld.long 0x04 13. " BKSCD1 ,Break signal assignment for short-circuit detector on channel 3" "Not assigned,Assigned"
|
|
bitfld.long 0x04 12. " BKSCD0 ,Break signal assignment for short-circuit detector on channel 3" "Not assigned,Assigned"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 3"
|
|
else
|
|
group.long (0x60+0x04)++0x07
|
|
line.long 0x00 "DFSDM_CH3CFGR2,DFSDM Channel 3 Configuration Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 3"
|
|
rbitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "DFSDM_CH3AWSCDR,DFSDM Channel 3 Analog Watchdog And Short-circuit Detector Register"
|
|
rbitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 3" "FastSinc,Sinc1,Sinc2,Sinc3"
|
|
rbitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 15. " BKSCD3 ,Break 3 signal assignment for short-circuit detector on channel 3" "Not assigned,Assigned"
|
|
bitfld.long 0x04 14. " BKSCD2 ,Break 2 signal assignment for short-circuit detector on channel 3" "Not assigned,Assigned"
|
|
textline " "
|
|
bitfld.long 0x04 13. " BKSCD1 ,Break 1 signal assignment for short-circuit detector on channel 3" "Not assigned,Assigned"
|
|
bitfld.long 0x04 12. " BKSCD0 ,Break 0 signal assignment for short-circuit detector on channel 3" "Not assigned,Assigned"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 3"
|
|
endif
|
|
rgroup.long (0x60+0x0C)++0x03
|
|
line.long 0x00 "DFSDM_CH3WDATR,DFSDM Channel 3 Watchdog Filter Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " WDATA ,Input channel 3 watchdog data"
|
|
if (((per.l(ad:0x40017400+0x60))&0x3000)==0x2000)
|
|
if (((per.l(ad:0x40017400+0x60))&0xC000)==0x00)
|
|
group.long (0x60+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH3DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 3"
|
|
elif (((per.l(ad:0x40017400+0x60))&0xC000)==0x4000)
|
|
group.long (0x60+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH3DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 3"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 3"
|
|
else
|
|
group.long (0x60+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH3DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 3"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40017400+0x60))&0xC000)==0x00)
|
|
rgroup.long (0x60+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH3DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 3"
|
|
elif (((per.l(ad:0x40017400+0x60))&0xC000)==0x4000)
|
|
rgroup.long (0x60+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH3DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 3"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 3"
|
|
else
|
|
rgroup.long (0x60+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH3DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 3"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Channel 4"
|
|
if (((per.l(ad:0x40017400+0x80))&0x80)==0x00)
|
|
if (((per.l(ad:0x40017400))&0x80000000)==0x00)
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "DFSDM_CH4CFGR1,DFSDM Channel 4 Configuration Register"
|
|
bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN4R register" "Standard,Interleaved,Dual,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 4" "Ext serial inputs,,Internal DFSDM_CHDATIN4R,?..."
|
|
bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(4+1) mod 8 channel"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHEN ,Channel 4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 4" "Ext DFSDM_CKIN4(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 4" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)"
|
|
else
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "DFSDM_CH4CFGR1,DFSDM Channel 4 Configuration Register"
|
|
bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN4R register" "Standard,Interleaved,Dual,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 4" "Ext serial inputs,,Internal DFSDM_CHDATIN4R,?..."
|
|
bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(4+1) mod 8 channel"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHEN ,Channel 4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 4" "Ext DFSDM_CKIN4(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 4" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40017400))&0x80000000)==0x00)
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "DFSDM_CH4CFGR1,DFSDM Channel 4 Configuration Register"
|
|
rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN4R register" "Standard,Interleaved,Dual,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 4" "Ext serial inputs,,Internal DFSDM_CHDATIN4R,?..."
|
|
rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(4+1) mod 8 channel"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHEN ,Channel 4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 4" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 4" "Ext DFSDM_CKIN4(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)"
|
|
textline " "
|
|
rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 4" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)"
|
|
else
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "DFSDM_CH4CFGR1,DFSDM Channel 4 Configuration Register"
|
|
rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN4R register" "Standard,Interleaved,Dual,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 4" "Ext serial inputs,,Internal DFSDM_CHDATIN4R,?..."
|
|
rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(4+1) mod 8 channel"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHEN ,Channel 4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 4" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 4" "Ext DFSDM_CKIN4(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)"
|
|
textline " "
|
|
rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 4" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40017400+0x80))&0x80)==0x0)
|
|
group.long (0x80+0x04)++0x07
|
|
line.long 0x00 "DFSDM_CH4CFGR2,DFSDM Channel 4 Configuration Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 4"
|
|
bitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "DFSDM_CH4AWSCDR,DFSDM Channel 4 Analog Watchdog And Short-circuit Detector Register"
|
|
bitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 4" "FastSinc,Sinc1,Sinc2,Sinc3"
|
|
bitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 15. " BKSCD3 ,Break signal assignment for short-circuit detector on channel 4" "Not assigned,Assigned"
|
|
bitfld.long 0x04 14. " BKSCD2 ,Break signal assignment for short-circuit detector on channel 4" "Not assigned,Assigned"
|
|
textline " "
|
|
bitfld.long 0x04 13. " BKSCD1 ,Break signal assignment for short-circuit detector on channel 4" "Not assigned,Assigned"
|
|
bitfld.long 0x04 12. " BKSCD0 ,Break signal assignment for short-circuit detector on channel 4" "Not assigned,Assigned"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 4"
|
|
else
|
|
group.long (0x80+0x04)++0x07
|
|
line.long 0x00 "DFSDM_CH4CFGR2,DFSDM Channel 4 Configuration Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 4"
|
|
rbitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "DFSDM_CH4AWSCDR,DFSDM Channel 4 Analog Watchdog And Short-circuit Detector Register"
|
|
rbitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 4" "FastSinc,Sinc1,Sinc2,Sinc3"
|
|
rbitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 15. " BKSCD3 ,Break 3 signal assignment for short-circuit detector on channel 4" "Not assigned,Assigned"
|
|
bitfld.long 0x04 14. " BKSCD2 ,Break 2 signal assignment for short-circuit detector on channel 4" "Not assigned,Assigned"
|
|
textline " "
|
|
bitfld.long 0x04 13. " BKSCD1 ,Break 1 signal assignment for short-circuit detector on channel 4" "Not assigned,Assigned"
|
|
bitfld.long 0x04 12. " BKSCD0 ,Break 0 signal assignment for short-circuit detector on channel 4" "Not assigned,Assigned"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 4"
|
|
endif
|
|
rgroup.long (0x80+0x0C)++0x03
|
|
line.long 0x00 "DFSDM_CH4WDATR,DFSDM Channel 4 Watchdog Filter Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " WDATA ,Input channel 4 watchdog data"
|
|
if (((per.l(ad:0x40017400+0x80))&0x3000)==0x2000)
|
|
if (((per.l(ad:0x40017400+0x80))&0xC000)==0x00)
|
|
group.long (0x80+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH4DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 4"
|
|
elif (((per.l(ad:0x40017400+0x80))&0xC000)==0x4000)
|
|
group.long (0x80+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH4DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 4"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 4"
|
|
else
|
|
group.long (0x80+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH4DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 4+1"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 4"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40017400+0x80))&0xC000)==0x00)
|
|
rgroup.long (0x80+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH4DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 4"
|
|
elif (((per.l(ad:0x40017400+0x80))&0xC000)==0x4000)
|
|
rgroup.long (0x80+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH4DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 4"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 4"
|
|
else
|
|
rgroup.long (0x80+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH4DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 4+1"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 4"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Channel 5"
|
|
if (((per.l(ad:0x40017400+0xA0))&0x80)==0x00)
|
|
if (((per.l(ad:0x40017400))&0x80000000)==0x00)
|
|
group.long 0xA0++0x3
|
|
line.long 0x00 "DFSDM_CH5CFGR1,DFSDM Channel 5 Configuration Register"
|
|
bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN5R register" "Standard,Interleaved,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 5" "Ext serial inputs,,Internal DFSDM_CHDATIN5R,?..."
|
|
bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(5+1) mod 8 channel"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHEN ,Channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 5" "Ext DFSDM_CKIN5(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 5" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)"
|
|
else
|
|
group.long 0xA0++0x3
|
|
line.long 0x00 "DFSDM_CH5CFGR1,DFSDM Channel 5 Configuration Register"
|
|
bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN5R register" "Standard,Interleaved,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 5" "Ext serial inputs,,Internal DFSDM_CHDATIN5R,?..."
|
|
bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(5+1) mod 8 channel"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHEN ,Channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 5" "Ext DFSDM_CKIN5(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 5" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40017400))&0x80000000)==0x00)
|
|
group.long 0xA0++0x3
|
|
line.long 0x00 "DFSDM_CH5CFGR1,DFSDM Channel 5 Configuration Register"
|
|
rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN5R register" "Standard,Interleaved,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 5" "Ext serial inputs,,Internal DFSDM_CHDATIN5R,?..."
|
|
rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(5+1) mod 8 channel"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHEN ,Channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 5" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 5" "Ext DFSDM_CKIN5(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)"
|
|
textline " "
|
|
rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 5" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)"
|
|
else
|
|
group.long 0xA0++0x3
|
|
line.long 0x00 "DFSDM_CH5CFGR1,DFSDM Channel 5 Configuration Register"
|
|
rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN5R register" "Standard,Interleaved,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 5" "Ext serial inputs,,Internal DFSDM_CHDATIN5R,?..."
|
|
rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(5+1) mod 8 channel"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHEN ,Channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 5" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 5" "Ext DFSDM_CKIN5(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)"
|
|
textline " "
|
|
rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 5" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40017400+0xA0))&0x80)==0x0)
|
|
group.long (0xA0+0x04)++0x07
|
|
line.long 0x00 "DFSDM_CH5CFGR2,DFSDM Channel 5 Configuration Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 5"
|
|
bitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "DFSDM_CH5AWSCDR,DFSDM Channel 5 Analog Watchdog And Short-circuit Detector Register"
|
|
bitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 5" "FastSinc,Sinc1,Sinc2,Sinc3"
|
|
bitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 15. " BKSCD3 ,Break signal assignment for short-circuit detector on channel 5" "Not assigned,Assigned"
|
|
bitfld.long 0x04 14. " BKSCD2 ,Break signal assignment for short-circuit detector on channel 5" "Not assigned,Assigned"
|
|
textline " "
|
|
bitfld.long 0x04 13. " BKSCD1 ,Break signal assignment for short-circuit detector on channel 5" "Not assigned,Assigned"
|
|
bitfld.long 0x04 12. " BKSCD0 ,Break signal assignment for short-circuit detector on channel 5" "Not assigned,Assigned"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 5"
|
|
else
|
|
group.long (0xA0+0x04)++0x07
|
|
line.long 0x00 "DFSDM_CH5CFGR2,DFSDM Channel 5 Configuration Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 5"
|
|
rbitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "DFSDM_CH5AWSCDR,DFSDM Channel 5 Analog Watchdog And Short-circuit Detector Register"
|
|
rbitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 5" "FastSinc,Sinc1,Sinc2,Sinc3"
|
|
rbitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 15. " BKSCD3 ,Break 3 signal assignment for short-circuit detector on channel 5" "Not assigned,Assigned"
|
|
bitfld.long 0x04 14. " BKSCD2 ,Break 2 signal assignment for short-circuit detector on channel 5" "Not assigned,Assigned"
|
|
textline " "
|
|
bitfld.long 0x04 13. " BKSCD1 ,Break 1 signal assignment for short-circuit detector on channel 5" "Not assigned,Assigned"
|
|
bitfld.long 0x04 12. " BKSCD0 ,Break 0 signal assignment for short-circuit detector on channel 5" "Not assigned,Assigned"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 5"
|
|
endif
|
|
rgroup.long (0xA0+0x0C)++0x03
|
|
line.long 0x00 "DFSDM_CH5WDATR,DFSDM Channel 5 Watchdog Filter Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " WDATA ,Input channel 5 watchdog data"
|
|
if (((per.l(ad:0x40017400+0xA0))&0x3000)==0x2000)
|
|
if (((per.l(ad:0x40017400+0xA0))&0xC000)==0x00)
|
|
group.long (0xA0+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH5DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 5"
|
|
elif (((per.l(ad:0x40017400+0xA0))&0xC000)==0x4000)
|
|
group.long (0xA0+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH5DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 5"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 5"
|
|
else
|
|
group.long (0xA0+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH5DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 5"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40017400+0xA0))&0xC000)==0x00)
|
|
rgroup.long (0xA0+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH5DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 5"
|
|
elif (((per.l(ad:0x40017400+0xA0))&0xC000)==0x4000)
|
|
rgroup.long (0xA0+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH5DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 5"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 5"
|
|
else
|
|
rgroup.long (0xA0+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH5DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 5"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Channel 6"
|
|
if (((per.l(ad:0x40017400+0xC0))&0x80)==0x00)
|
|
if (((per.l(ad:0x40017400))&0x80000000)==0x00)
|
|
group.long 0xC0++0x3
|
|
line.long 0x00 "DFSDM_CH6CFGR1,DFSDM Channel 6 Configuration Register"
|
|
bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN6R register" "Standard,Interleaved,Dual,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 6" "Ext serial inputs,,Internal DFSDM_CHDATIN6R,?..."
|
|
bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(6+1) mod 8 channel"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHEN ,Channel 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 6" "Ext DFSDM_CKIN6(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 6" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)"
|
|
else
|
|
group.long 0xC0++0x3
|
|
line.long 0x00 "DFSDM_CH6CFGR1,DFSDM Channel 6 Configuration Register"
|
|
bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN6R register" "Standard,Interleaved,Dual,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 6" "Ext serial inputs,,Internal DFSDM_CHDATIN6R,?..."
|
|
bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(6+1) mod 8 channel"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHEN ,Channel 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 6" "Ext DFSDM_CKIN6(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 6" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40017400))&0x80000000)==0x00)
|
|
group.long 0xC0++0x3
|
|
line.long 0x00 "DFSDM_CH6CFGR1,DFSDM Channel 6 Configuration Register"
|
|
rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN6R register" "Standard,Interleaved,Dual,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 6" "Ext serial inputs,,Internal DFSDM_CHDATIN6R,?..."
|
|
rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(6+1) mod 8 channel"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHEN ,Channel 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 6" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 6" "Ext DFSDM_CKIN6(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)"
|
|
textline " "
|
|
rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 6" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)"
|
|
else
|
|
group.long 0xC0++0x3
|
|
line.long 0x00 "DFSDM_CH6CFGR1,DFSDM Channel 6 Configuration Register"
|
|
rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN6R register" "Standard,Interleaved,Dual,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 6" "Ext serial inputs,,Internal DFSDM_CHDATIN6R,?..."
|
|
rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(6+1) mod 8 channel"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHEN ,Channel 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 6" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 6" "Ext DFSDM_CKIN6(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)"
|
|
textline " "
|
|
rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 6" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40017400+0xC0))&0x80)==0x0)
|
|
group.long (0xC0+0x04)++0x07
|
|
line.long 0x00 "DFSDM_CH6CFGR2,DFSDM Channel 6 Configuration Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 6"
|
|
bitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "DFSDM_CH6AWSCDR,DFSDM Channel 6 Analog Watchdog And Short-circuit Detector Register"
|
|
bitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 6" "FastSinc,Sinc1,Sinc2,Sinc3"
|
|
bitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 15. " BKSCD3 ,Break signal assignment for short-circuit detector on channel 6" "Not assigned,Assigned"
|
|
bitfld.long 0x04 14. " BKSCD2 ,Break signal assignment for short-circuit detector on channel 6" "Not assigned,Assigned"
|
|
textline " "
|
|
bitfld.long 0x04 13. " BKSCD1 ,Break signal assignment for short-circuit detector on channel 6" "Not assigned,Assigned"
|
|
bitfld.long 0x04 12. " BKSCD0 ,Break signal assignment for short-circuit detector on channel 6" "Not assigned,Assigned"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 6"
|
|
else
|
|
group.long (0xC0+0x04)++0x07
|
|
line.long 0x00 "DFSDM_CH6CFGR2,DFSDM Channel 6 Configuration Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 6"
|
|
rbitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "DFSDM_CH6AWSCDR,DFSDM Channel 6 Analog Watchdog And Short-circuit Detector Register"
|
|
rbitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 6" "FastSinc,Sinc1,Sinc2,Sinc3"
|
|
rbitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 15. " BKSCD3 ,Break 3 signal assignment for short-circuit detector on channel 6" "Not assigned,Assigned"
|
|
bitfld.long 0x04 14. " BKSCD2 ,Break 2 signal assignment for short-circuit detector on channel 6" "Not assigned,Assigned"
|
|
textline " "
|
|
bitfld.long 0x04 13. " BKSCD1 ,Break 1 signal assignment for short-circuit detector on channel 6" "Not assigned,Assigned"
|
|
bitfld.long 0x04 12. " BKSCD0 ,Break 0 signal assignment for short-circuit detector on channel 6" "Not assigned,Assigned"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 6"
|
|
endif
|
|
rgroup.long (0xC0+0x0C)++0x03
|
|
line.long 0x00 "DFSDM_CH6WDATR,DFSDM Channel 6 Watchdog Filter Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " WDATA ,Input channel 6 watchdog data"
|
|
if (((per.l(ad:0x40017400+0xC0))&0x3000)==0x2000)
|
|
if (((per.l(ad:0x40017400+0xC0))&0xC000)==0x00)
|
|
group.long (0xC0+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH6DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 6"
|
|
elif (((per.l(ad:0x40017400+0xC0))&0xC000)==0x4000)
|
|
group.long (0xC0+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH6DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 6"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 6"
|
|
else
|
|
group.long (0xC0+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH6DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 6+1"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 6"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40017400+0xC0))&0xC000)==0x00)
|
|
rgroup.long (0xC0+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH6DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 6"
|
|
elif (((per.l(ad:0x40017400+0xC0))&0xC000)==0x4000)
|
|
rgroup.long (0xC0+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH6DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 6"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 6"
|
|
else
|
|
rgroup.long (0xC0+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH6DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 6+1"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 6"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Channel 7"
|
|
if (((per.l(ad:0x40017400+0xE0))&0x80)==0x00)
|
|
if (((per.l(ad:0x40017400))&0x80000000)==0x00)
|
|
group.long 0xE0++0x3
|
|
line.long 0x00 "DFSDM_CH7CFGR1,DFSDM Channel 7 Configuration Register"
|
|
bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN7R register" "Standard,Interleaved,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 7" "Ext serial inputs,,Internal DFSDM_CHDATIN7R,?..."
|
|
bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(7+1) mod 8 channel"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHEN ,Channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 7" "Ext DFSDM_CKIN7(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 7" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)"
|
|
else
|
|
group.long 0xE0++0x3
|
|
line.long 0x00 "DFSDM_CH7CFGR1,DFSDM Channel 7 Configuration Register"
|
|
bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN7R register" "Standard,Interleaved,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 7" "Ext serial inputs,,Internal DFSDM_CHDATIN7R,?..."
|
|
bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(7+1) mod 8 channel"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHEN ,Channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 7" "Ext DFSDM_CKIN7(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 7" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40017400))&0x80000000)==0x00)
|
|
group.long 0xE0++0x3
|
|
line.long 0x00 "DFSDM_CH7CFGR1,DFSDM Channel 7 Configuration Register"
|
|
rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN7R register" "Standard,Interleaved,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 7" "Ext serial inputs,,Internal DFSDM_CHDATIN7R,?..."
|
|
rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(7+1) mod 8 channel"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHEN ,Channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 7" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 7" "Ext DFSDM_CKIN7(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)"
|
|
textline " "
|
|
rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 7" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)"
|
|
else
|
|
group.long 0xE0++0x3
|
|
line.long 0x00 "DFSDM_CH7CFGR1,DFSDM Channel 7 Configuration Register"
|
|
rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN7R register" "Standard,Interleaved,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 7" "Ext serial inputs,,Internal DFSDM_CHDATIN7R,?..."
|
|
rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(7+1) mod 8 channel"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHEN ,Channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 7" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 7" "Ext DFSDM_CKIN7(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)"
|
|
textline " "
|
|
rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 7" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40017400+0xE0))&0x80)==0x0)
|
|
group.long (0xE0+0x04)++0x07
|
|
line.long 0x00 "DFSDM_CH7CFGR2,DFSDM Channel 7 Configuration Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 7"
|
|
bitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "DFSDM_CH7AWSCDR,DFSDM Channel 7 Analog Watchdog And Short-circuit Detector Register"
|
|
bitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 7" "FastSinc,Sinc1,Sinc2,Sinc3"
|
|
bitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 15. " BKSCD3 ,Break signal assignment for short-circuit detector on channel 7" "Not assigned,Assigned"
|
|
bitfld.long 0x04 14. " BKSCD2 ,Break signal assignment for short-circuit detector on channel 7" "Not assigned,Assigned"
|
|
textline " "
|
|
bitfld.long 0x04 13. " BKSCD1 ,Break signal assignment for short-circuit detector on channel 7" "Not assigned,Assigned"
|
|
bitfld.long 0x04 12. " BKSCD0 ,Break signal assignment for short-circuit detector on channel 7" "Not assigned,Assigned"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 7"
|
|
else
|
|
group.long (0xE0+0x04)++0x07
|
|
line.long 0x00 "DFSDM_CH7CFGR2,DFSDM Channel 7 Configuration Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 7"
|
|
rbitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "DFSDM_CH7AWSCDR,DFSDM Channel 7 Analog Watchdog And Short-circuit Detector Register"
|
|
rbitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 7" "FastSinc,Sinc1,Sinc2,Sinc3"
|
|
rbitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 15. " BKSCD3 ,Break 3 signal assignment for short-circuit detector on channel 7" "Not assigned,Assigned"
|
|
bitfld.long 0x04 14. " BKSCD2 ,Break 2 signal assignment for short-circuit detector on channel 7" "Not assigned,Assigned"
|
|
textline " "
|
|
bitfld.long 0x04 13. " BKSCD1 ,Break 1 signal assignment for short-circuit detector on channel 7" "Not assigned,Assigned"
|
|
bitfld.long 0x04 12. " BKSCD0 ,Break 0 signal assignment for short-circuit detector on channel 7" "Not assigned,Assigned"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 7"
|
|
endif
|
|
rgroup.long (0xE0+0x0C)++0x03
|
|
line.long 0x00 "DFSDM_CH7WDATR,DFSDM Channel 7 Watchdog Filter Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " WDATA ,Input channel 7 watchdog data"
|
|
if (((per.l(ad:0x40017400+0xE0))&0x3000)==0x2000)
|
|
if (((per.l(ad:0x40017400+0xE0))&0xC000)==0x00)
|
|
group.long (0xE0+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH7DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 7"
|
|
elif (((per.l(ad:0x40017400+0xE0))&0xC000)==0x4000)
|
|
group.long (0xE0+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH7DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 7"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 7"
|
|
else
|
|
group.long (0xE0+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH7DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 7"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40017400+0xE0))&0xC000)==0x00)
|
|
rgroup.long (0xE0+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH7DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 7"
|
|
elif (((per.l(ad:0x40017400+0xE0))&0xC000)==0x4000)
|
|
rgroup.long (0xE0+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH7DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 7"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 7"
|
|
else
|
|
rgroup.long (0xE0+0x10)++0x03
|
|
line.long 0x00 "DFSDM_CH7DATINR,DFSDM Channel Data Input Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 7"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Module 0 registers"
|
|
if (((per.l(ad:0x40017400+0x100))&0x01)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DFSDM_FLT0CR1,DFSDM Control Register 1"
|
|
bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Channel transceivers value"
|
|
bitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7"
|
|
bitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM0" "Not launched,Launched"
|
|
bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly"
|
|
bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "Not started,Started"
|
|
bitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM10_OC1,TIM6_TRGO,TIM7_TRGO,,,,,,,,,,,,,,,EXTI11,EXTI15,LPTIMER1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " JDMAEN ,DMA channel enabled to read data for the injected channel group" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One,Series"
|
|
bitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger" "Not launched,Launched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DFEN ,DFSDM_FLT0 enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DFSDM_FLT0CR1,DFSDM Control Register 1"
|
|
bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value"
|
|
rbitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7"
|
|
rbitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM0" "Not launched,Launched"
|
|
bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly"
|
|
bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "Not started,Started"
|
|
rbitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM10_OC1,TIM6_TRGO,TIM7_TRGO,,,,,,,,,,,,,,,EXTI11,EXTI15,LPTIMER1,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 5. " JDMAEN ,DMA channel enabled to read data for the injected channel group" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One,Series"
|
|
rbitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger" "Not launched,Launched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DFEN ,DFSDM_FLT0 enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x100+0x04)++0x03
|
|
line.long 0x00 "DFSDM_FLT0CR2,DFSDM Filter 0 Control Register"
|
|
bitfld.long 0x00 23. " AWDCH[7] ,Analog watchdog channel 7 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " AWDCH[6] ,Analog watchdog channel 6 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " AWDCH[5] ,Analog watchdog channel 5 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " AWDCH[4] ,Analog watchdog channel 4 selection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " AWDCH[3] ,Analog watchdog channel 3 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " AWDCH[2] ,Analog watchdog channel 2 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " AWDCH[1] ,Analog watchdog channel 1 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " AWDCH[0] ,Analog watchdog channel 0 selection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EXCH[7] ,Extremes detector channel 7 selection" "No data accept,Accepts data"
|
|
bitfld.long 0x00 14. " EXCH[6] ,Extremes detector channel 6 selection" "No data accept,Accepts data"
|
|
bitfld.long 0x00 13. " EXCH[5] ,Extremes detector channel 5 selection" "No data accept,Accepts data"
|
|
bitfld.long 0x00 12. " EXCH[4] ,Extremes detector channel 4 selection" "No data accept,Accepts data"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EXCH[3] ,Extremes detector channel 3 selection" "No data accept,Accepts data"
|
|
bitfld.long 0x00 10. " EXCH[2] ,Extremes detector channel 2 selection" "No data accept,Accepts data"
|
|
bitfld.long 0x00 9. " EXCH[1] ,Extremes detector channel 1 selection" "No data accept,Accepts data"
|
|
bitfld.long 0x00 8. " EXCH[0] ,Extremes detector channel 0 selection" "No data accept,Accepts data"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CKABIE ,Clock absence interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCDIE ,Short-circuit detector interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " JOVRIE ,Injected data overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled"
|
|
rgroup.long (0x100+0x08)++0x03
|
|
line.long 0x00 "DFSDM_FLT0ISR,DFSDM Interrupt And Status Register"
|
|
bitfld.long 0x00 31. " SCDF[7] ,Short-circuit 7 detector flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " SCDF[6] ,Short-circuit 6 detector flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 29. " SCDF[5] ,Short-circuit 5 detector flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 28. " SCDF[4] ,Short-circuit 4 detector flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SCDF[3] ,Short-circuit 3 detector flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 26. " SCDF[2] ,Short-circuit 2 detector flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 25. " SCDF[1] ,Short-circuit 1 detector flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 24. " SCDF[0] ,Short-circuit 0 detector flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CKABF[7] ,Clock absence flag 7" "Present,Absent"
|
|
bitfld.long 0x00 22. " CKABF[6] ,Clock absence flag 6" "Present,Absent"
|
|
bitfld.long 0x00 21. " CKABF[5] ,Clock absence flag 5" "Present,Absent"
|
|
bitfld.long 0x00 20. " CKABF[4] ,Clock absence flag 4" "Present,Absent"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CKABF[3] ,Clock absence flag 3" "Present,Absent"
|
|
bitfld.long 0x00 18. " CKABF[2] ,Clock absence flag 2" "Present,Absent"
|
|
bitfld.long 0x00 17. " CKABF[1] ,Clock absence flag 1" "Present,Absent"
|
|
bitfld.long 0x00 16. " CKABF[0] ,Clock absence flag 0" "Present,Absent"
|
|
textline " "
|
|
bitfld.long 0x00 14. " RCIP ,Regular conversion in progress status" "No request,In progress"
|
|
bitfld.long 0x00 13. " JCIP ,Injected conversion in progress status" "No request,In progress"
|
|
bitfld.long 0x00 4. " AWDF ,Analog watchdog" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ROVRF ,Regular conversion overrun flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " JOVRF ,Injected conversion overrun flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " REOCF ,End of regular conversion flag" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " JEOCF ,End of injected conversion flag" "Not completed,Completed"
|
|
group.long (0x100+0x0C)++0x07
|
|
line.long 0x00 "DFSDM_FLT0ICR,DFSDM Interrupt Flag Clear Register"
|
|
eventfld.long 0x00 31. " CLRSCDF[7] ,Clear the short-circuit detector flag 7" "No effect,Clear"
|
|
eventfld.long 0x00 30. " CLRSCDF[6] ,Clear the short-circuit detector flag 6" "No effect,Clear"
|
|
eventfld.long 0x00 29. " CLRSCDF[5] ,Clear the short-circuit detector flag 5" "No effect,Clear"
|
|
eventfld.long 0x00 28. " CLRSCDF[4] ,Clear the short-circuit detector flag 4" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 27. " CLRSCDF[3] ,Clear the short-circuit detector flag 3" "No effect,Clear"
|
|
eventfld.long 0x00 26. " CLRSCDF[2] ,Clear the short-circuit detector flag 2" "No effect,Clear"
|
|
eventfld.long 0x00 25. " CLRSCDF[1] ,Clear the short-circuit detector flag 1" "No effect,Clear"
|
|
eventfld.long 0x00 24. " CLRSCDF[0] ,Clear the short-circuit detector flag 0" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 23. " CLRCKABF[7] ,Clear the clock absence flag 7" "No effect,Clear"
|
|
eventfld.long 0x00 22. " CLRCKABF[6] ,Clear the clock absence flag 6" "No effect,Clear"
|
|
eventfld.long 0x00 21. " CLRCKABF[5] ,Clear the clock absence flag 5" "No effect,Clear"
|
|
eventfld.long 0x00 20. " CLRCKABF[4] ,Clear the clock absence flag 4" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 19. " CLRCKABF[3] ,Clear the clock absence flag 3" "No effect,Clear"
|
|
eventfld.long 0x00 18. " CLRCKABF[2] ,Clear the clock absence flag 2" "No effect,Clear"
|
|
eventfld.long 0x00 17. " CLRCKABF[1] ,Clear the clock absence flag 1" "No effect,Clear"
|
|
eventfld.long 0x00 16. " CLRCKABF[0] ,Clear the clock absence flag 0" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 3. " CLRROVRF ,Clear the regular conversion overrun flag" "No effect,Clear"
|
|
eventfld.long 0x00 2. " CLRJOVRF ,Clear the injected conversion overrun flag" "No effect,Clear"
|
|
line.long 0x04 "DFSDM_FLT0JCHGR,DFSDM Injected Channel Group Selection Register"
|
|
bitfld.long 0x04 7. " JCHG[7] ,Injected channel 7 group selection" "Excluded,Included"
|
|
bitfld.long 0x04 6. " JCHG[6] ,Injected channel 6 group selection" "Excluded,Included"
|
|
bitfld.long 0x04 5. " JCHG[5] ,Injected channel 5 group selection" "Excluded,Included"
|
|
bitfld.long 0x04 4. " JCHG[4] ,Injected channel 4 group selection" "Excluded,Included"
|
|
textline " "
|
|
bitfld.long 0x04 3. " JCHG[3] ,Injected channel 3 group selection" "Excluded,Included"
|
|
bitfld.long 0x04 2. " JCHG[2] ,Injected channel 2 group selection" "Excluded,Included"
|
|
bitfld.long 0x04 1. " JCHG[1] ,Injected channel 1 group selection" "Excluded,Included"
|
|
bitfld.long 0x04 0. " JCHG[0] ,Injected channel 0 group selection" "Excluded,Included"
|
|
if (((per.l(ad:0x40017400+0x100))&0x01)==0x00)
|
|
group.long (0x100+0x14)++0x03
|
|
line.long 0x00 "DFSDM_FLT0FCR,DFSDM Filter Control Register"
|
|
bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..."
|
|
hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)"
|
|
else
|
|
rgroup.long (0x100+0x14)++0x03
|
|
line.long 0x00 "DFSDM_FLT0FCR,DFSDM Filter Control Register"
|
|
bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..."
|
|
hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)"
|
|
endif
|
|
hgroup.long (0x100+0x18)++0x03
|
|
hide.long 0x00 "DFSDM_FLT0JDATAR,DFSDM Filter 0 Data Register For Injected Group"
|
|
in
|
|
hgroup.long (0x100+0x1C)++0x03
|
|
hide.long 0x00 "DFSDM_FLT0RDATAR,DFSDM Filter 0 Data Register For The Regular Channel"
|
|
in
|
|
if (((per.l(ad:0x40017400+0x100))&0x40000000)==0x00)
|
|
group.long (0x100+0x20)++0x07
|
|
line.long 0x00 "DFSDM_FLT0AWHTR,DFSDM Analog Watchdog High Threshold Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " AWHT ,Analog watchdog high threshold"
|
|
bitfld.long 0x00 3. " BKAWH3 ,Break signal 3 assignment to analog watchdog high threshold event" "Not assigned,Assigned"
|
|
bitfld.long 0x00 2. " BKAWH2 ,Break signal 2 assignment to analog watchdog high threshold event" "Not assigned,Assigned"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BKAWH1 ,Break signal 1 assignment to analog watchdog high threshold event" "Not assigned,Assigned"
|
|
bitfld.long 0x00 0. " BKAWH0 ,Break signal 0 assignment to analog watchdog high threshold event" "Not assigned,Assigned"
|
|
line.long 0x04 "DFSDM_FLT0AWLTR,DFSDM analog watchdog low threshold register"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. " AWLT ,Analog watchdog low threshold"
|
|
bitfld.long 0x04 3. " BKAWL3 ,Break signal 3 assignment to analog watchdog low threshold event" "Not assigned,Assigned"
|
|
bitfld.long 0x04 2. " BKAWL2 ,Break signal 2 assignment to analog watchdog low threshold event" "Not assigned,Assigned"
|
|
textline " "
|
|
bitfld.long 0x04 1. " BKAWL1 ,Break signal 1 assignment to analog watchdog low threshold event" "Not assigned,Assigned"
|
|
bitfld.long 0x04 0. " BKAWL0 ,Break signal 0 assignment to analog watchdog low threshold event" "Not assigned,Assigned"
|
|
else
|
|
group.long (0x100+0x20)++0x07
|
|
line.long 0x00 "DFSDM_FLT0AWHTR,DFSDM Analog Watchdog High Threshold Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " AWHT ,Analog watchdog high threshold"
|
|
bitfld.long 0x00 3. " BKAWH3 ,Break signal 3 assignment to analog watchdog high threshold event" "Not assigned,Assigned"
|
|
bitfld.long 0x00 2. " BKAWH2 ,Break signal 2 assignment to analog watchdog high threshold event" "Not assigned,Assigned"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BKAWH1 ,Break signal 1 assignment to analog watchdog high threshold event" "Not assigned,Assigned"
|
|
bitfld.long 0x00 0. " BKAWH0 ,Break signal 0 assignment to analog watchdog high threshold event" "Not assigned,Assigned"
|
|
line.long 0x04 "DFSDM_FLT0AWLTR,DFSDM analog watchdog low threshold register"
|
|
hexmask.long.word 0x04 16.--31. 1. " AWLT ,Analog watchdog low threshold"
|
|
bitfld.long 0x04 3. " BKAWL3 ,Break signal 3 assignment to analog watchdog low threshold event" "Not assigned,Assigned"
|
|
bitfld.long 0x04 2. " BKAWL2 ,Break signal 2 assignment to analog watchdog low threshold event" "Not assigned,Assigned"
|
|
textline " "
|
|
bitfld.long 0x04 1. " BKAWL1 ,Break signal 1 assignment to analog watchdog low threshold event" "Not assigned,Assigned"
|
|
bitfld.long 0x04 0. " BKAWL0 ,Break signal 0 assignment to analog watchdog low threshold event" "Not assigned,Assigned"
|
|
endif
|
|
rgroup.long (0x100+0x28)++0x03
|
|
line.long 0x00 "DFSDM_FLT0AWSR,DFSDM Analog Watchdog Status Register"
|
|
bitfld.long 0x00 15. " AWHTF[7] ,Analog watchdog high threshold flag 7" "No error,Error"
|
|
bitfld.long 0x00 14. " AWHTF[6] ,Analog watchdog high threshold flag 6" "No error,Error"
|
|
bitfld.long 0x00 13. " AWHTF[5] ,Analog watchdog high threshold flag 5" "No error,Error"
|
|
bitfld.long 0x00 12. " AWHTF[4] ,Analog watchdog high threshold flag 4" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 11. " AWHTF[3] ,Analog watchdog high threshold flag 3" "No error,Error"
|
|
bitfld.long 0x00 10. " AWHTF[2] ,Analog watchdog high threshold flag 2" "No error,Error"
|
|
bitfld.long 0x00 9. " AWHTF[1] ,Analog watchdog high threshold flag 1" "No error,Error"
|
|
bitfld.long 0x00 8. " AWHTF[0] ,Analog watchdog high threshold flag 0" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AWLTF[7] ,Analog watchdog low threshold flag 7" "No error,Error"
|
|
bitfld.long 0x00 6. " AWLTF[6] ,Analog watchdog low threshold flag 6" "No error,Error"
|
|
bitfld.long 0x00 5. " AWLTF[5] ,Analog watchdog low threshold flag 5" "No error,Error"
|
|
bitfld.long 0x00 4. " AWLTF[4] ,Analog watchdog low threshold flag 4" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AWLTF[3] ,Analog watchdog low threshold flag 3" "No error,Error"
|
|
bitfld.long 0x00 2. " AWLTF[2] ,Analog watchdog low threshold flag 2" "No error,Error"
|
|
bitfld.long 0x00 1. " AWLTF[1] ,Analog watchdog low threshold flag 1" "No error,Error"
|
|
bitfld.long 0x00 0. " AWLTF[0] ,Analog watchdog low threshold flag 0" "No error,Error"
|
|
group.long (0x100+0x2C)++0x03
|
|
line.long 0x00 "DFSDM_FLT0AWCFR,DFSDM Analog Watchdog Clear Flag Register"
|
|
eventfld.long 0x00 15. " CLRAWHTF[7] ,Clear the analog watchdog high threshold flag 7" "No effect,Clear"
|
|
eventfld.long 0x00 14. " CLRAWHTF[6] ,Clear the analog watchdog high threshold flag 6" "No effect,Clear"
|
|
eventfld.long 0x00 13. " CLRAWHTF[5] ,Clear the analog watchdog high threshold flag 5" "No effect,Clear"
|
|
eventfld.long 0x00 12. " CLRAWHTF[4] ,Clear the analog watchdog high threshold flag 4" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 11. " CLRAWHTF[3] ,Clear the analog watchdog high threshold flag 3" "No effect,Clear"
|
|
eventfld.long 0x00 10. " CLRAWHTF[2] ,Clear the analog watchdog high threshold flag 2" "No effect,Clear"
|
|
eventfld.long 0x00 9. " CLRAWHTF[1] ,Clear the analog watchdog high threshold flag 1" "No effect,Clear"
|
|
eventfld.long 0x00 8. " CLRAWHTF[0] ,Clear the analog watchdog high threshold flag 0" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CLRAWLTF[7] ,Clear the analog watchdog low threshold flag 7" "No effect,Clear"
|
|
eventfld.long 0x00 6. " CLRAWLTF[6] ,Clear the analog watchdog low threshold flag 6" "No effect,Clear"
|
|
eventfld.long 0x00 5. " CLRAWLTF[5] ,Clear the analog watchdog low threshold flag 5" "No effect,Clear"
|
|
eventfld.long 0x00 4. " CLRAWLTF[4] ,Clear the analog watchdog low threshold flag 4" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 3. " CLRAWLTF[3] ,Clear the analog watchdog low threshold flag 3" "No effect,Clear"
|
|
eventfld.long 0x00 2. " CLRAWLTF[2] ,Clear the analog watchdog low threshold flag 2" "No effect,Clear"
|
|
eventfld.long 0x00 1. " CLRAWLTF[1] ,Clear the analog watchdog low threshold flag 1" "No effect,Clear"
|
|
eventfld.long 0x00 0. " CLRAWLTF[0] ,Clear the analog watchdog low threshold flag 0" "No effect,Clear"
|
|
hgroup.long (0x100+0x30)++0x03
|
|
hide.long 0x00 "DFSDM_FLT0EXMAX,DFSDM Extremes Detector Maximum Register"
|
|
in
|
|
hgroup.long (0x100+0x34)++0x03
|
|
hide.long 0x00 "DFSDM_FLT0EXMIN,DFSDM Extremes Detector Minimum Register"
|
|
in
|
|
rgroup.long (0x100+0x38)++0x03
|
|
line.long 0x00 "DFSDM_FLT0CNVTIMR,DFSDM Conversion Timer Register"
|
|
hexmask.long 0x00 4.--31. 1. " CNVCNT ,28-bit timer counting conversion time t = CNVCNT / fDFSDM_CKIN"
|
|
tree.end
|
|
tree "Module 1 registers"
|
|
if (((per.l(ad:0x40017400+0x180))&0x01)==0x00)
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "DFSDM_FLT1CR1,DFSDM Control Register 1"
|
|
bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Channel transceivers value"
|
|
bitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7"
|
|
bitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM0" "Not launched,Launched"
|
|
bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly"
|
|
bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "Not started,Started"
|
|
bitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM10_OC1,TIM6_TRGO,TIM7_TRGO,,,,,,,,,,,,,,,EXTI11,EXTI15,LPTIMER1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " JDMAEN ,DMA channel enabled to read data for the injected channel group" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One,Series"
|
|
bitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger" "Not launched,Launched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DFEN ,DFSDM_FLT1 enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "DFSDM_FLT1CR1,DFSDM Control Register 1"
|
|
bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value"
|
|
rbitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7"
|
|
rbitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM0" "Not launched,Launched"
|
|
bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly"
|
|
bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "Not started,Started"
|
|
rbitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM10_OC1,TIM6_TRGO,TIM7_TRGO,,,,,,,,,,,,,,,EXTI11,EXTI15,LPTIMER1,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 5. " JDMAEN ,DMA channel enabled to read data for the injected channel group" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One,Series"
|
|
rbitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger" "Not launched,Launched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DFEN ,DFSDM_FLT1 enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x180+0x04)++0x03
|
|
line.long 0x00 "DFSDM_FLT1CR2,DFSDM Filter 1 Control Register"
|
|
bitfld.long 0x00 23. " AWDCH[7] ,Analog watchdog channel 7 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " AWDCH[6] ,Analog watchdog channel 6 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " AWDCH[5] ,Analog watchdog channel 5 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " AWDCH[4] ,Analog watchdog channel 4 selection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " AWDCH[3] ,Analog watchdog channel 3 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " AWDCH[2] ,Analog watchdog channel 2 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " AWDCH[1] ,Analog watchdog channel 1 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " AWDCH[0] ,Analog watchdog channel 0 selection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EXCH[7] ,Extremes detector channel 7 selection" "No data accept,Accepts data"
|
|
bitfld.long 0x00 14. " EXCH[6] ,Extremes detector channel 6 selection" "No data accept,Accepts data"
|
|
bitfld.long 0x00 13. " EXCH[5] ,Extremes detector channel 5 selection" "No data accept,Accepts data"
|
|
bitfld.long 0x00 12. " EXCH[4] ,Extremes detector channel 4 selection" "No data accept,Accepts data"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EXCH[3] ,Extremes detector channel 3 selection" "No data accept,Accepts data"
|
|
bitfld.long 0x00 10. " EXCH[2] ,Extremes detector channel 2 selection" "No data accept,Accepts data"
|
|
bitfld.long 0x00 9. " EXCH[1] ,Extremes detector channel 1 selection" "No data accept,Accepts data"
|
|
bitfld.long 0x00 8. " EXCH[0] ,Extremes detector channel 0 selection" "No data accept,Accepts data"
|
|
textline " "
|
|
bitfld.long 0x00 4. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " JOVRIE ,Injected data overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled"
|
|
rgroup.long (0x180+0x08)++0x03
|
|
line.long 0x00 "DFSDM_FLT1ISR,DFSDM Interrupt And Status Register"
|
|
bitfld.long 0x00 14. " RCIP ,Regular conversion in progress status" "No request,In progress"
|
|
bitfld.long 0x00 13. " JCIP ,Injected conversion in progress status" "No request,In progress"
|
|
bitfld.long 0x00 4. " AWDF ,Analog watchdog" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ROVRF ,Regular conversion overrun flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " JOVRF ,Injected conversion overrun flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " REOCF ,End of regular conversion flag" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " JEOCF ,End of injected conversion flag" "Not completed,Completed"
|
|
group.long (0x180+0x0C)++0x07
|
|
line.long 0x00 "DFSDM_FLT1ICR,DFSDM Interrupt Flag Clear Register"
|
|
eventfld.long 0x00 3. " CLRROVRF ,Clear the regular conversion overrun flag" "No effect,Clear"
|
|
eventfld.long 0x00 2. " CLRJOVRF ,Clear the injected conversion overrun flag" "No effect,Clear"
|
|
line.long 0x04 "DFSDM_FLT1JCHGR,DFSDM Injected Channel Group Selection Register"
|
|
bitfld.long 0x04 7. " JCHG[7] ,Injected channel 7 group selection" "Excluded,Included"
|
|
bitfld.long 0x04 6. " JCHG[6] ,Injected channel 6 group selection" "Excluded,Included"
|
|
bitfld.long 0x04 5. " JCHG[5] ,Injected channel 5 group selection" "Excluded,Included"
|
|
bitfld.long 0x04 4. " JCHG[4] ,Injected channel 4 group selection" "Excluded,Included"
|
|
textline " "
|
|
bitfld.long 0x04 3. " JCHG[3] ,Injected channel 3 group selection" "Excluded,Included"
|
|
bitfld.long 0x04 2. " JCHG[2] ,Injected channel 2 group selection" "Excluded,Included"
|
|
bitfld.long 0x04 1. " JCHG[1] ,Injected channel 1 group selection" "Excluded,Included"
|
|
bitfld.long 0x04 0. " JCHG[0] ,Injected channel 0 group selection" "Excluded,Included"
|
|
if (((per.l(ad:0x40017400+0x180))&0x01)==0x00)
|
|
group.long (0x180+0x14)++0x03
|
|
line.long 0x00 "DFSDM_FLT1FCR,DFSDM Filter Control Register"
|
|
bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..."
|
|
hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)"
|
|
else
|
|
rgroup.long (0x180+0x14)++0x03
|
|
line.long 0x00 "DFSDM_FLT1FCR,DFSDM Filter Control Register"
|
|
bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..."
|
|
hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)"
|
|
endif
|
|
hgroup.long (0x180+0x18)++0x03
|
|
hide.long 0x00 "DFSDM_FLT1JDATAR,DFSDM Filter 1 Data Register For Injected Group"
|
|
in
|
|
hgroup.long (0x180+0x1C)++0x03
|
|
hide.long 0x00 "DFSDM_FLT1RDATAR,DFSDM Filter 1 Data Register For The Regular Channel"
|
|
in
|
|
if (((per.l(ad:0x40017400+0x180))&0x40000000)==0x00)
|
|
group.long (0x180+0x20)++0x07
|
|
line.long 0x00 "DFSDM_FLT1AWHTR,DFSDM Analog Watchdog High Threshold Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " AWHT ,Analog watchdog high threshold"
|
|
bitfld.long 0x00 3. " BKAWH3 ,Break signal 3 assignment to analog watchdog high threshold event" "Not assigned,Assigned"
|
|
bitfld.long 0x00 2. " BKAWH2 ,Break signal 2 assignment to analog watchdog high threshold event" "Not assigned,Assigned"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BKAWH1 ,Break signal 1 assignment to analog watchdog high threshold event" "Not assigned,Assigned"
|
|
bitfld.long 0x00 0. " BKAWH0 ,Break signal 0 assignment to analog watchdog high threshold event" "Not assigned,Assigned"
|
|
line.long 0x04 "DFSDM_FLT1AWLTR,DFSDM analog watchdog low threshold register"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. " AWLT ,Analog watchdog low threshold"
|
|
bitfld.long 0x04 3. " BKAWL3 ,Break signal 3 assignment to analog watchdog low threshold event" "Not assigned,Assigned"
|
|
bitfld.long 0x04 2. " BKAWL2 ,Break signal 2 assignment to analog watchdog low threshold event" "Not assigned,Assigned"
|
|
textline " "
|
|
bitfld.long 0x04 1. " BKAWL1 ,Break signal 1 assignment to analog watchdog low threshold event" "Not assigned,Assigned"
|
|
bitfld.long 0x04 0. " BKAWL0 ,Break signal 0 assignment to analog watchdog low threshold event" "Not assigned,Assigned"
|
|
else
|
|
group.long (0x180+0x20)++0x07
|
|
line.long 0x00 "DFSDM_FLT1AWHTR,DFSDM Analog Watchdog High Threshold Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " AWHT ,Analog watchdog high threshold"
|
|
bitfld.long 0x00 3. " BKAWH3 ,Break signal 3 assignment to analog watchdog high threshold event" "Not assigned,Assigned"
|
|
bitfld.long 0x00 2. " BKAWH2 ,Break signal 2 assignment to analog watchdog high threshold event" "Not assigned,Assigned"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BKAWH1 ,Break signal 1 assignment to analog watchdog high threshold event" "Not assigned,Assigned"
|
|
bitfld.long 0x00 0. " BKAWH0 ,Break signal 0 assignment to analog watchdog high threshold event" "Not assigned,Assigned"
|
|
line.long 0x04 "DFSDM_FLT1AWLTR,DFSDM analog watchdog low threshold register"
|
|
hexmask.long.word 0x04 16.--31. 1. " AWLT ,Analog watchdog low threshold"
|
|
bitfld.long 0x04 3. " BKAWL3 ,Break signal 3 assignment to analog watchdog low threshold event" "Not assigned,Assigned"
|
|
bitfld.long 0x04 2. " BKAWL2 ,Break signal 2 assignment to analog watchdog low threshold event" "Not assigned,Assigned"
|
|
textline " "
|
|
bitfld.long 0x04 1. " BKAWL1 ,Break signal 1 assignment to analog watchdog low threshold event" "Not assigned,Assigned"
|
|
bitfld.long 0x04 0. " BKAWL0 ,Break signal 0 assignment to analog watchdog low threshold event" "Not assigned,Assigned"
|
|
endif
|
|
rgroup.long (0x180+0x28)++0x03
|
|
line.long 0x00 "DFSDM_FLT1AWSR,DFSDM Analog Watchdog Status Register"
|
|
bitfld.long 0x00 15. " AWHTF[7] ,Analog watchdog high threshold flag 7" "No error,Error"
|
|
bitfld.long 0x00 14. " AWHTF[6] ,Analog watchdog high threshold flag 6" "No error,Error"
|
|
bitfld.long 0x00 13. " AWHTF[5] ,Analog watchdog high threshold flag 5" "No error,Error"
|
|
bitfld.long 0x00 12. " AWHTF[4] ,Analog watchdog high threshold flag 4" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 11. " AWHTF[3] ,Analog watchdog high threshold flag 3" "No error,Error"
|
|
bitfld.long 0x00 10. " AWHTF[2] ,Analog watchdog high threshold flag 2" "No error,Error"
|
|
bitfld.long 0x00 9. " AWHTF[1] ,Analog watchdog high threshold flag 1" "No error,Error"
|
|
bitfld.long 0x00 8. " AWHTF[0] ,Analog watchdog high threshold flag 0" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AWLTF[7] ,Analog watchdog low threshold flag 7" "No error,Error"
|
|
bitfld.long 0x00 6. " AWLTF[6] ,Analog watchdog low threshold flag 6" "No error,Error"
|
|
bitfld.long 0x00 5. " AWLTF[5] ,Analog watchdog low threshold flag 5" "No error,Error"
|
|
bitfld.long 0x00 4. " AWLTF[4] ,Analog watchdog low threshold flag 4" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AWLTF[3] ,Analog watchdog low threshold flag 3" "No error,Error"
|
|
bitfld.long 0x00 2. " AWLTF[2] ,Analog watchdog low threshold flag 2" "No error,Error"
|
|
bitfld.long 0x00 1. " AWLTF[1] ,Analog watchdog low threshold flag 1" "No error,Error"
|
|
bitfld.long 0x00 0. " AWLTF[0] ,Analog watchdog low threshold flag 0" "No error,Error"
|
|
group.long (0x180+0x2C)++0x03
|
|
line.long 0x00 "DFSDM_FLT1AWCFR,DFSDM Analog Watchdog Clear Flag Register"
|
|
eventfld.long 0x00 15. " CLRAWHTF[7] ,Clear the analog watchdog high threshold flag 7" "No effect,Clear"
|
|
eventfld.long 0x00 14. " CLRAWHTF[6] ,Clear the analog watchdog high threshold flag 6" "No effect,Clear"
|
|
eventfld.long 0x00 13. " CLRAWHTF[5] ,Clear the analog watchdog high threshold flag 5" "No effect,Clear"
|
|
eventfld.long 0x00 12. " CLRAWHTF[4] ,Clear the analog watchdog high threshold flag 4" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 11. " CLRAWHTF[3] ,Clear the analog watchdog high threshold flag 3" "No effect,Clear"
|
|
eventfld.long 0x00 10. " CLRAWHTF[2] ,Clear the analog watchdog high threshold flag 2" "No effect,Clear"
|
|
eventfld.long 0x00 9. " CLRAWHTF[1] ,Clear the analog watchdog high threshold flag 1" "No effect,Clear"
|
|
eventfld.long 0x00 8. " CLRAWHTF[0] ,Clear the analog watchdog high threshold flag 0" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CLRAWLTF[7] ,Clear the analog watchdog low threshold flag 7" "No effect,Clear"
|
|
eventfld.long 0x00 6. " CLRAWLTF[6] ,Clear the analog watchdog low threshold flag 6" "No effect,Clear"
|
|
eventfld.long 0x00 5. " CLRAWLTF[5] ,Clear the analog watchdog low threshold flag 5" "No effect,Clear"
|
|
eventfld.long 0x00 4. " CLRAWLTF[4] ,Clear the analog watchdog low threshold flag 4" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 3. " CLRAWLTF[3] ,Clear the analog watchdog low threshold flag 3" "No effect,Clear"
|
|
eventfld.long 0x00 2. " CLRAWLTF[2] ,Clear the analog watchdog low threshold flag 2" "No effect,Clear"
|
|
eventfld.long 0x00 1. " CLRAWLTF[1] ,Clear the analog watchdog low threshold flag 1" "No effect,Clear"
|
|
eventfld.long 0x00 0. " CLRAWLTF[0] ,Clear the analog watchdog low threshold flag 0" "No effect,Clear"
|
|
hgroup.long (0x180+0x30)++0x03
|
|
hide.long 0x00 "DFSDM_FLT1EXMAX,DFSDM Extremes Detector Maximum Register"
|
|
in
|
|
hgroup.long (0x180+0x34)++0x03
|
|
hide.long 0x00 "DFSDM_FLT1EXMIN,DFSDM Extremes Detector Minimum Register"
|
|
in
|
|
rgroup.long (0x180+0x38)++0x03
|
|
line.long 0x00 "DFSDM_FLT1CNVTIMR,DFSDM Conversion Timer Register"
|
|
hexmask.long 0x00 4.--31. 1. " CNVCNT ,28-bit timer counting conversion time t = CNVCNT / fDFSDM_CKIN"
|
|
tree.end
|
|
tree "Module 2 registers"
|
|
if (((per.l(ad:0x40017400+0x200))&0x01)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "DFSDM_FLT2CR1,DFSDM Control Register 1"
|
|
bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Channel transceivers value"
|
|
bitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7"
|
|
bitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM0" "Not launched,Launched"
|
|
bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly"
|
|
bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "Not started,Started"
|
|
bitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM10_OC1,TIM6_TRGO,TIM7_TRGO,,,,,,,,,,,,,,,EXTI11,EXTI15,LPTIMER1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " JDMAEN ,DMA channel enabled to read data for the injected channel group" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One,Series"
|
|
bitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger" "Not launched,Launched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DFEN ,DFSDM_FLT2 enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "DFSDM_FLT2CR1,DFSDM Control Register 1"
|
|
bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value"
|
|
rbitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7"
|
|
rbitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM0" "Not launched,Launched"
|
|
bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly"
|
|
bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "Not started,Started"
|
|
rbitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM10_OC1,TIM6_TRGO,TIM7_TRGO,,,,,,,,,,,,,,,EXTI11,EXTI15,LPTIMER1,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 5. " JDMAEN ,DMA channel enabled to read data for the injected channel group" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One,Series"
|
|
rbitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger" "Not launched,Launched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DFEN ,DFSDM_FLT2 enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x200+0x04)++0x03
|
|
line.long 0x00 "DFSDM_FLT2CR2,DFSDM Filter 2 Control Register"
|
|
bitfld.long 0x00 23. " AWDCH[7] ,Analog watchdog channel 7 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " AWDCH[6] ,Analog watchdog channel 6 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " AWDCH[5] ,Analog watchdog channel 5 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " AWDCH[4] ,Analog watchdog channel 4 selection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " AWDCH[3] ,Analog watchdog channel 3 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " AWDCH[2] ,Analog watchdog channel 2 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " AWDCH[1] ,Analog watchdog channel 1 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " AWDCH[0] ,Analog watchdog channel 0 selection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EXCH[7] ,Extremes detector channel 7 selection" "No data accept,Accepts data"
|
|
bitfld.long 0x00 14. " EXCH[6] ,Extremes detector channel 6 selection" "No data accept,Accepts data"
|
|
bitfld.long 0x00 13. " EXCH[5] ,Extremes detector channel 5 selection" "No data accept,Accepts data"
|
|
bitfld.long 0x00 12. " EXCH[4] ,Extremes detector channel 4 selection" "No data accept,Accepts data"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EXCH[3] ,Extremes detector channel 3 selection" "No data accept,Accepts data"
|
|
bitfld.long 0x00 10. " EXCH[2] ,Extremes detector channel 2 selection" "No data accept,Accepts data"
|
|
bitfld.long 0x00 9. " EXCH[1] ,Extremes detector channel 1 selection" "No data accept,Accepts data"
|
|
bitfld.long 0x00 8. " EXCH[0] ,Extremes detector channel 0 selection" "No data accept,Accepts data"
|
|
textline " "
|
|
bitfld.long 0x00 4. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " JOVRIE ,Injected data overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled"
|
|
rgroup.long (0x200+0x08)++0x03
|
|
line.long 0x00 "DFSDM_FLT2ISR,DFSDM Interrupt And Status Register"
|
|
bitfld.long 0x00 14. " RCIP ,Regular conversion in progress status" "No request,In progress"
|
|
bitfld.long 0x00 13. " JCIP ,Injected conversion in progress status" "No request,In progress"
|
|
bitfld.long 0x00 4. " AWDF ,Analog watchdog" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ROVRF ,Regular conversion overrun flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " JOVRF ,Injected conversion overrun flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " REOCF ,End of regular conversion flag" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " JEOCF ,End of injected conversion flag" "Not completed,Completed"
|
|
group.long (0x200+0x0C)++0x07
|
|
line.long 0x00 "DFSDM_FLT2ICR,DFSDM Interrupt Flag Clear Register"
|
|
eventfld.long 0x00 3. " CLRROVRF ,Clear the regular conversion overrun flag" "No effect,Clear"
|
|
eventfld.long 0x00 2. " CLRJOVRF ,Clear the injected conversion overrun flag" "No effect,Clear"
|
|
line.long 0x04 "DFSDM_FLT2JCHGR,DFSDM Injected Channel Group Selection Register"
|
|
bitfld.long 0x04 7. " JCHG[7] ,Injected channel 7 group selection" "Excluded,Included"
|
|
bitfld.long 0x04 6. " JCHG[6] ,Injected channel 6 group selection" "Excluded,Included"
|
|
bitfld.long 0x04 5. " JCHG[5] ,Injected channel 5 group selection" "Excluded,Included"
|
|
bitfld.long 0x04 4. " JCHG[4] ,Injected channel 4 group selection" "Excluded,Included"
|
|
textline " "
|
|
bitfld.long 0x04 3. " JCHG[3] ,Injected channel 3 group selection" "Excluded,Included"
|
|
bitfld.long 0x04 2. " JCHG[2] ,Injected channel 2 group selection" "Excluded,Included"
|
|
bitfld.long 0x04 1. " JCHG[1] ,Injected channel 1 group selection" "Excluded,Included"
|
|
bitfld.long 0x04 0. " JCHG[0] ,Injected channel 0 group selection" "Excluded,Included"
|
|
if (((per.l(ad:0x40017400+0x200))&0x01)==0x00)
|
|
group.long (0x200+0x14)++0x03
|
|
line.long 0x00 "DFSDM_FLT2FCR,DFSDM Filter Control Register"
|
|
bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..."
|
|
hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)"
|
|
else
|
|
rgroup.long (0x200+0x14)++0x03
|
|
line.long 0x00 "DFSDM_FLT2FCR,DFSDM Filter Control Register"
|
|
bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..."
|
|
hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)"
|
|
endif
|
|
hgroup.long (0x200+0x18)++0x03
|
|
hide.long 0x00 "DFSDM_FLT2JDATAR,DFSDM Filter 2 Data Register For Injected Group"
|
|
in
|
|
hgroup.long (0x200+0x1C)++0x03
|
|
hide.long 0x00 "DFSDM_FLT2RDATAR,DFSDM Filter 2 Data Register For The Regular Channel"
|
|
in
|
|
if (((per.l(ad:0x40017400+0x200))&0x40000000)==0x00)
|
|
group.long (0x200+0x20)++0x07
|
|
line.long 0x00 "DFSDM_FLT2AWHTR,DFSDM Analog Watchdog High Threshold Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " AWHT ,Analog watchdog high threshold"
|
|
bitfld.long 0x00 3. " BKAWH3 ,Break signal 3 assignment to analog watchdog high threshold event" "Not assigned,Assigned"
|
|
bitfld.long 0x00 2. " BKAWH2 ,Break signal 2 assignment to analog watchdog high threshold event" "Not assigned,Assigned"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BKAWH1 ,Break signal 1 assignment to analog watchdog high threshold event" "Not assigned,Assigned"
|
|
bitfld.long 0x00 0. " BKAWH0 ,Break signal 0 assignment to analog watchdog high threshold event" "Not assigned,Assigned"
|
|
line.long 0x04 "DFSDM_FLT2AWLTR,DFSDM analog watchdog low threshold register"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. " AWLT ,Analog watchdog low threshold"
|
|
bitfld.long 0x04 3. " BKAWL3 ,Break signal 3 assignment to analog watchdog low threshold event" "Not assigned,Assigned"
|
|
bitfld.long 0x04 2. " BKAWL2 ,Break signal 2 assignment to analog watchdog low threshold event" "Not assigned,Assigned"
|
|
textline " "
|
|
bitfld.long 0x04 1. " BKAWL1 ,Break signal 1 assignment to analog watchdog low threshold event" "Not assigned,Assigned"
|
|
bitfld.long 0x04 0. " BKAWL0 ,Break signal 0 assignment to analog watchdog low threshold event" "Not assigned,Assigned"
|
|
else
|
|
group.long (0x200+0x20)++0x07
|
|
line.long 0x00 "DFSDM_FLT2AWHTR,DFSDM Analog Watchdog High Threshold Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " AWHT ,Analog watchdog high threshold"
|
|
bitfld.long 0x00 3. " BKAWH3 ,Break signal 3 assignment to analog watchdog high threshold event" "Not assigned,Assigned"
|
|
bitfld.long 0x00 2. " BKAWH2 ,Break signal 2 assignment to analog watchdog high threshold event" "Not assigned,Assigned"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BKAWH1 ,Break signal 1 assignment to analog watchdog high threshold event" "Not assigned,Assigned"
|
|
bitfld.long 0x00 0. " BKAWH0 ,Break signal 0 assignment to analog watchdog high threshold event" "Not assigned,Assigned"
|
|
line.long 0x04 "DFSDM_FLT2AWLTR,DFSDM analog watchdog low threshold register"
|
|
hexmask.long.word 0x04 16.--31. 1. " AWLT ,Analog watchdog low threshold"
|
|
bitfld.long 0x04 3. " BKAWL3 ,Break signal 3 assignment to analog watchdog low threshold event" "Not assigned,Assigned"
|
|
bitfld.long 0x04 2. " BKAWL2 ,Break signal 2 assignment to analog watchdog low threshold event" "Not assigned,Assigned"
|
|
textline " "
|
|
bitfld.long 0x04 1. " BKAWL1 ,Break signal 1 assignment to analog watchdog low threshold event" "Not assigned,Assigned"
|
|
bitfld.long 0x04 0. " BKAWL0 ,Break signal 0 assignment to analog watchdog low threshold event" "Not assigned,Assigned"
|
|
endif
|
|
rgroup.long (0x200+0x28)++0x03
|
|
line.long 0x00 "DFSDM_FLT2AWSR,DFSDM Analog Watchdog Status Register"
|
|
bitfld.long 0x00 15. " AWHTF[7] ,Analog watchdog high threshold flag 7" "No error,Error"
|
|
bitfld.long 0x00 14. " AWHTF[6] ,Analog watchdog high threshold flag 6" "No error,Error"
|
|
bitfld.long 0x00 13. " AWHTF[5] ,Analog watchdog high threshold flag 5" "No error,Error"
|
|
bitfld.long 0x00 12. " AWHTF[4] ,Analog watchdog high threshold flag 4" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 11. " AWHTF[3] ,Analog watchdog high threshold flag 3" "No error,Error"
|
|
bitfld.long 0x00 10. " AWHTF[2] ,Analog watchdog high threshold flag 2" "No error,Error"
|
|
bitfld.long 0x00 9. " AWHTF[1] ,Analog watchdog high threshold flag 1" "No error,Error"
|
|
bitfld.long 0x00 8. " AWHTF[0] ,Analog watchdog high threshold flag 0" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AWLTF[7] ,Analog watchdog low threshold flag 7" "No error,Error"
|
|
bitfld.long 0x00 6. " AWLTF[6] ,Analog watchdog low threshold flag 6" "No error,Error"
|
|
bitfld.long 0x00 5. " AWLTF[5] ,Analog watchdog low threshold flag 5" "No error,Error"
|
|
bitfld.long 0x00 4. " AWLTF[4] ,Analog watchdog low threshold flag 4" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AWLTF[3] ,Analog watchdog low threshold flag 3" "No error,Error"
|
|
bitfld.long 0x00 2. " AWLTF[2] ,Analog watchdog low threshold flag 2" "No error,Error"
|
|
bitfld.long 0x00 1. " AWLTF[1] ,Analog watchdog low threshold flag 1" "No error,Error"
|
|
bitfld.long 0x00 0. " AWLTF[0] ,Analog watchdog low threshold flag 0" "No error,Error"
|
|
group.long (0x200+0x2C)++0x03
|
|
line.long 0x00 "DFSDM_FLT2AWCFR,DFSDM Analog Watchdog Clear Flag Register"
|
|
eventfld.long 0x00 15. " CLRAWHTF[7] ,Clear the analog watchdog high threshold flag 7" "No effect,Clear"
|
|
eventfld.long 0x00 14. " CLRAWHTF[6] ,Clear the analog watchdog high threshold flag 6" "No effect,Clear"
|
|
eventfld.long 0x00 13. " CLRAWHTF[5] ,Clear the analog watchdog high threshold flag 5" "No effect,Clear"
|
|
eventfld.long 0x00 12. " CLRAWHTF[4] ,Clear the analog watchdog high threshold flag 4" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 11. " CLRAWHTF[3] ,Clear the analog watchdog high threshold flag 3" "No effect,Clear"
|
|
eventfld.long 0x00 10. " CLRAWHTF[2] ,Clear the analog watchdog high threshold flag 2" "No effect,Clear"
|
|
eventfld.long 0x00 9. " CLRAWHTF[1] ,Clear the analog watchdog high threshold flag 1" "No effect,Clear"
|
|
eventfld.long 0x00 8. " CLRAWHTF[0] ,Clear the analog watchdog high threshold flag 0" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CLRAWLTF[7] ,Clear the analog watchdog low threshold flag 7" "No effect,Clear"
|
|
eventfld.long 0x00 6. " CLRAWLTF[6] ,Clear the analog watchdog low threshold flag 6" "No effect,Clear"
|
|
eventfld.long 0x00 5. " CLRAWLTF[5] ,Clear the analog watchdog low threshold flag 5" "No effect,Clear"
|
|
eventfld.long 0x00 4. " CLRAWLTF[4] ,Clear the analog watchdog low threshold flag 4" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 3. " CLRAWLTF[3] ,Clear the analog watchdog low threshold flag 3" "No effect,Clear"
|
|
eventfld.long 0x00 2. " CLRAWLTF[2] ,Clear the analog watchdog low threshold flag 2" "No effect,Clear"
|
|
eventfld.long 0x00 1. " CLRAWLTF[1] ,Clear the analog watchdog low threshold flag 1" "No effect,Clear"
|
|
eventfld.long 0x00 0. " CLRAWLTF[0] ,Clear the analog watchdog low threshold flag 0" "No effect,Clear"
|
|
hgroup.long (0x200+0x30)++0x03
|
|
hide.long 0x00 "DFSDM_FLT2EXMAX,DFSDM Extremes Detector Maximum Register"
|
|
in
|
|
hgroup.long (0x200+0x34)++0x03
|
|
hide.long 0x00 "DFSDM_FLT2EXMIN,DFSDM Extremes Detector Minimum Register"
|
|
in
|
|
rgroup.long (0x200+0x38)++0x03
|
|
line.long 0x00 "DFSDM_FLT2CNVTIMR,DFSDM Conversion Timer Register"
|
|
hexmask.long 0x00 4.--31. 1. " CNVCNT ,28-bit timer counting conversion time t = CNVCNT / fDFSDM_CKIN"
|
|
tree.end
|
|
tree "Module 3 registers"
|
|
if (((per.l(ad:0x40017400+0x280))&0x01)==0x00)
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "DFSDM_FLT3CR1,DFSDM Control Register 1"
|
|
bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Channel transceivers value"
|
|
bitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7"
|
|
bitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM0" "Not launched,Launched"
|
|
bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly"
|
|
bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "Not started,Started"
|
|
bitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM10_OC1,TIM6_TRGO,TIM7_TRGO,,,,,,,,,,,,,,,EXTI11,EXTI15,LPTIMER1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " JDMAEN ,DMA channel enabled to read data for the injected channel group" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One,Series"
|
|
bitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger" "Not launched,Launched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DFEN ,DFSDM_FLT3 enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "DFSDM_FLT3CR1,DFSDM Control Register 1"
|
|
bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value"
|
|
rbitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7"
|
|
rbitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM0" "Not launched,Launched"
|
|
bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly"
|
|
bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "Not started,Started"
|
|
rbitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM10_OC1,TIM6_TRGO,TIM7_TRGO,,,,,,,,,,,,,,,EXTI11,EXTI15,LPTIMER1,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 5. " JDMAEN ,DMA channel enabled to read data for the injected channel group" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One,Series"
|
|
rbitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger" "Not launched,Launched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DFEN ,DFSDM_FLT3 enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x280+0x04)++0x03
|
|
line.long 0x00 "DFSDM_FLT3CR2,DFSDM Filter 3 Control Register"
|
|
bitfld.long 0x00 23. " AWDCH[7] ,Analog watchdog channel 7 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " AWDCH[6] ,Analog watchdog channel 6 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " AWDCH[5] ,Analog watchdog channel 5 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " AWDCH[4] ,Analog watchdog channel 4 selection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " AWDCH[3] ,Analog watchdog channel 3 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " AWDCH[2] ,Analog watchdog channel 2 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " AWDCH[1] ,Analog watchdog channel 1 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " AWDCH[0] ,Analog watchdog channel 0 selection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EXCH[7] ,Extremes detector channel 7 selection" "No data accept,Accepts data"
|
|
bitfld.long 0x00 14. " EXCH[6] ,Extremes detector channel 6 selection" "No data accept,Accepts data"
|
|
bitfld.long 0x00 13. " EXCH[5] ,Extremes detector channel 5 selection" "No data accept,Accepts data"
|
|
bitfld.long 0x00 12. " EXCH[4] ,Extremes detector channel 4 selection" "No data accept,Accepts data"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EXCH[3] ,Extremes detector channel 3 selection" "No data accept,Accepts data"
|
|
bitfld.long 0x00 10. " EXCH[2] ,Extremes detector channel 2 selection" "No data accept,Accepts data"
|
|
bitfld.long 0x00 9. " EXCH[1] ,Extremes detector channel 1 selection" "No data accept,Accepts data"
|
|
bitfld.long 0x00 8. " EXCH[0] ,Extremes detector channel 0 selection" "No data accept,Accepts data"
|
|
textline " "
|
|
bitfld.long 0x00 4. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " JOVRIE ,Injected data overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled"
|
|
rgroup.long (0x280+0x08)++0x03
|
|
line.long 0x00 "DFSDM_FLT3ISR,DFSDM Interrupt And Status Register"
|
|
bitfld.long 0x00 14. " RCIP ,Regular conversion in progress status" "No request,In progress"
|
|
bitfld.long 0x00 13. " JCIP ,Injected conversion in progress status" "No request,In progress"
|
|
bitfld.long 0x00 4. " AWDF ,Analog watchdog" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ROVRF ,Regular conversion overrun flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " JOVRF ,Injected conversion overrun flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " REOCF ,End of regular conversion flag" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " JEOCF ,End of injected conversion flag" "Not completed,Completed"
|
|
group.long (0x280+0x0C)++0x07
|
|
line.long 0x00 "DFSDM_FLT3ICR,DFSDM Interrupt Flag Clear Register"
|
|
eventfld.long 0x00 3. " CLRROVRF ,Clear the regular conversion overrun flag" "No effect,Clear"
|
|
eventfld.long 0x00 2. " CLRJOVRF ,Clear the injected conversion overrun flag" "No effect,Clear"
|
|
line.long 0x04 "DFSDM_FLT3JCHGR,DFSDM Injected Channel Group Selection Register"
|
|
bitfld.long 0x04 7. " JCHG[7] ,Injected channel 7 group selection" "Excluded,Included"
|
|
bitfld.long 0x04 6. " JCHG[6] ,Injected channel 6 group selection" "Excluded,Included"
|
|
bitfld.long 0x04 5. " JCHG[5] ,Injected channel 5 group selection" "Excluded,Included"
|
|
bitfld.long 0x04 4. " JCHG[4] ,Injected channel 4 group selection" "Excluded,Included"
|
|
textline " "
|
|
bitfld.long 0x04 3. " JCHG[3] ,Injected channel 3 group selection" "Excluded,Included"
|
|
bitfld.long 0x04 2. " JCHG[2] ,Injected channel 2 group selection" "Excluded,Included"
|
|
bitfld.long 0x04 1. " JCHG[1] ,Injected channel 1 group selection" "Excluded,Included"
|
|
bitfld.long 0x04 0. " JCHG[0] ,Injected channel 0 group selection" "Excluded,Included"
|
|
if (((per.l(ad:0x40017400+0x280))&0x01)==0x00)
|
|
group.long (0x280+0x14)++0x03
|
|
line.long 0x00 "DFSDM_FLT3FCR,DFSDM Filter Control Register"
|
|
bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..."
|
|
hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)"
|
|
else
|
|
rgroup.long (0x280+0x14)++0x03
|
|
line.long 0x00 "DFSDM_FLT3FCR,DFSDM Filter Control Register"
|
|
bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..."
|
|
hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)"
|
|
endif
|
|
hgroup.long (0x280+0x18)++0x03
|
|
hide.long 0x00 "DFSDM_FLT3JDATAR,DFSDM Filter 3 Data Register For Injected Group"
|
|
in
|
|
hgroup.long (0x280+0x1C)++0x03
|
|
hide.long 0x00 "DFSDM_FLT3RDATAR,DFSDM Filter 3 Data Register For The Regular Channel"
|
|
in
|
|
if (((per.l(ad:0x40017400+0x280))&0x40000000)==0x00)
|
|
group.long (0x280+0x20)++0x07
|
|
line.long 0x00 "DFSDM_FLT3AWHTR,DFSDM Analog Watchdog High Threshold Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " AWHT ,Analog watchdog high threshold"
|
|
bitfld.long 0x00 3. " BKAWH3 ,Break signal 3 assignment to analog watchdog high threshold event" "Not assigned,Assigned"
|
|
bitfld.long 0x00 2. " BKAWH2 ,Break signal 2 assignment to analog watchdog high threshold event" "Not assigned,Assigned"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BKAWH1 ,Break signal 1 assignment to analog watchdog high threshold event" "Not assigned,Assigned"
|
|
bitfld.long 0x00 0. " BKAWH0 ,Break signal 0 assignment to analog watchdog high threshold event" "Not assigned,Assigned"
|
|
line.long 0x04 "DFSDM_FLT3AWLTR,DFSDM analog watchdog low threshold register"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. " AWLT ,Analog watchdog low threshold"
|
|
bitfld.long 0x04 3. " BKAWL3 ,Break signal 3 assignment to analog watchdog low threshold event" "Not assigned,Assigned"
|
|
bitfld.long 0x04 2. " BKAWL2 ,Break signal 2 assignment to analog watchdog low threshold event" "Not assigned,Assigned"
|
|
textline " "
|
|
bitfld.long 0x04 1. " BKAWL1 ,Break signal 1 assignment to analog watchdog low threshold event" "Not assigned,Assigned"
|
|
bitfld.long 0x04 0. " BKAWL0 ,Break signal 0 assignment to analog watchdog low threshold event" "Not assigned,Assigned"
|
|
else
|
|
group.long (0x280+0x20)++0x07
|
|
line.long 0x00 "DFSDM_FLT3AWHTR,DFSDM Analog Watchdog High Threshold Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " AWHT ,Analog watchdog high threshold"
|
|
bitfld.long 0x00 3. " BKAWH3 ,Break signal 3 assignment to analog watchdog high threshold event" "Not assigned,Assigned"
|
|
bitfld.long 0x00 2. " BKAWH2 ,Break signal 2 assignment to analog watchdog high threshold event" "Not assigned,Assigned"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BKAWH1 ,Break signal 1 assignment to analog watchdog high threshold event" "Not assigned,Assigned"
|
|
bitfld.long 0x00 0. " BKAWH0 ,Break signal 0 assignment to analog watchdog high threshold event" "Not assigned,Assigned"
|
|
line.long 0x04 "DFSDM_FLT3AWLTR,DFSDM analog watchdog low threshold register"
|
|
hexmask.long.word 0x04 16.--31. 1. " AWLT ,Analog watchdog low threshold"
|
|
bitfld.long 0x04 3. " BKAWL3 ,Break signal 3 assignment to analog watchdog low threshold event" "Not assigned,Assigned"
|
|
bitfld.long 0x04 2. " BKAWL2 ,Break signal 2 assignment to analog watchdog low threshold event" "Not assigned,Assigned"
|
|
textline " "
|
|
bitfld.long 0x04 1. " BKAWL1 ,Break signal 1 assignment to analog watchdog low threshold event" "Not assigned,Assigned"
|
|
bitfld.long 0x04 0. " BKAWL0 ,Break signal 0 assignment to analog watchdog low threshold event" "Not assigned,Assigned"
|
|
endif
|
|
rgroup.long (0x280+0x28)++0x03
|
|
line.long 0x00 "DFSDM_FLT3AWSR,DFSDM Analog Watchdog Status Register"
|
|
bitfld.long 0x00 15. " AWHTF[7] ,Analog watchdog high threshold flag 7" "No error,Error"
|
|
bitfld.long 0x00 14. " AWHTF[6] ,Analog watchdog high threshold flag 6" "No error,Error"
|
|
bitfld.long 0x00 13. " AWHTF[5] ,Analog watchdog high threshold flag 5" "No error,Error"
|
|
bitfld.long 0x00 12. " AWHTF[4] ,Analog watchdog high threshold flag 4" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 11. " AWHTF[3] ,Analog watchdog high threshold flag 3" "No error,Error"
|
|
bitfld.long 0x00 10. " AWHTF[2] ,Analog watchdog high threshold flag 2" "No error,Error"
|
|
bitfld.long 0x00 9. " AWHTF[1] ,Analog watchdog high threshold flag 1" "No error,Error"
|
|
bitfld.long 0x00 8. " AWHTF[0] ,Analog watchdog high threshold flag 0" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AWLTF[7] ,Analog watchdog low threshold flag 7" "No error,Error"
|
|
bitfld.long 0x00 6. " AWLTF[6] ,Analog watchdog low threshold flag 6" "No error,Error"
|
|
bitfld.long 0x00 5. " AWLTF[5] ,Analog watchdog low threshold flag 5" "No error,Error"
|
|
bitfld.long 0x00 4. " AWLTF[4] ,Analog watchdog low threshold flag 4" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AWLTF[3] ,Analog watchdog low threshold flag 3" "No error,Error"
|
|
bitfld.long 0x00 2. " AWLTF[2] ,Analog watchdog low threshold flag 2" "No error,Error"
|
|
bitfld.long 0x00 1. " AWLTF[1] ,Analog watchdog low threshold flag 1" "No error,Error"
|
|
bitfld.long 0x00 0. " AWLTF[0] ,Analog watchdog low threshold flag 0" "No error,Error"
|
|
group.long (0x280+0x2C)++0x03
|
|
line.long 0x00 "DFSDM_FLT3AWCFR,DFSDM Analog Watchdog Clear Flag Register"
|
|
eventfld.long 0x00 15. " CLRAWHTF[7] ,Clear the analog watchdog high threshold flag 7" "No effect,Clear"
|
|
eventfld.long 0x00 14. " CLRAWHTF[6] ,Clear the analog watchdog high threshold flag 6" "No effect,Clear"
|
|
eventfld.long 0x00 13. " CLRAWHTF[5] ,Clear the analog watchdog high threshold flag 5" "No effect,Clear"
|
|
eventfld.long 0x00 12. " CLRAWHTF[4] ,Clear the analog watchdog high threshold flag 4" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 11. " CLRAWHTF[3] ,Clear the analog watchdog high threshold flag 3" "No effect,Clear"
|
|
eventfld.long 0x00 10. " CLRAWHTF[2] ,Clear the analog watchdog high threshold flag 2" "No effect,Clear"
|
|
eventfld.long 0x00 9. " CLRAWHTF[1] ,Clear the analog watchdog high threshold flag 1" "No effect,Clear"
|
|
eventfld.long 0x00 8. " CLRAWHTF[0] ,Clear the analog watchdog high threshold flag 0" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CLRAWLTF[7] ,Clear the analog watchdog low threshold flag 7" "No effect,Clear"
|
|
eventfld.long 0x00 6. " CLRAWLTF[6] ,Clear the analog watchdog low threshold flag 6" "No effect,Clear"
|
|
eventfld.long 0x00 5. " CLRAWLTF[5] ,Clear the analog watchdog low threshold flag 5" "No effect,Clear"
|
|
eventfld.long 0x00 4. " CLRAWLTF[4] ,Clear the analog watchdog low threshold flag 4" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 3. " CLRAWLTF[3] ,Clear the analog watchdog low threshold flag 3" "No effect,Clear"
|
|
eventfld.long 0x00 2. " CLRAWLTF[2] ,Clear the analog watchdog low threshold flag 2" "No effect,Clear"
|
|
eventfld.long 0x00 1. " CLRAWLTF[1] ,Clear the analog watchdog low threshold flag 1" "No effect,Clear"
|
|
eventfld.long 0x00 0. " CLRAWLTF[0] ,Clear the analog watchdog low threshold flag 0" "No effect,Clear"
|
|
hgroup.long (0x280+0x30)++0x03
|
|
hide.long 0x00 "DFSDM_FLT3EXMAX,DFSDM Extremes Detector Maximum Register"
|
|
in
|
|
hgroup.long (0x280+0x34)++0x03
|
|
hide.long 0x00 "DFSDM_FLT3EXMIN,DFSDM Extremes Detector Minimum Register"
|
|
in
|
|
rgroup.long (0x280+0x38)++0x03
|
|
line.long 0x00 "DFSDM_FLT3CNVTIMR,DFSDM Conversion Timer Register"
|
|
hexmask.long 0x00 4.--31. 1. " CNVCNT ,28-bit timer counting conversion time t = CNVCNT / fDFSDM_CKIN"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
tree "DCMI (Digital Camera Interface)"
|
|
base ad:0x50050000
|
|
width 8.
|
|
sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x50050000)&0x08))==0x08)
|
|
if (((per.l(ad:0x50050000)&0xC00))==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,DCMI Control Register"
|
|
bitfld.long 0x00 20. " OELS ,Odd/even line select (line select start)" "Odd,Even"
|
|
bitfld.long 0x00 19. " LSM ,Line select mode" "All lines,1 out of 2"
|
|
bitfld.long 0x00 18. " OEBS ,Odd/even byte select (byte select start)" "Odd,Even"
|
|
bitfld.long 0x00 16.--17. " BSM ,Byte select mode" "All data,Every other,1B out of 4B,2B out of 4B"
|
|
newline
|
|
bitfld.long 0x00 14. " ENABLE ,DCMI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EDM ,Extended data mode (data per pixel clock)" "8-bit,10-bit,12-bit,14-bit"
|
|
bitfld.long 0x00 8.--9. " FCRC ,Frame capture rate control" "Capture all frames,Capture every alternate frame,Capture one frame in 4 frames,?..."
|
|
bitfld.long 0x00 7. " VSPOL ,Vertical synchronization polarity" "Active low,Active high"
|
|
newline
|
|
bitfld.long 0x00 6. " HSPOL ,Horizontal synchronization polarity" "Active low,Active high"
|
|
bitfld.long 0x00 5. " PCKPOL ,Pixel clock polarity" "Falling edge,Rising edge"
|
|
newline
|
|
bitfld.long 0x00 3. " JPEG ,JPEG format" "Uncompressed video,Compressed video"
|
|
newline
|
|
sif (!cpuis("STM32F76*")&&!cpuis("STM32F77*"))
|
|
bitfld.long 0x00 2. " CROP ,Crop feature" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " CM ,Capture mode" "Continuous grab,Snapshot"
|
|
bitfld.long 0x00 0. " CAPTURE ,Capture enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,DCMI Control Register"
|
|
bitfld.long 0x00 20. " OELS ,Odd/even line select (line select start)" "Odd,Even"
|
|
bitfld.long 0x00 19. " LSM ,Line select mode" "All lines,1 out of 2"
|
|
bitfld.long 0x00 18. " OEBS ,Odd/even byte select (byte select start)" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 14. " ENABLE ,DCMI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EDM ,Extended data mode (data per pixel clock)" "8-bit,10-bit,12-bit,14-bit"
|
|
bitfld.long 0x00 8.--9. " FCRC ,Frame capture rate control" "Capture all frames,Capture every alternate frame,Capture one frame in 4 frames,?..."
|
|
bitfld.long 0x00 7. " VSPOL ,Vertical synchronization polarity" "Active low,Active high"
|
|
newline
|
|
bitfld.long 0x00 6. " HSPOL ,Horizontal synchronization polarity" "Active low,Active high"
|
|
bitfld.long 0x00 5. " PCKPOL ,Pixel clock polarity" "Falling edge,Rising edge"
|
|
newline
|
|
bitfld.long 0x00 3. " JPEG ,JPEG format" "Uncompressed video,Compressed video"
|
|
newline
|
|
sif (!cpuis("STM32F76*")&&!cpuis("STM32F77*"))
|
|
bitfld.long 0x00 2. " CROP ,Crop feature" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " CM ,Capture mode" "Continuous grab,Snapshot"
|
|
bitfld.long 0x00 0. " CAPTURE ,Capture enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x50050000)&0xC00))==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,DCMI Control Register"
|
|
bitfld.long 0x00 20. " OELS ,Odd/even line select (line select start)" "Odd,Even"
|
|
bitfld.long 0x00 19. " LSM ,Line select mode" "All lines,1 out of 2"
|
|
bitfld.long 0x00 18. " OEBS ,Odd/even byte select (byte select start)" "Odd,Even"
|
|
bitfld.long 0x00 16.--17. " BSM ,Byte select mode" "All data,Every other,1B out of 4B,2B out of 4B"
|
|
newline
|
|
bitfld.long 0x00 14. " ENABLE ,DCMI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EDM ,Extended data mode (data per pixel clock)" "8-bit,10-bit,12-bit,14-bit"
|
|
bitfld.long 0x00 8.--9. " FCRC ,Frame capture rate control" "Capture all frames,Capture every alternate frame,Capture one frame in 4 frames,?..."
|
|
bitfld.long 0x00 7. " VSPOL ,Vertical synchronization polarity" "Active low,Active high"
|
|
newline
|
|
bitfld.long 0x00 6. " HSPOL ,Horizontal synchronization polarity" "Active low,Active high"
|
|
bitfld.long 0x00 5. " PCKPOL ,Pixel clock polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 4. " ESS ,Embedded synchronization select" "Hardware,Embedded"
|
|
newline
|
|
bitfld.long 0x00 3. " JPEG ,JPEG format" "Uncompressed video,Compressed video"
|
|
newline
|
|
sif (!cpuis("STM32F76*")&&!cpuis("STM32F77*"))
|
|
bitfld.long 0x00 2. " CROP ,Crop feature" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " CM ,Capture mode" "Continuous grab,Snapshot"
|
|
bitfld.long 0x00 0. " CAPTURE ,Capture enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,DCMI Control Register"
|
|
bitfld.long 0x00 20. " OELS ,Odd/even line select (line select start)" "Odd,Even"
|
|
bitfld.long 0x00 19. " LSM ,Line select mode" "All lines,1 out of 2"
|
|
bitfld.long 0x00 18. " OEBS ,Odd/even byte select (byte select start)" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 14. " ENABLE ,DCMI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EDM ,Extended data mode (data per pixel clock)" "8-bit,10-bit,12-bit,14-bit"
|
|
bitfld.long 0x00 8.--9. " FCRC ,Frame capture rate control" "Capture all frames,Capture every alternate frame,Capture one frame in 4 frames,?..."
|
|
newline
|
|
bitfld.long 0x00 7. " VSPOL ,Vertical synchronization polarity" "Active low,Active high"
|
|
bitfld.long 0x00 6. " HSPOL ,Horizontal synchronization polarity" "Active low,Active high"
|
|
bitfld.long 0x00 5. " PCKPOL ,Pixel clock polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 4. " ESS ,Embedded synchronization select" "Hardware,Embedded"
|
|
newline
|
|
bitfld.long 0x00 3. " JPEG ,JPEG format" "Uncompressed video,Compressed video"
|
|
newline
|
|
sif (!cpuis("STM32F76*")&&!cpuis("STM32F77*"))
|
|
bitfld.long 0x00 2. " CROP ,Crop feature" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " CM ,Capture mode" "Continuous grab,Snapshot"
|
|
bitfld.long 0x00 0. " CAPTURE ,Capture enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x50050000)&0x08))==0x08)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,DCMI Control Register"
|
|
bitfld.long 0x00 14. " ENABLE ,DCMI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EDM ,Extended data mode (data per pixel clock)" "8-bit,10-bit,12-bit,14-bit"
|
|
bitfld.long 0x00 8.--9. " FCRC ,Frame capture rate control" "Capture all frames,Capture every alternate frame,Capture one frame in 4 frames,?..."
|
|
newline
|
|
bitfld.long 0x00 7. " VSPOL ,Vertical synchronization polarity" "Active low,Active high"
|
|
bitfld.long 0x00 6. " HSPOL ,Horizontal synchronization polarity" "Active low,Active high"
|
|
bitfld.long 0x00 5. " PCKPOL ,Pixel clock polarity" "Falling edge,Rising edge"
|
|
newline
|
|
bitfld.long 0x00 3. " JPEG ,JPEG format" "Uncompressed video,Compressed video"
|
|
newline
|
|
bitfld.long 0x00 2. " CROP ,Crop feature" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM ,Capture mode" "Continuous grab,Snapshot"
|
|
newline
|
|
bitfld.long 0x00 0. " CAPTURE ,Capture enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,DCMI Control Register"
|
|
bitfld.long 0x00 14. " ENABLE ,DCMI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EDM ,Extended data mode (data per pixel clock)" "8-bit,10-bit,12-bit,14-bit"
|
|
bitfld.long 0x00 8.--9. " FCRC ,Frame capture rate control" "Capture all frames,Capture every alternate frame,Capture one frame in 4 frames,?..."
|
|
newline
|
|
bitfld.long 0x00 7. " VSPOL ,Vertical synchronization polarity" "Active low,Active high"
|
|
bitfld.long 0x00 6. " HSPOL ,Horizontal synchronization polarity" "Active low,Active high"
|
|
bitfld.long 0x00 5. " PCKPOL ,Pixel clock polarity" "Falling edge,Rising edge"
|
|
newline
|
|
bitfld.long 0x00 4. " ESS ,Embedded synchronization select" "HSYNC/VSYNC signals,Synchronization codes"
|
|
bitfld.long 0x00 3. " JPEG ,JPEG format" "Uncompressed video,Compressed video"
|
|
newline
|
|
bitfld.long 0x00 2. " CROP ,Crop feature" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CM ,Capture mode" "Continuous grab,Snapshot"
|
|
bitfld.long 0x00 0. " CAPTURE ,Capture enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SR,DCMI Status Register"
|
|
bitfld.long 0x00 2. " FNE ,FIFO not empty" "Empty,Not empty"
|
|
bitfld.long 0x00 1. " VSYNC ,VSYNC pin state" "Active frame,Synchronization between frames"
|
|
newline
|
|
bitfld.long 0x00 0. " HSYNC ,HSYNC pin state" "Active line,Synchronization between lines"
|
|
newline
|
|
sif (cpuis("STM32F4*")||cpuis("STM32F7*")||cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x50050000)&0x10))==0x10)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "RIS,DCMI Raw Interrupt Status Register"
|
|
bitfld.long 0x00 4. " LINE_RIS ,Line raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " VSYNC_RIS ,VSYNC raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " ERR_RIS ,Synchronization error raw interrupt status" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 1. " OVR_RIS ,Overrun raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " FRAME_RIS ,Capture complete raw interrupt status" "No interrupt,Interrupt"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "RIS,DCMI Raw Interrupt Status Register"
|
|
bitfld.long 0x00 4. " LINE_RIS ,Line raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " VSYNC_RIS ,VSYNC raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " OVR_RIS ,Overrun raw interrupt status" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 0. " FRAME_RIS ,Capture complete raw interrupt status" "No interrupt,Interrupt"
|
|
endif
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "RIS,DCMI Raw Interrupt Status Register"
|
|
bitfld.long 0x00 4. " LINE_RIS ,Line raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " VSYNC_RIS ,VSYNC raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " ERR_RIS ,Synchronization error raw interrupt status" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 1. " OVR_RIS ,Overrun raw interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " FRAME_RIS ,Capture complete raw interrupt status" "No interrupt,Interrupt"
|
|
endif
|
|
sif (cpuis("STM32F4*")||cpuis("STM32F7*")||cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x50050000)&0x10))==0x10)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IER,DCMI Interrupt Enable Register"
|
|
bitfld.long 0x00 4. " LINE_IE ,Line interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " VSYNC_IE ,VSYNC interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ERR_IE ,Synchronization error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " OVR_IE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FRAME_IE ,Capture complete interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IER,DCMI Interrupt Enable Register"
|
|
bitfld.long 0x00 4. " LINE_IE ,Line interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " VSYNC_IE ,VSYNC interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " OVR_IE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " FRAME_IE ,Capture complete interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IER,DCMI Interrupt Enable Register"
|
|
bitfld.long 0x00 4. " LINE_IE ,Line interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " VSYNC_IE ,VSYNC interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ERR_IE ,Synchronization error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " OVR_IE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FRAME_IE ,Capture complete interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("STM32F4*")||cpuis("STM32F7*")||cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x50050000)&0x10))==0x10)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "MIS,DCMI Masked Interrupt Status Register"
|
|
bitfld.long 0x00 4. " LINE_MIS ,Line masked interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " VSYNC_MIS ,VSYNC masked interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " ERR_MIS ,Synchronization error masked interrupt status" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 1. " OVR_MIS ,Overrun masked interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " FRAME_MIS ,Capture complete masked interrupt status" "No interrupt,Interrupt"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "MIS,DCMI Masked Interrupt Status Register"
|
|
bitfld.long 0x00 4. " LINE_MIS ,Line masked interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " VSYNC_MIS ,VSYNC masked interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " OVR_MIS ,Overrun masked interrupt status" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 0. " FRAME_MIS ,Capture complete masked interrupt status" "No interrupt,Interrupt"
|
|
endif
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "MIS,DCMI Masked Interrupt Status Register"
|
|
bitfld.long 0x00 4. " LINE_MIS ,Line masked interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " VSYNC_MIS ,VSYNC masked interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " ERR_MIS ,Synchronization error masked interrupt status" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 1. " OVR_MIS ,Overrun masked interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " FRAME_MIS ,Capture complete masked interrupt status" "No interrupt,Interrupt"
|
|
endif
|
|
sif (cpuis("STM32F4*")||cpuis("STM32F7*")||cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x50050000)&0x10))==0x10)
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "ICR,DCMI Interrupt Clear Register"
|
|
bitfld.long 0x00 4. " LINE_ISC ,Line interrupt status clear" "No effect,Clear"
|
|
bitfld.long 0x00 3. " VSYNC_ISC ,VSYNC interrupt status clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " ERR_ISC ,Synchronization error interrupt status clear" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 1. " OVR_ISC ,Overrun interrupt status clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " FRAME_ISC ,Capture complete interrupt status clear" "No effect,Clear"
|
|
else
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "ICR,DCMI Interrupt Clear Register"
|
|
bitfld.long 0x00 4. " LINE_ISC ,Line interrupt status clear" "No effect,Clear"
|
|
bitfld.long 0x00 3. " VSYNC_ISC ,VSYNC interrupt status clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " OVR_ISC ,Overrun interrupt status clear" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 0. " FRAME_ISC ,Capture complete interrupt status clear" "No effect,Clear"
|
|
endif
|
|
else
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "ICR,DCMI Interrupt Clear Register"
|
|
bitfld.long 0x00 4. " LINE_ISC ,Line interrupt status clear" "No effect,Clear"
|
|
bitfld.long 0x00 3. " VSYNC_ISC ,VSYNC interrupt status clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " ERR_ISC ,Synchronization error interrupt status clear" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 1. " OVR_ISC ,Overrun interrupt status clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " FRAME_ISC ,Capture complete interrupt status clear" "No effect,Clear"
|
|
endif
|
|
newline
|
|
group.long 0x18++0x0F
|
|
line.long 0x00 "ESCR,DCMI Embedded Synchronization Code Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " FEC ,Frame end delimiter code"
|
|
hexmask.long.byte 0x00 16.--23. 1. " LEC ,Line end delimiter code"
|
|
hexmask.long.byte 0x00 8.--15. 1. " LSC ,Line start delimiter code"
|
|
hexmask.long.byte 0x00 0.--7. 1. " FSC ,Frame start delimiter code"
|
|
line.long 0x04 "ESUR,DCMI Embedded Synchronization Unmask Register"
|
|
bitfld.long 0x04 31. " FEU[7] ,Frame end delimiter unmask [7]" "Masked,Unmasked"
|
|
bitfld.long 0x04 30. " [6] ,Frame end delimiter unmask [6]" "Masked,Unmasked"
|
|
bitfld.long 0x04 29. " [5] ,Frame end delimiter unmask [5]" "Masked,Unmasked"
|
|
bitfld.long 0x04 28. " [4] ,Frame end delimiter unmask [4]" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x04 27. " [3] ,Frame end delimiter unmask [3]" "Masked,Unmasked"
|
|
bitfld.long 0x04 26. " [2] ,Frame end delimiter unmask [2]" "Masked,Unmasked"
|
|
bitfld.long 0x04 25. " [1] ,Frame end delimiter unmask [1]" "Masked,Unmasked"
|
|
bitfld.long 0x04 24. " [0] ,Frame end delimiter unmask [0]" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x04 23. " LEU[7] ,Line end delimiter unmask [7]" "Masked,Unmasked"
|
|
bitfld.long 0x04 22. " [6] ,Line end delimiter unmask [6]" "Masked,Unmasked"
|
|
bitfld.long 0x04 21. " [5] ,Line end delimiter unmask [5]" "Masked,Unmasked"
|
|
bitfld.long 0x04 20. " [4] ,Line end delimiter unmask [4]" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x04 19. " [3] ,Line end delimiter unmask [3]" "Masked,Unmasked"
|
|
bitfld.long 0x04 18. " [2] ,Line end delimiter unmask [2]" "Masked,Unmasked"
|
|
bitfld.long 0x04 17. " [1] ,Line end delimiter unmask [1]" "Masked,Unmasked"
|
|
bitfld.long 0x04 16. " [0] ,Line end delimiter unmask [0]" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x04 15. " LSU[7] ,Line start delimiter unmask [7]" "Masked,Unmasked"
|
|
bitfld.long 0x04 14. " [6] ,Line start delimiter unmask [6]" "Masked,Unmasked"
|
|
bitfld.long 0x04 13. " [5] ,Line start delimiter unmask [5]" "Masked,Unmasked"
|
|
bitfld.long 0x04 12. " [4] ,Line start delimiter unmask [4]" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x04 11. " [3] ,Line start delimiter unmask [3]" "Masked,Unmasked"
|
|
bitfld.long 0x04 10. " [2] ,Line start delimiter unmask [2]" "Masked,Unmasked"
|
|
bitfld.long 0x04 9. " [1] ,Line start delimiter unmask [1]" "Masked,Unmasked"
|
|
bitfld.long 0x04 8. " [0] ,Line start delimiter unmask [0]" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x04 7. " FSU[7] ,Frame start delimiter unmask [7]" "Masked,Unmasked"
|
|
bitfld.long 0x04 6. " [6] ,Frame start delimiter unmask [6]" "Masked,Unmasked"
|
|
bitfld.long 0x04 5. " [5] ,Frame start delimiter unmask [5]" "Masked,Unmasked"
|
|
bitfld.long 0x04 4. " [4] ,Frame start delimiter unmask [4]" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,Frame start delimiter unmask [3]" "Masked,Unmasked"
|
|
bitfld.long 0x04 2. " [2] ,Frame start delimiter unmask [2]" "Masked,Unmasked"
|
|
bitfld.long 0x04 1. " [1] ,Frame start delimiter unmask [1]" "Masked,Unmasked"
|
|
bitfld.long 0x04 0. " [0] ,Frame start delimiter unmask [0]" "Masked,Unmasked"
|
|
line.long 0x08 "CWSTRT,DCMI Crop Window Start Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " VST ,Vertical start line count"
|
|
hexmask.long.word 0x08 0.--13. 1. " HOFFCNT ,Horizontal offset count"
|
|
line.long 0x0C "CWSIZE,DCMI Crop Window Size Register"
|
|
hexmask.long.word 0x0C 16.--29. 1. " VLINE ,Vertical line count"
|
|
hexmask.long.word 0x0C 0.--13. 1. " CAPCNT ,Capture count"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "DR,DCMI Data Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BYTE3 ,Data byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BYTE2 ,Data byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BYTE1 ,Data byte 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BYTE0 ,Data byte 0"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F746*")||cpuis("STM32F756*")||cpuis("STM32F77*")||cpuis("STM32F767V*")||cpuis("STM32F769V*")||cpuis("STM32F767Z*")||cpuis("STM32F769Z*")||cpuis("STM32F769A*")||cpuis("STM32F767I*")||cpuis("STM32F769I*")||cpuis("STM32F767B*")||cpuis("STM32F769B*")||cpuis("STM32F767N*")||cpuis("STM32F769N*")||cpuis("STM32F750*"))
|
|
tree "LTDC (LCD-TFT Controller)"
|
|
base ad:0x40016800
|
|
width 7.
|
|
group.long 0x08++0x13
|
|
line.long 0x00 "SSCR,LTDC Synchronization Size Configuration Register"
|
|
hexmask.long.word 0x00 16.--27. 1. " HSW ,Horizontal synchronization width value"
|
|
hexmask.long.word 0x00 0.--10. 1. " VSH ,Vertical synchronization height value"
|
|
line.long 0x04 "BPCR,LTDC Back Porch Configuration Register"
|
|
hexmask.long.word 0x04 16.--27. 1. " AHBP ,Accumulated horizontal back porch value"
|
|
hexmask.long.word 0x04 0.--10. 1. " AVBP ,Accumulated vertical back porch value"
|
|
line.long 0x08 "AWCR,LTDC Active Width Configuration Register"
|
|
hexmask.long.word 0x08 16.--27. 1. " AAW ,Accumulated active width value"
|
|
hexmask.long.word 0x08 0.--10. 1. " AAH ,Accumulated active height value"
|
|
line.long 0x0C "TWCR,LTDC Total Width Configuration Register"
|
|
hexmask.long.word 0x0C 16.--27. 1. " TOTALW ,Total width value"
|
|
hexmask.long.word 0x0C 0.--10. 1. " TOTALH ,Total height value"
|
|
line.long 0x10 "GCR,LTDC Global Control Register"
|
|
bitfld.long 0x10 31. " HSPOL ,Horizontal synchronization polarity" "Active low,Active high"
|
|
bitfld.long 0x10 30. " VSPOL ,Vertical synchronization polarity" "Active low,Active high"
|
|
bitfld.long 0x10 29. " DEPOL ,Data enable polarity" "Active low,Active high"
|
|
bitfld.long 0x10 28. " PCPOL ,Pixel clock polarity" "Active low,Active high"
|
|
bitfld.long 0x10 16. " DEN ,Dither enable" "Disabled,Enabled"
|
|
rbitfld.long 0x10 12.--14. " DRW ,Dither red width" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x10 8.--10. " DGW ,Dither green width" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x10 4.--6. " DBW ,Dither blue width" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 0. " LTDCEN ,LCD-TFT controller enable" "Disabled,Enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SRCR,LTDC Shadow Reload Configuration Register"
|
|
bitfld.long 0x00 1. " VBR ,Vertical blanking reload" "No effect,Reloaded"
|
|
bitfld.long 0x00 0. " IMR ,Immediate reload" "No effect,Reloaded"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "BCCR,LTDC Background Color Configuration Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BCRED ,Background color red value"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BCGREEN ,Background color green value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BCBLUE ,Background color blue value"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "IER,LTDC Interrupt Enable Register"
|
|
bitfld.long 0x00 3. " RRIE ,Register reload interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TERRIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FUIE ,FIFO under-run interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LIE ,Line interrupt enable" "Disabled,Enabled"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "ISR,LTDC Interrupt Status Register"
|
|
bitfld.long 0x00 3. " RRIF ,Register reload interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " TERRIF ,Transfer error interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " FUIF ,FIFO under-run interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " LIF ,Line interrupt flag" "No interrupt,Interrupt"
|
|
wgroup.long 0x3C++0x03
|
|
line.long 0x00 "ICR,LTDC Interrupt Clear Register"
|
|
bitfld.long 0x00 3. " CRRIF ,Clears register reload interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CTERRIF ,Clears the transfer error interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 1. " CFUIF ,Clears the FIFO under-run interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CLIF ,Clears the line interrupt flag" "No effect,Clear"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "LIPCR,LTDC Line Interrupt Position Configuration Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " LIPOS ,Line interrupt position value"
|
|
rgroup.long 0x44++0x07
|
|
line.long 0x00 "CPSR,LTDC Current Position Status Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CXPOS ,Current X position value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CYPOS ,Current Y position value"
|
|
line.long 0x04 "CDSR,LTDC Current Display Status Register"
|
|
bitfld.long 0x04 3. " HSYNCS ,Horizontal synchronization display status" "Low,High"
|
|
bitfld.long 0x04 2. " VSYNCS ,Vertical synchronization display status" "Low,High"
|
|
bitfld.long 0x04 1. " HDES ,Horizontal data enable display status" "Low,High"
|
|
bitfld.long 0x04 0. " VDES ,Vertical data enable display status" "Low,High"
|
|
width 10.
|
|
tree "Layer 1 Registers"
|
|
group.long (0x84+0x0)++0x1F
|
|
line.long 0x00 "L1CR,LTDC Layer 1 Control Register"
|
|
bitfld.long 0x00 4. " CLUTEN ,Color look-up table enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " COLKEN ,Color keying enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LEN ,Layer enable" "Disabled,Enabled"
|
|
line.long 0x04 "L1WHPCR,LTDC Layer 1 Window Horizontal Position Configuration Register"
|
|
hexmask.long.word 0x04 16.--27. 1. " WHSPPOS ,Window horizontal stop position value"
|
|
hexmask.long.word 0x04 0.--11. 1. " WHSTPOS ,Window horizontal start position value"
|
|
line.long 0x08 "L1WVPCR,LTDC Layer 1 Window Vertical Position Configuration Register"
|
|
hexmask.long.word 0x08 16.--26. 1. " WVSPPOS ,Window vertical stop position value"
|
|
hexmask.long.word 0x08 0.--10. 1. " WVSTPOS ,Window vertical start position value"
|
|
line.long 0x0C "L1CKCR,LTDC Layer 1 Color Keying Configuration Register"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " CKRED ,Color key red value"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " CKGREEN ,Color key green value"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " CKBLUE ,Color key blue value"
|
|
line.long 0x10 "L1PFCR,LTDC Layer 1 Pixel Format Configuration Register"
|
|
bitfld.long 0x10 0.--2. " PF ,Pixel format" "ARGB8888,RGB888,RGB565,ARGB1555,ARGB4444,L8,AL44,AL88"
|
|
line.long 0x14 "L1CACR,LTDC Layer 1 Constant Alpha Configuration Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " CONSTA ,Constant alpha value"
|
|
line.long 0x18 "L1DCCR,LTDC Layer 1 Default Color Configuration Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " DCALPHA ,Default color alpha value"
|
|
hexmask.long.byte 0x18 16.--23. 1. " DCRED ,Default color red value"
|
|
hexmask.long.byte 0x18 8.--15. 1. " DCGREEN ,Default color green value"
|
|
hexmask.long.byte 0x18 0.--7. 1. " DCBLUE ,Default color blue value"
|
|
line.long 0x1C "L1BFCR,LTDC Layer 1 Blending Factors Configuration Register"
|
|
bitfld.long 0x1C 8.--10. " BF1 ,Blending factor 1" ",,,,Constant alpha,,Pixel alpha x constant alpha,?..."
|
|
bitfld.long 0x1C 0.--2. " BF2 ,Blending factor 2" ",,,,,Constant alpha,,Pixel alpha x constant alpha"
|
|
group.long (0xAC+0x0)++0x0B
|
|
line.long 0x00 "L1CFBAR,LTDC Layer 1 Color Frame Buffer Address Register"
|
|
line.long 0x04 "L1CFBLR,LTDC Layer 1 Color Frame Buffer Length Register"
|
|
hexmask.long.word 0x04 16.--28. 1. " CFBP ,Color frame buffer pitch in bytes"
|
|
hexmask.long.word 0x04 0.--12. 1. " CFBLL ,Color frame buffer line length value"
|
|
line.long 0x08 "L1CFBLNR,LTDC Layer 1 Color Frame Buffer Line Number Register"
|
|
hexmask.long.word 0x08 0.--10. 1. " CFBLNBR ,Frame buffer line number"
|
|
if (((per.l(ad:0x40016800+0x84+0x0+0x10))&0x07)>=0x05)
|
|
wgroup.long (0xC4+0x0)++0x03
|
|
line.long 0x00 "L1CLUTWR,LTDC Layer 1 CLUT Write Register"
|
|
hexmask.long.byte 0x00 24.--31. 0x01 " CLUTADD ,CLUT address"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED ,Red value"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN ,Green value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE ,Blue value"
|
|
else
|
|
hgroup.long (0xC4+0x0)++0x03
|
|
hide.long 0x00 "L1CLUTWR,LTDC Layer 1 CLUT Write Register"
|
|
endif
|
|
tree.end
|
|
tree "Layer 2 Registers"
|
|
group.long (0x84+0x80)++0x1F
|
|
line.long 0x00 "L2CR,LTDC Layer 2 Control Register"
|
|
bitfld.long 0x00 4. " CLUTEN ,Color look-up table enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " COLKEN ,Color keying enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LEN ,Layer enable" "Disabled,Enabled"
|
|
line.long 0x04 "L2WHPCR,LTDC Layer 2 Window Horizontal Position Configuration Register"
|
|
hexmask.long.word 0x04 16.--27. 1. " WHSPPOS ,Window horizontal stop position value"
|
|
hexmask.long.word 0x04 0.--11. 1. " WHSTPOS ,Window horizontal start position value"
|
|
line.long 0x08 "L2WVPCR,LTDC Layer 2 Window Vertical Position Configuration Register"
|
|
hexmask.long.word 0x08 16.--26. 1. " WVSPPOS ,Window vertical stop position value"
|
|
hexmask.long.word 0x08 0.--10. 1. " WVSTPOS ,Window vertical start position value"
|
|
line.long 0x0C "L2CKCR,LTDC Layer 2 Color Keying Configuration Register"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " CKRED ,Color key red value"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " CKGREEN ,Color key green value"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " CKBLUE ,Color key blue value"
|
|
line.long 0x10 "L2PFCR,LTDC Layer 2 Pixel Format Configuration Register"
|
|
bitfld.long 0x10 0.--2. " PF ,Pixel format" "ARGB8888,RGB888,RGB565,ARGB1555,ARGB4444,L8,AL44,AL88"
|
|
line.long 0x14 "L2CACR,LTDC Layer 2 Constant Alpha Configuration Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " CONSTA ,Constant alpha value"
|
|
line.long 0x18 "L2DCCR,LTDC Layer 2 Default Color Configuration Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " DCALPHA ,Default color alpha value"
|
|
hexmask.long.byte 0x18 16.--23. 1. " DCRED ,Default color red value"
|
|
hexmask.long.byte 0x18 8.--15. 1. " DCGREEN ,Default color green value"
|
|
hexmask.long.byte 0x18 0.--7. 1. " DCBLUE ,Default color blue value"
|
|
line.long 0x1C "L2BFCR,LTDC Layer 2 Blending Factors Configuration Register"
|
|
bitfld.long 0x1C 8.--10. " BF1 ,Blending factor 1" ",,,,Constant alpha,,Pixel alpha x constant alpha,?..."
|
|
bitfld.long 0x1C 0.--2. " BF2 ,Blending factor 2" ",,,,,Constant alpha,,Pixel alpha x constant alpha"
|
|
group.long (0xAC+0x80)++0x0B
|
|
line.long 0x00 "L2CFBAR,LTDC Layer 2 Color Frame Buffer Address Register"
|
|
line.long 0x04 "L2CFBLR,LTDC Layer 2 Color Frame Buffer Length Register"
|
|
hexmask.long.word 0x04 16.--28. 1. " CFBP ,Color frame buffer pitch in bytes"
|
|
hexmask.long.word 0x04 0.--12. 1. " CFBLL ,Color frame buffer line length value"
|
|
line.long 0x08 "L2CFBLNR,LTDC Layer 2 Color Frame Buffer Line Number Register"
|
|
hexmask.long.word 0x08 0.--10. 1. " CFBLNBR ,Frame buffer line number"
|
|
if (((per.l(ad:0x40016800+0x84+0x80+0x10))&0x07)>=0x05)
|
|
wgroup.long (0xC4+0x80)++0x03
|
|
line.long 0x00 "L2CLUTWR,LTDC Layer 2 CLUT Write Register"
|
|
hexmask.long.byte 0x00 24.--31. 0x01 " CLUTADD ,CLUT address"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RED ,Red value"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GREEN ,Green value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BLUE ,Blue value"
|
|
else
|
|
hgroup.long (0xC4+0x80)++0x03
|
|
hide.long 0x00 "L2CLUTWR,LTDC Layer 2 CLUT Write Register"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
tree "DSIHOST (DSI Host)"
|
|
base ad:0x40016C00
|
|
width 14.
|
|
tree "DSI Host registers"
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DSI_VR,DSI Host Version Register"
|
|
group.long 0x04++0x17
|
|
line.long 0x00 "DSI_CR,DSI Host Control Register"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
line.long 0x04 "DSI_CCR,DSI HOST Clock Control Register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " TOCKDIV ,Timeout clock division"
|
|
hexmask.long.byte 0x04 0.--7. 1. " TXECKDIV ,TX Escape clock division"
|
|
line.long 0x08 "DSI_LVCIDR,DSI Host LTDC VCID Register"
|
|
bitfld.long 0x08 0.--1. " VCID ,Virtual channel ID" "0,1,2,3"
|
|
line.long 0x0C "DSI_LCOLCR,DSI Host LTDC Color Coding Register"
|
|
bitfld.long 0x0C 8. " LPE ,Loosely packet enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0.--3. " COLC ,Color coding" "16b 1,16b 2,16b 3,18b 1,18b 2,24b,?..."
|
|
line.long 0x10 "DSI_LPCR,DSI Host LTDC Polarity Configuration Register"
|
|
bitfld.long 0x10 2. " HSP ,HSYNC polarity" "High,Low"
|
|
bitfld.long 0x10 1. " VSP ,VSYNC polarity" "High,Low"
|
|
bitfld.long 0x10 0. " DEP ,Data enable polarity" "High,Low"
|
|
line.long 0x14 "DSI_LPMCR,DSI Host Low-Power mode Configuration Register"
|
|
hexmask.long.byte 0x14 16.--23. 1. " LPSIZE ,Largest packet size"
|
|
hexmask.long.byte 0x14 0.--7. 1. " VLPSIZE ,VACT Largest packet size"
|
|
group.long 0x2C++0x47
|
|
line.long 0x00 "DSI_PCR,DSI Host Protocol Configuration Register"
|
|
bitfld.long 0x00 4. " CRCRXE ,CRC reception enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ECCRXE ,ECC reception enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BTAE ,Bus turn around enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ETRXE ,EoTp reception enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ETTXE ,EoTp transmission enable" "Disabled,Enabled"
|
|
line.long 0x04 "DSI_GVCIDR,DSI Host Generic VCID Register"
|
|
bitfld.long 0x04 0.--1. " VCID ,Virtual Channel ID" "0,1,2,3"
|
|
line.long 0x08 "DSI_MCR,DSI Host mode Configuration Register"
|
|
bitfld.long 0x08 0. " CMDM ,Command mode" "Video,Command"
|
|
line.long 0x0C "DSI_VMCR,DSI Host Video mode Configuration Register"
|
|
bitfld.long 0x0C 24. " PGO ,Pattern generator orientation" "Vertical,Horizontal"
|
|
bitfld.long 0x0C 20. " PGM ,Pattern generator mode" "Color,Ber"
|
|
bitfld.long 0x0C 16. " PGE ,Pattern generator enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " LPCE ,Power command enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " FBTAAE ,Frame Bus-Turn-Around acknowledge enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " LPHFPE ,Low-Power horizontal Front-Porch enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 12. " LPHBPE ,Low-Power horizontal Back-Porch Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 11. " LPVAE ,Low-power vertical active enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " LPVFPE ,Low-power vertical Front-Porch enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " LPVBPE ,Low-power vertical Back-Porch enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " LPVSAE ,Low-Power vertical sync active enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0.--1. " VMT ,Video mode type" "Non-burst pulses,Non-burst events,Burst,Burst"
|
|
line.long 0x10 "DSI_VPCR,DSI Host Video Packet Configuration Register"
|
|
hexmask.long.word 0x10 0.--13. 1. " VPSIZE ,Video packet size"
|
|
line.long 0x14 "DSI_VCCR,DSI Host Video Chunks Configuration Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " NUMC ,Number of chunks"
|
|
line.long 0x18 "DSI_VNPCR,DSI Host Video Null Packet Configuration Register"
|
|
hexmask.long.word 0x18 0.--12. 1. " NPSIZE ,Null packet size"
|
|
line.long 0x1C "DSI_VHSACR,DSI Host Video HSA Configuration Register"
|
|
hexmask.long.word 0x1C 0.--11. 1. " HSA ,Horizontal synchronism active duration"
|
|
line.long 0x20 "DSI_VHBPCR,DSI Host Video HBP Configuration Register"
|
|
hexmask.long.word 0x20 0.--11. 1. " HBP ,Horizontal Back-Porch duration"
|
|
line.long 0x24 "DSI_VLCR,DSI Host Video Line Configuration Register"
|
|
hexmask.long.word 0x24 0.--14. 1. " HLINE ,Horizontal line duration"
|
|
line.long 0x28 "DSI_VVSACR,DSI Host Video VSA Configuration Register"
|
|
hexmask.long.word 0x28 0.--9. 1. " VSA ,Vertical synchronism active duration"
|
|
line.long 0x2C "DSI_VVBPCR,DSI Host Video VBP Configuration Register"
|
|
hexmask.long.word 0x2C 0.--9. 1. " VBP ,Vertical Back-Porch duration"
|
|
line.long 0x30 "SI_VVFPCR,DSI Host Video VFP Configuration Register"
|
|
hexmask.long.word 0x30 0.--9. 1. " VFP ,Vertical Front-Porch duration"
|
|
line.long 0x34 "DSI_VVACR,DSI Host Video VA Configuration Register"
|
|
hexmask.long.word 0x34 0.--13. 1. " VA ,Vertical active duration"
|
|
line.long 0x38 "DSI_LCCR,DSI Host LTDC Command Configuration Register"
|
|
hexmask.long.word 0x38 0.--15. 1. " CMDSIZE ,Command size"
|
|
line.long 0x3C "DSI_CMCR,DSI Host Command mode Configuration Register"
|
|
bitfld.long 0x3C 24. " MRDPS ,Maximum read packet size" "High-speed,Low-power"
|
|
bitfld.long 0x3C 19. " DLWTX ,DCS long write transmission" "High-speed,Low-power"
|
|
bitfld.long 0x3C 18. " DSR0TX ,DCS short read zero parameter transmission" "High-speed,Low-power"
|
|
textline " "
|
|
bitfld.long 0x3C 17. " DSW1TX ,DCS short read one parameter transmission" "High-speed,Low-power"
|
|
bitfld.long 0x3C 16. " DSW0TX ,DCS short write zero parameter transmission" "High-speed,Low-power"
|
|
bitfld.long 0x3C 14. " GLWTX ,Generic long write transmission" "High-speed,Low-power"
|
|
textline " "
|
|
bitfld.long 0x3C 13. " GSR2TX ,Generic short read two parameters transmission" "High-speed,Low-power"
|
|
bitfld.long 0x3C 12. " GSR1TX ,Generic short read one parameters transmission" "High-speed,Low-power"
|
|
bitfld.long 0x3C 11. " GSR0TX ,Generic short read zero parameters transmission" "High-speed,Low-power"
|
|
textline " "
|
|
bitfld.long 0x3C 10. " GSW2TX ,Generic short write two parameters transmission" "High-speed,Low-power"
|
|
bitfld.long 0x3C 9. " GSW1TX ,Generic short write one parameters transmission" "High-speed,Low-power"
|
|
bitfld.long 0x3C 8. " GSW0TX ,Generic short write zero parameters transmission" "High-speed,Low-power"
|
|
textline " "
|
|
bitfld.long 0x3C 1. " ARE ,Acknowledge request enable" "Disabled,Enabled"
|
|
bitfld.long 0x3C 0. " TEARE ,Tearing effect acknowledge request enable" "Disabled,Enabled"
|
|
line.long 0x40 "DSI_GHCR,DSI Host Generic Header Configuration Register"
|
|
hexmask.long.byte 0x40 16.--23. 1. " WCMSB ,WordCount MSB"
|
|
hexmask.long.byte 0x40 8.--15. 1. " WCLSB ,WordCount LSB"
|
|
bitfld.long 0x40 6.--7. " VCID ,Channel" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x40 0.--5. " DT ,Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x44 "DSI_GPDR,DSI Host Generic Payload Data Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " DATA4 ,Payload Byte 4"
|
|
hexmask.long.byte 0x44 16.--23. 1. " DATA3 ,Payload byte 3"
|
|
hexmask.long.byte 0x44 8.--15. 1. " DATA2 ,Payload byte 2"
|
|
textline " "
|
|
hexmask.long.byte 0x44 0.--7. 1. " DATA1 ,Payload byte 1"
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "DSI_GPSR,DSI Host Generic Packet Status Register"
|
|
bitfld.long 0x00 6. " RCB ,Read command busy" "Not busy,Busy"
|
|
bitfld.long 0x00 5. " PRDFF ,Payload read FIFO full" "Not full,Full"
|
|
bitfld.long 0x00 4. " PRDFE ,Payload read FIFO empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWRFF ,Payload write FIFO full" "Not full,Full"
|
|
bitfld.long 0x00 2. " PWRFE ,Payload write FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x00 1. " CMDFF ,Command FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMDFE ,Command FIFO empty" "Not empty,Empty"
|
|
group.long 0x78++0x17
|
|
line.long 0x00 "DSI_TCCR0,DSI Host Timeout Counter Configuration Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " HSTX_TOCNT ,High-Speed transmission timeout counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " LPRX_TOCNT ,Low-power reception timeout counter"
|
|
line.long 0x04 "DSI_TCCR1,DSI Host Timeout Counter Configuration Register 1"
|
|
hexmask.long.word 0x04 0.--15. 1. " HSRD_TOCNT ,High-Speed read timeout counter"
|
|
line.long 0x08 "DSI_TCCR2,DSI Host Timeout Counter Configuration Register 2"
|
|
hexmask.long.word 0x08 0.--15. 1. " LPRD_TOCNT ,Low-Power read timeout counter"
|
|
line.long 0x0C "DSI_TCCR3,DSI Host Timeout Counter Configuration Register 3"
|
|
bitfld.long 0x0C 24. " PM ,Presp mode" "0,1"
|
|
hexmask.long.word 0x0C 0.--15. 1. " HSWR_TOCNT ,High-Speed write timeout counter"
|
|
line.long 0x10 "DSI_TCCR4,DSI Host Timeout Counter Configuration Register 4"
|
|
hexmask.long.word 0x10 0.--15. 1. " LSWR_TOCNT ,Low-Power write timeout counter"
|
|
line.long 0x14 "DSI_TCCR5,DSI Host Timeout Counter Configuration Register 5"
|
|
hexmask.long.word 0x14 0.--15. 1. " BTA_TOCNT ,Bus-Turn-Around timeout counter"
|
|
group.long 0x94++0x1B
|
|
line.long 0x00 "DSI_CLCR,DSI Host Clock Lane Configuration Register"
|
|
bitfld.long 0x00 1. " ACR ,Automatic clock lane control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DPCC ,D-PHY Clock control" "Low power,High speed"
|
|
line.long 0x04 "DSI_CLTCR,DSI Host Clock Lane Timer Configuration Register"
|
|
hexmask.long.word 0x04 16.--25. 1. " HS2LP_TIME ,High-Speed to Low-Power time"
|
|
hexmask.long.word 0x04 0.--9. 1. " LP2HS_TIME ,Low-Power to high-speed time"
|
|
line.long 0x08 "DSI_DLTCR,DSI Host Data Lane Timer Configuration Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " HS2LP_TIME ,High-Speed to low-power time"
|
|
hexmask.long.byte 0x08 16.--23. 1. " LP2HS_TIME ,Low-Power to high-speed time"
|
|
hexmask.long.word 0x08 0.--14. 1. " MRD_TIME ,Maximum read time"
|
|
line.long 0x0C "DSI_PCTLR,DSI Host PHY Control Register"
|
|
bitfld.long 0x0C 2. " CKE ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " DEN ,Digital enable" "Disabled,Enabled"
|
|
line.long 0x10 "DSI_PCONFR,DSI Host PHY Configuration Register"
|
|
hexmask.long.byte 0x10 8.--15. 1. " SW_TIME ,Stop wait time"
|
|
bitfld.long 0x10 0.--1. " NL ,Number of lanes" "One,Two,,"
|
|
line.long 0x14 "DSI_PUCR,DSI Host PHY ULPS Control Register"
|
|
bitfld.long 0x14 3. " UEDL ,ULPS exit on data lane" "Not requested,Requested"
|
|
bitfld.long 0x14 2. " URDL ,ULPS request on data lane" "Not requested,Requested"
|
|
bitfld.long 0x14 1. " UECL ,ULPS exit on clock lane" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x14 0. " URCL ,ULPS request on clock lane" "Not requested,Requested"
|
|
line.long 0x18 "DSI_PTTCR,DSI Host PHY TX Triggers Configuration Register"
|
|
bitfld.long 0x18 0.--3. " TX_TRIG ,Transmission trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "DSI_PSR,DSI Host PHY Status Register"
|
|
bitfld.long 0x00 8. " UAN1 ,ULPS active not lane 1" "Low,High"
|
|
bitfld.long 0x00 7. " PSS1 ,PHY stop state lane 1" "Low,High"
|
|
bitfld.long 0x00 6. " RUE0 ,RX ULPS escape lane 0" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " UAN0 ,ULPS active Not lane 1" "Low,High"
|
|
bitfld.long 0x00 4. " PSS0 ,PHY stop state lane 0" "Low,High"
|
|
bitfld.long 0x00 3. " UANC ,ULPS active not clock lane" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PSSC ,PHY stop state clock lane" "Low,High"
|
|
bitfld.long 0x00 1. " PD ,PHY direction" "Low,High"
|
|
rgroup.long 0xBC++0x07
|
|
line.long 0x00 "DSI_ISR0,DSI Host Interrupt & Status Register 0"
|
|
bitfld.long 0x00 20. " PE4 ,PHY error 4" "No error,Error"
|
|
bitfld.long 0x00 19. " PE3 ,PHY error 3" "No error,Error"
|
|
bitfld.long 0x00 18. " PE2 ,PHY error 2" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PE1 ,PHY error 1" "No error,Error"
|
|
bitfld.long 0x00 16. " PE0 ,PHY error 0" "No error,Error"
|
|
bitfld.long 0x00 15. " AE15 ,Acknowledge error 15" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 14. " AE14 ,Acknowledge error 14" "No error,Error"
|
|
bitfld.long 0x00 13. " AE13 ,Acknowledge error 13" "No error,Error"
|
|
bitfld.long 0x00 12. " AE12 ,Acknowledge error 12" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 11. " AE11 ,Acknowledge error 11" "No error,Error"
|
|
bitfld.long 0x00 10. " AE10 ,Acknowledge error 10" "No error,Error"
|
|
bitfld.long 0x00 9. " AE9 ,Acknowledge error 9" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 8. " AE8 ,Acknowledge error 8" "No error,Error"
|
|
bitfld.long 0x00 7. " AE7 ,Acknowledge error 7" "No error,Error"
|
|
bitfld.long 0x00 6. " AE6 ,Acknowledge error 6" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 5. " AE5 ,Acknowledge error 5" "No error,Error"
|
|
bitfld.long 0x00 4. " AE4 ,Acknowledge error 4" "No error,Error"
|
|
bitfld.long 0x00 3. " AE3 ,Acknowledge error 3" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AE2 ,Acknowledge error 2" "No error,Error"
|
|
bitfld.long 0x00 1. " AE1 ,Acknowledge error 1" "No error,Error"
|
|
bitfld.long 0x00 0. " AE0 ,Acknowledge error 0" "No error,Error"
|
|
line.long 0x04 "DSI_ISR1,DSI Host Interrupt & Status Register 1"
|
|
bitfld.long 0x04 12. " GPRXE ,Generic Payload receive Error" "No error,Error"
|
|
bitfld.long 0x04 11. " GPRDE ,Generic payload read error" "No error,Error"
|
|
bitfld.long 0x04 10. " GPTXE ,Generic payload transmit error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 9. " GPWRE ,Generic payload write error" "No error,Error"
|
|
bitfld.long 0x04 8. " GCWRE ,Generic command write error" "No error,Error"
|
|
bitfld.long 0x04 7. " LPWRE ,LTDC payload write error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 6. " EOTPE ,EoTp error" "No error,Error"
|
|
bitfld.long 0x04 5. " PSE ,Packet size error" "No error,Error"
|
|
bitfld.long 0x04 4. " CRCE ,CRC error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 3. " ECCME ,ECC multi-bit error" "No error,Error"
|
|
bitfld.long 0x04 2. " ECCSE ,ECC single-bit error" "No error,Error"
|
|
bitfld.long 0x04 1. " TOLPRX ,Timeout low-power reception" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TOHSTX ,Timeout high-speed transmission" "No error,Error"
|
|
group.long 0xC4++0x07
|
|
line.long 0x00 "DSI_IER0,DSI Host Interrupt Enable Register 0"
|
|
bitfld.long 0x00 20. " PE4IE ,PHY error 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PE3IE ,PHY error 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PE2IE ,PHY error 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PE1IE ,PHY error 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " PE0IE ,PHY error 0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " AE15IE ,Acknowledge error 15 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " AE14IE ,Acknowledge error 14 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " AE13IE ,Acknowledge error 13 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " AE12IE ,Acknowledge error 12 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " AE11IE ,Acknowledge error 11 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " AE10IE ,Acknowledge error 10 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " AE9IE ,Acknowledge error 9 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " AE8IE ,Acknowledge error 8 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " AE7IE ,Acknowledge error 7 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " AE6IE ,Acknowledge error 6 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " AE5IE ,Acknowledge error 5 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " AE4IE ,Acknowledge error 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " AE3IE ,Acknowledge error 3 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AE2IE ,Acknowledge error 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AE1IE ,Acknowledge error 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " AE0IE ,Acknowledge error 0 interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "DSI_IER1,DSI Host Interrupt Enable Register 1"
|
|
bitfld.long 0x04 12. " GPRXEIE ,Generic payload receive error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " GPRDEIE ,Generic payload read error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " GPTXEIE ,Generic payload transmit error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " GPWREIE ,Generic payload write error interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " GCWREIE ,Generic command write error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " LPWREIE ,LTDC Payload write error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " EOTPEIE ,EoTp Error Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " PSEIE ,Packet size error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " CRCEIE ,CRC Error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " ECCMEIE ,ECC multi-bit error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " ECCSEIE ,ECC single-bit Error Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " TOLPRXIE ,Timeout low-power reception interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TOHSTXIE ,Timeout high-speed transmission interrupt enable" "Disabled,Enabled"
|
|
wgroup.long 0xD8++0x07
|
|
line.long 0x00 "DSI_FIR0,DSI Host Force Interrupt Register 0"
|
|
bitfld.long 0x00 20. " FPE4 ,Force PHY error 4" "No effect,Force error"
|
|
bitfld.long 0x00 19. " FPE3 ,Force PHY error 3" "No effect,Force error"
|
|
bitfld.long 0x00 18. " FPE2 ,Force PHY error 2" "No effect,Force error"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FPE1 ,Force PHY error 1" "No effect,Force error"
|
|
bitfld.long 0x00 16. " FPE0 ,Force PHY error 0" "No effect,Force error"
|
|
bitfld.long 0x00 15. " FAE15 ,Force acknowledge error 15" "No effect,Force error"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FAE14 ,Force acknowledge error 14" "No effect,Force error"
|
|
bitfld.long 0x00 13. " FAE13 ,Force acknowledge error 13" "No effect,Force error"
|
|
bitfld.long 0x00 12. " FAE12 ,Force acknowledge error 12" "No effect,Force error"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FAE11 ,Force acknowledge error 11" "No effect,Force error"
|
|
bitfld.long 0x00 10. " FAE10 ,Force acknowledge error 10" "No effect,Force error"
|
|
bitfld.long 0x00 9. " FAE9 ,Force acknowledge error 9" "No effect,Force error"
|
|
textline " "
|
|
bitfld.long 0x00 8. " FAE8 ,Force acknowledge error 8" "No effect,Force error"
|
|
bitfld.long 0x00 7. " FAE7 ,Force acknowledge error 7" "No effect,Force error"
|
|
bitfld.long 0x00 6. " FAE6 ,Force acknowledge error 6" "No effect,Force error"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FAE5 ,Force acknowledge error 5" "No effect,Force error"
|
|
bitfld.long 0x00 4. " FAE4 ,Force acknowledge error 4" "No effect,Force error"
|
|
bitfld.long 0x00 3. " FAE3 ,Force acknowledge error 3" "No effect,Force error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FAE2 ,Force acknowledge error 2" "No effect,Force error"
|
|
bitfld.long 0x00 1. " FAE1 ,Force acknowledge error 1" "No effect,Force error"
|
|
bitfld.long 0x00 0. " FAE0 ,Force acknowledge error 0" "No effect,Force error"
|
|
line.long 0x04 "DSI_FIR1,DSI Host Force Interrupt register 1"
|
|
bitfld.long 0x04 12. " FGPRXE ,Generic payload receive error Force" "No effect,Force error"
|
|
bitfld.long 0x04 11. " FGPRDE ,Generic payload read error Force" "No effect,Force error"
|
|
bitfld.long 0x04 10. " FGPTXE ,Generic payload transmit error force" "No effect,Force error"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FGPWRE ,Generic payload write error force" "No effect,Force error"
|
|
bitfld.long 0x04 8. " FGCWRE ,Generic command write error force" "No effect,Force error"
|
|
bitfld.long 0x04 7. " FLPWRE ,LTDC payload write error force" "No effect,Force error"
|
|
textline " "
|
|
bitfld.long 0x04 6. " FEOTPE ,EoTp error force" "No effect,Force error"
|
|
bitfld.long 0x04 5. " FPSE ,Packet size error force" "No effect,Force error"
|
|
bitfld.long 0x04 4. " FCRCE ,CRC error force" "No effect,Force error"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FECCME ,ECC multi-bit error force" "No effect,Force error"
|
|
bitfld.long 0x04 2. " FECCSE ,ECC single-bit error force" "No effect,Force error"
|
|
bitfld.long 0x04 1. " FTOLPRX ,Timeout low-power reception force" "No effect,Force error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " FTOHSTX ,Timeout High-Speed transmission force" "No effect,Force error"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DSI_VSCR,DSI Host Video Shadow Control Register"
|
|
bitfld.long 0x00 8. " UR ,Update register" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
rgroup.long 0x10C++0x03
|
|
line.long 0x00 "DSI_LCVCIDR,DSI Host LTDC Current VCID Register"
|
|
bitfld.long 0x00 0.--1. " VCID ,Virtual channel ID" "0,1,2,3"
|
|
if (((per.l(ad:0x40016C00+0x34)&0x01))==0x00)
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "DSI_LCCCR,DSI Host LTDC Current Color Coding Register"
|
|
bitfld.long 0x00 8. " LPE ,Loosely packed enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " COLC ,Color coding" "16b 1,16b 2,16b 3,18b 1,18b 2,24b,?..."
|
|
else
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "DSI_LCCCR,DSI Host LTDC Current Color Coding Register"
|
|
bitfld.long 0x00 8. " LPE ,Loosely packed enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " COLC ,Color coding" "16b 1,16b 2,16b 3,18b 1,18b 2,24b,24b,24b,24b,24b,24b,24b,24b,24b,24b,24b"
|
|
endif
|
|
rgroup.long 0x118++0x03
|
|
line.long 0x00 "DSI_LPMCCR,DSI Host Low-Power mode Current Configuration Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " LPSIZE ,Largest packet size"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VLPSIZE ,VACT largest packet size"
|
|
rgroup.long 0x138++0x0B
|
|
line.long 0x00 "DSI_VMCCR,DSI Host Video mode Current Configuration Register"
|
|
bitfld.long 0x00 9. " LPCE ,Low-Power command enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FBTAAE ,BTA acknowledge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " LPHFE ,Low-Power horizontal Front-Porch enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LPHBPE ,Low-power horizontal Back-Porch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LPVAE ,Low-Power vertical active enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LPVFPE ,Low-power vertical Front-Porch enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LPVBPE ,Low-power vertical Back-Porch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " LPVSAE ,Low-Power vertical Sync time enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " VMT ,Video mode type" "Non-burst pulses,Non-burst events,Burst,Burst"
|
|
line.long 0x04 "DSI_VPCCR,DSI Host Video Packet Current Configuration Register"
|
|
hexmask.long.word 0x04 0.--13. 1. " VPSIZE ,Video packet size"
|
|
line.long 0x08 "DSI_VCCCR,DSI Host Video Chunks Current Configuration Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " NUMC ,Number of chunks"
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
rgroup.long 0x144++0x0B
|
|
line.long 0x00 "DSI_VNPCCR,DSI Host Video Null Packet Current Configuration Register"
|
|
hexmask.long.word 0x00 0.--12. 1. " NPSIZE ,Null packet size"
|
|
line.long 0x04 "DSI_VHSACCR,DSI Host Video HSA Current Configuration Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " HSA ,Horizontal synchronism active duration"
|
|
line.long 0x08 "DSI_VHBPCCR,DSI Host Video HBP Current Configuration Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " HBP ,Horizontal Back-Porch duration"
|
|
else
|
|
rgroup.long 0x144++0x07
|
|
line.long 0x00 "DSI_VNPCCR,DSI Host Video Null Packet Current Configuration Register"
|
|
hexmask.long.word 0x00 0.--12. 1. " HSA ,Horizontal Synchronism Active duration"
|
|
line.long 0x04 "DSI_VHBPCCR,DSI Host Video HBP Current Configuration Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " HBP ,Horizontal Back-Porch duration"
|
|
endif
|
|
rgroup.long 0x150++0x13
|
|
line.long 0x00 "DSI_VLCCR,DSI Host Video Line Current Configuration Register"
|
|
hexmask.long.word 0x00 0.--14. 1. " HLINE ,Horizontal line duration"
|
|
line.long 0x04 "DSI_VVSACCR,DSI Host Video VSA Current Configuration Register"
|
|
hexmask.long.word 0x04 0.--9. 1. " VSA ,Vertical synchronism active duration"
|
|
line.long 0x08 "DSI_VVBPCCR,DSI Host Video VBP Current Configuration Register"
|
|
hexmask.long.word 0x08 0.--9. 1. " VBP ,Vertical Back-Porch duration"
|
|
line.long 0x0C "DSI_VVFPCCR,DSI Host Video VFP Current Configuration Register"
|
|
hexmask.long.word 0x0C 0.--9. 1. " VFP ,Vertical Front-Porch duration"
|
|
line.long 0x10 "DSI_VVACCR,DSI Host Video VA Current Configuration Register"
|
|
hexmask.long.word 0x10 0.--13. 1. " VA ,Vertical active duration"
|
|
tree.end
|
|
tree "DSI Wrapper Registers"
|
|
if (((per.l(ad:0x40016C00+0x04)&0x01))==0x00)
|
|
if (((per.l(ad:0x40016C00+0x404)&0x08))==0x00)
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "DSI_WCFGR,DSI Wrapper Configuration Register"
|
|
bitfld.long 0x00 7. " VSPOL ,VSync polarity" "Falling,Rising"
|
|
bitfld.long 0x00 6. " AR ,Automatic refresh" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TEPOL ,TE polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TESRC ,TE source" "DSI,External"
|
|
bitfld.long 0x00 1.--3. " COLMUX ,Color multiplexing" "16 bit,16 bit,16 bit,18 bit,18 bit,24 bit,?..."
|
|
bitfld.long 0x00 0. " DSIM ,DSI mode" "Video,Adapted command"
|
|
else
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "DSI_WCFGR,DSI Wrapper Configuration Register"
|
|
rbitfld.long 0x00 7. " VSPOL ,VSync polarity" "Falling,Rising"
|
|
bitfld.long 0x00 6. " AR ,Automatic refresh" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TEPOL ,TE polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TESRC ,TE Source" "DSI,External"
|
|
rbitfld.long 0x00 1.--3. " COLMUX ,Color multiplexing" "16 bit,16 bit,16 bit,18 bit,18 bit,24 bit,?..."
|
|
bitfld.long 0x00 0. " DSIM ,DSI mode" "Video,Adapted command"
|
|
endif
|
|
else
|
|
rgroup.long 0x400++0x03
|
|
line.long 0x00 "DSI_WCFGR,DSI Wrapper Configuration Register"
|
|
bitfld.long 0x00 7. " VSPOL ,VSync polarity" "Falling,Rising"
|
|
bitfld.long 0x00 6. " AR ,Automatic refresh" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TEPOL ,TE polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TESRC ,TE Source" "DSI,External"
|
|
bitfld.long 0x00 1.--3. " COLMUX ,Color multiplexing" "16 bit,16 bit,16 bit,18 bit,18 bit,24 bit,?..."
|
|
bitfld.long 0x00 0. " DSIM ,DSI mode" "Video,Adapted command"
|
|
endif
|
|
group.long 0x404++0x07
|
|
line.long 0x00 "DSI_WCR,DSI Wrapper Control Register"
|
|
bitfld.long 0x00 3. " DSIEN ,DSI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " LTDCEN ,LTDC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SHTDN ,Shutdown" "ON,OFF"
|
|
textline " "
|
|
bitfld.long 0x00 0. " COLM ,Color mode" "Full color,Eight color"
|
|
line.long 0x04 "DSI_WIER,DSI Wrapper Interrupt Enable Register"
|
|
bitfld.long 0x04 13. " RRIE ,Regulator ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " PLLUIE ,PLL unlock interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " PLLLIE ,PLL lock interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ERIE ,End of refresh interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " TEIE ,Tearing effect interrupt enable" "Disabled,Enabled"
|
|
rgroup.long 0x408++0x03
|
|
line.long 0x00 "DSI_WISR,DSI Wrapper Interrupt & Status Register"
|
|
bitfld.long 0x00 13. " RRIF ,Regulator ready interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " RRS ,Regulator ready status" "Not ready,Ready"
|
|
bitfld.long 0x00 10. " PLLUIF ,PLL unlock interrupt flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PLLLIF ,PLL lock interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " PLLLS ,PLL lock status" "Unlocked,Locked"
|
|
bitfld.long 0x00 2. " BUSY ,Busy flag" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ERIF ,End of refresh interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " TEIF ,Tearing effect interrupt flag" "Not occurred,Occurred"
|
|
wgroup.long 0x410++0x03
|
|
line.long 0x00 "DSI_WIFCR,DSI Wrapper Interrupt Flag Clear Register"
|
|
bitfld.long 0x00 13. " CRRIF ,Clear regulator ready interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CPLLUIF ,Clear PLL unlock interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 9. " CPLLLIF ,Clear PLL lock interrupt flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CERIF ,Clear end of refresh interrupt flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CTEIF ,Clear tearing effect interrupt flag" "No effect,Clear"
|
|
group.long 0x418++0x03
|
|
line.long 0x00 "DSI_WPCR0,DSI Wrapper PHY Configuration Register 0"
|
|
bitfld.long 0x00 27. " TCLKPOSTEN ,Custom time for tCLK-POST enable" "Default,Programmable"
|
|
bitfld.long 0x00 26. " TLPXCEN ,Custom time for tLPX for Clock lane enable" "Default,Programmable"
|
|
bitfld.long 0x00 25. " THSEXITEN ,Custom time for tHS-EXIT enable" "Default,Programmable"
|
|
textline " "
|
|
bitfld.long 0x00 24. " TLPXDEN ,Custom time for tLPX for data lanes enable" "Default,Programmable"
|
|
bitfld.long 0x00 23. " THSZEROEN ,Custom time for tHS-ZERO enable" "Default,Programmable"
|
|
bitfld.long 0x00 22. " THSTRAILEN ,Custom time for tHS-TRAIL enable" "Default,Programmable"
|
|
textline " "
|
|
bitfld.long 0x00 21. " THSPREPEN ,Custom time for tHS-PREPARE enable" "Default,Programmable"
|
|
bitfld.long 0x00 20. " TCLKZEROEN ,Custom time for tCLK-ZERO enable" "Default,Programmable"
|
|
bitfld.long 0x00 19. " TCLKPREPEN ,Custom time for tCLK-PREPARE enable" "Default,Programmable"
|
|
textline " "
|
|
bitfld.long 0x00 18. " PDEN ,Pull-Down enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " TDDL ,Turn disable data lanes" "No effect,Force data"
|
|
bitfld.long 0x00 14. " CDOFFDL ,Contention detection OFF on data lanes" "ON,OFF"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FTXSMDL ,Force in TX stop mode the data lanes" "No effect,Force data"
|
|
bitfld.long 0x00 12. " FTXSMCL ,Force in TX stop mode the clock lane" "No effect,Force clock"
|
|
bitfld.long 0x00 11. " HSIDL1 ,Invert the High-Speed data signal on data lane 1" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 10. " HSIDL0 ,Invert the High-Speed data signal on data lane 0" "Normal,Inverted"
|
|
bitfld.long 0x00 9. " HSICL ,Invert High-Speed data signal on clock lane" "Normal,Inverted"
|
|
bitfld.long 0x00 8. " SWDL1 ,Swap data lane 1 pins" "Regular,Swapped"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SWDL0 ,Swap data lane 0 pins" "Regular,Swapped"
|
|
bitfld.long 0x00 6. " SWCL ,Swap clock lane pins" "Regular,Swapped"
|
|
bitfld.long 0x00 0.--5. " UIX4 ,Unit interval multiplied by 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
if (((per.l(ad:0x40016C00+0x04)&0x01))==0x00)&&(((per.l(ad:0x40016C00+0x404)&0x08))==0x00)
|
|
group.long 0x41C++0x0F
|
|
line.long 0x00 "DSI_WPCR1,DSI Wrapper PHY Configuration Register 1"
|
|
bitfld.long 0x00 25.--26. " LPRXFT ,Low-Power RX low-pass filtering tuning" "0,1,2,3"
|
|
bitfld.long 0x00 22. " FLPRXLPM ,Forces LP receiver in Low-Power mode" "No effect,Forced"
|
|
bitfld.long 0x00 18.--19. " HSTXSRCDL ,High-Speed transmission slew rate control" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " HSTXSRCCL ,High-Speed transmission slew rate control" "0,1,2,3"
|
|
bitfld.long 0x00 12. " SDDC ,SDD Control" "No effect,Activate"
|
|
bitfld.long 0x00 8.--9. " LPSRCDL ,Low-Power transmission Slew rate compensation" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " LPSRCCL ,Low-Power transmission Slew rate compensation" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " HSTXDDL ,High-Speed transmission delay on data lanes" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " HSTXDCL ,High-Speed transmission delay on clock lane" "0,1,2,3"
|
|
line.long 0x04 "DSI_WPCR2,DSI Wrapper PHY Configuration Register 2"
|
|
hexmask.long.byte 0x04 24.--31. 1. " THSTRAIL ,tHSTRAIL"
|
|
hexmask.long.byte 0x04 16.--23. 1. " THSPREP ,tHS-PREPARE"
|
|
hexmask.long.byte 0x04 8.--15. 1. " TCLKZERO ,tCLK-ZERO"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " TCLKPREP ,tCLK-PREPARE"
|
|
line.long 0x08 "DSI_WPCR3,DSI Wrapper PHY Configuration Register 3"
|
|
hexmask.long.byte 0x08 24.--31. 1. " TLPXC ,tLPXC for clock lane"
|
|
hexmask.long.byte 0x08 16.--23. 1. " THSEXIT ,tHSEXIT"
|
|
hexmask.long.byte 0x08 8.--15. 1. " TLPXD ,tLPX for data lanes"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--7. 1. " THSZERO ,tHS-ZERO"
|
|
line.long 0x0C "DSI_WPCR4,DSI Wrapper PHY Configuration Register 4"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " TCLKPOST ,tCLK-POST"
|
|
else
|
|
rgroup.long 0x41C++0x0F
|
|
line.long 0x00 "DSI_WPCR1,DSI Wrapper PHY Configuration Register 1"
|
|
bitfld.long 0x00 25.--26. " LPRXFT ,Low-Power RX low-pass Filtering Tuning" "0,1,2,3"
|
|
bitfld.long 0x00 22. " FLPRXLPM ,Forces LP receiver in Low-Power mode" "No effect,Forced"
|
|
bitfld.long 0x00 18.--19. " HSTXSRCDL ,High-Speed Transmission slew rate control" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " HSTXSRCCL ,High-Speed transmission slew rate control" "0,1,2,3"
|
|
bitfld.long 0x00 12. " SDDC ,SDD Control" "No effect,Activate"
|
|
bitfld.long 0x00 8.--9. " LPSRCDL ,Low-Power transmission slew rate compensation" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " LPSRCCL ,Low-Power transmission slew rate compensation" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " HSTXDDL ,High-Speed Transmission delay on data lanes" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " HSTXDCL ,High-Speed transmission delay on clock lane" "0,1,2,3"
|
|
line.long 0x04 "DSI_WPCR2,DSI Wrapper PHY Configuration Register 2"
|
|
hexmask.long.byte 0x04 24.--31. 1. " THSTRAIL ,tHSTRAIL"
|
|
hexmask.long.byte 0x04 16.--23. 1. " THSPREP ,tHS-PREPARE"
|
|
hexmask.long.byte 0x04 8.--15. 1. " TCLKZERO ,tCLK-ZERO"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " TCLKPREP ,tCLK-PREPARE"
|
|
line.long 0x08 "DSI_WPCR3,DSI Wrapper PHY Configuration Register 3"
|
|
hexmask.long.byte 0x08 24.--31. 1. " TLPXC ,tLPXC for clock lane"
|
|
hexmask.long.byte 0x08 16.--23. 1. " THSEXIT ,tHSEXIT"
|
|
hexmask.long.byte 0x08 8.--15. 1. " TCLKZERO ,tLPX for data lanes"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--7. 1. " THSZERO ,tHS-ZERO"
|
|
line.long 0x0C "DSI_WPCR4,DSI Wrapper PHY Configuration Register 4"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " TCLKPOST ,tCLK-POST"
|
|
endif
|
|
group.long 0x430++0x03
|
|
line.long 0x00 "DSI_WRPCR,DSI Wrapper Regulator and PLL Control Register"
|
|
bitfld.long 0x00 24. " REGEN ,Regulator enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " ODF ,PLL Output division factor" "/1,/2,/4,/8"
|
|
bitfld.long 0x00 11.--14. " IDF ,PLL Input division factor" "/1,/1,/2,/3,/4,/5,/6,/7,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 2.--8. 1. " NDIV ,PLL Loop division factor"
|
|
bitfld.long 0x00 0. " PLLEN ,PLL Enable" "Disabled,Enabled"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F77*")||cpuis("STM32F767V*")||cpuis("STM32F769V*")||cpuis("STM32F767Z*")||cpuis("STM32F769Z*")||cpuis("STM32F769A*")||cpuis("STM32F767I*")||cpuis("STM32F769I*")||cpuis("STM32F767B*")||cpuis("STM32F769B*")||cpuis("STM32F767N*")||cpuis("STM32F769N*"))
|
|
tree "JPEG (JPEG codec)"
|
|
base ad:0x50051000
|
|
width 13.
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32H76*")||cpuis("STM32H77*"))
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "JPEG_CONFR0,JPEG Codec Control Register"
|
|
bitfld.long 0x00 0. " START ,Start" "Stop,Start"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "JPEG_CONFR0,JPEG Codec Control Register"
|
|
bitfld.long 0x00 0. " START ,Start" "Stop,Start"
|
|
endif
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "JPEG_CONFR1,JPEG Codec Configuration Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " YSIZE ,Y size"
|
|
bitfld.long 0x00 8. " HDR ,Header processing" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " NS ,Number of components for scan" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " COLORSPACE ,Color space" "Grayscale,YUV,RGB,CMYK"
|
|
bitfld.long 0x00 3. " DE ,Decoding enable" "Coding,Decoding"
|
|
bitfld.long 0x00 0.--1. " NF ,Number of color components" "1,2,3,4"
|
|
line.long 0x04 "JPEG_CONFR2,JPEG Codec Configuration Register 2"
|
|
hexmask.long 0x04 0.--25. 1. " NMCU ,Number of MCU"
|
|
line.long 0x08 "JPEG_CONFR3,JPEG Codec Configuration Register 3"
|
|
hexmask.long.word 0x08 16.--31. 1. " XSIZE ,X size"
|
|
group.long (0x10+0x0)++0x03
|
|
line.long 0x00 "JPEG_CONFR4,JPEG Codec Configuration Register 4"
|
|
bitfld.long 0x00 12.--15. " HSF ,Horizontal sampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " VSF ,Vertical sampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " NB ,Number of block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " QT ,Quantization table" "0,1,2,3"
|
|
bitfld.long 0x00 1. " HA ,Huffman AC" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " HD ,Huffman DC" "Not selected,Selected"
|
|
group.long (0x10+0x4)++0x03
|
|
line.long 0x00 "JPEG_CONFR5,JPEG Codec Configuration Register 5"
|
|
bitfld.long 0x00 12.--15. " HSF ,Horizontal sampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " VSF ,Vertical sampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " NB ,Number of block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " QT ,Quantization table" "0,1,2,3"
|
|
bitfld.long 0x00 1. " HA ,Huffman AC" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " HD ,Huffman DC" "Not selected,Selected"
|
|
group.long (0x10+0x8)++0x03
|
|
line.long 0x00 "JPEG_CONFR6,JPEG Codec Configuration Register 6"
|
|
bitfld.long 0x00 12.--15. " HSF ,Horizontal sampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " VSF ,Vertical sampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " NB ,Number of block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " QT ,Quantization table" "0,1,2,3"
|
|
bitfld.long 0x00 1. " HA ,Huffman AC" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " HD ,Huffman DC" "Not selected,Selected"
|
|
group.long (0x10+0xC)++0x03
|
|
line.long 0x00 "JPEG_CONFR7,JPEG Codec Configuration Register 7"
|
|
bitfld.long 0x00 12.--15. " HSF ,Horizontal sampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " VSF ,Vertical sampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " NB ,Number of block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " QT ,Quantization table" "0,1,2,3"
|
|
bitfld.long 0x00 1. " HA ,Huffman AC" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " HD ,Huffman DC" "Not selected,Selected"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "JPEG_CR,JPEG Control Register"
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
bitfld.long 0x00 14. " OFF ,Output FIFO flush" "No effect,Flushed"
|
|
bitfld.long 0x00 13. " IFF ,Input FIFO flush" "No effect,Flushed"
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x00 14. " OFF ,Output FIFO flush" "No effect,Flushed"
|
|
rbitfld.long 0x00 13. " IFF ,Input FIFO flush" "No effect,Flushed"
|
|
bitfld.long 0x00 12. " ODMAEN ,Output DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IDMAEN ,Input DMA enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6. " HPDIE ,Header parsing done interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EOCIE ,End of conversion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " OFNEIE ,Output FIFO not empty interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OFTIE ,Output FIFO threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " IFNFIE ,Input FIFO not full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IFTIE ,Input FIFO threshold interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " JCEN ,JPEG core enable" "Disabled,Enabled"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "JPEG_SR,JPEG Status Register"
|
|
bitfld.long 0x00 7. " COF ,Codec operation flag" "Not in progress,In progress"
|
|
bitfld.long 0x00 6. " HPDF ,Header parsing done flag" "Not completed,Completed"
|
|
bitfld.long 0x00 5. " EOCF ,End of conversion flag" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 4. " OFNEF ,Output FIFO not empty flag" "Empty,Not empty"
|
|
bitfld.long 0x00 3. " OFTF ,Output FIFO threshold flag" "Bellow,Above"
|
|
bitfld.long 0x00 2. " IFNFF ,Input FIFO not full flag" "Full,Not full"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IFTF ,Input FIFO threshold flag" "Above,Bellow"
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
wgroup.long 0x38++0x03
|
|
line.long 0x00 "JPEG_CFR,JPEG Clear Flag Register"
|
|
bitfld.long 0x00 6. " CHPDF ,Clear header parsing done flag" "No effect,Clear"
|
|
bitfld.long 0x00 5. " CEOCF ,Clear end of conversion flag" "No effect,Clear"
|
|
else
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "JPEG_CFR,JPEG Clear Flag Register"
|
|
eventfld.long 0x00 6. " CHPDF ,Clear header parsing done flag" "No effect,Clear"
|
|
eventfld.long 0x00 5. " CEOCF ,Clear end of conversion flag" "No effect,Clear"
|
|
endif
|
|
wgroup.long 0x40++0x03
|
|
line.long 0x00 "JPEG_DIR,JPEG Data Input Register"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "JPEG_DOR,JPEG Data Output Register"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "RNG (Random Number Generator)"
|
|
base ad:0x50060800
|
|
width 4.
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
if (((per.l(ad:0x50060800)&0x04)==0x04))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,RNG Control Register"
|
|
rbitfld.long 0x00 6. " BYP ,Bypass mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CED ,Clock error detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " IE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RNGEN ,Random number generator enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,RNG Control Register"
|
|
bitfld.long 0x00 6. " BYP ,Bypass mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CED ,Clock error detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " IE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RNGEN ,Random number generator enable" "Disabled,Enabled"
|
|
endif
|
|
elif (cpuis("STM32F730*")||cpuis("STM32F750*"))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,RNG Control Register"
|
|
bitfld.long 0x00 5. " CED ,Clock error detection" "Enabled,Disabled"
|
|
bitfld.long 0x00 3. " IE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RNGEN ,Random number generator enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,RNG Control Register"
|
|
bitfld.long 0x00 3. " IE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RNGEN ,Random number generator enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32F730*")||cpuis("STM32F750*"))
|
|
if (((per.l(ad:0x50060800))&0x20)==0x20)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SR,RNG Status Register"
|
|
bitfld.long 0x00 6. " SEIS ,Seed error interrupt status" "No error,Error"
|
|
bitfld.long 0x00 5. " CEIS ,Clock error interrupt status" "No error,Error"
|
|
rbitfld.long 0x00 2. " SECS ,Seed error current status" "No error,Error"
|
|
rbitfld.long 0x00 0. " DRDY ,Data ready" "Invalid register,Valid random data"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SR,RNG Status Register"
|
|
bitfld.long 0x00 6. " SEIS ,Seed error interrupt status" "No error,Error"
|
|
bitfld.long 0x00 5. " CEIS ,Clock error interrupt status" "No error,Error"
|
|
rbitfld.long 0x00 2. " SECS ,Seed error current status" "No error,Error"
|
|
rbitfld.long 0x00 1. " CECS ,Clock error current status" "No error,Error"
|
|
newline
|
|
rbitfld.long 0x00 0. " DRDY ,Data ready" "Invalid register,Valid random data"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SR,RNG Status Register"
|
|
bitfld.long 0x00 6. " SEIS ,Seed error interrupt status" "No error,Error"
|
|
bitfld.long 0x00 5. " CEIS ,Clock error interrupt status" "No error,Error"
|
|
rbitfld.long 0x00 2. " SECS ,Seed error current status" "No error,Error"
|
|
rbitfld.long 0x00 1. " CECS ,Clock error current status" "No error,Error"
|
|
newline
|
|
rbitfld.long 0x00 0. " DRDY ,Data ready" "Invalid register,Valid random data"
|
|
endif
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32F730*")||cpuis("STM32F750*"))
|
|
if (((per.l(ad:0x50060800+0x04))&0x01)==0x01)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "DR,RNG Data Register"
|
|
else
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "DR,RNG Data Register"
|
|
endif
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "DR,RNG Data Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif cpuis("STM32F73*")
|
|
tree "AES (Advanced encryption standard hardware accelerator)"
|
|
base ad:0x50060000
|
|
width 8.
|
|
if (((per.l(ad:0x50060000))&0x10081)==0x80)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,AES Control Register"
|
|
bitfld.long 0x00 18. " KEYSIZE ,Key size selection" "128b,256b"
|
|
bitfld.long 0x00 13.--14. " GCMPH ,GCM phase" ",Header,,Final"
|
|
bitfld.long 0x00 12. " DMAOUTEN ,Enable DMA management of data output phase" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " DMAINEN ,Enable DMA management of data input phase" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " ERRIE ,Error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CCFIE ,CCF flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ERRC ,Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 7. " CCFC ,Computation complete flag clear" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 5.--6. 16. " CHMOD ,AES chaining mode" "ECB,CBC,CTR,GCM&GMAC,CMAC,?..."
|
|
bitfld.long 0x00 3.--4. " MODE ,AES operating mode" "Encryption,Key derivation,Decryption,Key derivation + decryption"
|
|
bitfld.long 0x00 1.--2. " DATATYPE ,Data type selection" "32-bit data,16-bit data/half-word,8-bit data/bytes,Bit data"
|
|
bitfld.long 0x00 0. " EN ,AES enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50060000))&0x10081)==0x81)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,AES Control Register"
|
|
rbitfld.long 0x00 18. " KEYSIZE ,Key size selection" "128b,256b"
|
|
bitfld.long 0x00 13.--14. " GCMPH ,GCM phase" ",Header,,Final"
|
|
bitfld.long 0x00 12. " DMAOUTEN ,Enable DMA management of data output phase" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " DMAINEN ,Enable DMA management of data input phase" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " ERRIE ,Error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CCFIE ,CCF flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ERRC ,Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 7. " CCFC ,Computation complete flag clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 5.--6. 16. " CHMOD ,AES chaining mode" "ECB,CBC,CTR,GCM&GMAC,CMAC,?..."
|
|
rbitfld.long 0x00 3.--4. " MODE ,AES operating mode" "Encryption,Key derivation,Decryption,Key derivation + decryption"
|
|
rbitfld.long 0x00 1.--2. " DATATYPE ,Data type selection" "32-bit data,16-bit data/half-word,8-bit data/bytes,Bit data"
|
|
bitfld.long 0x00 0. " EN ,AES enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50060000))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,AES Control Register"
|
|
bitfld.long 0x00 18. " KEYSIZE ,Key size selection" "128b,256b"
|
|
bitfld.long 0x00 13.--14. " GCMPH ,GCM phase" "Init,Header,Payload,Final"
|
|
bitfld.long 0x00 12. " DMAOUTEN ,Enable DMA management of data output phase" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " DMAINEN ,Enable DMA management of data input phase" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " ERRIE ,Error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CCFIE ,CCF flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ERRC ,Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 7. " CCFC ,Computation complete flag clear" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 5.--6. 16. " CHMOD ,AES chaining mode" "ECB,CBC,CTR,GCM&GMAC,CMAC,?..."
|
|
bitfld.long 0x00 3.--4. " MODE ,AES operating mode" "Encryption,Key derivation,Decryption,Key derivation + decryption"
|
|
bitfld.long 0x00 1.--2. " DATATYPE ,Data type selection" "32-bit data,16-bit data/half-word,8-bit data/bytes,Bit data"
|
|
bitfld.long 0x00 0. " EN ,AES enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,AES Control Register"
|
|
rbitfld.long 0x00 18. " KEYSIZE ,Key size selection" "128b,256b"
|
|
bitfld.long 0x00 13.--14. " GCMPH ,GCM phase" "Init,Header,Payload,Final"
|
|
bitfld.long 0x00 12. " DMAOUTEN ,Enable DMA management of data output phase" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " DMAINEN ,Enable DMA management of data input phase" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " ERRIE ,Error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CCFIE ,CCF flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ERRC ,Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 7. " CCFC ,Computation complete flag clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 5.--6. 16. " CHMOD ,AES chaining mode" "ECB,CBC,CTR,GCM&GMAC,CMAC,?..."
|
|
rbitfld.long 0x00 3.--4. " MODE ,AES operating mode" "Encryption,Key derivation,Decryption,Key derivation + decryption"
|
|
rbitfld.long 0x00 1.--2. " DATATYPE ,Data type selection" "32-bit data,16-bit data/half-word,8-bit data/bytes,Bit data"
|
|
bitfld.long 0x00 0. " EN ,AES enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SR,AES Status Register"
|
|
bitfld.long 0x00 3. " BUSY ,Busy flag" "Idle,Busy"
|
|
bitfld.long 0x00 2. " WRERR ,Write error flag" "No error,Error"
|
|
bitfld.long 0x00 1. " RDERR ,Read error flag" "No error,Error"
|
|
bitfld.long 0x00 0. " CCF ,Computation complete flag" "Not completed,Completed"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DINR,AES Data Input Register"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "DOUTR,AES Data Output Register"
|
|
if (((per.l(ad:0x50060000))&0x01)==0x00)
|
|
group.long 0x10++0x1F
|
|
line.long 0x00 "KEYR0,AES Key Register 0"
|
|
line.long 0x04 "KEYR1,AES Key Register 1"
|
|
line.long 0x08 "KEYR2,AES Key Register 2"
|
|
line.long 0x0C "KEYR3,AES Key Register 3"
|
|
line.long 0x10 "IVR0,AES Initialization Vector Register 0"
|
|
line.long 0x14 "IVR1,AES Initialization Vector Register 1"
|
|
line.long 0x18 "IVR2,AES Initialization Vector Register 2"
|
|
line.long 0x1C "IVR3,AES Initialization Vector Register 3"
|
|
else
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "KEYR0,AES Key Register 0"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "KEYR1,AES Key Register 1"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "KEYR2,AES Key Register 2"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "KEYR3,AES Key Register 3"
|
|
rgroup.long 0x20++0x0F
|
|
line.long 0x00 "IVR0,AES Initialization Vector Register 0"
|
|
line.long 0x04 "IVR1,AES Initialization Vector Register 1"
|
|
line.long 0x08 "IVR2,AES Initialization Vector Register 2"
|
|
line.long 0x0C "IVR3,AES Initialization Vector Register 3"
|
|
endif
|
|
if (((per.l(ad:0x50060000))&0x40001)==0x40000)
|
|
group.long 0x30++0x0F
|
|
line.long 0x00 "KEYR4,AES Key Register 4"
|
|
line.long 0x04 "KEYR5,AES Key Register 5"
|
|
line.long 0x08 "KEYR6,AES Key Register 6"
|
|
line.long 0x0C "KEYR7,AES Key Register 7"
|
|
elif (((per.l(ad:0x50060000))&0x40001)==0x40001)
|
|
rgroup.long 0x30++0x0F
|
|
line.long 0x00 "KEYR4,AES Key Register 4"
|
|
line.long 0x04 "KEYR5,AES Key Register 5"
|
|
line.long 0x08 "KEYR6,AES Key Register 6"
|
|
line.long 0x0C "KEYR7,AES Key Register 7"
|
|
else
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "KEYR4,AES Key Register 4"
|
|
hgroup.long 0x34++0x03
|
|
hide.long 0x00 "KEYR5,AES Key Register 5"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "KEYR6,AES Key Register 6"
|
|
hgroup.long 0x3C++0x03
|
|
hide.long 0x00 "KEYR7,AES Key Register 7"
|
|
endif
|
|
if (((per.l(ad:0x50060000))&0x10081)==0x10031)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "SUSP0R,AES Suspend Register"
|
|
elif (((per.l(ad:0x50060000))&0x10081)==0x10030)
|
|
wgroup.long 0x40++0x03
|
|
line.long 0x00 "SUSP0R,AES Suspend Register"
|
|
else
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "SUSP0R,AES Suspend Register"
|
|
endif
|
|
if (((per.l(ad:0x50060000))&0x10081)==0x10031)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SUSP1R,AES Suspend Register"
|
|
elif (((per.l(ad:0x50060000))&0x10081)==0x10030)
|
|
wgroup.long 0x44++0x03
|
|
line.long 0x00 "SUSP1R,AES Suspend Register"
|
|
else
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "SUSP1R,AES Suspend Register"
|
|
endif
|
|
if (((per.l(ad:0x50060000))&0x10081)==0x10031)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SUSP2R,AES Suspend Register"
|
|
elif (((per.l(ad:0x50060000))&0x10081)==0x10030)
|
|
wgroup.long 0x48++0x03
|
|
line.long 0x00 "SUSP2R,AES Suspend Register"
|
|
else
|
|
hgroup.long 0x48++0x03
|
|
hide.long 0x00 "SUSP2R,AES Suspend Register"
|
|
endif
|
|
if (((per.l(ad:0x50060000))&0x10081)==0x10031)
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "SUSP3R,AES Suspend Register"
|
|
elif (((per.l(ad:0x50060000))&0x10081)==0x10030)
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "SUSP3R,AES Suspend Register"
|
|
else
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "SUSP3R,AES Suspend Register"
|
|
endif
|
|
if (((per.l(ad:0x50060000))&0x10081)==0x10031)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "SUSP4R,AES Suspend Register"
|
|
elif (((per.l(ad:0x50060000))&0x10081)==0x10030)
|
|
wgroup.long 0x50++0x03
|
|
line.long 0x00 "SUSP4R,AES Suspend Register"
|
|
else
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "SUSP4R,AES Suspend Register"
|
|
endif
|
|
if (((per.l(ad:0x50060000))&0x10081)==0x10031)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "SUSP5R,AES Suspend Register"
|
|
elif (((per.l(ad:0x50060000))&0x10081)==0x10030)
|
|
wgroup.long 0x54++0x03
|
|
line.long 0x00 "SUSP5R,AES Suspend Register"
|
|
else
|
|
hgroup.long 0x54++0x03
|
|
hide.long 0x00 "SUSP5R,AES Suspend Register"
|
|
endif
|
|
if (((per.l(ad:0x50060000))&0x10081)==0x10031)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SUSP6R,AES Suspend Register"
|
|
elif (((per.l(ad:0x50060000))&0x10081)==0x10030)
|
|
wgroup.long 0x58++0x03
|
|
line.long 0x00 "SUSP6R,AES Suspend Register"
|
|
else
|
|
hgroup.long 0x58++0x03
|
|
hide.long 0x00 "SUSP6R,AES Suspend Register"
|
|
endif
|
|
if (((per.l(ad:0x50060000))&0x10081)==0x10031)
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "SUSP7R,AES Suspend Register"
|
|
elif (((per.l(ad:0x50060000))&0x10081)==0x10030)
|
|
wgroup.long 0x5C++0x03
|
|
line.long 0x00 "SUSP7R,AES Suspend Register"
|
|
else
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "SUSP7R,AES Suspend Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F756*")||cpuis("STM32F77*")||cpuis("STM32F750*"))
|
|
tree "CRYP (Cryptographic Processor)"
|
|
base ad:0x50060000
|
|
width 12.
|
|
sif (cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F7*")||cpuis("STM32F479*"))
|
|
sif cpuis("STM32F77*")||cpuis("STM32F750*")
|
|
if ((per.l(ad:0x50060000+0x04)&0x10)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,CRYP Control Register"
|
|
bitfld.long 0x00 16.--17. " GCM_CCMPH ,GCM_CCM phase" "Init,Header,Payload,Final"
|
|
bitfld.long 0x00 15. " CRYPEN ,Cryptographic processor enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " FFLUSH ,FIFO flush" "No effect,Flush"
|
|
bitfld.long 0x00 8.--9. " KEYSIZE ,Key size selection (AES mode only)" "128-bit,192-bit,256-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 6.--7. " DATATYPE ,Data type selection" "32-bit,16-bit,8-bit,1-bit"
|
|
bitfld.long 0x00 3.--5. 19. " ALGOMODE ,Algorithm mode" "TDES-ECB,TDES-CBC,DES-ECB,DES-CBC,AES-ECB,AES-CBC,AES-CTR,AES-Key,GCM,CCM,?..."
|
|
bitfld.long 0x00 2. " ALGODIR ,Algorithm direction" "Encryption,Decryption"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,CRYP Control Register"
|
|
bitfld.long 0x00 16.--17. " GCM_CCMPH ,GCM_CCM phase" "Init,Header,Payload,Final"
|
|
bitfld.long 0x00 15. " CRYPEN ,Cryptographic processor enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " FFLUSH ,FIFO flush" "No effect,Flush"
|
|
rbitfld.long 0x00 8.--9. " KEYSIZE ,Key size selection (AES mode only)" "128-bit,192-bit,256-bit,?..."
|
|
newline
|
|
rbitfld.long 0x00 6.--7. " DATATYPE ,Data type selection" "32-bit,16-bit,8-bit,1-bit"
|
|
rbitfld.long 0x00 3.--5. 19. " ALGOMODE ,Algorithm mode" "TDES-ECB,TDES-CBC,DES-ECB,DES-CBC,AES-ECB,AES-CBC,AES-CTR,AES-Key,GCM,CCM,?..."
|
|
rbitfld.long 0x00 2. " ALGODIR ,Algorithm direction" "Encryption,Decryption"
|
|
endif
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,CRYP Control Register"
|
|
bitfld.long 0x00 16.--17. " GCM_CCMPH ,GCM_CCM phase" "Init,Header,Payload,Final"
|
|
bitfld.long 0x00 15. " CRYPEN ,Cryptographic processor enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " FFLUSH ,FIFO flush" "No effect,Flush"
|
|
bitfld.long 0x00 8.--9. " KEYSIZE ,Key size selection (AES mode only)" "128-bit,192-bit,256-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 6.--7. " DATATYPE ,Data type selection" "32-bit,16-bit,8-bit,1-bit"
|
|
bitfld.long 0x00 3.--5. 19. " ALGOMODE ,Algorithm mode" "TDES-ECB,TDES-CBC,DES-ECB,DES-CBC,AES-ECB,AES-CBC,AES-CTR,AES-Key,GCM,CCM,?..."
|
|
bitfld.long 0x00 2. " ALGODIR ,Algorithm direction" "Encryption,Decryption"
|
|
endif
|
|
elif (cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32F750*"))
|
|
if ((per.l(ad:0x50060000+0x04)&0x10)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,CRYP Control Register"
|
|
bitfld.long 0x00 16.--17. " GCM_CCMPH ,GCM_CCM phase" "Init,Header,Payload,Final"
|
|
bitfld.long 0x00 15. " CRYPEN ,Cryptographic processor enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " FFLUSH ,FIFO flush" "No effect,Flush"
|
|
bitfld.long 0x00 8.--9. " KEYSIZE ,Key size selection (AES mode only)" "128-bit,192-bit,256-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 6.--7. " DATATYPE ,Data type selection" "32-bit,16-bit,8-bit,1-bit"
|
|
bitfld.long 0x00 3.--5. 19. " ALGOMODE ,Algorithm mode" "TDES-ECB,TDES-CBC,DES-ECB,DES-CBC,AES-ECB,AES-CBC,AES-CTR,AES-Key,AES-GCM,AES-CCM,?..."
|
|
bitfld.long 0x00 2. " ALGODIR ,Algorithm direction" "Encryption,Decryption"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,CRYP Control Register"
|
|
bitfld.long 0x00 16.--17. " GCM_CCMPH ,GCM_CCM phase" "Init,Header,Payload,Final"
|
|
bitfld.long 0x00 15. " CRYPEN ,Cryptographic processor enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " FFLUSH ,FIFO flush" "No effect,Flush"
|
|
rbitfld.long 0x00 8.--9. " KEYSIZE ,Key size selection (AES mode only)" "128-bit,192-bit,256-bit,?..."
|
|
newline
|
|
rbitfld.long 0x00 6.--7. " DATATYPE ,Data type selection" "32-bit,16-bit,8-bit,1-bit"
|
|
rbitfld.long 0x00 3.--5. 19. " ALGOMODE ,Algorithm mode" "TDES-ECB,TDES-CBC,DES-ECB,DES-CBC,AES-ECB,AES-CBC,AES-CTR,AES-Key,AES-GCM,AES-CCM,?..."
|
|
rbitfld.long 0x00 2. " ALGODIR ,Algorithm direction" "Encryption,Decryption"
|
|
endif
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,CRYP Control Register"
|
|
bitfld.long 0x00 15. " CRYPEN ,Cryptographic processor enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " FFLUSH ,FIFO flush" "No effect,Flush"
|
|
bitfld.long 0x00 8.--9. " KEYSIZE ,Key size selection (AES mode only)" "128-bit,192-bit,256-bit,?..."
|
|
bitfld.long 0x00 6.--7. " DATATYPE ,Data type selection" "32-bit,16-bit,8-bit,1-bit"
|
|
newline
|
|
bitfld.long 0x00 3.--5. " ALGOMODE ,Algorithm mode" "TDES-ECB,TDES-CBC,DES-ECB,DES-CBC,AES-ECB,AES-CBC,AES-CTR,AES-Key"
|
|
bitfld.long 0x00 2. " ALGODIR ,Algorithm direction" "Encryption,Decryption"
|
|
endif
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SR,CRYP Status Register"
|
|
bitfld.long 0x00 4. " BUSY ,Busy bit" "Not busy,Busy"
|
|
bitfld.long 0x00 3. " OFFU ,Output FIFO full flag" "Not full,Full"
|
|
bitfld.long 0x00 2. " OFNE ,Output FIFO not empty flag" "Empty,Not empty"
|
|
bitfld.long 0x00 1. " IFNF ,Input FIFO not full flag" "Full,Not full"
|
|
newline
|
|
bitfld.long 0x00 0. " IFEM ,Input FIFO empty flag" "Not empty,Empty"
|
|
newline
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "DIN,CRYP Data Input Register"
|
|
in
|
|
newline
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "DOUT,CRYP Data Output Register"
|
|
in
|
|
newline
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "DMACR,CRYP DMA Control Register"
|
|
bitfld.long 0x00 1. " DOEN ,DMA output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DIEN ,DMA input enable" "Disabled,Enabled"
|
|
line.long 0x04 "IMSCR,CRYP Interrupt Mask Set/Clear Register"
|
|
bitfld.long 0x04 1. " OUTIM ,Output FIFO service interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " INIM ,Input FIFO service interrupt mask" "Masked,Not masked"
|
|
rgroup.long 0x18++0x07
|
|
line.long 0x00 "RISR,CRYP Raw Interrupt Status Register"
|
|
bitfld.long 0x00 1. " OUTRIS ,Output FIFO service raw interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " INRIS ,Input FIFO service raw interrupt status" "Not pending,Pending"
|
|
line.long 0x04 "MISR,CRYP Masked Interrupt Status Register"
|
|
bitfld.long 0x04 1. " OUTMIS ,Output FIFO service masked interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x04 0. " INMIS ,Input FIFO service masked interrupt status" "Not pending,Pending"
|
|
wgroup.long 0x20++0x1F
|
|
line.long 0x00 "K0LR,Key 0 Leftmost Register"
|
|
line.long 0x04 "K0RR,Key 0 Rightmost Register"
|
|
line.long 0x08 "K1LR,Key 1 Leftmost Register"
|
|
line.long 0x0C "K1RR,Key 1 Rightmost Register"
|
|
line.long 0x10 "K2LR,Key 2 Leftmost Register"
|
|
line.long 0x14 "K2RR,Key 2 Rightmost Register"
|
|
line.long 0x18 "K3LR,Key 3 Leftmost Register"
|
|
line.long 0x1C "K3RR,Key 3 Rightmost Register"
|
|
if ((per.l((ad:0x50060000+0x04))&0x10)==0x00)
|
|
group.long 0x40++0x0F
|
|
line.long 0x00 "IV0LR,Initialization Vector 0 Leftmost Register"
|
|
line.long 0x04 "IV0RR,Initialization Vector 0 Rightmost Register"
|
|
line.long 0x08 "IV1LR,Initialization Vector 1 Leftmost Register"
|
|
line.long 0x0C "IV1RR,Initialization Vector 1 Rightmost Register"
|
|
else
|
|
rgroup.long 0x40++0x0F
|
|
line.long 0x00 "IV0LR,Initialization Vector 0 Leftmost Register"
|
|
line.long 0x04 "IV0RR,Initialization Vector 0 Rightmost Register"
|
|
line.long 0x08 "IV1LR,Initialization Vector 1 Leftmost Register"
|
|
line.long 0x0C "IV1RR,Initialization Vector 1 Rightmost Register"
|
|
endif
|
|
sif (cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F7*")||cpuis("STM32F479*"))
|
|
sif !cpuis("STM32F750*")
|
|
if ((per.l(ad:0x50060000)&0x80038)==0x80000)||(((per.l(ad:0x50060000)&0x80038)==0x80008))
|
|
group.long 0x50++0x1F
|
|
line.long 0x00 "CSGCMCCM0R,Context Swap Register 0 For GCM/GMAC Or CCM/CMAC"
|
|
line.long 0x04 "CSGCMCCM1R,Context Swap Register 1 For GCM/GMAC Or CCM/CMAC"
|
|
line.long 0x08 "CSGCMCCM2R,Context Swap Register 2 For GCM/GMAC Or CCM/CMAC"
|
|
line.long 0x0C "CSGCMCCM3R,Context Swap Register 3 For GCM/GMAC Or CCM/CMAC"
|
|
line.long 0x10 "CSGCMCCM4R,Context Swap Register 4 For GCM/GMAC Or CCM/CMAC"
|
|
line.long 0x14 "CSGCMCCM5R,Context Swap Register 5 For GCM/GMAC Or CCM/CMAC"
|
|
line.long 0x18 "CSGCMCCM6R,Context Swap Register 6 For GCM/GMAC Or CCM/CMAC"
|
|
line.long 0x1C "CSGCMCCM7R,Context Swap Register 7 For GCM/GMAC Or CCM/CMAC"
|
|
else
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "CSGCMCCM0R,Context Swap Register 0 For GCM/GMAC Or CCM/CMAC"
|
|
hgroup.long 0x54++0x03
|
|
hide.long 0x00 "CSGCMCCM1R,Context Swap Register 1 For GCM/GMAC Or CCM/CMAC"
|
|
hgroup.long 0x58++0x03
|
|
hide.long 0x00 "CSGCMCCM2R,Context Swap Register 2 For GCM/GMAC Or CCM/CMAC"
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "CSGCMCCM3R,Context Swap Register 3 For GCM/GMAC Or CCM/CMAC"
|
|
hgroup.long 0x60++0x03
|
|
hide.long 0x00 "CSGCMCCM4R,Context Swap Register 4 For GCM/GMAC Or CCM/CMAC"
|
|
hgroup.long 0x64++0x03
|
|
hide.long 0x00 "CSGCMCCM5R,Context Swap Register 5 For GCM/GMAC Or CCM/CMAC"
|
|
hgroup.long 0x68++0x03
|
|
hide.long 0x00 "CSGCMCCM6R,Context Swap Register 6 For GCM/GMAC Or CCM/CMAC"
|
|
hgroup.long 0x6C++0x03
|
|
hide.long 0x00 "CSGCMCCM7R,Context Swap Register 7 For GCM/GMAC Or CCM/CMAC"
|
|
endif
|
|
if ((per.l(ad:0x50060000)&0x80038)==0x80000)
|
|
group.long 0x70++0x1F
|
|
line.long 0x00 "CSGCM0R,Context Swap Register 0 For GCM/GMAC"
|
|
line.long 0x04 "CSGCM1R,Context Swap Register 1 For GCM/GMAC"
|
|
line.long 0x08 "CSGCM2R,Context Swap Register 2 For GCM/GMAC"
|
|
line.long 0x0C "CSGCM3R,Context Swap Register 3 For GCM/GMAC"
|
|
line.long 0x10 "CSGCM4R,Context Swap Register 4 For GCM/GMAC"
|
|
line.long 0x14 "CSGCM5R,Context Swap Register 5 For GCM/GMAC"
|
|
line.long 0x18 "CSGCM6R,Context Swap Register 6 For GCM/GMAC"
|
|
line.long 0x1C "CSGCM7R,Context Swap Register 7 For GCM/GMAC"
|
|
else
|
|
hgroup.long 0x70++0x03
|
|
hide.long 0x00 "CSGCM0R,Context Swap Register 0 For GCM/GMAC"
|
|
hgroup.long 0x74++0x03
|
|
hide.long 0x00 "CSGCM1R,Context Swap Register 1 For GCM/GMAC"
|
|
hgroup.long 0x78++0x03
|
|
hide.long 0x00 "CSGCM2R,Context Swap Register 2 For GCM/GMAC"
|
|
hgroup.long 0x7C++0x03
|
|
hide.long 0x00 "CSGCM3R,Context Swap Register 3 For GCM/GMAC"
|
|
hgroup.long 0x80++0x03
|
|
hide.long 0x00 "CSGCM4R,Context Swap Register 4 For GCM/GMAC"
|
|
hgroup.long 0x84++0x03
|
|
hide.long 0x00 "CSGCM5R,Context Swap Register 5 For GCM/GMAC"
|
|
hgroup.long 0x88++0x03
|
|
hide.long 0x00 "CSGCM6R,Context Swap Register 6 For GCM/GMAC"
|
|
hgroup.long 0x8C++0x03
|
|
hide.long 0x00 "CSGCM7R,Context Swap Register 7 For GCM/GMAC"
|
|
endif
|
|
endif
|
|
elif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
if ((per.l(ad:0x50060000)&0x80038)==0x80000)||(((per.l(ad:0x50060000)&0x80038)==0x80008))
|
|
group.long 0x50++0x1F
|
|
line.long 0x00 "CSGCMCCM0R,Context Swap Register 0 For GCM/GMAC Or CCM/CMAC"
|
|
line.long 0x04 "CSGCMCCM1R,Context Swap Register 1 For GCM/GMAC Or CCM/CMAC"
|
|
line.long 0x08 "CSGCMCCM2R,Context Swap Register 2 For GCM/GMAC Or CCM/CMAC"
|
|
line.long 0x0C "CSGCMCCM3R,Context Swap Register 3 For GCM/GMAC Or CCM/CMAC"
|
|
line.long 0x10 "CSGCMCCM4R,Context Swap Register 4 For GCM/GMAC Or CCM/CMAC"
|
|
line.long 0x14 "CSGCMCCM5R,Context Swap Register 5 For GCM/GMAC Or CCM/CMAC"
|
|
line.long 0x18 "CSGCMCCM6R,Context Swap Register 6 For GCM/GMAC Or CCM/CMAC"
|
|
line.long 0x1C "CSGCMCCM7R,Context Swap Register 7 For GCM/GMAC Or CCM/CMAC"
|
|
else
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "CSGCMCCM0R,Context Swap Register 0 For GCM/GMAC Or CCM/CMAC"
|
|
hgroup.long 0x54++0x03
|
|
hide.long 0x00 "CSGCMCCM1R,Context Swap Register 1 For GCM/GMAC Or CCM/CMAC"
|
|
hgroup.long 0x58++0x03
|
|
hide.long 0x00 "CSGCMCCM2R,Context Swap Register 2 For GCM/GMAC Or CCM/CMAC"
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "CSGCMCCM3R,Context Swap Register 3 For GCM/GMAC Or CCM/CMAC"
|
|
hgroup.long 0x60++0x03
|
|
hide.long 0x00 "CSGCMCCM4R,Context Swap Register 4 For GCM/GMAC Or CCM/CMAC"
|
|
hgroup.long 0x64++0x03
|
|
hide.long 0x00 "CSGCMCCM5R,Context Swap Register 5 For GCM/GMAC Or CCM/CMAC"
|
|
hgroup.long 0x68++0x03
|
|
hide.long 0x00 "CSGCMCCM6R,Context Swap Register 6 For GCM/GMAC Or CCM/CMAC"
|
|
hgroup.long 0x6C++0x03
|
|
hide.long 0x00 "CSGCMCCM7R,Context Swap Register 7 For GCM/GMAC Or CCM/CMAC"
|
|
endif
|
|
if ((per.l(ad:0x50060000)&0x80038)==0x80000)
|
|
group.long 0x70++0x1F
|
|
line.long 0x00 "CSGCM0R,Context Swap Register 0 For GCM/GMAC"
|
|
line.long 0x04 "CSGCM1R,Context Swap Register 1 For GCM/GMAC"
|
|
line.long 0x08 "CSGCM2R,Context Swap Register 2 For GCM/GMAC"
|
|
line.long 0x0C "CSGCM3R,Context Swap Register 3 For GCM/GMAC"
|
|
line.long 0x10 "CSGCM4R,Context Swap Register 4 For GCM/GMAC"
|
|
line.long 0x14 "CSGCM5R,Context Swap Register 5 For GCM/GMAC"
|
|
line.long 0x18 "CSGCM6R,Context Swap Register 6 For GCM/GMAC"
|
|
line.long 0x1C "CSGCM7R,Context Swap Register 7 For GCM/GMAC"
|
|
else
|
|
hgroup.long 0x70++0x03
|
|
hide.long 0x00 "CSGCM0R,Context Swap Register 0 For GCM/GMAC"
|
|
hgroup.long 0x74++0x03
|
|
hide.long 0x00 "CSGCM1R,Context Swap Register 1 For GCM/GMAC"
|
|
hgroup.long 0x78++0x03
|
|
hide.long 0x00 "CSGCM2R,Context Swap Register 2 For GCM/GMAC"
|
|
hgroup.long 0x7C++0x03
|
|
hide.long 0x00 "CSGCM3R,Context Swap Register 3 For GCM/GMAC"
|
|
hgroup.long 0x80++0x03
|
|
hide.long 0x00 "CSGCM4R,Context Swap Register 4 For GCM/GMAC"
|
|
hgroup.long 0x84++0x03
|
|
hide.long 0x00 "CSGCM5R,Context Swap Register 5 For GCM/GMAC"
|
|
hgroup.long 0x88++0x03
|
|
hide.long 0x00 "CSGCM6R,Context Swap Register 6 For GCM/GMAC"
|
|
hgroup.long 0x8C++0x03
|
|
hide.long 0x00 "CSGCM7R,Context Swap Register 7 For GCM/GMAC"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "HASH (Hash Processor)"
|
|
base ad:0x50060400
|
|
width 5.
|
|
if (((per.l(ad:0x50060400))&0x1000)==0x1000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 16. " LKEY ,Long key selection" "Short,Long"
|
|
sif (cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F7*")||cpuis("STM32F479*")||cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
newline
|
|
bitfld.long 0x00 13. " MDMAT ,Multiple DMA transfers" "Single,Multiple"
|
|
endif
|
|
newline
|
|
rbitfld.long 0x00 12. " DINNE ,DIN not empty" "Empty,Not empty"
|
|
rbitfld.long 0x00 8.--11. " NBW ,Number of words already pushed" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
newline
|
|
sif (cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F7*")||cpuis("STM32F479*")||cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
bitfld.long 0x00 7. 18. " ALGO ,Algorithm selection" "SHA-1,MD5,SHA224,SHA256"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 7. " ALGO ,Algorithm selection" "SHA-1,MD5"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 6. " MODE ,Mode selection" "Hash,HMAC"
|
|
bitfld.long 0x00 4.--5. " DATATYPE ,Data type selection" "32-bit data,16-bit data,8-bit data,Bit data"
|
|
bitfld.long 0x00 3. " DMAE ,DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INIT ,Initialize message digest calculation" "No effect,Initialize"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 16. " LKEY ,Long key selection" "Short,Long"
|
|
sif (cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F7*")||cpuis("STM32F479*")||cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
newline
|
|
bitfld.long 0x00 13. " MDMAT ,Multiple DMA transfers" "Single,Multiple"
|
|
endif
|
|
newline
|
|
rbitfld.long 0x00 12. " DINNE ,DIN not empty" "Empty,Not empty"
|
|
rbitfld.long 0x00 8.--11. " NBW ,Number of words already pushed" "0,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
newline
|
|
sif (cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F7*")||cpuis("STM32F479*"))
|
|
bitfld.long 0x00 7. 18. " ALGO ,Algorithm selection" "SHA-1,MD5,SHA224,SHA256"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 7. " ALGO ,Algorithm selection" "SHA-1,MD5"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 6. " MODE ,Mode selection" "Hash,HMAC"
|
|
bitfld.long 0x00 4.--5. " DATATYPE ,Data type selection" "32-bit data,16-bit data,8-bit data,Bit data"
|
|
bitfld.long 0x00 3. " DMAE ,DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INIT ,Initialize message digest calculation" "No effect,Initialize"
|
|
endif
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "DIN,Data Input Register"
|
|
line.long 0x04 "STR,Start Register"
|
|
bitfld.long 0x04 8. " DCAL ,Digest calculation" "No effect,Start"
|
|
bitfld.long 0x04 0.--4. " NBLW ,Number of valid bits in the last word of the message" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32F7*"))
|
|
if (((per.l(ad:0x50060400)&0x40080)==0x00))
|
|
rgroup.long 0x0C++0x13
|
|
line.long 0x00 "HR0,Digest Register H0"
|
|
line.long 0x04 "HR1,Digest Register H1"
|
|
line.long 0x08 "HR2,Digest Register H2"
|
|
line.long 0x0C "HR3,Digest Register H3"
|
|
line.long 0x10 "HR4,Digest Register H4"
|
|
rgroup.long 0x310++0x13
|
|
line.long 0x00 "HR0,Digest Register H0"
|
|
line.long 0x04 "HR1,Digest Register H1"
|
|
line.long 0x08 "HR2,Digest Register H2"
|
|
line.long 0x0C "HR3,Digest Register H3"
|
|
line.long 0x10 "HR4,Digest Register H4"
|
|
elif (((per.l(ad:0x50060400)&0x40080)==0x80))
|
|
rgroup.long 0x0C++0x0F
|
|
line.long 0x00 "HR0,Digest Register H0"
|
|
line.long 0x04 "HR1,Digest Register H1"
|
|
line.long 0x08 "HR2,Digest Register H2"
|
|
line.long 0x0C "HR3,Digest Register H3"
|
|
rgroup.long 0x310++0x0F
|
|
line.long 0x00 "HR0,Digest Register H0"
|
|
line.long 0x04 "HR1,Digest Register H1"
|
|
line.long 0x08 "HR2,Digest Register H2"
|
|
line.long 0x0C "HR3,Digest Register H3"
|
|
elif (((per.l(ad:0x50060400)&0x40080)==0x40000))
|
|
rgroup.long 0x0C++0x13
|
|
line.long 0x00 "HR0,Digest Register H0"
|
|
line.long 0x04 "HR1,Digest Register H1"
|
|
line.long 0x08 "HR2,Digest Register H2"
|
|
line.long 0x0C "HR3,Digest Register H3"
|
|
line.long 0x10 "HR4,Digest Register H4"
|
|
rgroup.long 0x310++0x1B
|
|
line.long 0x00 "HR0,Digest Register H0"
|
|
line.long 0x04 "HR1,Digest Register H1"
|
|
line.long 0x08 "HR2,Digest Register H2"
|
|
line.long 0x0C "HR3,Digest Register H3"
|
|
line.long 0x10 "HR4,Digest Register H4"
|
|
line.long 0x14 "HR5,Digest Register H5"
|
|
line.long 0x18 "HR6,Digest Register H6"
|
|
else
|
|
rgroup.long 0x0C++0x13
|
|
line.long 0x00 "HR0,Digest Register H0"
|
|
line.long 0x04 "HR1,Digest Register H1"
|
|
line.long 0x08 "HR2,Digest Register H2"
|
|
line.long 0x0C "HR3,Digest Register H3"
|
|
line.long 0x10 "HR4,Digest Register H4"
|
|
rgroup.long 0x310++0x1F
|
|
line.long 0x00 "HR0,Digest Register H0"
|
|
line.long 0x04 "HR1,Digest Register H1"
|
|
line.long 0x08 "HR2,Digest Register H2"
|
|
line.long 0x0C "HR3,Digest Register H3"
|
|
line.long 0x10 "HR4,Digest Register H4"
|
|
line.long 0x14 "HR5,Digest Register H5"
|
|
line.long 0x18 "HR6,Digest Register H6"
|
|
line.long 0x1C "HR7,Digest Register H7"
|
|
endif
|
|
else
|
|
rgroup.long 0x0C++0x13
|
|
line.long 0x00 "HR0,Digest Register H0"
|
|
line.long 0x04 "HR1,Digest Register H1"
|
|
line.long 0x08 "HR2,Digest Register H2"
|
|
line.long 0x0C "HR3,Digest Register H3"
|
|
line.long 0x10 "HR4,Digest Register H4"
|
|
rgroup.long 0x310++0x13
|
|
line.long 0x00 "HR0,Digest Register H0"
|
|
line.long 0x04 "HR1,Digest Register H1"
|
|
line.long 0x08 "HR2,Digest Register H2"
|
|
line.long 0x0C "HR3,Digest Register H3"
|
|
line.long 0x10 "HR4,Digest Register H4"
|
|
sif (cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F479*"))
|
|
rgroup.long 0x324++0x0B
|
|
line.long 0x00 "HR5,Digest Register H5"
|
|
line.long 0x04 "HR6,Digest Register H6"
|
|
line.long 0x08 "HR7,Digest Register H7"
|
|
endif
|
|
endif
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "IMR,Interrupt Mask Register"
|
|
sif (cpuis("STM32F405*")||cpuis("STM32F407*")||cpuis("STM32F41*")||cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F479*")||cpuis("STM32F7*")||cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
bitfld.long 0x00 1. " DCIE ,Digest calculation completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DINIE ,Data input interrupt enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 1. " DCIM ,Digest calculation completion interrupt mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DINIM ,Data input interrupt mask" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "SR,Status Register"
|
|
rbitfld.long 0x04 3. " BUSY ,Busy bit" "Not busy,Busy"
|
|
rbitfld.long 0x04 2. " DMAS ,DMA interface/transfer status" "Disabled/No transfer,Enabled/Transfer"
|
|
bitfld.long 0x04 1. " DCIS ,Digest calculation completion interrupt status" "Not completed,Completed"
|
|
bitfld.long 0x04 0. " DINIS ,Data input interrupt status" "Not ready,Ready"
|
|
width 7.
|
|
tree "Context Swap Registers"
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32F7*"))
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "CSR0,Context Swap Register 0"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "CSR1,Context Swap Register 1"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "CSR2,Context Swap Register 2"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "CSR3,Context Swap Register 3"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "CSR4,Context Swap Register 4"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "CSR5,Context Swap Register 5"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "CSR6,Context Swap Register 6"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "CSR7,Context Swap Register 7"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "CSR8,Context Swap Register 8"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "CSR9,Context Swap Register 9"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "CSR10,Context Swap Register 10"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "CSR11,Context Swap Register 11"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "CSR12,Context Swap Register 12"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "CSR13,Context Swap Register 13"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "CSR14,Context Swap Register 14"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "CSR15,Context Swap Register 15"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "CSR16,Context Swap Register 16"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "CSR17,Context Swap Register 17"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "CSR18,Context Swap Register 18"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "CSR19,Context Swap Register 19"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "CSR20,Context Swap Register 20"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "CSR21,Context Swap Register 21"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "CSR22,Context Swap Register 22"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "CSR23,Context Swap Register 23"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "CSR24,Context Swap Register 24"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "CSR25,Context Swap Register 25"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "CSR26,Context Swap Register 26"
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "CSR27,Context Swap Register 27"
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "CSR28,Context Swap Register 28"
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "CSR29,Context Swap Register 29"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "CSR30,Context Swap Register 30"
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "CSR31,Context Swap Register 31"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "CSR32,Context Swap Register 32"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "CSR33,Context Swap Register 33"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "CSR34,Context Swap Register 34"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "CSR35,Context Swap Register 35"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "CSR36,Context Swap Register 36"
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "CSR37,Context Swap Register 37"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "CSR38,Context Swap Register 38"
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "CSR39,Context Swap Register 39"
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "CSR40,Context Swap Register 40"
|
|
group.long 0x19C++0x03
|
|
line.long 0x00 "CSR41,Context Swap Register 41"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "CSR42,Context Swap Register 42"
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "CSR43,Context Swap Register 43"
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "CSR44,Context Swap Register 44"
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "CSR45,Context Swap Register 45"
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "CSR46,Context Swap Register 46"
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "CSR47,Context Swap Register 47"
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "CSR48,Context Swap Register 48"
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "CSR49,Context Swap Register 49"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "CSR50,Context Swap Register 50"
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "CSR51,Context Swap Register 51"
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "CSR52,Context Swap Register 52"
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "CSR53,Context Swap Register 53"
|
|
else
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "CSR0,Context Swap Register 0"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "CSR1,Context Swap Register 1"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "CSR2,Context Swap Register 2"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "CSR3,Context Swap Register 3"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "CSR4,Context Swap Register 4"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "CSR5,Context Swap Register 5"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "CSR6,Context Swap Register 6"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "CSR7,Context Swap Register 7"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "CSR8,Context Swap Register 8"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "CSR9,Context Swap Register 9"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "CSR10,Context Swap Register 10"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "CSR11,Context Swap Register 11"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "CSR12,Context Swap Register 12"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "CSR13,Context Swap Register 13"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "CSR14,Context Swap Register 14"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "CSR15,Context Swap Register 15"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "CSR16,Context Swap Register 16"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "CSR17,Context Swap Register 17"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "CSR18,Context Swap Register 18"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "CSR19,Context Swap Register 19"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "CSR20,Context Swap Register 20"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "CSR21,Context Swap Register 21"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "CSR22,Context Swap Register 22"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "CSR23,Context Swap Register 23"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "CSR24,Context Swap Register 24"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "CSR25,Context Swap Register 25"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "CSR26,Context Swap Register 26"
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "CSR27,Context Swap Register 27"
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "CSR28,Context Swap Register 28"
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "CSR29,Context Swap Register 29"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "CSR30,Context Swap Register 30"
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "CSR31,Context Swap Register 31"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "CSR32,Context Swap Register 32"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "CSR33,Context Swap Register 33"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "CSR34,Context Swap Register 34"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "CSR35,Context Swap Register 35"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "CSR36,Context Swap Register 36"
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "CSR37,Context Swap Register 37"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "CSR38,Context Swap Register 38"
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "CSR39,Context Swap Register 39"
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "CSR40,Context Swap Register 40"
|
|
group.long 0x19C++0x03
|
|
line.long 0x00 "CSR41,Context Swap Register 41"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "CSR42,Context Swap Register 42"
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "CSR43,Context Swap Register 43"
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "CSR44,Context Swap Register 44"
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "CSR45,Context Swap Register 45"
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "CSR46,Context Swap Register 46"
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "CSR47,Context Swap Register 47"
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "CSR48,Context Swap Register 48"
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "CSR49,Context Swap Register 49"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "CSR50,Context Swap Register 50"
|
|
endif
|
|
sif (cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F479*"))
|
|
group.long 0x1C4++0x0B
|
|
line.long 0x00 "CSR51,Context Swap Register 51"
|
|
line.long 0x04 "CSR52,Context Swap Register 52"
|
|
line.long 0x08 "CSR53,Context Swap Register 53"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.open "ACT (Advanced-control Timers)"
|
|
tree "TIM 1"
|
|
base ad:0x40010000
|
|
width 7.
|
|
if ((per.w(ad:0x40010000)&0x60)!=0x00)||((per.w(ad:0x40010000+0x08)&0x07)==(0x01||0x02||0x03))
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,Control Register 1"
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Not remapped,Remapped"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
newline
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
newline
|
|
rbitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
newline
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,Control Register 1"
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Not remapped,Remapped"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
newline
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
newline
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
newline
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.l(ad:0x40010000+0x44)&0x03)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 20.--23. " MMS2 ,Master mode selection 2" "Reset,Enable,Update,Compare Pulse,Compare - OC1REF,Compare - OC2REF,Compare - OC3REF,Compare - OC4REF,Compare - OC5REF,Compare - OC6REF,Compare Pulse - OC4REF,Compare Pulse - OC6REF,Compare Pulse - OC4REF or OC6REF rising,Compare Pulse - OC4REF rising or OC6REF falling,Compare Pulse - OC5REF or OC6REF rising,Compare Pulse - OC5REF rising or OC6REF falling"
|
|
bitfld.long 0x00 18. " OIS6 ,OC6 output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. " OIS5 ,OC5 output" "0,1"
|
|
bitfld.long 0x00 14. " OIS4 ,OC4 output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. " OIS3N ,OC3N output" "0,1"
|
|
bitfld.long 0x00 12. " OIS3 ,OC3 output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " OIS2N ,OC2N output" "0,1"
|
|
bitfld.long 0x00 10. " OIS2 ,OC2 output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. " OIS1N ,OC1N output" "0,1"
|
|
bitfld.long 0x00 8. " OIS1 ,OC1 output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " TI1S ,TI1 selection" "CH1,CH1/CH2/CH3"
|
|
bitfld.long 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,OC3REF,OC4REF"
|
|
newline
|
|
bitfld.long 0x00 3. " CCDS ,Capture/Compare DMA selection" "CCx,Update"
|
|
bitfld.long 0x00 2. " CCUS ,Capture/Compare control update selection" "COMG bit only,COMG bit/Rising edge"
|
|
newline
|
|
bitfld.long 0x00 0. " CCPC ,Capture/Compare preloaded control" "Not preloaded,Preloaded"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 20.--23. " MMS2 ,Master mode selection 2" "Reset,Enable,Update,Compare Pulse,Compare - OC1REF,Compare - OC2REF,Compare - OC3REF,Compare - OC4REF,Compare - OC5REF,Compare - OC6REF,Compare Pulse - OC4REF,Compare Pulse - OC6REF,Compare Pulse - OC4REF or OC6REF rising,Compare Pulse - OC4REF rising or OC6REF falling,Compare Pulse - OC5REF or OC6REF rising,Compare Pulse - OC5REF rising or OC6REF falling"
|
|
rbitfld.long 0x00 18. " OIS6 ,OC6 output" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 16. " OIS5 ,OC5 output" "0,1"
|
|
rbitfld.long 0x00 14. " OIS4 ,OC4 output" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 13. " OIS3N ,OC3N output" "0,1"
|
|
rbitfld.long 0x00 12. " OIS3 ,OC3 output" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 11. " OIS2N ,OC2N output" "0,1"
|
|
rbitfld.long 0x00 10. " OIS2 ,OC2 output" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 9. " OIS1N ,OC1N output" "0,1"
|
|
rbitfld.long 0x00 8. " OIS1 ,OC1 output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " TI1S ,TI1 selection" "CH1,CH1/CH2/CH3"
|
|
bitfld.long 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,OC3REF,OC4REF"
|
|
newline
|
|
bitfld.long 0x00 3. " CCDS ,Capture/Compare DMA selection" "CCx,Update"
|
|
bitfld.long 0x00 2. " CCUS ,Capture/Compare control update selection" "COMG bit only,COMG bit/Rising edge"
|
|
newline
|
|
bitfld.long 0x00 0. " CCPC ,Capture/Compare preloaded control" "Not preloaded,Preloaded"
|
|
endif
|
|
if ((per.w(ad:0x40010000+0x08)&0x07)!=0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SMCR,Slave Mode Control Register"
|
|
bitfld.long 0x00 15. " ETP ,External trigger polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " ETF ,External trigger filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 7. " MSM ,Master/slave mode" "No action,TRGO delayed"
|
|
sif !cpuis("STM32F730*8")
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
rbitfld.long 0x00 4.--6. 20.--21. " TS ,Trigger selection" "TIM5,TIM2,TIM3,TIM4,?..."
|
|
else
|
|
rbitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
endif
|
|
else
|
|
rbitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 0.--2. 16. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock,Reset + Trigger,?..."
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SMCR,Slave Mode Control Register"
|
|
bitfld.long 0x00 15. " ETP ,External trigger polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " ETF ,External trigger filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 7. " MSM ,Master/Slave mode" "No action,TRGO delayed"
|
|
sif !cpuis("STM32F730*8")
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 4.--6. 20.--21. " TS ,Trigger selection" "TIM5,TIM2,TIM3,TIM4,?..."
|
|
else
|
|
bitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
endif
|
|
else
|
|
bitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 0.--2. 16. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock,Reset + Trigger,?..."
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "DIER,DMA/Interrupt Enable Register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " COMDE ,COM DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " BIE ,Break interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 5. " COMIE ,COM interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
bitfld.long 0x00 17. " CC6IF ,Capture/Compare 6 interrupt flag input/output" "Not captured/Not matched,Captured/Matched"
|
|
bitfld.long 0x00 16. " CC5IF ,Capture/Compare 5 interrupt flag input/output" "Not captured/Not matched,Captured/Matched"
|
|
newline
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
bitfld.long 0x00 13. " SBIF ,System break interrupt flag" "Not occurred,Occurred"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 12. " CC4OF ,Capture/Compare 4 overcapture flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 11. " CC3OF ,Capture/Compare 3 overcapture flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " CC2OF ,Capture/Compare 2 overcapture flag" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 9. " CC1OF ,Capture/Compare 1 overcapture flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " B2IF ,Break 2 interrupt flag" "No break,Break"
|
|
bitfld.long 0x00 7. " BIF ,Break interrupt flag" "No break,Break"
|
|
newline
|
|
bitfld.long 0x00 6. " TIF ,Trigger interrupt flag" "No trigger,Trigger"
|
|
bitfld.long 0x00 5. " COMIF ,COM interrupt flag" "No COM,COM"
|
|
bitfld.long 0x00 4. " CC4IF ,Capture/Compare 4 interrupt flag input/output" "Not captured/Not matched,Captured/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " CC3IF ,Capture/Compare 3 interrupt flag input/output" "Not captured/Not matched,Captured/Matched"
|
|
bitfld.long 0x00 2. " CC2IF ,Capture/Compare 2 interrupt flag input/output" "Not captured/Not matched,Captured/Matched"
|
|
bitfld.long 0x00 1. " CC1IF ,Capture/Compare 1 interrupt flag input/output" "Not captured/Not matched,Captured/Matched"
|
|
newline
|
|
bitfld.long 0x00 0. " UIF ,Update interrupt flag" "Not updated,Updated"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "EGR,Event Generation Register"
|
|
bitfld.word 0x00 8. " B2G ,Break 2 generation" "No action,Break 2"
|
|
bitfld.word 0x00 7. " BG ,Break generation" "No action,Break"
|
|
bitfld.word 0x00 6. " TG ,Trigger generation" "No action,Trigger"
|
|
newline
|
|
bitfld.word 0x00 5. " COMG ,Capture/Compare control update generation" "No action,Update"
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 generation input/output" "No action/No action,Capture 4/compare 4"
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 generation input/output" "No action/No action,Capture 3/compare 3"
|
|
newline
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 generation input/output" "No action/No action,Capture 2/compare 2"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 generation input/output" "No action/No action,Capture 1/compare 1"
|
|
bitfld.word 0x00 0. " UG ,Update generation" "No action,Update"
|
|
if (((per.l((ad:0x40010000+0x18)))&0x303)==0x000)
|
|
if ((per.l(ad:0x40010000+0x20)&0x01)==0x00)&&((per.l(ad:0x40010000+0x20)&0x100)==0x00)
|
|
if ((per.l(ad:0x40010000+0x44)&0x300)!=0x300)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif ((per.l(ad:0x40010000+0x20)&0x01)==0x01)&&((per.l(ad:0x40010000+0x20)&0x100)==0x00)
|
|
if ((per.l(ad:0x40010000+0x44)&0x300)!=0x300)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif ((per.l(ad:0x40010000+0x20)&0x01)==0x00)&&((per.l(ad:0x40010000+0x20)&0x100)==0x100)
|
|
if ((per.l(ad:0x40010000+0x44)&0x300)!=0x300)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40010000+0x44)&0x300)!=0x300)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
elif (((per.l((ad:0x40010000+0x18)))&0x300)!=0x00)&&(((per.l((ad:0x40010000+0x18)))&0x03)!=0x00)
|
|
if ((per.l(ad:0x40010000+0x20)&0x01)==0x00)&&((per.l(ad:0x40010000+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40010000+0x20)&0x01)==0x01)&&((per.l(ad:0x40010000+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40010000+0x20)&0x01)==0x00)&&((per.l(ad:0x40010000+0x20)&0x100)==0x100)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.l((ad:0x40010000+0x18)))&0x300)==0x00)&&(((per.l((ad:0x40010000+0x18)))&0x03)!=0x00)
|
|
if ((per.l(ad:0x40010000+0x20)&0x01)==0x00)&&((per.l(ad:0x40010000+0x20)&0x100)==0x00)
|
|
if ((per.l(ad:0x40010000+0x44)&0x300)!=0x300)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif ((per.l(ad:0x40010000+0x20)&0x01)==0x01)&&((per.l(ad:0x40010000+0x20)&0x100)==0x00)
|
|
if ((per.l(ad:0x40010000+0x44)&0x300)!=0x300)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif ((per.l(ad:0x40010000+0x20)&0x01)==0x00)&&((per.l(ad:0x40010000+0x20)&0x100)==0x100)
|
|
if ((per.l(ad:0x40010000+0x44)&0x300)!=0x300)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40010000+0x44)&0x300)!=0x300)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40010000+0x20)&0x01)==0x00)&&((per.l(ad:0x40010000+0x20)&0x100)==0x00)
|
|
if ((per.l(ad:0x40010000+0x44)&0x300)!=0x300)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif ((per.l(ad:0x40010000+0x20)&0x01)==0x01)&&((per.l(ad:0x40010000+0x20)&0x100)==0x00)
|
|
if ((per.l(ad:0x40010000+0x44)&0x300)!=0x300)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif ((per.l(ad:0x40010000+0x20)&0x01)==0x00)&&((per.l(ad:0x40010000+0x20)&0x100)==0x100)
|
|
if ((per.l(ad:0x40010000+0x44)&0x300)!=0x300)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40010000+0x44)&0x300)!=0x300)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40010000+0x1C)&0x303)==0x00))
|
|
if ((per.l(ad:0x40010000+0x20)&0x1100)==0x00)
|
|
if ((per.l(ad:0x40010000+0x44)&0x300)!=0x300)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
elif ((per.l(ad:0x40010000+0x20)&0x1100)==0x100)
|
|
if ((per.l(ad:0x40010000+0x44)&0x300)!=0x300)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
elif ((per.l(ad:0x40010000+0x20)&0x1100)==0x1000)
|
|
if ((per.l(ad:0x40010000+0x44)&0x300)!=0x300)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40010000+0x44)&0x300)!=0x300)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
endif
|
|
elif (((per.l(ad:0x40010000+0x1C)&0x300)==0x00))&&(((per.l(ad:0x40010000+0x1C)&0x03)!=0x00))
|
|
if ((per.l(ad:0x40010000+0x20)&0x1100)==0x00)
|
|
if ((per.l(ad:0x40010000+0x44)&0x300)!=0x300)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif ((per.l(ad:0x40010000+0x20)&0x1100)==0x100)
|
|
if ((per.l(ad:0x40010000+0x44)&0x300)!=0x300)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif ((per.l(ad:0x40010000+0x20)&0x1100)==0x1000)
|
|
if ((per.l(ad:0x40010000+0x44)&0x300)!=0x300)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40010000+0x44)&0x300)!=0x300)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
elif (((per.l(ad:0x40010000+0x1C)&0x300)!=0x00))&&(((per.l(ad:0x40010000+0x1C)&0x03)==0x00))
|
|
if ((per.l(ad:0x40010000+0x20)&0x1100)==0x00)
|
|
if ((per.l(ad:0x40010000+0x44)&0x300)!=0x300)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
elif ((per.l(ad:0x40010000+0x20)&0x1100)==0x100)
|
|
if ((per.l(ad:0x40010000+0x44)&0x300)!=0x300)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
elif ((per.l(ad:0x40010000+0x20)&0x1100)==0x1000)
|
|
if ((per.l(ad:0x40010000+0x44)&0x300)!=0x300)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40010000+0x44)&0x300)!=0x300)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40010000+0x20)&0x1100)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40010000+0x20)&0x1100)==0x100)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40010000+0x20)&0x1100)==0x1000)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
newline
|
|
if ((((per.l((ad:0x40010000+0x18)))&0x303)==0x000)&&(((per.l((ad:0x40010000+0x1C)))&0x303)==0x000))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.long 0x00 21. " CC6P ,Compare 6 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 20. " CC6E ,Compare 6 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CC5P ,Compare 5 output polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 16. " CC5E ,Compare 5 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " CC3NE ,Compare 3 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " CC2NE ,Compare 2 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CC1NE ,Compare 1 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40010000+0x18)))&0x300)==0x00)&&(((per.l((ad:0x40010000+0x1C)))&0x303)==0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.long 0x00 21. " CC6P ,Compare 6 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 20. " CC6E ,Compare 6 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CC5P ,Compare 5 output polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 16. " CC5E ,Compare 5 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " CC3NE ,Compare 3 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " CC2NE ,Compare 2 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CC1NE ,Capture 1 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40010000+0x18)))&0x03)==0x00)&&(((per.l((ad:0x40010000+0x1C)))&0x303)==0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.long 0x00 21. " CC6P ,Compare 6 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 20. " CC6E ,Compare 6 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CC5P ,Compare 5 output polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 16. " CC5E ,Compare 5 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " CC3NE ,Compare 3 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " CC2NE ,Capture 2 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CC1NE ,Compare 1 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40010000+0x18)))&0x303)==0x00)&&(((per.l((ad:0x40010000+0x1C)))&0x300)==0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.long 0x00 21. " CC6P ,Compare 6 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 20. " CC6E ,Compare 6 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CC5P ,Compare 5 output polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 16. " CC5E ,Compare 5 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " CC3NE ,Capture 3 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " CC2NE ,Compare 2 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CC1NE ,Compare 1 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40010000+0x18)))&0x303)==0x00)&&(((per.l((ad:0x40010000+0x1C)))&0x03)==0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.long 0x00 21. " CC6P ,Compare 6 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 20. " CC6E ,Compare 6 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CC5P ,Compare 5 output polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 16. " CC5E ,Compare 5 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " CC3NE ,Compare 3 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " CC2NE ,Compare 2 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CC1NE ,Compare 1 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40010000+0x18)))&0x303)!=0x00)&&(((per.l((ad:0x40010000+0x1C)))&0x303)==0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.long 0x00 21. " CC6P ,Compare 6 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 20. " CC6E ,Compare 6 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CC5P ,Compare 5 output polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 16. " CC5E ,Compare 5 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " CC3NE ,Compare 3 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " CC2NE ,Capture 2 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CC1NE ,Capture 1 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40010000+0x18)))&0x300)==0x00)&&(((per.l((ad:0x40010000+0x1C)))&0x300)==0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.long 0x00 21. " CC6P ,Compare 6 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 20. " CC6E ,Compare 6 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CC5P ,Compare 5 output polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 16. " CC5E ,Compare 5 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " CC3NE ,Capture 3 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " CC2NE ,Compare 2 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CC1NE ,Capture 1 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40010000+0x18)))&0x300)==0x00)&&(((per.l((ad:0x40010000+0x1C)))&0x03)==0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.long 0x00 21. " CC6P ,Compare 6 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 20. " CC6E ,Compare 6 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CC5P ,Compare 5 output polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 16. " CC5E ,Compare 5 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " CC3NE ,Compare 3 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " CC2NE ,Compare 2 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CC1NE ,Capture 1 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40010000+0x18)))&0x03)==0x00)&&(((per.l((ad:0x40010000+0x1C)))&0x300)==0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.long 0x00 21. " CC6P ,Compare 6 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 20. " CC6E ,Compare 6 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CC5P ,Compare 5 output polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 16. " CC5E ,Compare 5 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " CC3NE ,Capture 3 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " CC2NE ,Capture 2 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CC1NE ,Compare 1 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40010000+0x18)))&0x03)==0x00)&&(((per.l((ad:0x40010000+0x1C)))&0x03)==0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.long 0x00 21. " CC6P ,Compare 6 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 20. " CC6E ,Compare 6 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CC5P ,Compare 5 output polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 16. " CC5E ,Compare 5 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " CC3NE ,Compare 3 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " CC2NE ,Capture 2 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CC1NE ,Compare 1 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40010000+0x18)))&0x303)!=0x00)&&(((per.l((ad:0x40010000+0x1C)))&0x300)==0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.long 0x00 21. " CC6P ,Compare 6 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 20. " CC6E ,Compare 6 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CC5P ,Compare 5 output polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 16. " CC5E ,Compare 5 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " CC3NE ,Capture 3 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " CC2NE ,Capture 2 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CC1NE ,Capture 1 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40010000+0x18)))&0x303)!=0x00)&&(((per.l((ad:0x40010000+0x1C)))&0x03)==0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.long 0x00 21. " CC6P ,Compare 6 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 20. " CC6E ,Compare 6 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CC5P ,Compare 5 output polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 16. " CC5E ,Compare 5 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " CC3NE ,Compare 3 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " CC2NE ,Capture 2 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CC1NE ,Capture 1 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40010000+0x18)))&0x303)==0x00)&&(((per.l((ad:0x40010000+0x1C)))&0x303)!=0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.long 0x00 21. " CC6P ,Compare 6 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 20. " CC6E ,Compare 6 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CC5P ,Compare 5 output polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 16. " CC5E ,Compare 5 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " CC3NE ,Capture 3 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " CC2NE ,Compare 2 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CC1NE ,Compare 1 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40010000+0x18)))&0x300)==0x00)&&(((per.l((ad:0x40010000+0x1C)))&0x303)!=0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.long 0x00 21. " CC6P ,Compare 6 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 20. " CC6E ,Compare 6 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CC5P ,Compare 5 output polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 16. " CC5E ,Compare 5 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " CC3NE ,Capture 3 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " CC2NE ,Compare 2 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CC1NE ,Capture 1 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40010000+0x18)))&0x03)==0x00)&&(((per.l((ad:0x40010000+0x1C)))&0x303)!=0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.long 0x00 21. " CC6P ,Compare 6 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 20. " CC6E ,Compare 6 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CC5P ,Compare 5 output polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 16. " CC5E ,Compare 5 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " CC3NE ,Capture 3 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " CC2NE ,Capture 2 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CC1NE ,Compare 1 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.long 0x00 21. " CC6P ,Compare 6 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 20. " CC6E ,Compare 6 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CC5P ,Compare 5 output polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 16. " CC5E ,Compare 5 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " CC3NE ,Capture 3 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " CC2NE ,Capture 2 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CC1NE ,Capture 1 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.w(ad:0x40010000))&0x800)==0x800)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,Counter"
|
|
rbitfld.long 0x00 31. " UIFCPY ,Update interrupt flag copy" "Not updated,Updated"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
endif
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "PSC,Prescaler"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "ARR,Auto-Reload Register"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "RCR,Repetition Counter Register"
|
|
if (((per.l(ad:0x40010000+0x18)&0x03)==0x00))
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "CCR1,Capture/Compare Register 1"
|
|
else
|
|
hgroup.word 0x34++0x01
|
|
hide.word 0x00 "CCR1,Capture/Compare Register 1"
|
|
in
|
|
endif
|
|
if (((per.l(ad:0x40010000+0x18)&0x300)==0x00))
|
|
group.word 0x38++0x01
|
|
line.word 0x00 "CCR2,Capture/Compare Register 2"
|
|
else
|
|
hgroup.word 0x38++0x01
|
|
hide.word 0x00 "CCR2,Capture/Compare Register 2"
|
|
in
|
|
endif
|
|
if (((per.l(ad:0x40010000+0x1C)&0x03)==0x00))
|
|
group.word 0x3C++0x01
|
|
line.word 0x00 "CCR3,Capture/Compare Register 3"
|
|
else
|
|
hgroup.word 0x3C++0x01
|
|
hide.word 0x00 "CCR3,Capture/Compare Register 3"
|
|
in
|
|
endif
|
|
if (((per.l(ad:0x40010000+0x1C)&0x300)==0x00))
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "CCR4,Capture/Compare Register 4"
|
|
else
|
|
hgroup.word 0x40++0x01
|
|
hide.word 0x00 "CCR4,Capture/Compare Register 4"
|
|
in
|
|
endif
|
|
if ((per.l(ad:0x40010000+0x44)&0x300)==0x00)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "BDTR,Break And Dead-Time Register"
|
|
bitfld.long 0x00 25. " BK2P ,Break 2 polarity" "Active low,Active high"
|
|
bitfld.long 0x00 24. " BK2E ,Break 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--23. " BK2F ,Break 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 15. " MOE ,Main output enable" "Disabled/Forced,Enabled"
|
|
bitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
bitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " OSSR ,Off-State selection for run mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OSSI ,Off-State selection for idle mode" "Disabled,Forced"
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "Off,Level 1,Level 2,Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator set-up"
|
|
elif ((per.l(ad:0x40010000+0x44)&0x300)==0x100)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "BDTR,Break And Dead-Time Register"
|
|
rbitfld.long 0x00 25. " BK2P ,Break 2 polarity" "Active low,Active high"
|
|
rbitfld.long 0x00 24. " BK2E ,Break 2 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20.--23. " BK2F ,Break 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
rbitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 15. " MOE ,Main output enable" "Disabled/Forced,Enabled"
|
|
rbitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
rbitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " OSSR ,Off-State selection for run mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OSSI ,Off-State selection for idle mode" "Disabled,Forced"
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "Off,Level 1,Level 2,Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator set-up"
|
|
else
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "BDTR,Break And Dead-Time Register"
|
|
rbitfld.long 0x00 25. " BK2P ,Break 2 polarity" "Active low,Active high"
|
|
rbitfld.long 0x00 24. " BK2E ,Break 2 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20.--23. " BK2F ,Break 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
rbitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 15. " MOE ,Main output enable" "Disabled/Forced,Enabled"
|
|
rbitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
rbitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 11. " OSSR ,Off-State selection for run mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 10. " OSSI ,Off-State selection for idle mode" "Disabled,Forced"
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "Off,Level 1,Level 2,Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-Time generator set-up"
|
|
endif
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "DCR,DMA Control Register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA burst length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA base address" "CR1,CR2,SMCR,DIER,SR,EGR,CCMR1,CCMR2,CCER,CNT,PSC,ARR,RCR,CCR1,CCR2,CCR3,CCR4,BDTR,DCR,DMAR,?..."
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "DMAR,DMA Address For Burst Mode"
|
|
group.long 0x54++0x07
|
|
line.long 0x00 "CCMR3,Capture/Compare Mode Register 3"
|
|
bitfld.long 0x00 15. " OC6CE ,Output compare 6 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC6M ,Output compare 6 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC6PE ,Output compare 6 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC6FE ,Output compare 6 fast enable" "Normal,Fast"
|
|
bitfld.long 0x00 7. " OC5CE ,Output compare 5 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC5M ,Output compare 5 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
newline
|
|
bitfld.long 0x00 3. " OC5PE ,Output compare 5 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC5FE ,Output compare 5 fast enable" "Normal,Fast"
|
|
line.long 0x04 "CCR5,Capture/Compare Register 5"
|
|
bitfld.long 0x04 31. " GC5C3 ,Group channel 5 and channel 3" "No effect,OC3REFC && OC5REF"
|
|
bitfld.long 0x04 30. " GC5C2 ,Group channel 5 and channel 2" "No effect,OC2REFC && OC5REF"
|
|
bitfld.long 0x04 29. " GC5C1 ,Group channel 5 and channel 1" "No effect,OC1REFC && OC5REF"
|
|
newline
|
|
hexmask.long.word 0x04 0.--15. 1. " CCR5 ,Capture/Compare 5 value"
|
|
group.word 0x5C++0x01
|
|
line.word 0x00 "CCR6,Capture/Compare Register 6"
|
|
sif (cpuis("STM32F77*")||cpuis("STM32F76*"))
|
|
if ((per.l(ad:0x40010000+0x44)&0x300)==0x00)
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "AF1,TIM1/TIM8 Alternate Function Option Register 1"
|
|
bitfld.long 0x00 9. " BKINP ,BRK BKIN input polarity" "High,Low"
|
|
bitfld.long 0x00 8. " BKDFBKE ,BRK DFSDM_BREAK[0] enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BKINE ,BRK BKIN input enable" "Disabled,Enabled"
|
|
line.long 0x04 "AF2,TIM1/TIM8 Alternate Function Option Register 2"
|
|
bitfld.long 0x04 9. " BK2INP ,BRK2 BKIN2 input polarity" "High,Low"
|
|
bitfld.long 0x04 8. " BK2DFBKE ,BRK2 DFSDM_BREAK enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " BK2INE ,BRK2 BKIN input enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x60++0x07
|
|
line.long 0x00 "AF1,TIM1/TIM8 Alternate Function Option Register 1"
|
|
bitfld.long 0x00 9. " BKINP ,BRK BKIN input polarity" "High,Low"
|
|
bitfld.long 0x00 8. " BKDFBKE ,BRK DFSDM_BREAK[0] enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BKINE ,BRK BKIN input enable" "Disabled,Enabled"
|
|
line.long 0x04 "AF2,TIM1/TIM8 Alternate Function Option Register 2"
|
|
bitfld.long 0x04 9. " BK2INP ,BRK2 BKIN2 input polarity" "High,Low"
|
|
bitfld.long 0x04 8. " BK2DFBKE ,BRK2 DFSDM_BREAK enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " BK2INE ,BRK2 BKIN input enable" "Disabled,Enabled"
|
|
endif
|
|
elif cpuis("STM32H743*")||cpuis("STM32H753*")
|
|
if ((per.l(ad:0x40010000+0x44)&0x300)==0x00)
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "AF1,TIM1 Alternate Function Option Register 1"
|
|
bitfld.long 0x00 14.--17. " ETRSEL ,ETR source selection" "ETR input I/O,COMP1 out,COMP2 out,ADC1 AWD1,ADC1 AWD2,ADC1 AWD3,ADC3 AWD1,ADC3 AWD2,ADC3 AWD3,?..."
|
|
newline
|
|
bitfld.long 0x00 11. " BKCMP2P ,BRK COMP2 input polarity" "High,Low"
|
|
bitfld.long 0x00 10. " BKCMP1P ,BRK COMP1 input polarity" "High,Low"
|
|
bitfld.long 0x00 9. " BKINP ,BRK BKIN input polarity" "High,Low"
|
|
newline
|
|
bitfld.long 0x00 8. " BKDF1BK0E ,BRK dfsdm1_break[0] enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " BKCMP2E ,BRK COMP2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BKCMP1E ,BRK COMP1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BKINE ,BRK BKIN input enable" "Disabled,Enabled"
|
|
line.long 0x04 "AF2,TIM1 Alternate Function Option Register 2"
|
|
bitfld.long 0x04 11. " BK2CMP2P ,BRK2 COMP2 input polarity" "Low,High"
|
|
bitfld.long 0x04 10. " BK2CMP1P ,BRK2 COMP1 input polarity" "Low,High"
|
|
bitfld.long 0x04 9. " BK2INP ,BRK2 BKIN2 input polarity" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 8. " BK2DFBKE ,BRK2 dfsdm1_break[1] enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 2. " BK2CMP2E ,BRK2 COMP2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " BK2CMP1E ,BRK2 COMP1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " BK2INE ,BRK2 BKIN input enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x60++0x07
|
|
line.long 0x00 "AF1,TIM1 Alternate Function Option Register 1"
|
|
bitfld.long 0x00 14.--17. " ETRSEL ,ETR source selection" "ETR input I/O,COMP1 out,COMP2 out,ADC1 AWD1,ADC1 AWD2,ADC1 AWD3,ADC3 AWD1,ADC3 AWD2,ADC3 AWD3,?..."
|
|
newline
|
|
bitfld.long 0x00 11. " BKCMP2P ,BRK COMP2 input polarity" "High,Low"
|
|
bitfld.long 0x00 10. " BKCMP1P ,BRK COMP1 input polarity" "High,Low"
|
|
bitfld.long 0x00 9. " BKINP ,BRK BKIN input polarity" "High,Low"
|
|
newline
|
|
bitfld.long 0x00 8. " BKDF1BK0E ,BRK dfsdm1_break[0] enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " BKCMP2E ,BRK COMP2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BKCMP1E ,BRK COMP1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BKINE ,BRK BKIN input enable" "Disabled,Enabled"
|
|
line.long 0x04 "AF2,TIM1 Alternate Function Option Register 2"
|
|
bitfld.long 0x04 11. " BK2CMP2P ,BRK2 COMP2 input polarity" "Low,High"
|
|
bitfld.long 0x04 10. " BK2CMP1P ,BRK2 COMP1 input polarity" "Low,High"
|
|
bitfld.long 0x04 9. " BK2INP ,BRK2 BKIN2 input polarity" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 8. " BK2DFBKE ,BRK2 dfsdm1_break[1] enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 2. " BK2CMP2E ,BRK2 COMP2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " BK2CMP1E ,BRK2 COMP1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " BK2INE ,BRK2 BKIN input enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "TISEL,TIM1 Alternate Function Option Register 1"
|
|
bitfld.long 0x00 24.--27. " TI4SEL ,Selects TI4[0] to TI4[15] input" "TIM8_CH4 input,?..."
|
|
bitfld.long 0x00 16.--19. " TI3SEL ,Selects TI3[0] to TI3[15] input" "TIM8_CH3 input,?..."
|
|
bitfld.long 0x00 8.--11. " TI2SEL ,Selects TI2[0] to TI2[15] input" "TIM8_CH2 input,?..."
|
|
bitfld.long 0x00 0.--3. " TI1SEL ,Selects TI1[0] to TI1[15] input" "TIM8_CH1 input,COMP2 output,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "TIM 8"
|
|
base ad:0x40010400
|
|
width 7.
|
|
if ((per.w(ad:0x40010400)&0x60)!=0x00)||((per.w(ad:0x40010400+0x08)&0x07)==(0x01||0x02||0x03))
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,Control Register 1"
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Not remapped,Remapped"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
newline
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
newline
|
|
rbitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
newline
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,Control Register 1"
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Not remapped,Remapped"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
newline
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
newline
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
newline
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.l(ad:0x40010400+0x44)&0x03)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 20.--23. " MMS2 ,Master mode selection 2" "Reset,Enable,Update,Compare Pulse,Compare - OC1REF,Compare - OC2REF,Compare - OC3REF,Compare - OC4REF,Compare - OC5REF,Compare - OC6REF,Compare Pulse - OC4REF,Compare Pulse - OC6REF,Compare Pulse - OC4REF or OC6REF rising,Compare Pulse - OC4REF rising or OC6REF falling,Compare Pulse - OC5REF or OC6REF rising,Compare Pulse - OC5REF rising or OC6REF falling"
|
|
bitfld.long 0x00 18. " OIS6 ,OC6 output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. " OIS5 ,OC5 output" "0,1"
|
|
bitfld.long 0x00 14. " OIS4 ,OC4 output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. " OIS3N ,OC3N output" "0,1"
|
|
bitfld.long 0x00 12. " OIS3 ,OC3 output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " OIS2N ,OC2N output" "0,1"
|
|
bitfld.long 0x00 10. " OIS2 ,OC2 output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. " OIS1N ,OC1N output" "0,1"
|
|
bitfld.long 0x00 8. " OIS1 ,OC1 output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " TI1S ,TI1 selection" "CH1,CH1/CH2/CH3"
|
|
bitfld.long 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,OC3REF,OC4REF"
|
|
newline
|
|
bitfld.long 0x00 3. " CCDS ,Capture/Compare DMA selection" "CCx,Update"
|
|
bitfld.long 0x00 2. " CCUS ,Capture/Compare control update selection" "COMG bit only,COMG bit/Rising edge"
|
|
newline
|
|
bitfld.long 0x00 0. " CCPC ,Capture/Compare preloaded control" "Not preloaded,Preloaded"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 20.--23. " MMS2 ,Master mode selection 2" "Reset,Enable,Update,Compare Pulse,Compare - OC1REF,Compare - OC2REF,Compare - OC3REF,Compare - OC4REF,Compare - OC5REF,Compare - OC6REF,Compare Pulse - OC4REF,Compare Pulse - OC6REF,Compare Pulse - OC4REF or OC6REF rising,Compare Pulse - OC4REF rising or OC6REF falling,Compare Pulse - OC5REF or OC6REF rising,Compare Pulse - OC5REF rising or OC6REF falling"
|
|
rbitfld.long 0x00 18. " OIS6 ,OC6 output" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 16. " OIS5 ,OC5 output" "0,1"
|
|
rbitfld.long 0x00 14. " OIS4 ,OC4 output" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 13. " OIS3N ,OC3N output" "0,1"
|
|
rbitfld.long 0x00 12. " OIS3 ,OC3 output" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 11. " OIS2N ,OC2N output" "0,1"
|
|
rbitfld.long 0x00 10. " OIS2 ,OC2 output" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 9. " OIS1N ,OC1N output" "0,1"
|
|
rbitfld.long 0x00 8. " OIS1 ,OC1 output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " TI1S ,TI1 selection" "CH1,CH1/CH2/CH3"
|
|
bitfld.long 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,OC3REF,OC4REF"
|
|
newline
|
|
bitfld.long 0x00 3. " CCDS ,Capture/Compare DMA selection" "CCx,Update"
|
|
bitfld.long 0x00 2. " CCUS ,Capture/Compare control update selection" "COMG bit only,COMG bit/Rising edge"
|
|
newline
|
|
bitfld.long 0x00 0. " CCPC ,Capture/Compare preloaded control" "Not preloaded,Preloaded"
|
|
endif
|
|
if ((per.w(ad:0x40010400+0x08)&0x07)!=0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SMCR,Slave Mode Control Register"
|
|
bitfld.long 0x00 15. " ETP ,External trigger polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " ETF ,External trigger filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 7. " MSM ,Master/slave mode" "No action,TRGO delayed"
|
|
sif !cpuis("STM32F730*8")
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
rbitfld.long 0x00 4.--6. 20.--21. " TS ,Trigger selection" "TIM1,TIM2,TIM4,TIM5,?..."
|
|
else
|
|
rbitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
endif
|
|
else
|
|
rbitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 0.--2. 16. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock,Reset + Trigger,?..."
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SMCR,Slave Mode Control Register"
|
|
bitfld.long 0x00 15. " ETP ,External trigger polarity" "Non-inverted,Inverted"
|
|
bitfld.long 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " ETF ,External trigger filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 7. " MSM ,Master/Slave mode" "No action,TRGO delayed"
|
|
sif !cpuis("STM32F730*8")
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 4.--6. 20.--21. " TS ,Trigger selection" "TIM1,TIM2,TIM4,TIM5,?..."
|
|
else
|
|
bitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
endif
|
|
else
|
|
bitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 0.--2. 16. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock,Reset + Trigger,?..."
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "DIER,DMA/Interrupt Enable Register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " COMDE ,COM DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " BIE ,Break interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 5. " COMIE ,COM interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
bitfld.long 0x00 17. " CC6IF ,Capture/Compare 6 interrupt flag input/output" "Not captured/Not matched,Captured/Matched"
|
|
bitfld.long 0x00 16. " CC5IF ,Capture/Compare 5 interrupt flag input/output" "Not captured/Not matched,Captured/Matched"
|
|
newline
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
bitfld.long 0x00 13. " SBIF ,System break interrupt flag" "Not occurred,Occurred"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 12. " CC4OF ,Capture/Compare 4 overcapture flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 11. " CC3OF ,Capture/Compare 3 overcapture flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " CC2OF ,Capture/Compare 2 overcapture flag" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 9. " CC1OF ,Capture/Compare 1 overcapture flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " B2IF ,Break 2 interrupt flag" "No break,Break"
|
|
bitfld.long 0x00 7. " BIF ,Break interrupt flag" "No break,Break"
|
|
newline
|
|
bitfld.long 0x00 6. " TIF ,Trigger interrupt flag" "No trigger,Trigger"
|
|
bitfld.long 0x00 5. " COMIF ,COM interrupt flag" "No COM,COM"
|
|
bitfld.long 0x00 4. " CC4IF ,Capture/Compare 4 interrupt flag input/output" "Not captured/Not matched,Captured/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " CC3IF ,Capture/Compare 3 interrupt flag input/output" "Not captured/Not matched,Captured/Matched"
|
|
bitfld.long 0x00 2. " CC2IF ,Capture/Compare 2 interrupt flag input/output" "Not captured/Not matched,Captured/Matched"
|
|
bitfld.long 0x00 1. " CC1IF ,Capture/Compare 1 interrupt flag input/output" "Not captured/Not matched,Captured/Matched"
|
|
newline
|
|
bitfld.long 0x00 0. " UIF ,Update interrupt flag" "Not updated,Updated"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "EGR,Event Generation Register"
|
|
bitfld.word 0x00 8. " B2G ,Break 2 generation" "No action,Break 2"
|
|
bitfld.word 0x00 7. " BG ,Break generation" "No action,Break"
|
|
bitfld.word 0x00 6. " TG ,Trigger generation" "No action,Trigger"
|
|
newline
|
|
bitfld.word 0x00 5. " COMG ,Capture/Compare control update generation" "No action,Update"
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 generation input/output" "No action/No action,Capture 4/compare 4"
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 generation input/output" "No action/No action,Capture 3/compare 3"
|
|
newline
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 generation input/output" "No action/No action,Capture 2/compare 2"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 generation input/output" "No action/No action,Capture 1/compare 1"
|
|
bitfld.word 0x00 0. " UG ,Update generation" "No action,Update"
|
|
if (((per.l((ad:0x40010400+0x18)))&0x303)==0x000)
|
|
if ((per.l(ad:0x40010400+0x20)&0x01)==0x00)&&((per.l(ad:0x40010400+0x20)&0x100)==0x00)
|
|
if ((per.l(ad:0x40010400+0x44)&0x300)!=0x300)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif ((per.l(ad:0x40010400+0x20)&0x01)==0x01)&&((per.l(ad:0x40010400+0x20)&0x100)==0x00)
|
|
if ((per.l(ad:0x40010400+0x44)&0x300)!=0x300)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif ((per.l(ad:0x40010400+0x20)&0x01)==0x00)&&((per.l(ad:0x40010400+0x20)&0x100)==0x100)
|
|
if ((per.l(ad:0x40010400+0x44)&0x300)!=0x300)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40010400+0x44)&0x300)!=0x300)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
elif (((per.l((ad:0x40010400+0x18)))&0x300)!=0x00)&&(((per.l((ad:0x40010400+0x18)))&0x03)!=0x00)
|
|
if ((per.l(ad:0x40010400+0x20)&0x01)==0x00)&&((per.l(ad:0x40010400+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40010400+0x20)&0x01)==0x01)&&((per.l(ad:0x40010400+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40010400+0x20)&0x01)==0x00)&&((per.l(ad:0x40010400+0x20)&0x100)==0x100)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.l((ad:0x40010400+0x18)))&0x300)==0x00)&&(((per.l((ad:0x40010400+0x18)))&0x03)!=0x00)
|
|
if ((per.l(ad:0x40010400+0x20)&0x01)==0x00)&&((per.l(ad:0x40010400+0x20)&0x100)==0x00)
|
|
if ((per.l(ad:0x40010400+0x44)&0x300)!=0x300)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif ((per.l(ad:0x40010400+0x20)&0x01)==0x01)&&((per.l(ad:0x40010400+0x20)&0x100)==0x00)
|
|
if ((per.l(ad:0x40010400+0x44)&0x300)!=0x300)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif ((per.l(ad:0x40010400+0x20)&0x01)==0x00)&&((per.l(ad:0x40010400+0x20)&0x100)==0x100)
|
|
if ((per.l(ad:0x40010400+0x44)&0x300)!=0x300)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40010400+0x44)&0x300)!=0x300)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40010400+0x20)&0x01)==0x00)&&((per.l(ad:0x40010400+0x20)&0x100)==0x00)
|
|
if ((per.l(ad:0x40010400+0x44)&0x300)!=0x300)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif ((per.l(ad:0x40010400+0x20)&0x01)==0x01)&&((per.l(ad:0x40010400+0x20)&0x100)==0x00)
|
|
if ((per.l(ad:0x40010400+0x44)&0x300)!=0x300)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif ((per.l(ad:0x40010400+0x20)&0x01)==0x00)&&((per.l(ad:0x40010400+0x20)&0x100)==0x100)
|
|
if ((per.l(ad:0x40010400+0x44)&0x300)!=0x300)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40010400+0x44)&0x300)!=0x300)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40010400+0x1C)&0x303)==0x00))
|
|
if ((per.l(ad:0x40010400+0x20)&0x1100)==0x00)
|
|
if ((per.l(ad:0x40010400+0x44)&0x300)!=0x300)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
elif ((per.l(ad:0x40010400+0x20)&0x1100)==0x100)
|
|
if ((per.l(ad:0x40010400+0x44)&0x300)!=0x300)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
elif ((per.l(ad:0x40010400+0x20)&0x1100)==0x1000)
|
|
if ((per.l(ad:0x40010400+0x44)&0x300)!=0x300)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40010400+0x44)&0x300)!=0x300)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
endif
|
|
elif (((per.l(ad:0x40010400+0x1C)&0x300)==0x00))&&(((per.l(ad:0x40010400+0x1C)&0x03)!=0x00))
|
|
if ((per.l(ad:0x40010400+0x20)&0x1100)==0x00)
|
|
if ((per.l(ad:0x40010400+0x44)&0x300)!=0x300)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif ((per.l(ad:0x40010400+0x20)&0x1100)==0x100)
|
|
if ((per.l(ad:0x40010400+0x44)&0x300)!=0x300)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif ((per.l(ad:0x40010400+0x20)&0x1100)==0x1000)
|
|
if ((per.l(ad:0x40010400+0x44)&0x300)!=0x300)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40010400+0x44)&0x300)!=0x300)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
elif (((per.l(ad:0x40010400+0x1C)&0x300)!=0x00))&&(((per.l(ad:0x40010400+0x1C)&0x03)==0x00))
|
|
if ((per.l(ad:0x40010400+0x20)&0x1100)==0x00)
|
|
if ((per.l(ad:0x40010400+0x44)&0x300)!=0x300)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
elif ((per.l(ad:0x40010400+0x20)&0x1100)==0x100)
|
|
if ((per.l(ad:0x40010400+0x44)&0x300)!=0x300)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
elif ((per.l(ad:0x40010400+0x20)&0x1100)==0x1000)
|
|
if ((per.l(ad:0x40010400+0x44)&0x300)!=0x300)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40010400+0x44)&0x300)!=0x300)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
rbitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40010400+0x20)&0x1100)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40010400+0x20)&0x1100)==0x100)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40010400+0x20)&0x1100)==0x1000)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
newline
|
|
if ((((per.l((ad:0x40010400+0x18)))&0x303)==0x000)&&(((per.l((ad:0x40010400+0x1C)))&0x303)==0x000))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.long 0x00 21. " CC6P ,Compare 6 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 20. " CC6E ,Compare 6 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CC5P ,Compare 5 output polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 16. " CC5E ,Compare 5 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " CC3NE ,Compare 3 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " CC2NE ,Compare 2 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CC1NE ,Compare 1 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40010400+0x18)))&0x300)==0x00)&&(((per.l((ad:0x40010400+0x1C)))&0x303)==0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.long 0x00 21. " CC6P ,Compare 6 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 20. " CC6E ,Compare 6 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CC5P ,Compare 5 output polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 16. " CC5E ,Compare 5 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " CC3NE ,Compare 3 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " CC2NE ,Compare 2 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CC1NE ,Capture 1 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40010400+0x18)))&0x03)==0x00)&&(((per.l((ad:0x40010400+0x1C)))&0x303)==0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.long 0x00 21. " CC6P ,Compare 6 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 20. " CC6E ,Compare 6 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CC5P ,Compare 5 output polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 16. " CC5E ,Compare 5 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " CC3NE ,Compare 3 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " CC2NE ,Capture 2 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CC1NE ,Compare 1 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40010400+0x18)))&0x303)==0x00)&&(((per.l((ad:0x40010400+0x1C)))&0x300)==0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.long 0x00 21. " CC6P ,Compare 6 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 20. " CC6E ,Compare 6 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CC5P ,Compare 5 output polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 16. " CC5E ,Compare 5 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " CC3NE ,Capture 3 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " CC2NE ,Compare 2 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CC1NE ,Compare 1 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40010400+0x18)))&0x303)==0x00)&&(((per.l((ad:0x40010400+0x1C)))&0x03)==0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.long 0x00 21. " CC6P ,Compare 6 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 20. " CC6E ,Compare 6 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CC5P ,Compare 5 output polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 16. " CC5E ,Compare 5 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " CC3NE ,Compare 3 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " CC2NE ,Compare 2 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CC1NE ,Compare 1 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40010400+0x18)))&0x303)!=0x00)&&(((per.l((ad:0x40010400+0x1C)))&0x303)==0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.long 0x00 21. " CC6P ,Compare 6 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 20. " CC6E ,Compare 6 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CC5P ,Compare 5 output polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 16. " CC5E ,Compare 5 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " CC3NE ,Compare 3 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " CC2NE ,Capture 2 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CC1NE ,Capture 1 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40010400+0x18)))&0x300)==0x00)&&(((per.l((ad:0x40010400+0x1C)))&0x300)==0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.long 0x00 21. " CC6P ,Compare 6 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 20. " CC6E ,Compare 6 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CC5P ,Compare 5 output polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 16. " CC5E ,Compare 5 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " CC3NE ,Capture 3 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " CC2NE ,Compare 2 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CC1NE ,Capture 1 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40010400+0x18)))&0x300)==0x00)&&(((per.l((ad:0x40010400+0x1C)))&0x03)==0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.long 0x00 21. " CC6P ,Compare 6 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 20. " CC6E ,Compare 6 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CC5P ,Compare 5 output polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 16. " CC5E ,Compare 5 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " CC3NE ,Compare 3 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " CC2NE ,Compare 2 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CC1NE ,Capture 1 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40010400+0x18)))&0x03)==0x00)&&(((per.l((ad:0x40010400+0x1C)))&0x300)==0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.long 0x00 21. " CC6P ,Compare 6 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 20. " CC6E ,Compare 6 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CC5P ,Compare 5 output polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 16. " CC5E ,Compare 5 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " CC3NE ,Capture 3 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " CC2NE ,Capture 2 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CC1NE ,Compare 1 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40010400+0x18)))&0x03)==0x00)&&(((per.l((ad:0x40010400+0x1C)))&0x03)==0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.long 0x00 21. " CC6P ,Compare 6 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 20. " CC6E ,Compare 6 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CC5P ,Compare 5 output polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 16. " CC5E ,Compare 5 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " CC3NE ,Compare 3 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " CC2NE ,Capture 2 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CC1NE ,Compare 1 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40010400+0x18)))&0x303)!=0x00)&&(((per.l((ad:0x40010400+0x1C)))&0x300)==0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.long 0x00 21. " CC6P ,Compare 6 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 20. " CC6E ,Compare 6 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CC5P ,Compare 5 output polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 16. " CC5E ,Compare 5 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " CC3NE ,Capture 3 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " CC2NE ,Capture 2 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CC1NE ,Capture 1 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40010400+0x18)))&0x303)!=0x00)&&(((per.l((ad:0x40010400+0x1C)))&0x03)==0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.long 0x00 21. " CC6P ,Compare 6 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 20. " CC6E ,Compare 6 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CC5P ,Compare 5 output polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 16. " CC5E ,Compare 5 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " CC3NE ,Compare 3 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " CC2NE ,Capture 2 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CC1NE ,Capture 1 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40010400+0x18)))&0x303)==0x00)&&(((per.l((ad:0x40010400+0x1C)))&0x303)!=0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.long 0x00 21. " CC6P ,Compare 6 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 20. " CC6E ,Compare 6 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CC5P ,Compare 5 output polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 16. " CC5E ,Compare 5 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " CC3NE ,Capture 3 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " CC2NE ,Compare 2 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CC1NE ,Compare 1 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40010400+0x18)))&0x300)==0x00)&&(((per.l((ad:0x40010400+0x1C)))&0x303)!=0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.long 0x00 21. " CC6P ,Compare 6 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 20. " CC6E ,Compare 6 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CC5P ,Compare 5 output polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 16. " CC5E ,Compare 5 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " CC3NE ,Capture 3 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " CC2NE ,Compare 2 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CC1NE ,Capture 1 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40010400+0x18)))&0x03)==0x00)&&(((per.l((ad:0x40010400+0x1C)))&0x303)!=0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.long 0x00 21. " CC6P ,Compare 6 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 20. " CC6E ,Compare 6 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CC5P ,Compare 5 output polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 16. " CC5E ,Compare 5 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " CC3NE ,Capture 3 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " CC2NE ,Capture 2 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CC1NE ,Compare 1 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.long 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.long 0x00 21. " CC6P ,Compare 6 output polarity" "Active high,Active low"
|
|
bitfld.long 0x00 20. " CC6E ,Compare 6 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CC5P ,Compare 5 output polarity" "Active high,Active low"
|
|
newline
|
|
bitfld.long 0x00 16. " CC5E ,Compare 5 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " CC3NE ,Capture 3 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " CC2NE ,Capture 2 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CC1NE ,Capture 1 complementary output enable" "Off,On"
|
|
bitfld.long 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.long 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.w(ad:0x40010400))&0x800)==0x800)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,Counter"
|
|
rbitfld.long 0x00 31. " UIFCPY ,Update interrupt flag copy" "Not updated,Updated"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
endif
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "PSC,Prescaler"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "ARR,Auto-Reload Register"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "RCR,Repetition Counter Register"
|
|
if (((per.l(ad:0x40010400+0x18)&0x03)==0x00))
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "CCR1,Capture/Compare Register 1"
|
|
else
|
|
hgroup.word 0x34++0x01
|
|
hide.word 0x00 "CCR1,Capture/Compare Register 1"
|
|
in
|
|
endif
|
|
if (((per.l(ad:0x40010400+0x18)&0x300)==0x00))
|
|
group.word 0x38++0x01
|
|
line.word 0x00 "CCR2,Capture/Compare Register 2"
|
|
else
|
|
hgroup.word 0x38++0x01
|
|
hide.word 0x00 "CCR2,Capture/Compare Register 2"
|
|
in
|
|
endif
|
|
if (((per.l(ad:0x40010400+0x1C)&0x03)==0x00))
|
|
group.word 0x3C++0x01
|
|
line.word 0x00 "CCR3,Capture/Compare Register 3"
|
|
else
|
|
hgroup.word 0x3C++0x01
|
|
hide.word 0x00 "CCR3,Capture/Compare Register 3"
|
|
in
|
|
endif
|
|
if (((per.l(ad:0x40010400+0x1C)&0x300)==0x00))
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "CCR4,Capture/Compare Register 4"
|
|
else
|
|
hgroup.word 0x40++0x01
|
|
hide.word 0x00 "CCR4,Capture/Compare Register 4"
|
|
in
|
|
endif
|
|
if ((per.l(ad:0x40010400+0x44)&0x300)==0x00)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "BDTR,Break And Dead-Time Register"
|
|
bitfld.long 0x00 25. " BK2P ,Break 2 polarity" "Active low,Active high"
|
|
bitfld.long 0x00 24. " BK2E ,Break 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--23. " BK2F ,Break 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 15. " MOE ,Main output enable" "Disabled/Forced,Enabled"
|
|
bitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
bitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " OSSR ,Off-State selection for run mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OSSI ,Off-State selection for idle mode" "Disabled,Forced"
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "Off,Level 1,Level 2,Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator set-up"
|
|
elif ((per.l(ad:0x40010400+0x44)&0x300)==0x100)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "BDTR,Break And Dead-Time Register"
|
|
rbitfld.long 0x00 25. " BK2P ,Break 2 polarity" "Active low,Active high"
|
|
rbitfld.long 0x00 24. " BK2E ,Break 2 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20.--23. " BK2F ,Break 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
rbitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 15. " MOE ,Main output enable" "Disabled/Forced,Enabled"
|
|
rbitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
rbitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " OSSR ,Off-State selection for run mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OSSI ,Off-State selection for idle mode" "Disabled,Forced"
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "Off,Level 1,Level 2,Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator set-up"
|
|
else
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "BDTR,Break And Dead-Time Register"
|
|
rbitfld.long 0x00 25. " BK2P ,Break 2 polarity" "Active low,Active high"
|
|
rbitfld.long 0x00 24. " BK2E ,Break 2 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20.--23. " BK2F ,Break 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
rbitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 15. " MOE ,Main output enable" "Disabled/Forced,Enabled"
|
|
rbitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
rbitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 11. " OSSR ,Off-State selection for run mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 10. " OSSI ,Off-State selection for idle mode" "Disabled,Forced"
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "Off,Level 1,Level 2,Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-Time generator set-up"
|
|
endif
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "DCR,DMA Control Register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA burst length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA base address" "CR1,CR2,SMCR,DIER,SR,EGR,CCMR1,CCMR2,CCER,CNT,PSC,ARR,RCR,CCR1,CCR2,CCR3,CCR4,BDTR,DCR,DMAR,?..."
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "DMAR,DMA Address For Burst Mode"
|
|
group.long 0x54++0x07
|
|
line.long 0x00 "CCMR3,Capture/Compare Mode Register 3"
|
|
bitfld.long 0x00 15. " OC6CE ,Output compare 6 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC6M ,Output compare 6 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC6PE ,Output compare 6 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC6FE ,Output compare 6 fast enable" "Normal,Fast"
|
|
bitfld.long 0x00 7. " OC5CE ,Output compare 5 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC5M ,Output compare 5 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
newline
|
|
bitfld.long 0x00 3. " OC5PE ,Output compare 5 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC5FE ,Output compare 5 fast enable" "Normal,Fast"
|
|
line.long 0x04 "CCR5,Capture/Compare Register 5"
|
|
bitfld.long 0x04 31. " GC5C3 ,Group channel 5 and channel 3" "No effect,OC3REFC && OC5REF"
|
|
bitfld.long 0x04 30. " GC5C2 ,Group channel 5 and channel 2" "No effect,OC2REFC && OC5REF"
|
|
bitfld.long 0x04 29. " GC5C1 ,Group channel 5 and channel 1" "No effect,OC1REFC && OC5REF"
|
|
newline
|
|
hexmask.long.word 0x04 0.--15. 1. " CCR5 ,Capture/Compare 5 value"
|
|
group.word 0x5C++0x01
|
|
line.word 0x00 "CCR6,Capture/Compare Register 6"
|
|
sif (cpuis("STM32F77*")||cpuis("STM32F76*"))
|
|
if ((per.l(ad:0x40010400+0x44)&0x300)==0x00)
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "AF1,TIM1/TIM8 Alternate Function Option Register 1"
|
|
bitfld.long 0x00 9. " BKINP ,BRK BKIN input polarity" "High,Low"
|
|
bitfld.long 0x00 8. " BKDFBKE ,BRK DFSDM_BREAK[0] enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BKINE ,BRK BKIN input enable" "Disabled,Enabled"
|
|
line.long 0x04 "AF2,TIM1/TIM8 Alternate Function Option Register 2"
|
|
bitfld.long 0x04 9. " BK2INP ,BRK2 BKIN2 input polarity" "High,Low"
|
|
bitfld.long 0x04 8. " BK2DFBKE ,BRK2 DFSDM_BREAK enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " BK2INE ,BRK2 BKIN input enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x60++0x07
|
|
line.long 0x00 "AF1,TIM1/TIM8 Alternate Function Option Register 1"
|
|
bitfld.long 0x00 9. " BKINP ,BRK BKIN input polarity" "High,Low"
|
|
bitfld.long 0x00 8. " BKDFBKE ,BRK DFSDM_BREAK[0] enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BKINE ,BRK BKIN input enable" "Disabled,Enabled"
|
|
line.long 0x04 "AF2,TIM1/TIM8 Alternate Function Option Register 2"
|
|
bitfld.long 0x04 9. " BK2INP ,BRK2 BKIN2 input polarity" "High,Low"
|
|
bitfld.long 0x04 8. " BK2DFBKE ,BRK2 DFSDM_BREAK enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " BK2INE ,BRK2 BKIN input enable" "Disabled,Enabled"
|
|
endif
|
|
elif cpuis("STM32H743*")||cpuis("STM32H753*")
|
|
if ((per.l(ad:0x40010400+0x44)&0x300)==0x00)
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "AF1,TIM8 Alternate Function Option Register 1"
|
|
bitfld.long 0x00 14.--17. " ETRSEL ,ETR source selection" "ETR input I/O,COMP1 out,COMP2 out,ADC2 AWD1,ADC2 AWD2,ADC2 AWD3,ADC3 AWD1,ADC3 AWD2,ADC3 AWD3,?..."
|
|
newline
|
|
bitfld.long 0x00 11. " BKCMP2P ,BRK COMP2 input polarity" "High,Low"
|
|
bitfld.long 0x00 10. " BKCMP1P ,BRK COMP1 input polarity" "High,Low"
|
|
bitfld.long 0x00 9. " BKINP ,BRK BKIN input polarity" "High,Low"
|
|
newline
|
|
bitfld.long 0x00 8. " BKDF1BK0E ,BRK dfsdm1_break[2] enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " BKCMP2E ,BRK COMP2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BKCMP1E ,BRK COMP1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BKINE ,BRK BKIN input enable" "Disabled,Enabled"
|
|
line.long 0x04 "AF2,TIM8 Alternate Function Option Register 2"
|
|
bitfld.long 0x04 11. " BK2CMP2P ,BRK2 COMP2 input polarity" "Low,High"
|
|
bitfld.long 0x04 10. " BK2CMP1P ,BRK2 COMP1 input polarity" "Low,High"
|
|
bitfld.long 0x04 9. " BK2INP ,BRK2 BKIN2 input polarity" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 8. " BK2DFBKE ,BRK2 dfsdm1_break[3] enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 2. " BK2CMP2E ,BRK2 COMP2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " BK2CMP1E ,BRK2 COMP1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " BK2INE ,BRK2 BKIN input enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x60++0x07
|
|
line.long 0x00 "AF1,TIM8 Alternate Function Option Register 1"
|
|
bitfld.long 0x00 14.--17. " ETRSEL ,ETR source selection" "ETR input I/O,COMP1 out,COMP2 out,ADC2 AWD1,ADC2 AWD2,ADC2 AWD3,ADC3 AWD1,ADC3 AWD2,ADC3 AWD3,?..."
|
|
newline
|
|
bitfld.long 0x00 11. " BKCMP2P ,BRK COMP2 input polarity" "High,Low"
|
|
bitfld.long 0x00 10. " BKCMP1P ,BRK COMP1 input polarity" "High,Low"
|
|
bitfld.long 0x00 9. " BKINP ,BRK BKIN input polarity" "High,Low"
|
|
newline
|
|
bitfld.long 0x00 8. " BKDF1BK0E ,BRK dfsdm1_break[2] enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " BKCMP2E ,BRK COMP2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BKCMP1E ,BRK COMP1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BKINE ,BRK BKIN input enable" "Disabled,Enabled"
|
|
line.long 0x04 "AF2,TIM8 Alternate Function Option Register 2"
|
|
bitfld.long 0x04 11. " BK2CMP2P ,BRK2 COMP2 input polarity" "Low,High"
|
|
bitfld.long 0x04 10. " BK2CMP1P ,BRK2 COMP1 input polarity" "Low,High"
|
|
bitfld.long 0x04 9. " BK2INP ,BRK2 BKIN2 input polarity" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 8. " BK2DFBKE ,BRK2 dfsdm1_break[3] enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 2. " BK2CMP2E ,BRK2 COMP2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " BK2CMP1E ,BRK2 COMP1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " BK2INE ,BRK2 BKIN input enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "TISEL,TIM8 Alternate Function Option Register 1"
|
|
bitfld.long 0x00 24.--27. " TI4SEL ,Selects TI4[0] to TI4[15] input" "TIM1_CH4 input,?..."
|
|
bitfld.long 0x00 16.--19. " TI3SEL ,Selects TI3[0] to TI3[15] input" "TIM1_CH3 input,?..."
|
|
bitfld.long 0x00 8.--11. " TI2SEL ,Selects TI2[0] to TI2[15] input" "TIM1_CH2 input,?..."
|
|
bitfld.long 0x00 0.--3. " TI1SEL ,Selects TI1[0] to TI1[15] input" "TIM1_CH1 input,COMP1 output,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "GPT (General-purpose timers)"
|
|
tree "TIM 2"
|
|
base ad:0x40000000
|
|
width 7.
|
|
if ((per.w(ad:0x40000000)&0x60)!=0x00)||((per.w(ad:0x40000000+0x08)&0x07)==(0x01||0x02||0x03))
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,Control Register 1"
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Not remapped,Remapped"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
newline
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
newline
|
|
rbitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
newline
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,Control Register 1"
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Not remapped,Remapped"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
newline
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
newline
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
newline
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "CR2,TIM2 Control Register 2"
|
|
bitfld.word 0x00 7. " TI1S ,TI1 selection" "CH1,CH1/CH2/CH3"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,Compare pulse,Compare OC1REF,Compare OC2REF,Compare OC3REF,Compare OC4REF"
|
|
newline
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA selection" "CC2,Update"
|
|
newline
|
|
if ((per.l(ad:0x40000000)&0x10007)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SMCR,TIM2 Slave Mode Control Register"
|
|
bitfld.long 0x00 15. " ETP ,External trigger polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " ETF ,External trigger filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 7. " MSM ,Master/slave mode" "No action,TRGO delayed"
|
|
newline
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
bitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
newline
|
|
else
|
|
sif (cpuis("STM32F77*")||cpuis("STM32F76*"))
|
|
bitfld.long 0x00 4.--6. " TS ,Trigger selection" ",TIM8/ETH_PTP/OTG_FS_SOF/OTG_HS_SOF,TIM3,,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
else
|
|
bitfld.long 0x00 4.--6. " TS ,Trigger selection" ",TIM8/OTG_FS_SOF/OTG_HS_SOF,TIM3,,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 0.--2. 16. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock,Reset + Trigger,?..."
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SMCR,TIM2 Slave Mode Control Register"
|
|
bitfld.long 0x00 15. " ETP ,External trigger polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " ETF ,External trigger filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 7. " MSM ,Master/slave mode" "No action,TRGO delayed"
|
|
newline
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
rbitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
newline
|
|
else
|
|
sif (cpuis("STM32F77*")||cpuis("STM32F76*"))
|
|
rbitfld.long 0x00 4.--6. " TS ,Trigger selection" ",TIM8/ETH_PTP/OTG_FS_SOF/OTG_HS_SOF,TIM3,,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
else
|
|
rbitfld.long 0x00 4.--6. " TS ,Trigger selection" ",TIM8/OTG_FS_SOF/OTG_HS_SOF,TIM3,,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 0.--2. 16. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock,Reset + Trigger,?..."
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "DIER,TIM2 DMA/Interrupt Enable Register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "SR,TIM2 Status Register"
|
|
bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 overcapture flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 overcapture flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 overcapture flag" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 overcapture flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt flag" "No trigger,Trigger"
|
|
bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt flag input/output" "Not captured/Not matched,Captured/Matched"
|
|
newline
|
|
bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt flag input/output" "Not captured/Not matched,Captured/Matched"
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt flag input/output" "Not captured/Not matched,Captured/Matched"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt flag input/output" "Not captured/Not matched,Captured/Matched"
|
|
newline
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt flag" "Not updated,Updated"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "EGR,TIM2 Event Generation Register"
|
|
bitfld.word 0x00 6. " TG ,Trigger generation" "No action,Trigger"
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 generation input/output" "No action/No action,Capture 4/compare 4"
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 generation input/output" "No action/No action,Capture 3/compare 3"
|
|
newline
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 generation input/output" "No action/No action,Capture 2/compare 2"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 generation input/output" "No action/No action,Capture 1/compare 1"
|
|
bitfld.word 0x00 0. " UG ,Update generation" "No action,Update"
|
|
newline
|
|
if (((per.l((ad:0x40000000+0x18)))&0x303)==0x000)
|
|
if ((per.l(ad:0x40000000+0x20)&0x01)==0x00)&&((per.l(ad:0x40000000+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000000+0x20)&0x01)==0x01)&&((per.l(ad:0x40000000+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000000+0x20)&0x01)==0x00)&&((per.l(ad:0x40000000+0x20)&0x100)==0x100)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.l((ad:0x40000000+0x18)))&0x300)!=0x00)&&(((per.l((ad:0x40000000+0x18)))&0x03)!=0x00)
|
|
if ((per.l(ad:0x40000000+0x20)&0x01)==0x00)&&((per.l(ad:0x40000000+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000000+0x20)&0x01)==0x01)&&((per.l(ad:0x40000000+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000000+0x20)&0x01)==0x00)&&((per.l(ad:0x40000000+0x20)&0x100)==0x100)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.l((ad:0x40000000+0x18)))&0x300)==0x00)&&(((per.l((ad:0x40000000+0x18)))&0x03)!=0x00)
|
|
if ((per.l(ad:0x40000000+0x20)&0x01)==0x00)&&((per.l(ad:0x40000000+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000000+0x20)&0x01)==0x01)&&((per.l(ad:0x40000000+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000000+0x20)&0x01)==0x00)&&((per.l(ad:0x40000000+0x20)&0x100)==0x100)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40000000+0x20)&0x01)==0x00)&&((per.l(ad:0x40000000+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000000+0x20)&0x01)==0x01)&&((per.l(ad:0x40000000+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000000+0x20)&0x01)==0x00)&&((per.l(ad:0x40000000+0x20)&0x100)==0x100)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40000000+0x1C)&0x303)==0x00))
|
|
if ((per.l(ad:0x40000000+0x20)&0x1100)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif ((per.l(ad:0x40000000+0x20)&0x1100)==0x100)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif ((per.l(ad:0x40000000+0x20)&0x1100)==0x1000)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
elif (((per.l(ad:0x40000000+0x1C)&0x300)==0x00))&&(((per.l(ad:0x40000000+0x1C)&0x03)!=0x00))
|
|
if ((per.l(ad:0x40000000+0x20)&0x1100)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000000+0x20)&0x1100)==0x100)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000000+0x20)&0x1100)==0x1000)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.l(ad:0x40000000+0x1C)&0x300)!=0x00))&&(((per.l(ad:0x40000000+0x1C)&0x03)==0x00))
|
|
if ((per.l(ad:0x40000000+0x20)&0x1100)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif ((per.l(ad:0x40000000+0x20)&0x1100)==0x100)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif ((per.l(ad:0x40000000+0x20)&0x1100)==0x1000)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40000000+0x20)&0x1100)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000000+0x20)&0x1100)==0x100)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000000+0x20)&0x1100)==0x1000)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
newline
|
|
if ((((per.l((ad:0x40000000+0x18)))&0x303)==0x000)&&(((per.l((ad:0x40000000+0x1C)))&0x303)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000000+0x18)))&0x300)==0x00)&&(((per.l((ad:0x40000000+0x1C)))&0x303)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000000+0x18)))&0x03)==0x00)&&(((per.l((ad:0x40000000+0x1C)))&0x303)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000000+0x18)))&0x303)==0x00)&&(((per.l((ad:0x40000000+0x1C)))&0x300)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000000+0x18)))&0x303)==0x00)&&(((per.l((ad:0x40000000+0x1C)))&0x03)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000000+0x18)))&0x303)!=0x00)&&(((per.l((ad:0x40000000+0x1C)))&0x303)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000000+0x18)))&0x300)==0x00)&&(((per.l((ad:0x40000000+0x1C)))&0x300)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000000+0x18)))&0x300)==0x00)&&(((per.l((ad:0x40000000+0x1C)))&0x03)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000000+0x18)))&0x03)==0x00)&&(((per.l((ad:0x40000000+0x1C)))&0x300)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000000+0x18)))&0x03)==0x00)&&(((per.l((ad:0x40000000+0x1C)))&0x03)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000000+0x18)))&0x303)!=0x00)&&(((per.l((ad:0x40000000+0x1C)))&0x300)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000000+0x18)))&0x303)!=0x00)&&(((per.l((ad:0x40000000+0x1C)))&0x03)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000000+0x18)))&0x303)==0x00)&&(((per.l((ad:0x40000000+0x1C)))&0x303)!=0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000000+0x18)))&0x300)==0x00)&&(((per.l((ad:0x40000000+0x1C)))&0x303)!=0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000000+0x18)))&0x03)==0x00)&&(((per.l((ad:0x40000000+0x1C)))&0x303)!=0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.w(ad:0x40000000))&0x800)==0x800)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,Counter"
|
|
rbitfld.long 0x00 31. " UIFCPY ,Update interrupt flag copy" "Not updated,Updated"
|
|
hexmask.long 0x00 0.--30. 1. " CNT ,Counter value"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,Counter"
|
|
endif
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "PSC,Prescaler"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "ARR,Auto-Reload Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ARR[31:16] ,High auto-reload value"
|
|
hexmask.long.word 0x00 0.--15. 1. " ARR[15:0] ,Low auto-reload value"
|
|
if (((per.l(ad:0x40000000+0x18)&0x03)==0x00))
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CCR1,Capture/Compare Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " CCR1[31:16] ,High capture/compare 1 value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CCR1[15:0] ,Low capture/compare 1 value"
|
|
else
|
|
hgroup.long 0x34++0x03
|
|
hide.long 0x00 "CCR1,Capture/Compare Register 1"
|
|
in
|
|
endif
|
|
if (((per.l(ad:0x40000000+0x18)&0x300)==0x00))
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CCR2,Capture/Compare Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " CCR2[31:16] ,High capture/compare 2 value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CCR2[15:0] ,Low capture/compare 2 value"
|
|
else
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "CCR2,Capture/Compare Register 2"
|
|
in
|
|
endif
|
|
if (((per.l(ad:0x40000000+0x1C)&0x03)==0x00))
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CCR3,Capture/Compare Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " CCR3[31:16] ,High capture/compare 3 value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CCR3[15:0] ,Low capture/compare 3 value"
|
|
else
|
|
hgroup.long 0x3C++0x03
|
|
hide.long 0x00 "CCR3,Capture/Compare Register 3"
|
|
in
|
|
endif
|
|
if (((per.l(ad:0x40000000+0x1C)&0x300)==0x00))
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CCR4,Capture/Compare Register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " CCR4[31:16] ,High capture/compare 4 value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CCR4[15:0] ,Low capture/compare 4 value"
|
|
else
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "CCR4,Capture/Compare Register 4"
|
|
in
|
|
endif
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "DCR,DMA Control Register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA burst length" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,?..."
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA base address" "CR1,CR2,SMCR,DIER,SR,EGR,CCMR1,CCMR2,CCER,CNT,PSC,ARR,CCR1,CCR2,CCR3,CCR4,?..."
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "DMAR,DMA Address For Full Transfer"
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
group.word 0x50++0x01
|
|
line.word 0x00 "OR,TIM2 Option Register 1"
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*"))
|
|
bitfld.word 0x00 10.--11. " ITR1_RMP ,Internal trigger 1 remap" "TIM8_TRGOUT,,OTG FS SOF->TIM2_ITR1,OTG HS SOF->TIM2_ITR1"
|
|
else
|
|
bitfld.word 0x00 10.--11. " ITR1_RMP ,Internal trigger 1 remap" "TIM8_TRGOUT,PTP->TIM2_ITR1,OTG FS SOF->TIM2_ITR1,OTG HS SOF->TIM2_ITR1"
|
|
endif
|
|
else
|
|
newline
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "AF1,TIM2 Alternate Function Option Register 1"
|
|
bitfld.long 0x00 14.--17. " ETRSEL ,ETR source selection" "ETR input I/O,COMP1 output,COMP2 output,LSE,SAI1 FS_A,SAI1 FS_B,?..."
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "TISEL,TIM2 Timer Input Selection Register"
|
|
bitfld.long 0x00 24.--27. " TI4SEL ,TI4[0] to TI4[15] input selection" "TIM2_CH4,COMP1 output,COMP2 output,COMP1/COMP2 output,?..."
|
|
bitfld.long 0x00 16.--19. " TI3SEL ,TI3[0] to TI3[15] input selection" "TIM2_CH3,?..."
|
|
bitfld.long 0x00 8.--11. " TI2SEL ,TI2[0] to TI2[15] input selection" "TIM2_CH2,?..."
|
|
bitfld.long 0x00 0.--3. " TI1SEL ,TI1[0] to TI1[15] input selection" "TIM2_CH1,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "TIM 3"
|
|
base ad:0x40000400
|
|
width 7.
|
|
if ((per.w(ad:0x40000400)&0x60)!=0x00)||((per.w(ad:0x40000400+0x08)&0x07)==(0x01||0x02||0x03))
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,Control Register 1"
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Not remapped,Remapped"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
newline
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
newline
|
|
rbitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
newline
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,Control Register 1"
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Not remapped,Remapped"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
newline
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
newline
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
newline
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "CR2,TIM3 Control Register 2"
|
|
bitfld.word 0x00 7. " TI1S ,TI1 selection" "CH1,CH1/CH2/CH3"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,Compare pulse,Compare OC1REF,Compare OC2REF,Compare OC3REF,Compare OC4REF"
|
|
newline
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA selection" "CC3,Update"
|
|
newline
|
|
if ((per.l(ad:0x40000400)&0x10007)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SMCR,TIM3 Slave Mode Control Register"
|
|
bitfld.long 0x00 15. " ETP ,External trigger polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " ETF ,External trigger filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 7. " MSM ,Master/slave mode" "No action,TRGO delayed"
|
|
newline
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
bitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 4.--6. " TS ,Trigger selection" ",TIM2,TIM5,,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
newline
|
|
bitfld.long 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 0.--2. 16. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock,Reset + Trigger,?..."
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SMCR,TIM3 Slave Mode Control Register"
|
|
bitfld.long 0x00 15. " ETP ,External trigger polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " ETF ,External trigger filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 7. " MSM ,Master/slave mode" "No action,TRGO delayed"
|
|
newline
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
rbitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
newline
|
|
else
|
|
rbitfld.long 0x00 4.--6. " TS ,Trigger selection" ",TIM2,TIM5,,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
newline
|
|
bitfld.long 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 0.--2. 16. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock,Reset + Trigger,?..."
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "DIER,TIM3 DMA/Interrupt Enable Register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "SR,TIM3 Status Register"
|
|
bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 overcapture flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 overcapture flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 overcapture flag" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 overcapture flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt flag" "No trigger,Trigger"
|
|
bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt flag input/output" "Not captured/Not matched,Captured/Matched"
|
|
newline
|
|
bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt flag input/output" "Not captured/Not matched,Captured/Matched"
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt flag input/output" "Not captured/Not matched,Captured/Matched"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt flag input/output" "Not captured/Not matched,Captured/Matched"
|
|
newline
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt flag" "Not updated,Updated"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "EGR,TIM3 Event Generation Register"
|
|
bitfld.word 0x00 6. " TG ,Trigger generation" "No action,Trigger"
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 generation input/output" "No action/No action,Capture 4/compare 4"
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 generation input/output" "No action/No action,Capture 3/compare 3"
|
|
newline
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 generation input/output" "No action/No action,Capture 2/compare 2"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 generation input/output" "No action/No action,Capture 1/compare 1"
|
|
bitfld.word 0x00 0. " UG ,Update generation" "No action,Update"
|
|
newline
|
|
if (((per.l((ad:0x40000400+0x18)))&0x303)==0x000)
|
|
if ((per.l(ad:0x40000400+0x20)&0x01)==0x00)&&((per.l(ad:0x40000400+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000400+0x20)&0x01)==0x01)&&((per.l(ad:0x40000400+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000400+0x20)&0x01)==0x00)&&((per.l(ad:0x40000400+0x20)&0x100)==0x100)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.l((ad:0x40000400+0x18)))&0x300)!=0x00)&&(((per.l((ad:0x40000400+0x18)))&0x03)!=0x00)
|
|
if ((per.l(ad:0x40000400+0x20)&0x01)==0x00)&&((per.l(ad:0x40000400+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000400+0x20)&0x01)==0x01)&&((per.l(ad:0x40000400+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000400+0x20)&0x01)==0x00)&&((per.l(ad:0x40000400+0x20)&0x100)==0x100)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.l((ad:0x40000400+0x18)))&0x300)==0x00)&&(((per.l((ad:0x40000400+0x18)))&0x03)!=0x00)
|
|
if ((per.l(ad:0x40000400+0x20)&0x01)==0x00)&&((per.l(ad:0x40000400+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000400+0x20)&0x01)==0x01)&&((per.l(ad:0x40000400+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000400+0x20)&0x01)==0x00)&&((per.l(ad:0x40000400+0x20)&0x100)==0x100)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40000400+0x20)&0x01)==0x00)&&((per.l(ad:0x40000400+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000400+0x20)&0x01)==0x01)&&((per.l(ad:0x40000400+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000400+0x20)&0x01)==0x00)&&((per.l(ad:0x40000400+0x20)&0x100)==0x100)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40000400+0x1C)&0x303)==0x00))
|
|
if ((per.l(ad:0x40000400+0x20)&0x1100)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif ((per.l(ad:0x40000400+0x20)&0x1100)==0x100)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif ((per.l(ad:0x40000400+0x20)&0x1100)==0x1000)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
elif (((per.l(ad:0x40000400+0x1C)&0x300)==0x00))&&(((per.l(ad:0x40000400+0x1C)&0x03)!=0x00))
|
|
if ((per.l(ad:0x40000400+0x20)&0x1100)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000400+0x20)&0x1100)==0x100)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000400+0x20)&0x1100)==0x1000)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.l(ad:0x40000400+0x1C)&0x300)!=0x00))&&(((per.l(ad:0x40000400+0x1C)&0x03)==0x00))
|
|
if ((per.l(ad:0x40000400+0x20)&0x1100)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif ((per.l(ad:0x40000400+0x20)&0x1100)==0x100)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif ((per.l(ad:0x40000400+0x20)&0x1100)==0x1000)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40000400+0x20)&0x1100)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000400+0x20)&0x1100)==0x100)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000400+0x20)&0x1100)==0x1000)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
newline
|
|
if ((((per.l((ad:0x40000400+0x18)))&0x303)==0x000)&&(((per.l((ad:0x40000400+0x1C)))&0x303)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000400+0x18)))&0x300)==0x00)&&(((per.l((ad:0x40000400+0x1C)))&0x303)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000400+0x18)))&0x03)==0x00)&&(((per.l((ad:0x40000400+0x1C)))&0x303)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000400+0x18)))&0x303)==0x00)&&(((per.l((ad:0x40000400+0x1C)))&0x300)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000400+0x18)))&0x303)==0x00)&&(((per.l((ad:0x40000400+0x1C)))&0x03)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000400+0x18)))&0x303)!=0x00)&&(((per.l((ad:0x40000400+0x1C)))&0x303)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000400+0x18)))&0x300)==0x00)&&(((per.l((ad:0x40000400+0x1C)))&0x300)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000400+0x18)))&0x300)==0x00)&&(((per.l((ad:0x40000400+0x1C)))&0x03)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000400+0x18)))&0x03)==0x00)&&(((per.l((ad:0x40000400+0x1C)))&0x300)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000400+0x18)))&0x03)==0x00)&&(((per.l((ad:0x40000400+0x1C)))&0x03)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000400+0x18)))&0x303)!=0x00)&&(((per.l((ad:0x40000400+0x1C)))&0x300)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000400+0x18)))&0x303)!=0x00)&&(((per.l((ad:0x40000400+0x1C)))&0x03)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000400+0x18)))&0x303)==0x00)&&(((per.l((ad:0x40000400+0x1C)))&0x303)!=0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000400+0x18)))&0x300)==0x00)&&(((per.l((ad:0x40000400+0x1C)))&0x303)!=0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000400+0x18)))&0x03)==0x00)&&(((per.l((ad:0x40000400+0x1C)))&0x303)!=0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32F75*8"))
|
|
if (((per.w(ad:0x40000400))&0x800)==0x800)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,Counter"
|
|
rbitfld.long 0x00 31. " UIFCPY ,Update interrupt flag copy" "Not updated,Updated"
|
|
hexmask.long 0x00 0.--30. 1. " CNT ,Counter value"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,Counter"
|
|
textfld " "
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Least significant part counter value"
|
|
endif
|
|
else
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "CNT,Counter"
|
|
endif
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "PSC,Prescaler"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "ARR,Auto-reload Register"
|
|
if (((per.l(ad:0x40000400+0x18)&0x03)==0x00))
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CCR1,Capture/Compare Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " CCR1[15:0] ,Low capture/compare 1 value"
|
|
else
|
|
hgroup.long 0x34++0x03
|
|
hide.long 0x00 "CCR1,Capture/Compare Register 1"
|
|
in
|
|
endif
|
|
if (((per.l(ad:0x40000400+0x18)&0x300)==0x00))
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CCR2,Capture/Compare Register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. " CCR2[15:0] ,Low capture/compare 2 value"
|
|
else
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "CCR2,Capture/Compare Register 2"
|
|
in
|
|
endif
|
|
if (((per.l(ad:0x40000400+0x1C)&0x03)==0x00))
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CCR3,Capture/Compare Register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. " CCR1[15:0] ,Low capture/compare 3 value"
|
|
else
|
|
hgroup.long 0x3C++0x03
|
|
hide.long 0x00 "CCR3,Capture/Compare Register 3"
|
|
in
|
|
endif
|
|
if (((per.l(ad:0x40000400+0x1C)&0x300)==0x00))
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CCR4,Capture/Compare Register 4"
|
|
hexmask.long.word 0x00 0.--15. 1. " CCR1[15:0] ,Low capture/compare 4 value"
|
|
else
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "CCR4,Capture/Compare Register 4"
|
|
in
|
|
endif
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "DCR,DMA Control Register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA burst length" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,?..."
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA base address" "CR1,CR2,SMCR,DIER,SR,EGR,CCMR1,CCMR2,CCER,CNT,PSC,ARR,CCR1,CCR2,CCR3,CCR4,?..."
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "DMAR,DMA Address For Full Transfer"
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
else
|
|
newline
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "AF1,TIM3 Alternate Function Option Register 1"
|
|
bitfld.long 0x00 14.--17. " ETRSEL ,ETR source selection" "ETR input I/O,COMP1 output,?..."
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "TISEL,TIM3 Timer Input Selection Register"
|
|
bitfld.long 0x00 24.--27. " TI4SEL ,TI4[0] to TI4[15] input selection" "TIM3_CH4,?..."
|
|
bitfld.long 0x00 16.--19. " TI3SEL ,TI3[0] to TI3[15] input selection" "TIM3_CH3,?..."
|
|
bitfld.long 0x00 8.--11. " TI2SEL ,TI2[0] to TI2[15] input selection" "TIM3_CH2,?..."
|
|
bitfld.long 0x00 0.--3. " TI1SEL ,TI1[0] to TI1[15] input selection" "TIM3_CH1,COMP1 output,COMP2 output,COMP1/COMP2 output,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "TIM 4"
|
|
base ad:0x40000800
|
|
width 7.
|
|
if ((per.w(ad:0x40000800)&0x60)!=0x00)||((per.w(ad:0x40000800+0x08)&0x07)==(0x01||0x02||0x03))
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,Control Register 1"
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Not remapped,Remapped"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
newline
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
newline
|
|
rbitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
newline
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,Control Register 1"
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Not remapped,Remapped"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
newline
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
newline
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
newline
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "CR2,TIM4 Control Register 2"
|
|
bitfld.word 0x00 7. " TI1S ,TI1 selection" "CH1,CH1/CH2/CH3"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,Compare pulse,Compare OC1REF,Compare OC2REF,Compare OC3REF,Compare OC4REF"
|
|
newline
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA selection" "CC4,Update"
|
|
newline
|
|
if ((per.l(ad:0x40000800)&0x10007)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SMCR,TIM4 Slave Mode Control Register"
|
|
bitfld.long 0x00 15. " ETP ,External trigger polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " ETF ,External trigger filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 7. " MSM ,Master/slave mode" "No action,TRGO delayed"
|
|
newline
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
bitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 4.--6. " TS ,Trigger selection" ",TIM2,TIM3,,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
newline
|
|
bitfld.long 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 0.--2. 16. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock,Reset + Trigger,?..."
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SMCR,TIM4 Slave Mode Control Register"
|
|
bitfld.long 0x00 15. " ETP ,External trigger polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " ETF ,External trigger filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 7. " MSM ,Master/slave mode" "No action,TRGO delayed"
|
|
newline
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
rbitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
newline
|
|
else
|
|
rbitfld.long 0x00 4.--6. " TS ,Trigger selection" ",TIM2,TIM3,,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
newline
|
|
bitfld.long 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 0.--2. 16. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock,Reset + Trigger,?..."
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "DIER,TIM4 DMA/Interrupt Enable Register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "SR,TIM4 Status Register"
|
|
bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 overcapture flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 overcapture flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 overcapture flag" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 overcapture flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt flag" "No trigger,Trigger"
|
|
bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt flag input/output" "Not captured/Not matched,Captured/Matched"
|
|
newline
|
|
bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt flag input/output" "Not captured/Not matched,Captured/Matched"
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt flag input/output" "Not captured/Not matched,Captured/Matched"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt flag input/output" "Not captured/Not matched,Captured/Matched"
|
|
newline
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt flag" "Not updated,Updated"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "EGR,TIM4 Event Generation Register"
|
|
bitfld.word 0x00 6. " TG ,Trigger generation" "No action,Trigger"
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 generation input/output" "No action/No action,Capture 4/compare 4"
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 generation input/output" "No action/No action,Capture 3/compare 3"
|
|
newline
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 generation input/output" "No action/No action,Capture 2/compare 2"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 generation input/output" "No action/No action,Capture 1/compare 1"
|
|
bitfld.word 0x00 0. " UG ,Update generation" "No action,Update"
|
|
newline
|
|
if (((per.l((ad:0x40000800+0x18)))&0x303)==0x000)
|
|
if ((per.l(ad:0x40000800+0x20)&0x01)==0x00)&&((per.l(ad:0x40000800+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000800+0x20)&0x01)==0x01)&&((per.l(ad:0x40000800+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000800+0x20)&0x01)==0x00)&&((per.l(ad:0x40000800+0x20)&0x100)==0x100)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.l((ad:0x40000800+0x18)))&0x300)!=0x00)&&(((per.l((ad:0x40000800+0x18)))&0x03)!=0x00)
|
|
if ((per.l(ad:0x40000800+0x20)&0x01)==0x00)&&((per.l(ad:0x40000800+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000800+0x20)&0x01)==0x01)&&((per.l(ad:0x40000800+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000800+0x20)&0x01)==0x00)&&((per.l(ad:0x40000800+0x20)&0x100)==0x100)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.l((ad:0x40000800+0x18)))&0x300)==0x00)&&(((per.l((ad:0x40000800+0x18)))&0x03)!=0x00)
|
|
if ((per.l(ad:0x40000800+0x20)&0x01)==0x00)&&((per.l(ad:0x40000800+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000800+0x20)&0x01)==0x01)&&((per.l(ad:0x40000800+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000800+0x20)&0x01)==0x00)&&((per.l(ad:0x40000800+0x20)&0x100)==0x100)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40000800+0x20)&0x01)==0x00)&&((per.l(ad:0x40000800+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000800+0x20)&0x01)==0x01)&&((per.l(ad:0x40000800+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000800+0x20)&0x01)==0x00)&&((per.l(ad:0x40000800+0x20)&0x100)==0x100)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40000800+0x1C)&0x303)==0x00))
|
|
if ((per.l(ad:0x40000800+0x20)&0x1100)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif ((per.l(ad:0x40000800+0x20)&0x1100)==0x100)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif ((per.l(ad:0x40000800+0x20)&0x1100)==0x1000)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
elif (((per.l(ad:0x40000800+0x1C)&0x300)==0x00))&&(((per.l(ad:0x40000800+0x1C)&0x03)!=0x00))
|
|
if ((per.l(ad:0x40000800+0x20)&0x1100)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000800+0x20)&0x1100)==0x100)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000800+0x20)&0x1100)==0x1000)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.l(ad:0x40000800+0x1C)&0x300)!=0x00))&&(((per.l(ad:0x40000800+0x1C)&0x03)==0x00))
|
|
if ((per.l(ad:0x40000800+0x20)&0x1100)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif ((per.l(ad:0x40000800+0x20)&0x1100)==0x100)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif ((per.l(ad:0x40000800+0x20)&0x1100)==0x1000)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40000800+0x20)&0x1100)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000800+0x20)&0x1100)==0x100)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000800+0x20)&0x1100)==0x1000)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
newline
|
|
if ((((per.l((ad:0x40000800+0x18)))&0x303)==0x000)&&(((per.l((ad:0x40000800+0x1C)))&0x303)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000800+0x18)))&0x300)==0x00)&&(((per.l((ad:0x40000800+0x1C)))&0x303)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000800+0x18)))&0x03)==0x00)&&(((per.l((ad:0x40000800+0x1C)))&0x303)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000800+0x18)))&0x303)==0x00)&&(((per.l((ad:0x40000800+0x1C)))&0x300)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000800+0x18)))&0x303)==0x00)&&(((per.l((ad:0x40000800+0x1C)))&0x03)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000800+0x18)))&0x303)!=0x00)&&(((per.l((ad:0x40000800+0x1C)))&0x303)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000800+0x18)))&0x300)==0x00)&&(((per.l((ad:0x40000800+0x1C)))&0x300)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000800+0x18)))&0x300)==0x00)&&(((per.l((ad:0x40000800+0x1C)))&0x03)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000800+0x18)))&0x03)==0x00)&&(((per.l((ad:0x40000800+0x1C)))&0x300)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000800+0x18)))&0x03)==0x00)&&(((per.l((ad:0x40000800+0x1C)))&0x03)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000800+0x18)))&0x303)!=0x00)&&(((per.l((ad:0x40000800+0x1C)))&0x300)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000800+0x18)))&0x303)!=0x00)&&(((per.l((ad:0x40000800+0x1C)))&0x03)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000800+0x18)))&0x303)==0x00)&&(((per.l((ad:0x40000800+0x1C)))&0x303)!=0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000800+0x18)))&0x300)==0x00)&&(((per.l((ad:0x40000800+0x1C)))&0x303)!=0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000800+0x18)))&0x03)==0x00)&&(((per.l((ad:0x40000800+0x1C)))&0x303)!=0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32F75*8"))
|
|
if (((per.w(ad:0x40000800))&0x800)==0x800)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,Counter"
|
|
rbitfld.long 0x00 31. " UIFCPY ,Update interrupt flag copy" "Not updated,Updated"
|
|
hexmask.long 0x00 0.--30. 1. " CNT ,Counter value"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,Counter"
|
|
textfld " "
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Least significant part counter value"
|
|
endif
|
|
else
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "CNT,Counter"
|
|
endif
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "PSC,Prescaler"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "ARR,Auto-reload Register"
|
|
if (((per.l(ad:0x40000800+0x18)&0x03)==0x00))
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CCR1,Capture/Compare Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " CCR1[15:0] ,Low capture/compare 1 value"
|
|
else
|
|
hgroup.long 0x34++0x03
|
|
hide.long 0x00 "CCR1,Capture/Compare Register 1"
|
|
in
|
|
endif
|
|
if (((per.l(ad:0x40000800+0x18)&0x300)==0x00))
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CCR2,Capture/Compare Register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. " CCR2[15:0] ,Low capture/compare 2 value"
|
|
else
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "CCR2,Capture/Compare Register 2"
|
|
in
|
|
endif
|
|
if (((per.l(ad:0x40000800+0x1C)&0x03)==0x00))
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CCR3,Capture/Compare Register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. " CCR1[15:0] ,Low capture/compare 3 value"
|
|
else
|
|
hgroup.long 0x3C++0x03
|
|
hide.long 0x00 "CCR3,Capture/Compare Register 3"
|
|
in
|
|
endif
|
|
if (((per.l(ad:0x40000800+0x1C)&0x300)==0x00))
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CCR4,Capture/Compare Register 4"
|
|
hexmask.long.word 0x00 0.--15. 1. " CCR1[15:0] ,Low capture/compare 4 value"
|
|
else
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "CCR4,Capture/Compare Register 4"
|
|
in
|
|
endif
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "DCR,DMA Control Register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA burst length" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,?..."
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA base address" "CR1,CR2,SMCR,DIER,SR,EGR,CCMR1,CCMR2,CCER,CNT,PSC,ARR,CCR1,CCR2,CCR3,CCR4,?..."
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "DMAR,DMA Address For Full Transfer"
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
else
|
|
newline
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "TIM 5"
|
|
base ad:0x40000C00
|
|
width 7.
|
|
if ((per.w(ad:0x40000C00)&0x60)!=0x00)||((per.w(ad:0x40000C00+0x08)&0x07)==(0x01||0x02||0x03))
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,Control Register 1"
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Not remapped,Remapped"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
newline
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
newline
|
|
rbitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
newline
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,Control Register 1"
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Not remapped,Remapped"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
newline
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
newline
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
newline
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "CR2,TIM5 Control Register 2"
|
|
bitfld.word 0x00 7. " TI1S ,TI1 selection" "CH1,CH1/CH2/CH3"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,Compare pulse,Compare OC1REF,Compare OC2REF,Compare OC3REF,Compare OC4REF"
|
|
newline
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA selection" "CC5,Update"
|
|
newline
|
|
if ((per.l(ad:0x40000C00)&0x10007)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SMCR,TIM5 Slave Mode Control Register"
|
|
bitfld.long 0x00 15. " ETP ,External trigger polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " ETF ,External trigger filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 7. " MSM ,Master/slave mode" "No action,TRGO delayed"
|
|
newline
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
bitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 4.--6. " TS ,Trigger selection" ",TIM3,TIM4,,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
newline
|
|
bitfld.long 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 0.--2. 16. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock,Reset + Trigger,?..."
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SMCR,TIM5 Slave Mode Control Register"
|
|
bitfld.long 0x00 15. " ETP ,External trigger polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " ETF ,External trigger filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 7. " MSM ,Master/slave mode" "No action,TRGO delayed"
|
|
newline
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
rbitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
newline
|
|
else
|
|
rbitfld.long 0x00 4.--6. " TS ,Trigger selection" ",TIM3,TIM4,,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
newline
|
|
bitfld.long 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 0.--2. 16. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock,Reset + Trigger,?..."
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "DIER,TIM5 DMA/Interrupt Enable Register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "SR,TIM5 Status Register"
|
|
bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 overcapture flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 overcapture flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 overcapture flag" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 overcapture flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt flag" "No trigger,Trigger"
|
|
bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt flag input/output" "Not captured/Not matched,Captured/Matched"
|
|
newline
|
|
bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt flag input/output" "Not captured/Not matched,Captured/Matched"
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt flag input/output" "Not captured/Not matched,Captured/Matched"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt flag input/output" "Not captured/Not matched,Captured/Matched"
|
|
newline
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt flag" "Not updated,Updated"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "EGR,TIM5 Event Generation Register"
|
|
bitfld.word 0x00 6. " TG ,Trigger generation" "No action,Trigger"
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 generation input/output" "No action/No action,Capture 4/compare 4"
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 generation input/output" "No action/No action,Capture 3/compare 3"
|
|
newline
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 generation input/output" "No action/No action,Capture 2/compare 2"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 generation input/output" "No action/No action,Capture 1/compare 1"
|
|
bitfld.word 0x00 0. " UG ,Update generation" "No action,Update"
|
|
newline
|
|
if (((per.l((ad:0x40000C00+0x18)))&0x303)==0x000)
|
|
if ((per.l(ad:0x40000C00+0x20)&0x01)==0x00)&&((per.l(ad:0x40000C00+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000C00+0x20)&0x01)==0x01)&&((per.l(ad:0x40000C00+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000C00+0x20)&0x01)==0x00)&&((per.l(ad:0x40000C00+0x20)&0x100)==0x100)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.l((ad:0x40000C00+0x18)))&0x300)!=0x00)&&(((per.l((ad:0x40000C00+0x18)))&0x03)!=0x00)
|
|
if ((per.l(ad:0x40000C00+0x20)&0x01)==0x00)&&((per.l(ad:0x40000C00+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000C00+0x20)&0x01)==0x01)&&((per.l(ad:0x40000C00+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000C00+0x20)&0x01)==0x00)&&((per.l(ad:0x40000C00+0x20)&0x100)==0x100)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.l((ad:0x40000C00+0x18)))&0x300)==0x00)&&(((per.l((ad:0x40000C00+0x18)))&0x03)!=0x00)
|
|
if ((per.l(ad:0x40000C00+0x20)&0x01)==0x00)&&((per.l(ad:0x40000C00+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000C00+0x20)&0x01)==0x01)&&((per.l(ad:0x40000C00+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000C00+0x20)&0x01)==0x00)&&((per.l(ad:0x40000C00+0x20)&0x100)==0x100)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40000C00+0x20)&0x01)==0x00)&&((per.l(ad:0x40000C00+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000C00+0x20)&0x01)==0x01)&&((per.l(ad:0x40000C00+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000C00+0x20)&0x01)==0x00)&&((per.l(ad:0x40000C00+0x20)&0x100)==0x100)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40000C00+0x1C)&0x303)==0x00))
|
|
if ((per.l(ad:0x40000C00+0x20)&0x1100)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif ((per.l(ad:0x40000C00+0x20)&0x1100)==0x100)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif ((per.l(ad:0x40000C00+0x20)&0x1100)==0x1000)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
elif (((per.l(ad:0x40000C00+0x1C)&0x300)==0x00))&&(((per.l(ad:0x40000C00+0x1C)&0x03)!=0x00))
|
|
if ((per.l(ad:0x40000C00+0x20)&0x1100)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000C00+0x20)&0x1100)==0x100)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000C00+0x20)&0x1100)==0x1000)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output compare 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.l(ad:0x40000C00+0x1C)&0x300)!=0x00))&&(((per.l(ad:0x40000C00+0x1C)&0x03)==0x00))
|
|
if ((per.l(ad:0x40000C00+0x20)&0x1100)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif ((per.l(ad:0x40000C00+0x20)&0x1100)==0x100)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif ((per.l(ad:0x40000C00+0x20)&0x1100)==0x1000)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 7. " OC3CE ,Output compare 3 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40000C00+0x20)&0x1100)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000C00+0x20)&0x1100)==0x100)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40000C00+0x20)&0x1100)==0x1000)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " CC3S ,Capture/compare 3 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
newline
|
|
if ((((per.l((ad:0x40000C00+0x18)))&0x303)==0x000)&&(((per.l((ad:0x40000C00+0x1C)))&0x303)==0x000))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000C00+0x18)))&0x300)==0x00)&&(((per.l((ad:0x40000C00+0x1C)))&0x303)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000C00+0x18)))&0x03)==0x00)&&(((per.l((ad:0x40000C00+0x1C)))&0x303)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000C00+0x18)))&0x303)==0x00)&&(((per.l((ad:0x40000C00+0x1C)))&0x300)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000C00+0x18)))&0x303)==0x00)&&(((per.l((ad:0x40000C00+0x1C)))&0x03)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000C00+0x18)))&0x303)!=0x00)&&(((per.l((ad:0x40000C00+0x1C)))&0x303)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000C00+0x18)))&0x300)==0x00)&&(((per.l((ad:0x40000C00+0x1C)))&0x300)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000C00+0x18)))&0x300)==0x00)&&(((per.l((ad:0x40000C00+0x1C)))&0x03)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000C00+0x18)))&0x03)==0x00)&&(((per.l((ad:0x40000C00+0x1C)))&0x300)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000C00+0x18)))&0x03)==0x00)&&(((per.l((ad:0x40000C00+0x1C)))&0x03)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000C00+0x18)))&0x303)!=0x00)&&(((per.l((ad:0x40000C00+0x1C)))&0x300)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Compare 4 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 12. " CC4E ,Compare 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000C00+0x18)))&0x303)!=0x00)&&(((per.l((ad:0x40000C00+0x1C)))&0x03)==0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Compare 3 output polarity" "Active high,Active low,?..."
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Compare 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000C00+0x18)))&0x303)==0x00)&&(((per.l((ad:0x40000C00+0x1C)))&0x303)!=0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000C00+0x18)))&0x300)==0x00)&&(((per.l((ad:0x40000C00+0x1C)))&0x303)!=0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif ((((per.l((ad:0x40000C00+0x18)))&0x03)==0x00)&&(((per.l((ad:0x40000C00+0x1C)))&0x303)!=0x00))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. 15. " CC4NP_CC4P ,Capture 4 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 12. " CC4E ,Capture 4 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. 11. " CC3NP_CC3P ,Capture 3 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
newline
|
|
bitfld.word 0x00 8. " CC3E ,Capture 3 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.w(ad:0x40000C00))&0x800)==0x800)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,Counter"
|
|
rbitfld.long 0x00 31. " UIFCPY ,Update interrupt flag copy" "Not updated,Updated"
|
|
hexmask.long 0x00 0.--30. 1. " CNT ,Counter value"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,Counter"
|
|
endif
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "PSC,Prescaler"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "ARR,Auto-Reload Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ARR[31:16] ,High auto-reload value"
|
|
hexmask.long.word 0x00 0.--15. 1. " ARR[15:0] ,Low auto-reload value"
|
|
if (((per.l(ad:0x40000C00+0x18)&0x03)==0x00))
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CCR1,Capture/Compare Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " CCR1[31:16] ,High capture/compare 1 value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CCR1[15:0] ,Low capture/compare 1 value"
|
|
else
|
|
hgroup.long 0x34++0x03
|
|
hide.long 0x00 "CCR1,Capture/Compare Register 1"
|
|
in
|
|
endif
|
|
if (((per.l(ad:0x40000C00+0x18)&0x300)==0x00))
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CCR2,Capture/Compare Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " CCR2[31:16] ,High capture/compare 2 value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CCR2[15:0] ,Low capture/compare 2 value"
|
|
else
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "CCR2,Capture/Compare Register 2"
|
|
in
|
|
endif
|
|
if (((per.l(ad:0x40000C00+0x1C)&0x03)==0x00))
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CCR3,Capture/Compare Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " CCR3[31:16] ,High capture/compare 3 value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CCR3[15:0] ,Low capture/compare 3 value"
|
|
else
|
|
hgroup.long 0x3C++0x03
|
|
hide.long 0x00 "CCR3,Capture/Compare Register 3"
|
|
in
|
|
endif
|
|
if (((per.l(ad:0x40000C00+0x1C)&0x300)==0x00))
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CCR4,Capture/Compare Register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " CCR4[31:16] ,High capture/compare 4 value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CCR4[15:0] ,Low capture/compare 4 value"
|
|
else
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "CCR4,Capture/Compare Register 4"
|
|
in
|
|
endif
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "DCR,DMA Control Register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA burst length" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,?..."
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA base address" "CR1,CR2,SMCR,DIER,SR,EGR,CCMR1,CCMR2,CCER,CNT,PSC,ARR,CCR1,CCR2,CCR3,CCR4,?..."
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "DMAR,DMA Address For Full Transfer"
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
group.word 0x50++0x01
|
|
line.word 0x00 "OR,TIM5 Option Register 1"
|
|
bitfld.word 0x00 6.--7. " TI4_RMP ,Timer input 4 remap" "TIM5_CH4->GPIO,LSI->TIM5_CH4,LSE->TIM5_CH4,RTC->TIM5_CH4"
|
|
else
|
|
newline
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "AF1,TIM5 Alternate Function Option Register 1"
|
|
bitfld.long 0x00 14.--17. " ETRSEL ,ETR source selection" "ETR input I/O,SAI2 FS_A,SAI2 FS_B,?..."
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "TISEL,TIM5 Timer Input Selection Register"
|
|
bitfld.long 0x00 24.--27. " TI4SEL ,TI4[0] to TI4[15] input selection" "TIM5_CH4,?..."
|
|
bitfld.long 0x00 16.--19. " TI3SEL ,TI3[0] to TI3[15] input selection" "TIM5_CH3,?..."
|
|
bitfld.long 0x00 8.--11. " TI2SEL ,TI2[0] to TI2[15] input selection" "TIM5_CH2,?..."
|
|
bitfld.long 0x00 0.--3. " TI1SEL ,TI1[0] to TI1[15] input selection" "TIM5_CH1,fdcan1_tmp,fdcan1_rtp,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "TIM 9"
|
|
base ad:0x40014000
|
|
width 13.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TIM9_CR1,Control Register 1"
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32F730*8")||cpuis("STM32F750*8"))
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "No remapping,Remapping"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/UG set,Overflow"
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
if ((per.l(ad:0x40014000+0x08)&0x07)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TIM9_SMCR,Slave Mode Control Register"
|
|
bitfld.long 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
sif !cpuis("STM32F730*8")
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
newline
|
|
bitfld.long 0x00 4.--6. " TS ,Trigger selection" "TIM2,TIM3,TIM10_OC,TIM11_OC,?..."
|
|
else
|
|
newline
|
|
bitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,?..."
|
|
endif
|
|
else
|
|
newline
|
|
bitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 0.--2. 16. " SMS ,Slave mode selection" "Disabled,,,,Reset,Gated,Trigger,External Clk,Reset + trigger,?..."
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TIM9_SMCR,Slave Mode Control Register"
|
|
bitfld.long 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
newline
|
|
rbitfld.long 0x00 4.--6. " TS ,Trigger selection" "TIM2,TIM3,TIM10_OC,TIM11_OC,?..."
|
|
else
|
|
newline
|
|
rbitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 0.--2. 16. " SMS ,Slave mode selection" "Disabled,,,,Reset,Gated,Trigger,External Clk,Reset + trigger,?..."
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TIM9_DIER,DMA/Interrupt Enable Register"
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "TIM9_SR,Status Register"
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 overcapture flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 overcapture flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt flag" "No trigger,Trigger"
|
|
newline
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "Not captured/Not matched,Captured/Matched"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "Not captured/Not matched,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt flag" "No update,Update"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "TIM9_EGR,Event Generation Register"
|
|
bitfld.word 0x00 6. " TG ,Trigger generation" "No action,Trigger"
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 generation input/output" "No action/No action,Capture 2/compare 2"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 generation input/output" "No action/No action,Capture 1/compare 1"
|
|
newline
|
|
bitfld.word 0x00 0. " UG ,Update generation" "No action,Update"
|
|
newline
|
|
if (((per.l((ad:0x40014000+0x18)))&0x303)==0x000)
|
|
if ((per.l(ad:0x40014000+0x20)&0x01)==0x00)&&((per.l(ad:0x40014000+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM9_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,?..."
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,?..."
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40014000+0x20)&0x01)==0x01)&&((per.l(ad:0x40014000+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM9_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,?..."
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,?..."
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40014000+0x20)&0x01)==0x00)&&((per.l(ad:0x40014000+0x20)&0x100)==0x100)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM9_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,?..."
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,?..."
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM9_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,?..."
|
|
bitfld.long 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal,Fast"
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,?..."
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.l((ad:0x40014000+0x18)))&0x300)!=0x00)&&(((per.l((ad:0x40014000+0x18)))&0x03)!=0x00)
|
|
if ((per.l(ad:0x40014000+0x20)&0x01)==0x00)&&((per.l(ad:0x40014000+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM9_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40014000+0x20)&0x01)==0x01)&&((per.l(ad:0x40014000+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM9_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40014000+0x20)&0x01)==0x00)&&((per.l(ad:0x40014000+0x20)&0x100)==0x100)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM9_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM9_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input Capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.l((ad:0x40014000+0x18)))&0x300)==0x00)&&(((per.l((ad:0x40014000+0x18)))&0x03)!=0x00)
|
|
if ((per.l(ad:0x40014000+0x20)&0x01)==0x00)&&((per.l(ad:0x40014000+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM9_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40014000+0x20)&0x01)==0x01)&&((per.l(ad:0x40014000+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM9_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40014000+0x20)&0x01)==0x00)&&((per.l(ad:0x40014000+0x20)&0x100)==0x100)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM9_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output Compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal,Fast"
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM9_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40014000+0x20)&0x01)==0x00)&&((per.l(ad:0x40014000+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM9_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40014000+0x20)&0x01)==0x01)&&((per.l(ad:0x40014000+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM9_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40014000+0x20)&0x01)==0x00)&&((per.l(ad:0x40014000+0x20)&0x100)==0x100)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM9_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM9_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output Compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
newline
|
|
if (((per.w((ad:0x40014000+0x18)))&0x303)==0x000)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM9_CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
newline
|
|
bitfld.word 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif (((per.w((ad:0x40014000+0x18)))&0x300)==0x000)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM9_CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
newline
|
|
bitfld.word 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif (((per.w((ad:0x40014000+0x18)))&0x3)==0x0)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM9_CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
newline
|
|
bitfld.word 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM9_CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
newline
|
|
bitfld.word 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32F730*8")||cpuis("STM32F750*8"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM9_CNT,Counter"
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
rbitfld.long 0x00 31. " UIFCPY ,Update interrupt flag copy" "Not updated,Updated"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 31. " UIFCPY ,Update interrupt flag copy" "Not updated,Updated"
|
|
newline
|
|
endif
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
else
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "TIM9_CNT,Counter"
|
|
endif
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "TIM9_PSC,Prescaler"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "TIM9_ARR,Auto-Reload Register"
|
|
hgroup.word 0x34++0x01
|
|
hide.word 0x00 "TIM9_CCR1,Capture/Compare Register 1"
|
|
in
|
|
hgroup.word 0x38++0x01
|
|
hide.word 0x00 "TIM9_CCR2,Capture/Compare Register 2"
|
|
in
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
group.word 0x68++0x01
|
|
line.word 0x00 "TIM9_TISEL,Timer Input Selection Register"
|
|
bitfld.word 0x00 8.--11. " TI2SEL ,Selects TI2[0] to TI2[15] input" "TIM12_CH2,?..."
|
|
bitfld.word 0x00 0.--3. " TI1SEL ,Selects TI1[0] to TI1[15] input" "TIM12_CH1,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "TIM 10"
|
|
base ad:0x40014400
|
|
width 7.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,Control Register 1"
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32F730*")||cpuis("STM32F750*8"))
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "No remapping,Remapping"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
newline
|
|
bitfld.word 0x00 3. " OPM ,One-pulse mode" "Not stopped,Stopped"
|
|
newline
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/UG set,Overflow"
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
newline
|
|
else
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "DIER,DMA/Interrupt Enable Register"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "SR,Status Register"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 overcapture flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt flag input/output" "Not captured/Not matched,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt flag" "No update,Update"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "EGR,Event Generation Register"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 generation input/output" "No action/No action,Capture 1/compare 1"
|
|
bitfld.word 0x00 0. " UG ,Update generation" "No action,Update"
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*")&&!cpuis("STM32F72*")&&!cpuis("STM32F73*")&&!cpuis("STM32F76*")&&!cpuis("STM32F77*")&&!cpuis("STM32F75*0")&&!cpuis("STM32F750*"))
|
|
if (((per.w((ad:0x40014400+0x18)))&0x03)==0x00)&&((per.w(ad:0x40014400+0x20)&0x01)==0x00)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/ic1 mapped on TI2,Input/ic1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.l((ad:0x40014400+0x18)))&0x03)==0x00)
|
|
if ((per.l(ad:0x40014400+0x20)&0x01)==0x00)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40014400+0x20)&0x01)==0x00)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/ic1 mapped on TI2,Input/ic1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/ic1 mapped on TI2,Input/ic1 mapped on TRC"
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.w((ad:0x40014400+0x18)))&0x03)==0x00)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Both edges"
|
|
bitfld.word 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis(STM32F7*0*8))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,Counter"
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
rbitfld.long 0x00 31. " UIFCPY ,Update interrupt flag copy" "Not updated,Updated"
|
|
else
|
|
bitfld.long 0x00 31. " UIFCPY ,Update interrupt flag copy" "Not updated,Updated"
|
|
endif
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
else
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "CNT,Counter"
|
|
endif
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "PSC,Prescaler"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "ARR,Auto-Reload Register"
|
|
if (((per.l(ad:0x40014400+0x18)&0x03)==0x00))
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "CCR1,Capture/Compare Register 1"
|
|
else
|
|
hgroup.word 0x34++0x01
|
|
hide.word 0x00 "CCR1,Capture/Compare Register 1"
|
|
in
|
|
endif
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
group.word 0x50++0x01
|
|
line.word 0x00 "OR,TIM10 Option Register 1"
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*"))
|
|
bitfld.word 0x00 0.--1. " TI1_RMP ,TIM10 input 1 remapping capability" "TIM11_CH1->GPIO,,HSE->TIM11_CH1,MCO1->TIM11_CH1"
|
|
else
|
|
bitfld.word 0x00 0.--1. " TI1_RMP ,TIM10 input 1 remapping capability" "TIM11_CH1->GPIO,SPDIFRX Frame synchronous,HSE->TIM11_CH1,MCO1->TIM11_CH1"
|
|
endif
|
|
else
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "TIM 11"
|
|
base ad:0x40014800
|
|
width 7.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,Control Register 1"
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32F730*")||cpuis("STM32F750*8"))
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "No remapping,Remapping"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
newline
|
|
bitfld.word 0x00 3. " OPM ,One-pulse mode" "Not stopped,Stopped"
|
|
newline
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/UG set,Overflow"
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
newline
|
|
else
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "DIER,DMA/Interrupt Enable Register"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "SR,Status Register"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 overcapture flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt flag input/output" "Not captured/Not matched,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt flag" "No update,Update"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "EGR,Event Generation Register"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 generation input/output" "No action/No action,Capture 1/compare 1"
|
|
bitfld.word 0x00 0. " UG ,Update generation" "No action,Update"
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*")&&!cpuis("STM32F72*")&&!cpuis("STM32F73*")&&!cpuis("STM32F76*")&&!cpuis("STM32F77*")&&!cpuis("STM32F75*0")&&!cpuis("STM32F750*"))
|
|
if (((per.w((ad:0x40014800+0x18)))&0x03)==0x00)&&((per.w(ad:0x40014800+0x20)&0x01)==0x00)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/ic1 mapped on TI2,Input/ic1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.l((ad:0x40014800+0x18)))&0x03)==0x00)
|
|
if ((per.l(ad:0x40014800+0x20)&0x01)==0x00)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40014800+0x20)&0x01)==0x00)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/ic1 mapped on TI2,Input/ic1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/ic1 mapped on TI2,Input/ic1 mapped on TRC"
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.w((ad:0x40014800+0x18)))&0x03)==0x00)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Both edges"
|
|
bitfld.word 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis(STM32F7*0*8))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,Counter"
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
rbitfld.long 0x00 31. " UIFCPY ,Update interrupt flag copy" "Not updated,Updated"
|
|
else
|
|
bitfld.long 0x00 31. " UIFCPY ,Update interrupt flag copy" "Not updated,Updated"
|
|
endif
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
else
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "CNT,Counter"
|
|
endif
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "PSC,Prescaler"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "ARR,Auto-Reload Register"
|
|
if (((per.l(ad:0x40014800+0x18)&0x03)==0x00))
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "CCR1,Capture/Compare Register 1"
|
|
else
|
|
hgroup.word 0x34++0x01
|
|
hide.word 0x00 "CCR1,Capture/Compare Register 1"
|
|
in
|
|
endif
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
group.word 0x50++0x01
|
|
line.word 0x00 "OR,TIM11 Option Register 1"
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*"))
|
|
bitfld.word 0x00 0.--1. " TI1_RMP ,TIM11 input 1 remapping capability" "TIM11_CH1->GPIO,,HSE->TIM11_CH1,MCO1->TIM11_CH1"
|
|
else
|
|
bitfld.word 0x00 0.--1. " TI1_RMP ,TIM11 input 1 remapping capability" "TIM11_CH1->GPIO,SPDIFRX Frame synchronous,HSE->TIM11_CH1,MCO1->TIM11_CH1"
|
|
endif
|
|
else
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif (!cpuis("STM32F723R*")&&!cpuis("STM32F733R*")&&!cpuis("STM32F723V*")&&!cpuis("STM32F733V*")&&!cpuis("STM32F723Z*")&&!cpuis("STM32F733Z*"))
|
|
tree "TIM 12"
|
|
base ad:0x40001800
|
|
width 13.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TIM12_CR1,Control Register 1"
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32F730*8")||cpuis("STM32F750*8"))
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "No remapping,Remapping"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/UG set,Overflow"
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
if ((per.l(ad:0x40001800+0x08)&0x07)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TIM12_SMCR,Slave Mode Control Register"
|
|
bitfld.long 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
sif !cpuis("STM32F730*8")
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
newline
|
|
bitfld.long 0x00 4.--6. " TS ,Trigger selection" "TIM4,TIM5,TIM13_OC,TIM14_OC,?..."
|
|
else
|
|
newline
|
|
bitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,?..."
|
|
endif
|
|
else
|
|
newline
|
|
bitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 0.--2. 16. " SMS ,Slave mode selection" "Disabled,,,,Reset,Gated,Trigger,External Clk,Reset + trigger,?..."
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TIM12_SMCR,Slave Mode Control Register"
|
|
bitfld.long 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
newline
|
|
rbitfld.long 0x00 4.--6. " TS ,Trigger selection" "TIM4,TIM5,TIM13_OC,TIM14_OC,?..."
|
|
else
|
|
newline
|
|
rbitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 0.--2. 16. " SMS ,Slave mode selection" "Disabled,,,,Reset,Gated,Trigger,External Clk,Reset + trigger,?..."
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TIM12_DIER,DMA/Interrupt Enable Register"
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "TIM12_SR,Status Register"
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 overcapture flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 overcapture flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt flag" "No trigger,Trigger"
|
|
newline
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "Not captured/Not matched,Captured/Matched"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "Not captured/Not matched,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt flag" "No update,Update"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "TIM12_EGR,Event Generation Register"
|
|
bitfld.word 0x00 6. " TG ,Trigger generation" "No action,Trigger"
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 generation input/output" "No action/No action,Capture 2/compare 2"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 generation input/output" "No action/No action,Capture 1/compare 1"
|
|
newline
|
|
bitfld.word 0x00 0. " UG ,Update generation" "No action,Update"
|
|
newline
|
|
if (((per.l((ad:0x40001800+0x18)))&0x303)==0x000)
|
|
if ((per.l(ad:0x40001800+0x20)&0x01)==0x00)&&((per.l(ad:0x40001800+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM12_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,?..."
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,?..."
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40001800+0x20)&0x01)==0x01)&&((per.l(ad:0x40001800+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM12_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,?..."
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,?..."
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40001800+0x20)&0x01)==0x00)&&((per.l(ad:0x40001800+0x20)&0x100)==0x100)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM12_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,?..."
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,?..."
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM12_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,?..."
|
|
bitfld.long 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal,Fast"
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,?..."
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.l((ad:0x40001800+0x18)))&0x300)!=0x00)&&(((per.l((ad:0x40001800+0x18)))&0x03)!=0x00)
|
|
if ((per.l(ad:0x40001800+0x20)&0x01)==0x00)&&((per.l(ad:0x40001800+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM12_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40001800+0x20)&0x01)==0x01)&&((per.l(ad:0x40001800+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM12_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40001800+0x20)&0x01)==0x00)&&((per.l(ad:0x40001800+0x20)&0x100)==0x100)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM12_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM12_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input Capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.l((ad:0x40001800+0x18)))&0x300)==0x00)&&(((per.l((ad:0x40001800+0x18)))&0x03)!=0x00)
|
|
if ((per.l(ad:0x40001800+0x20)&0x01)==0x00)&&((per.l(ad:0x40001800+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM12_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40001800+0x20)&0x01)==0x01)&&((per.l(ad:0x40001800+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM12_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40001800+0x20)&0x01)==0x00)&&((per.l(ad:0x40001800+0x20)&0x100)==0x100)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM12_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output Compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal,Fast"
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM12_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal,Fast"
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40001800+0x20)&0x01)==0x00)&&((per.l(ad:0x40001800+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM12_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40001800+0x20)&0x01)==0x01)&&((per.l(ad:0x40001800+0x20)&0x100)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM12_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif ((per.l(ad:0x40001800+0x20)&0x01)==0x00)&&((per.l(ad:0x40001800+0x20)&0x100)==0x100)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM12_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM12_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
newline
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
bitfld.long 0x00 3. " OC1PE ,Output Compare 1 preload enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
newline
|
|
if (((per.w((ad:0x40001800+0x18)))&0x303)==0x000)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM12_CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
newline
|
|
bitfld.word 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
elif (((per.w((ad:0x40001800+0x18)))&0x300)==0x000)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM12_CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Compare 2 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 4. " CC2E ,Compare 2 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
newline
|
|
bitfld.word 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
elif (((per.w((ad:0x40001800+0x18)))&0x3)==0x0)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM12_CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
newline
|
|
bitfld.word 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM12_CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 5. 7. " CC2NP_CC2P ,Capture 2 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture 2 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Any edge"
|
|
newline
|
|
bitfld.word 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32F730*8")||cpuis("STM32F750*8"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM12_CNT,Counter"
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
rbitfld.long 0x00 31. " UIFCPY ,Update interrupt flag copy" "Not updated,Updated"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 31. " UIFCPY ,Update interrupt flag copy" "Not updated,Updated"
|
|
newline
|
|
endif
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
else
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "TIM12_CNT,Counter"
|
|
endif
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "TIM12_PSC,Prescaler"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "TIM12_ARR,Auto-Reload Register"
|
|
hgroup.word 0x34++0x01
|
|
hide.word 0x00 "TIM12_CCR1,Capture/Compare Register 1"
|
|
in
|
|
hgroup.word 0x38++0x01
|
|
hide.word 0x00 "TIM12_CCR2,Capture/Compare Register 2"
|
|
in
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
group.word 0x68++0x01
|
|
line.word 0x00 "TIM12_TISEL,Timer Input Selection Register"
|
|
bitfld.word 0x00 8.--11. " TI2SEL ,Selects TI2[0] to TI2[15] input" "TIM12_CH2,?..."
|
|
bitfld.word 0x00 0.--3. " TI1SEL ,Selects TI1[0] to TI1[15] input" "TIM12_CH1,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "TIM 13"
|
|
base ad:0x40001C00
|
|
width 7.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,Control Register 1"
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32F730*")||cpuis("STM32F750*8"))
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "No remapping,Remapping"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
newline
|
|
bitfld.word 0x00 3. " OPM ,One-pulse mode" "Not stopped,Stopped"
|
|
newline
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/UG set,Overflow"
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
newline
|
|
else
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "DIER,DMA/Interrupt Enable Register"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "SR,Status Register"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 overcapture flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt flag input/output" "Not captured/Not matched,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt flag" "No update,Update"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "EGR,Event Generation Register"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 generation input/output" "No action/No action,Capture 1/compare 1"
|
|
bitfld.word 0x00 0. " UG ,Update generation" "No action,Update"
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*")&&!cpuis("STM32F72*")&&!cpuis("STM32F73*")&&!cpuis("STM32F76*")&&!cpuis("STM32F77*")&&!cpuis("STM32F75*0")&&!cpuis("STM32F750*"))
|
|
if (((per.w((ad:0x40001C00+0x18)))&0x03)==0x00)&&((per.w(ad:0x40001C00+0x20)&0x01)==0x00)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/ic1 mapped on TI2,Input/ic1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.l((ad:0x40001C00+0x18)))&0x03)==0x00)
|
|
if ((per.l(ad:0x40001C00+0x20)&0x01)==0x00)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40001C00+0x20)&0x01)==0x00)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/ic1 mapped on TI2,Input/ic1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/ic1 mapped on TI2,Input/ic1 mapped on TRC"
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.w((ad:0x40001C00+0x18)))&0x03)==0x00)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Both edges"
|
|
bitfld.word 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis(STM32F7*0*8))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,Counter"
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
rbitfld.long 0x00 31. " UIFCPY ,Update interrupt flag copy" "Not updated,Updated"
|
|
else
|
|
bitfld.long 0x00 31. " UIFCPY ,Update interrupt flag copy" "Not updated,Updated"
|
|
endif
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
else
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "CNT,Counter"
|
|
endif
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "PSC,Prescaler"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "ARR,Auto-Reload Register"
|
|
if (((per.l(ad:0x40001C00+0x18)&0x03)==0x00))
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "CCR1,Capture/Compare Register 1"
|
|
else
|
|
hgroup.word 0x34++0x01
|
|
hide.word 0x00 "CCR1,Capture/Compare Register 1"
|
|
in
|
|
endif
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
group.word 0x50++0x01
|
|
line.word 0x00 "OR,TIM13 Option Register 1"
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*"))
|
|
bitfld.word 0x00 0.--1. " TI1_RMP ,TIM13 input 1 remapping capability" "TIM11_CH1->GPIO,,HSE->TIM11_CH1,MCO1->TIM11_CH1"
|
|
else
|
|
bitfld.word 0x00 0.--1. " TI1_RMP ,TIM13 input 1 remapping capability" "TIM11_CH1->GPIO,SPDIFRX Frame synchronous,HSE->TIM11_CH1,MCO1->TIM11_CH1"
|
|
endif
|
|
else
|
|
group.word 0x68++0x01
|
|
line.word 0x00 "OR,TIM13 Timer Input Selection Register"
|
|
bitfld.word 0x00 0.--3. " TI1SEL ,Selects TI1[0] to TI1[15] input" "TIM13_CH1,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "TIM 14"
|
|
base ad:0x40002000
|
|
width 7.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,Control Register 1"
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32F730*")||cpuis("STM32F750*8"))
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "No remapping,Remapping"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
newline
|
|
bitfld.word 0x00 3. " OPM ,One-pulse mode" "Not stopped,Stopped"
|
|
newline
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/UG set,Overflow"
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
newline
|
|
else
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "DIER,DMA/Interrupt Enable Register"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "SR,Status Register"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 overcapture flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt flag input/output" "Not captured/Not matched,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt flag" "No update,Update"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "EGR,Event Generation Register"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 generation input/output" "No action/No action,Capture 1/compare 1"
|
|
bitfld.word 0x00 0. " UG ,Update generation" "No action,Update"
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*")&&!cpuis("STM32F72*")&&!cpuis("STM32F73*")&&!cpuis("STM32F76*")&&!cpuis("STM32F77*")&&!cpuis("STM32F75*0")&&!cpuis("STM32F750*"))
|
|
if (((per.w((ad:0x40002000+0x18)))&0x03)==0x00)&&((per.w(ad:0x40002000+0x20)&0x01)==0x00)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/ic1 mapped on TI2,Input/ic1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.l((ad:0x40002000+0x18)))&0x03)==0x00)
|
|
if ((per.l(ad:0x40002000+0x20)&0x01)==0x00)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal,Fast"
|
|
newline
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40002000+0x20)&0x01)==0x00)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/ic1 mapped on TI2,Input/ic1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT | N=2,fCK_INT | N=4,fCK_INT | N=8,fDTS/2 | N=6,fDTS/2 | N=8,fDTS/4 | N=6,fDTS/4 | N=8,fDTS/8 | N=6,fDTS/8 | N=8,fDTS/16 | N=5,fDTS/16 | N=6,fDTS/16 | N=8,fDTS/32 | N=5,fDTS/32 | N=6,fDTS/32 | N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
newline
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/ic1 mapped on TI2,Input/ic1 mapped on TRC"
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.w((ad:0x40002000+0x18)))&0x03)==0x00)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Compare 1 output polarity" "Active high,Active low,?..."
|
|
bitfld.word 0x00 0. " CC1E ,Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture 1 output polarity" "Rising edge,Falling edge,,Both edges"
|
|
bitfld.word 0x00 0. " CC1E ,Capture 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis(STM32F7*0*8))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,Counter"
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
rbitfld.long 0x00 31. " UIFCPY ,Update interrupt flag copy" "Not updated,Updated"
|
|
else
|
|
bitfld.long 0x00 31. " UIFCPY ,Update interrupt flag copy" "Not updated,Updated"
|
|
endif
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
else
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "CNT,Counter"
|
|
endif
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "PSC,Prescaler"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "ARR,Auto-Reload Register"
|
|
if (((per.l(ad:0x40002000+0x18)&0x03)==0x00))
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "CCR1,Capture/Compare Register 1"
|
|
else
|
|
hgroup.word 0x34++0x01
|
|
hide.word 0x00 "CCR1,Capture/Compare Register 1"
|
|
in
|
|
endif
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
group.word 0x50++0x01
|
|
line.word 0x00 "OR,TIM14 Option Register 1"
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*"))
|
|
bitfld.word 0x00 0.--1. " TI1_RMP ,TIM14 input 1 remapping capability" "TIM11_CH1->GPIO,,HSE->TIM11_CH1,MCO1->TIM11_CH1"
|
|
else
|
|
bitfld.word 0x00 0.--1. " TI1_RMP ,TIM14 input 1 remapping capability" "TIM11_CH1->GPIO,SPDIFRX Frame synchronous,HSE->TIM11_CH1,MCO1->TIM11_CH1"
|
|
endif
|
|
else
|
|
group.word 0x68++0x01
|
|
line.word 0x00 "OR,TIM14 Timer Input Selection Register"
|
|
bitfld.word 0x00 0.--3. " TI1SEL ,Selects TI1[0] to TI1[15] input" "TIM14_CH1,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "BT (Basic Timers)"
|
|
tree "TIM 6"
|
|
base ad:0x40001000
|
|
width 6.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,Control Register 1"
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Not remapped,Remapped"
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "CR2,Control Register 2"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,?..."
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "DIER,DMA/Interrupt Enable Register"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "SR,Status Register"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt flag" "Not occurred,Occurred"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "EGR,Event Generation Register"
|
|
bitfld.word 0x00 0. " UG ,Update generation" "No effect,Generated"
|
|
if ((per.w(ad:0x40001000)&0x800)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,Counter"
|
|
rbitfld.long 0x00 31. " UIFCPY ,Update interrupt flag copy" "Not updated,Updated"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
endif
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "PSC,Prescaler"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "ARR,Auto-Reload Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "TIM 7"
|
|
base ad:0x40001400
|
|
width 6.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,Control Register 1"
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Not remapped,Remapped"
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "CR2,Control Register 2"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,?..."
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "DIER,DMA/Interrupt Enable Register"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "SR,Status Register"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt flag" "Not occurred,Occurred"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "EGR,Event Generation Register"
|
|
bitfld.word 0x00 0. " UG ,Update generation" "No effect,Generated"
|
|
if ((per.w(ad:0x40001400)&0x800)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT,Counter"
|
|
rbitfld.long 0x00 31. " UIFCPY ,Update interrupt flag copy" "Not updated,Updated"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
endif
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "PSC,Prescaler"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "ARR,Auto-Reload Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
sif !cpuis("STM32F72?R*")&&!cpuis("STM32F73?R*")
|
|
tree "LPTIM (Low-power Timer)"
|
|
base ad:0x40002400
|
|
width 7.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "ISR,Interrupt And Status Register"
|
|
bitfld.long 0x00 6. " DOWN ,Counter direction change up to down" "Not changed,Changed"
|
|
bitfld.long 0x00 5. " UP ,Counter direction change down to up" "Not changed,Changed"
|
|
bitfld.long 0x00 4. " ARROK ,Autoreload register update OK" "Not updated,Updated"
|
|
bitfld.long 0x00 3. " CMPOK ,Compare register update OK" "Not updated,Updated"
|
|
newline
|
|
bitfld.long 0x00 2. " EXTTRIG ,External trigger edge even" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " ARRM ,Autoreload match" "Not matched,Matched"
|
|
bitfld.long 0x00 0. " CMPM ,Compare match" "Not matched,Matched"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x00 6. " DOWNCF ,Direction change to down clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 5. " UPCF ,Direction change to UP clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 4. " ARROKCF ,Autoreload register update OK clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 3. " CMPOKCF ,Compare register update OK clear flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 2. " EXTTRIGCF ,External trigger valid edge clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 1. " ARRMCF ,Autoreload match clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CMPMCF ,Compare match clear flag" "No effect,Clear"
|
|
if ((per.l(ad:0x40002400+0x10)&0x01)==0x01)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x00 6. " DOWNIE ,Direction change to down interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " UPIE ,Direction change to UP interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ARROKIE ,Autoreload register update OK interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CMPOKIE ,Compare register update OK interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " EXTTRIGIE ,External trigger valid edge interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ARRMIE ,Autoreload match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CMPMIE ,Compare match interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x00 6. " DOWNIE ,Direction change to down interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " UPIE ,Direction change to UP interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ARROKIE ,Autoreload register update OK interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CMPOKIE ,Compare register update OK interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " EXTTRIGIE ,External trigger valid edge interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ARRMIE ,Autoreload match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CMPMIE ,Compare match interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40002400+0x10)&0x01)==0x01)&&(per.l(ad:0x40002400+0x0C)&0x1000000)==0x1000000)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CFGR,Configuration Register"
|
|
bitfld.long 0x00 24. " ENC ,Encoder mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " COUNTMODE ,Counter mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " PRELOAD ,Registers update mode" "After APB,End of LPTIM"
|
|
bitfld.long 0x00 21. " WAVPOL ,Waveform shape polarity" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 20. " WAVE ,Waveform shape" "PWM / One Pulse,Set Once"
|
|
bitfld.long 0x00 19. " TIMOUT ,Timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17.--18. " TRIGEN ,Trigger enable and polarity" "Software,Rising,Falling,Both"
|
|
newline
|
|
sif cpuis("STM32F410*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x00 13.--15. " TRIGSEL ,Trigger selector" "GPIO,RTC_ALARMA,RTC_ALARMB,RTC_TAMP,TIM1,TIM5,?..."
|
|
elif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
bitfld.long 0x00 13.--15. " TRIGSEL ,Trigger selector" "GPIO,RTC_ALARMA,RTC_ALARMB,RTC_TAMP1_OUT,RTC_TAMP2_OUT,RTC_TAMP3_OUT,COMP1_OUT,COMP2_OUT"
|
|
else
|
|
bitfld.long 0x00 13.--15. " TRIGSEL ,Trigger selector" "GPIO,RTC_ALARMA,RTC_ALARMB,RTC_TAMP1_OUT,RTC_TAMP2_OUT,RTC_TAMP3_OUT,?..."
|
|
endif
|
|
newline
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F750*")||cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 9.--11. " PRESC ,Clock prescaler" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
else
|
|
bitfld.long 0x00 9.--11. " PRESC ,Clock prescaler" "/1,/2,/6,/8,/16,/32,/64,/128"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 6.--7. " TRGFLT ,Configurable digital filter for trigger" "Any change,2 clk periods,4 clk periods,8 clk periods"
|
|
bitfld.long 0x00 3.--4. " CKFLT ,Configurable digital filter for external clock" "Any change,2 clk periods,4 clk periods,8 clk periods"
|
|
bitfld.long 0x00 1.--2. " CKPOL ,Clock polarity" "Sub-mode 1,Sub-mode 2,Sub-mode 3,?..."
|
|
bitfld.long 0x00 0. " CKSEL ,Clock selector" "Internal,External"
|
|
elif (((per.l(ad:0x40002400+0x10)&0x01)==0x00)&&(per.l(ad:0x40002400+0x0C)&0x1000000)==0x1000000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CFGR,Configuration Register"
|
|
bitfld.long 0x00 24. " ENC ,Encoder mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " COUNTMODE ,Counter mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " PRELOAD ,Registers update mode" "After APB,End of LPTIM"
|
|
bitfld.long 0x00 21. " WAVPOL ,Waveform shape polarity" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 20. " WAVE ,Waveform shape" "PWM / One Pulse,Set Once"
|
|
bitfld.long 0x00 19. " TIMOUT ,Timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17.--18. " TRIGEN ,Trigger enable and polarity" "Software,Rising,Falling,Both"
|
|
newline
|
|
sif cpuis("STM32F410*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x00 13.--15. " TRIGSEL ,Trigger selector" "GPIO,RTC_ALARMA,RTC_ALARMB,RTC_TAMP,TIM1,TIM5,?..."
|
|
elif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
bitfld.long 0x00 13.--15. " TRIGSEL ,Trigger selector" "GPIO,RTC_ALARMA,RTC_ALARMB,RTC_TAMP1_OUT,RTC_TAMP2_OUT,RTC_TAMP3_OUT,COMP1_OUT,COMP2_OUT"
|
|
else
|
|
bitfld.long 0x00 13.--15. " TRIGSEL ,Trigger selector" "GPIO,RTC_ALARMA,RTC_ALARMB,RTC_TAMP1_OUT,RTC_TAMP2_OUT,RTC_TAMP3_OUT,?..."
|
|
endif
|
|
newline
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 9.--11. " PRESC ,Clock prescaler" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
else
|
|
bitfld.long 0x00 9.--11. " PRESC ,Clock prescaler" "/1,/2,/6,/8,/16,/32,/64,/128"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 6.--7. " TRGFLT ,Configurable digital filter for trigger" "Any change,2 clk periods,4 clk periods,8 clk periods"
|
|
bitfld.long 0x00 3.--4. " CKFLT ,Configurable digital filter for external clock" "Any change,2 clk periods,4 clk periods,8 clk periods"
|
|
bitfld.long 0x00 1.--2. " CKPOL ,Clock polarity" "Sub-mode 1,Sub-mode 2,Sub-mode 3,?..."
|
|
bitfld.long 0x00 0. " CKSEL ,Clock selector" "Internal,External"
|
|
elif (((per.l(ad:0x40002400+0x10)&0x01)==0x01)&&(per.l(ad:0x40002400+0x0C)&0x1000000)==0x00)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CFGR,Configuration Register"
|
|
bitfld.long 0x00 24. " ENC ,Encoder mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " COUNTMODE ,Counter mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " PRELOAD ,Registers update mode" "After APB,End of LPTIM"
|
|
bitfld.long 0x00 21. " WAVPOL ,Waveform shape polarity" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 20. " WAVE ,Waveform shape" "PWM / One Pulse,Set Once"
|
|
bitfld.long 0x00 19. " TIMOUT ,Timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17.--18. " TRIGEN ,Trigger enable and polarity" "Software,Rising,Falling,Both"
|
|
newline
|
|
sif cpuis("STM32F410*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x00 13.--15. " TRIGSEL ,Trigger selector" "GPIO,RTC_ALARMA,RTC_ALARMB,RTC_TAMP,TIM1,TIM5,?..."
|
|
elif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
bitfld.long 0x00 13.--15. " TRIGSEL ,Trigger selector" "GPIO,RTC_ALARMA,RTC_ALARMB,RTC_TAMP1_OUT,RTC_TAMP2_OUT,RTC_TAMP3_OUT,COMP1_OUT,COMP2_OUT"
|
|
else
|
|
bitfld.long 0x00 13.--15. " TRIGSEL ,Trigger selector" "GPIO,RTC_ALARMA,RTC_ALARMB,RTC_TAMP1_OUT,RTC_TAMP2_OUT,RTC_TAMP3_OUT,?..."
|
|
endif
|
|
newline
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 9.--11. " PRESC ,Clock prescaler" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
else
|
|
bitfld.long 0x00 9.--11. " PRESC ,Clock prescaler" "/1,/2,/6,/8,/16,/32,/64,/128"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 6.--7. " TRGFLT ,Configurable digital filter for trigger" "Any change,2 clk periods,4 clk periods,8 clk periods"
|
|
bitfld.long 0x00 3.--4. " CKFLT ,Configurable digital filter for external clock" "Any change,2 clk periods,4 clk periods,8 clk periods"
|
|
bitfld.long 0x00 1.--2. " CKPOL ,Clock polarity" "Rising,Falling,Both,?..."
|
|
bitfld.long 0x00 0. " CKSEL ,Clock selector" "Internal,External"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CFGR,Configuration Register"
|
|
bitfld.long 0x00 24. " ENC ,Encoder mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " COUNTMODE ,Counter mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " PRELOAD ,Registers update mode" "After APB,End of LPTIM"
|
|
bitfld.long 0x00 21. " WAVPOL ,Waveform shape polarity" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 20. " WAVE ,Waveform shape" "PWM / One Pulse,Set Once"
|
|
bitfld.long 0x00 19. " TIMOUT ,Timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17.--18. " TRIGEN ,Trigger enable and polarity" "Software,Rising,Falling,Both"
|
|
newline
|
|
sif cpuis("STM32F410*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x00 13.--15. " TRIGSEL ,Trigger selector" "GPIO,RTC_ALARMA,RTC_ALARMB,RTC_TAMP,TIM1,TIM5,?..."
|
|
elif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
bitfld.long 0x00 13.--15. " TRIGSEL ,Trigger selector" "GPIO,RTC_ALARMA,RTC_ALARMB,RTC_TAMP1_OUT,RTC_TAMP2_OUT,RTC_TAMP3_OUT,COMP1_OUT,COMP2_OUT"
|
|
else
|
|
bitfld.long 0x00 13.--15. " TRIGSEL ,Trigger selector" "GPIO,RTC_ALARMA,RTC_ALARMB,RTC_TAMP1_OUT,RTC_TAMP2_OUT,RTC_TAMP3_OUT,?..."
|
|
endif
|
|
newline
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 9.--11. " PRESC ,Clock prescaler" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
else
|
|
bitfld.long 0x00 9.--11. " PRESC ,Clock prescaler" "/1,/2,/6,/8,/16,/32,/64,/128"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 6.--7. " TRGFLT ,Configurable digital filter for trigger" "Any change,2 clk periods,4 clk periods,8 clk periods"
|
|
bitfld.long 0x00 3.--4. " CKFLT ,Configurable digital filter for external clock" "Any change,2 clk periods,4 clk periods,8 clk periods"
|
|
bitfld.long 0x00 1.--2. " CKPOL ,Clock polarity" "Rising,Falling,Both,?..."
|
|
bitfld.long 0x00 0. " CKSEL ,Clock selector" "Internal,External"
|
|
endif
|
|
if ((per.l(ad:0x40002400+0x10)&0x01)==0x01)
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 2. " CNTSTRT ,Timer start in continuous mode" "Not started,Started"
|
|
bitfld.long 0x00 1. " SNGSTRT ,LPTIM start in single mode" "Not started,Started"
|
|
bitfld.long 0x00 0. " ENABLE ,LPTIM enable" "Disabled,Enabled"
|
|
line.long 0x04 "CMP,Compare Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CMP ,Compare value"
|
|
line.long 0x08 "ARR,Autoreload Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " ARR ,Auto reload value"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
rbitfld.long 0x00 2. " CNTSTRT ,Timer start in continuous mode" "Not started,Started"
|
|
rbitfld.long 0x00 1. " SNGSTRT ,LPTIM start in single mode" "Not started,Started"
|
|
bitfld.long 0x00 0. " ENABLE ,LPTIM enable" "Disabled,Enabled"
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "CMP,Compare Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMP ,Compare value"
|
|
line.long 0x04 "ARR,Autoreload Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " ARR ,Auto reload value"
|
|
endif
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "CNT,Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
sif cpuis("STM32F410*")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "OR,Option Register"
|
|
bitfld.long 0x00 0.--1. " OR ,Low-power timer input 1 remap" "PB5/PC0,PA4,PB9,TIM6/DAC"
|
|
elif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
newline
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CFGR2,Configuration Register 2"
|
|
bitfld.long 0x00 4.--5. " IN2SEL ,LPTIM1 input 2 selection" "GPIO,COMP2_OUT,?..."
|
|
bitfld.long 0x00 0.--1. " IN1SEL ,LPTIM1 input 1 selection" "GPIO,COMP1_OUT,?..."
|
|
elif cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
newline
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "OR,Option Register"
|
|
bitfld.long 0x00 4. " TIM9_ITR1_RMP ,TIMER9 input trigger 1 remap" "TIM3 output trigger,LPTIMERS out channel"
|
|
bitfld.long 0x00 3. " TIM5_ITR1_RMP ,TIMER5 intput trigger 1 remap" "TIM3 output trigger,LPTIMERS out channel"
|
|
newline
|
|
bitfld.long 0x00 2. " TIM1_ITR2_RMP ,TIMER1 input trigger 2 remap" "TIM3 output trigger,LPTIMERS out channel"
|
|
bitfld.long 0x00 0.--1. " LPT_IN1_RMP ,LPTimer input trigger 2 remap" "PB5/PC0,PA4 direct,PB9 direct,LPTIMER out channel"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "IWDG (Independent Watchdog)"
|
|
base ad:0x40003000
|
|
width 6.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "KR,Key Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " KEY ,Key value"
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32F750N8")||cpuis("STM32F750V8")||cpuis("STM32F750Z8"))
|
|
if ((per.l(ad:0x40003000+0x0C)&0x03)==0x00)
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "PR,Prescaler Register"
|
|
bitfld.long 0x00 0.--2. " PR ,Prescaler divider" "/4,/8,/16,/32,/64,/128,/256,/256"
|
|
line.long 0x04 "RLR,Reload Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " RL ,Watchdog counter reload value"
|
|
elif ((per.l(ad:0x40003000+0x0C)&0x03)==0x01)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PR,Prescaler Register"
|
|
bitfld.long 0x00 0.--2. " PR ,Prescaler divider" "/4,/8,/16,/32,/64,/128,/256,/256"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "RLR,Reload Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " RL ,Watchdog counter reload value"
|
|
elif ((per.l(ad:0x40003000+0x0C)&0x03)==0x02)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PR,Prescaler Register"
|
|
bitfld.long 0x00 0.--2. " PR ,Prescaler divider" "/4,/8,/16,/32,/64,/128,/256,/256"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLR,Reload Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " RL ,Watchdog counter reload value"
|
|
else
|
|
rgroup.long 0x04++0x07
|
|
line.long 0x00 "PR,Prescaler Register"
|
|
bitfld.long 0x00 0.--2. " PR ,Prescaler divider" "/4,/8,/16,/32,/64,/128,/256,/256"
|
|
line.long 0x04 "RLR,Reload Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " RL ,Watchdog counter reload value"
|
|
endif
|
|
else
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "PR,Prescaler Register"
|
|
bitfld.long 0x00 0.--2. " PR ,Prescaler divider" "/4,/8,/16,/32,/64,/128,/256,/256"
|
|
line.long 0x04 "RLR,Reload Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " RL ,Watchdog counter reload value"
|
|
endif
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
sif (cpuis("STM32F050C4")||cpuis("STM32F050C6")||cpuis("STM32F050K4")||cpuis("STM32F050K6")||cpuis("STM32F051C4")||cpuis("STM32F051C6")||cpuis("STM32F051C8")||cpuis("STM32F051K4")||cpuis("STM32F051K6")||cpuis("STM32F051K8")||cpuis("STM32F051R4")||cpuis("STM32F051R6")||cpuis("STM32F051R8")||cpuis("STM32F302CB")||cpuis("STM32F302VB")||cpuis("STM32F302CC")||cpuis("STM32F302VC")||cpuis("STM32F302RB")||cpuis("STM32F302RC")||cpuis("STM32F303RB")||cpuis("STM32F303RC")||cpuis("STM32F303CB")||cpuis("STM32F303VB")||cpuis("STM32F303CC")||cpuis("STM32F303VC")||cpuis("STM32F313CC")||cpuis("STM32F313RC")||cpuis("STM32F313VC")||cpuis("STM32F372CB")||cpuis("STM32F372RC")||cpuis("STM32F372CC")||cpuis("STM32F372V8")||cpuis("STM32F372R8")||cpuis("STM32F372VB")||cpuis("STM32F372C8")||cpuis("STM32F372RB")||cpuis("STM32F372VC")||cpuis("STM32F373C8")||cpuis("STM32F373RB")||cpuis("STM32F373VC")||cpuis("STM32F373CB")||cpuis("STM32F373RC")||cpuis("STM32F373CC")||cpuis("STM32F373V8")||cpuis("STM32F373R8")||cpuis("STM32F373VB")||cpuis("STM32F383CC")||cpuis("STM32F383RC")||cpuis("STM32F383VC")||(cpuis("STM32F7*"))||cpuis("STM32F038?6")||cpuis("STM32F048?6")||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")||cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB"))||(cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32F730I8")||cpuis("STM32F730R8")||cpuis("STM32F730V8")||cpuis("STM32F730Z8")||cpuis("STM32F750N8")||cpuis("STM32F750V8")||cpuis("STM32F750Z8"))
|
|
bitfld.long 0x00 2. " WVU ,Watchdog counter window value update" "Completed,Running"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " RVU ,Watchdog counter reload value update" "Completed,Running"
|
|
bitfld.long 0x00 0. " PVU ,Watchdog prescaler value update" "Completed,Running"
|
|
sif cpuis("STM32F050C4")||cpuis("STM32F050C6")||cpuis("STM32F050K4")||cpuis("STM32F050K6")||cpuis("STM32F051C4")||cpuis("STM32F051C6")||cpuis("STM32F051C8")||cpuis("STM32F051K4")||cpuis("STM32F051K6")||cpuis("STM32F051K8")||cpuis("STM32F051R4")||cpuis("STM32F051R6")||cpuis("STM32F051R8")||cpuis("STM32F302CB")||cpuis("STM32F302VB")||cpuis("STM32F302CC")||cpuis("STM32F302VC")||cpuis("STM32F302RB")||cpuis("STM32F302RC")||cpuis("STM32F303RB")||cpuis("STM32F303RC")||cpuis("STM32F303CB")||cpuis("STM32F303VB")||cpuis("STM32F303CC")||cpuis("STM32F303VC")||cpuis("STM32F313CC")||cpuis("STM32F313RC")||cpuis("STM32F313VC")||cpuis("STM32F372CB")||cpuis("STM32F372RC")||cpuis("STM32F372CC")||cpuis("STM32F372V8")||cpuis("STM32F372R8")||cpuis("STM32F372VB")||cpuis("STM32F372C8")||cpuis("STM32F372RB")||cpuis("STM32F372VC")||cpuis("STM32F373C8")||cpuis("STM32F373RB")||cpuis("STM32F373VC")||cpuis("STM32F373CB")||cpuis("STM32F373RC")||cpuis("STM32F373CC")||cpuis("STM32F373V8")||cpuis("STM32F373R8")||cpuis("STM32F373VB")||cpuis("STM32F383CC")||cpuis("STM32F383RC")||cpuis("STM32F383VC")||(cpuis("STM32F7*"))||cpuis("STM32F038?6")||cpuis("STM32F048?6")||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")||cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")||cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32F730I8")||cpuis("STM32F730R8")||cpuis("STM32F730V8")||cpuis("STM32F730Z8")
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F750*")||cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
if (((per.l(ad:0x40003000)+0x0C)&0x04)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "WINR,Window Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " WIN ,Watchdog counter window value"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "WINR,Window Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " WIN ,Watchdog counter window value"
|
|
endif
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "WINR,Window Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " WIN ,Watchdog counter window value"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "WWDG (Window Watchdog)"
|
|
base ad:0x40002C00
|
|
width 5.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 7. " WDGA ,Activation bit" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " T ,7-bit counter"
|
|
line.long 0x04 "CFR,Configuration Register"
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
bitfld.long 0x04 11.--13. " WDGTB ,Timer base" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 9. " EWI ,Early wakeup interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
sif !cpuis("STM32H743*")&&!cpuis("STM32H753*")
|
|
sif cpuis("STM32F730I8")||cpuis("STM32F730R8")||cpuis("STM32F730V8")||cpuis("STM32F730Z8")||cpuis("STM32F750N8")||cpuis("STM32F750V8")||cpuis("STM32F750Z8")
|
|
bitfld.long 0x04 7.--8. " WDGTB ,Timer base" "/1,/2,/4,/8"
|
|
newline
|
|
endif
|
|
endif
|
|
hexmask.long.byte 0x04 0.--6. 1. " W ,7-bit window value"
|
|
line.long 0x08 "SR,Status Register"
|
|
bitfld.long 0x08 0. " EWIF ,Early wakeup interrupt flag" "No interrupt,Interrupt"
|
|
width 0x0B
|
|
tree.end
|
|
tree "RTC (Real-Time Clock)"
|
|
base ad:0x40002800
|
|
width 10.
|
|
if (((per.l(ad:0x40002800+0x08)&0x40)==0x00)&&((per.l(ad:0x40002800)&0x300000)!=0x200000))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TR,RTC Time Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.l(ad:0x40002800+0x08)&0x40)==0x00)&&((per.l(ad:0x40002800)&0x300000)==0x200000))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TR,RTC Time Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.l(ad:0x40002800)&0x300000)==0x100000)&&((per.l(ad:0x40002800)&0x300000)==0x100000))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TR,RTC Time Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TR,RTC Time Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM"
|
|
endif
|
|
if ((per.l(ad:0x40002800+0x04)&0x1F00)==(0x0100||0x0300||0x0500||0x0700||0x0800||0x1000||0x1200))
|
|
if (((per.l(ad:0x40002800+0x04)&0x30)==0x30))
|
|
if ((per.l(ad:0x40002800+0x04)&0x1000)==0x1000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DR,RTC Date Register"
|
|
bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12. "/,Month tens in BCD format" "0,1"
|
|
bitfld.long 0x00 8.--11. ",Month units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 20.--23. "/,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DR,RTC Date Register"
|
|
bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12. "/,Month tens in BCD format" "0,1"
|
|
bitfld.long 0x00 8.--11. ",Month units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 20.--23. "/,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40002800+0x04)&0x1000)==0x1000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DR,RTC Date Register"
|
|
bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12. "/,Month tens in BCD format" "0,1"
|
|
bitfld.long 0x00 8.--11. ",Month units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 20.--23. "/,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DR,RTC Date Register"
|
|
bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12. "/,Month tens in BCD format" "0,1"
|
|
bitfld.long 0x00 8.--11. ",Month units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 20.--23. "/,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
endif
|
|
endif
|
|
elif ((per.l(ad:0x40002800+0x04)&0x1F00)==(0x400||0x600||0x900||0x1100))
|
|
if (((per.l(ad:0x40002800+0x04)&0x30)==0x30))
|
|
if ((per.l(ad:0x40002800+0x04)&0x1000)==0x1000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DR,RTC Date Register"
|
|
bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12. "/,Month tens in BCD format" "0,1"
|
|
bitfld.long 0x00 8.--11. ",Month units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 20.--23. "/,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DR,RTC Date Register"
|
|
bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12. "/,Month tens in BCD format" "0,1"
|
|
bitfld.long 0x00 8.--11. ",Month units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 20.--23. "/,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40002800+0x04)&0x1000)==0x1000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DR,RTC Date Register"
|
|
bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12. "/,Month tens in BCD format" "0,1"
|
|
bitfld.long 0x00 8.--11. ",Month units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 20.--23. "/,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DR,RTC Date Register"
|
|
bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12. "/,Month tens in BCD format" "0,1"
|
|
bitfld.long 0x00 8.--11. ",Month units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 20.--23. "/,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
endif
|
|
endif
|
|
elif ((per.l(ad:0x40002800+0x04)&0x1F00)==0x200)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DR,RTC Date Register"
|
|
bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12. "/,Month tens in BCD format" "0,1"
|
|
bitfld.long 0x00 8.--11. ",Month units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 20.--23. "/,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
if (((per.l(ad:0x40002800+0x04)&0x30)==0x30))
|
|
if ((per.l(ad:0x40002800+0x04)&0x1000)==0x1000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DR,RTC Date Register"
|
|
bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12. "/,Month tens in BCD format" "0,1"
|
|
bitfld.long 0x00 8.--11. ",Month units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 20.--23. "/,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DR,RTC Date Register"
|
|
bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12. "/,Month tens in BCD format" "0,1"
|
|
bitfld.long 0x00 8.--11. ",Month units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 20.--23. "/,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40002800+0x04)&0x1000)==0x1000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DR,RTC Date Register"
|
|
bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12. "/,Month tens in BCD format" "0,1"
|
|
bitfld.long 0x00 8.--11. ",Month units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 20.--23. "/,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DR,RTC Date Register"
|
|
bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12. "/,Month tens in BCD format" "0,1"
|
|
bitfld.long 0x00 8.--11. ",Month units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 20.--23. "/,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40002800+0x0C))&0x40)==0x40&&((per.l(ad:0x40002800+0x08))&0x400)==0x00&&((per.l(ad:0x40002800+0x0C))&0x400)==0x400)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR,RTC Control Register"
|
|
bitfld.long 0x00 24. " ITSE ,Timestamp on internal event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " COE ,Calibration output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " OSEL ,Output selection" "Disabled,AlarmA,AlarmB,Wakeup"
|
|
bitfld.long 0x00 20. " POL ,Output polarity" "High,Low"
|
|
newline
|
|
bitfld.long 0x00 19. " COSEL ,Calibration output selection" "512Hz,1Hz"
|
|
bitfld.long 0x00 18. " BKP ,Backup. DSTC(Daylight Saving Time Change)" "DSTC not performed,DSTC performed"
|
|
bitfld.long 0x00 17. " SUB1H ,Subtract 1 hour (winter time change)" "No effect,Subtracted"
|
|
bitfld.long 0x00 16. " ADD1H ,Add 1 hour (summer time change)" "No effect,Added"
|
|
newline
|
|
bitfld.long 0x00 15. " TSIE ,Time-stamp interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " WUTIE ,Wakeup timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ALRBIE ,Alarm B interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ALRAIE ,Alarm A interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " TSE ,Timestamp enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " WUTE ,Wakeup timer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ALRBE ,Alarm B enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ALRAE ,Alarm A enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " FMT ,Hour format" "24 hour,AM/PM"
|
|
bitfld.long 0x00 5. " BYPSHAD ,Bypass the shadow registers" "Calendar from shadow,Calendar directly"
|
|
bitfld.long 0x00 4. " REFCKON ,REFIN reference clock detection enable (50 or 60 Hz)" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TSEDGE ,Time-stamp event active edge" "Rising,Falling"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " WUCKSEL ,Wakeup clock selection" "RTC/16,RTC/8,RTC/4,RTC/2,ck_spre,ck_spre,ck_spre+2^16,ck_spre+2^16"
|
|
elif ((((per.l(ad:0x40002800+0x0C))&0x40)==0x00)&&(((per.l(ad:0x40002800+0x08))&0x400)==0x00)&&(((per.l(ad:0x40002800+0x0C))&0x400)==0x400))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR,RTC Control Register"
|
|
bitfld.long 0x00 24. " ITSE ,Timestamp on internal event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " COE ,Calibration output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " OSEL ,Output selection" "Disabled,AlarmA,AlarmB,Wakeup"
|
|
bitfld.long 0x00 20. " POL ,Output polarity" "High,Low"
|
|
newline
|
|
bitfld.long 0x00 19. " COSEL ,Calibration output selection" "512Hz,1Hz"
|
|
bitfld.long 0x00 18. " BKP ,Backup. DSTC(Daylight Saving Time Change)" "DSTC not performed,DSTC performed"
|
|
bitfld.long 0x00 17. " SUB1H ,Subtract 1 hour (winter time change)" "No effect,Subtracted"
|
|
bitfld.long 0x00 16. " ADD1H ,Add 1 hour (summer time change)" "No effect,Added"
|
|
newline
|
|
bitfld.long 0x00 15. " TSIE ,Time-stamp interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " WUTIE ,Wakeup timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ALRBIE ,Alarm B interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ALRAIE ,Alarm A interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " TSE ,Timestamp enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " WUTE ,Wakeup timer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ALRBE ,Alarm B enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ALRAE ,Alarm A enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 6. " FMT ,Hour format" "24 hour,AM/PM"
|
|
bitfld.long 0x00 5. " BYPSHAD ,Bypass the shadow registers" "Calendar from shadow,Calendar directly"
|
|
rbitfld.long 0x00 4. " REFCKON ,REFIN reference clock detection enable (50 or 60 Hz)" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TSEDGE ,Time-stamp event active edge" "Rising,Falling"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " WUCKSEL ,Wakeup clock selection" "RTC/16,RTC/8,RTC/4,RTC/2,ck_spre,ck_spre,ck_spre+2^16,ck_spre+2^16"
|
|
elif ((((per.l(ad:0x40002800+0x0C))&0x40)==0x40)&&(((per.l(ad:0x40002800+0x08))&0x400)==0x400)&&(((per.l(ad:0x40002800+0x0C))&0x400)==0x00))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR,RTC Control Register"
|
|
bitfld.long 0x00 24. " ITSE ,Timestamp on internal event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " COE ,Calibration output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " OSEL ,Output selection" "Disabled,AlarmA,AlarmB,Wakeup"
|
|
bitfld.long 0x00 20. " POL ,Output polarity" "High,Low"
|
|
newline
|
|
bitfld.long 0x00 19. " COSEL ,Calibration output selection" "512Hz,1Hz"
|
|
bitfld.long 0x00 18. " BKP ,Backup. DSTC(Daylight Saving Time Change)" "DSTC not performed,DSTC performed"
|
|
bitfld.long 0x00 17. " SUB1H ,Subtract 1 hour (winter time change)" "No effect,Subtracted"
|
|
bitfld.long 0x00 16. " ADD1H ,Add 1 hour (summer time change)" "No effect,Added"
|
|
newline
|
|
bitfld.long 0x00 15. " TSIE ,Time-stamp interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " WUTIE ,Wakeup timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ALRBIE ,Alarm B interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ALRAIE ,Alarm A interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " TSE ,Timestamp enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " WUTE ,Wakeup timer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ALRBE ,Alarm B enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ALRAE ,Alarm A enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " FMT ,Hour format" "24 hour,AM/PM"
|
|
bitfld.long 0x00 5. " BYPSHAD ,Bypass the shadow registers" "Calendar from shadow,Calendar directly"
|
|
bitfld.long 0x00 4. " REFCKON ,REFIN reference clock detection enable (50 or 60 Hz)" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TSEDGE ,Time-stamp event active edge" "Rising,Falling"
|
|
newline
|
|
rbitfld.long 0x00 0.--2. " WUCKSEL ,Wakeup clock selection" "RTC/16,RTC/8,RTC/4,RTC/2,ck_spre,ck_spre,ck_spre+2^16,ck_spre+2^16"
|
|
elif ((((per.l(ad:0x40002800+0x0C))&0x40)==0x00)&&(((per.l(ad:0x40002800+0x08))&0x400)==0x400)&&(((per.l(ad:0x40002800+0x0C))&0x400)==0x00))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR,RTC Control Register"
|
|
bitfld.long 0x00 24. " ITSE ,Timestamp on internal event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " COE ,Calibration output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " OSEL ,Output selection" "Disabled,AlarmA,AlarmB,Wakeup"
|
|
bitfld.long 0x00 20. " POL ,Output polarity" "High,Low"
|
|
newline
|
|
bitfld.long 0x00 19. " COSEL ,Calibration output selection" "512Hz,1Hz"
|
|
bitfld.long 0x00 18. " BKP ,Backup. DSTC(Daylight Saving Time Change)" "DSTC not performed,DSTC performed"
|
|
bitfld.long 0x00 17. " SUB1H ,Subtract 1 hour (winter time change)" "No effect,Subtracted"
|
|
bitfld.long 0x00 16. " ADD1H ,Add 1 hour (summer time change)" "No effect,Added"
|
|
newline
|
|
bitfld.long 0x00 15. " TSIE ,Time-stamp interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " WUTIE ,Wakeup timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ALRBIE ,Alarm B interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ALRAIE ,Alarm A interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " TSE ,Timestamp enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " WUTE ,Wakeup timer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ALRBE ,Alarm B enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ALRAE ,Alarm A enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 6. " FMT ,Hour format" "24 hour,AM/PM"
|
|
bitfld.long 0x00 5. " BYPSHAD ,Bypass the shadow registers" "Calendar from shadow,Calendar directly"
|
|
rbitfld.long 0x00 4. " REFCKON ,REFIN reference clock detection enable (50 or 60 Hz)" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TSEDGE ,Time-stamp event active edge" "Rising,Falling"
|
|
newline
|
|
rbitfld.long 0x00 0.--2. " WUCKSEL ,Wakeup clock selection" "RTC/16,RTC/8,RTC/4,RTC/2,ck_spre,ck_spre,ck_spre+2^16,ck_spre+2^16"
|
|
elif ((((per.l(ad:0x40002800+0x0C))&0x40)==0x00)&&(((per.l(ad:0x40002800+0x08))&0x400)==0x00)&&(((per.l(ad:0x40002800+0x0C))&0x400)==0x00))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR,RTC Control Register"
|
|
bitfld.long 0x00 24. " ITSE ,Timestamp on internal event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " COE ,Calibration output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " OSEL ,Output selection" "Disabled,AlarmA,AlarmB,Wakeup"
|
|
bitfld.long 0x00 20. " POL ,Output polarity" "High,Low"
|
|
newline
|
|
bitfld.long 0x00 19. " COSEL ,Calibration output selection" "512Hz,1Hz"
|
|
bitfld.long 0x00 18. " BKP ,Backup. DSTC(Daylight Saving Time Change)" "DSTC not performed,DSTC performed"
|
|
bitfld.long 0x00 17. " SUB1H ,Subtract 1 hour (winter time change)" "No effect,Subtracted"
|
|
bitfld.long 0x00 16. " ADD1H ,Add 1 hour (summer time change)" "No effect,Added"
|
|
newline
|
|
bitfld.long 0x00 15. " TSIE ,Time-stamp interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " WUTIE ,Wakeup timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ALRBIE ,Alarm B interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ALRAIE ,Alarm A interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " TSE ,Timestamp enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " WUTE ,Wakeup timer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ALRBE ,Alarm B enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ALRAE ,Alarm A enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 6. " FMT ,Hour format" "24 hour,AM/PM"
|
|
bitfld.long 0x00 5. " BYPSHAD ,Bypass the shadow registers" "Calendar from shadow,Calendar directly"
|
|
rbitfld.long 0x00 4. " REFCKON ,REFIN reference clock detection enable (50 or 60 Hz)" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TSEDGE ,Time-stamp event active edge" "Rising,Falling"
|
|
newline
|
|
rbitfld.long 0x00 0.--2. " WUCKSEL ,Wakeup clock selection" "RTC/16,RTC/8,RTC/4,RTC/2,ck_spre,ck_spre,ck_spre+2^16,ck_spre+2^16"
|
|
elif ((((per.l(ad:0x40002800+0x0C))&0x40)==0x00)&&(((per.l(ad:0x40002800+0x08))&0x400)==0x400)&&(((per.l(ad:0x40002800+0x0C))&0x400)==0x400))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR,RTC Control Register"
|
|
bitfld.long 0x00 24. " ITSE ,Timestamp on internal event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " COE ,Calibration output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " OSEL ,Output selection" "Disabled,AlarmA,AlarmB,Wakeup"
|
|
bitfld.long 0x00 20. " POL ,Output polarity" "High,Low"
|
|
newline
|
|
bitfld.long 0x00 19. " COSEL ,Calibration output selection" "512Hz,1Hz"
|
|
bitfld.long 0x00 18. " BKP ,Backup. DSTC(Daylight Saving Time Change)" "DSTC not performed,DSTC performed"
|
|
bitfld.long 0x00 17. " SUB1H ,Subtract 1 hour (winter time change)" "No effect,Subtracted"
|
|
bitfld.long 0x00 16. " ADD1H ,Add 1 hour (summer time change)" "No effect,Added"
|
|
newline
|
|
bitfld.long 0x00 15. " TSIE ,Time-stamp interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " WUTIE ,Wakeup timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ALRBIE ,Alarm B interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ALRAIE ,Alarm A interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " TSE ,Timestamp enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " WUTE ,Wakeup timer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ALRBE ,Alarm B enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ALRAE ,Alarm A enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 6. " FMT ,Hour format" "24 hour,AM/PM"
|
|
bitfld.long 0x00 5. " BYPSHAD ,Bypass the shadow registers" "Calendar from shadow,Calendar directly"
|
|
rbitfld.long 0x00 4. " REFCKON ,REFIN reference clock detection enable (50 or 60 Hz)" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TSEDGE ,Time-stamp event active edge" "Rising,Falling"
|
|
newline
|
|
rbitfld.long 0x00 0.--2. " WUCKSEL ,Wakeup clock selection" "RTC/16,RTC/8,RTC/4,RTC/2,ck_spre,ck_spre,ck_spre+2^16,ck_spre+2^16"
|
|
elif ((((per.l(ad:0x40002800+0x0C))&0x40)==0x40)&&(((per.l(ad:0x40002800+0x08))&0x400)==0x400)&&(((per.l(ad:0x40002800+0x0C))&0x400)==0x400))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR,RTC Control Register"
|
|
bitfld.long 0x00 24. " ITSE ,Timestamp on internal event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " COE ,Calibration output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " OSEL ,Output selection" "Disabled,AlarmA,AlarmB,Wakeup"
|
|
bitfld.long 0x00 20. " POL ,Output polarity" "High,Low"
|
|
newline
|
|
bitfld.long 0x00 19. " COSEL ,Calibration output selection" "512Hz,1Hz"
|
|
bitfld.long 0x00 18. " BKP ,Backup. DSTC(Daylight Saving Time Change)" "DSTC not performed,DSTC performed"
|
|
bitfld.long 0x00 17. " SUB1H ,Subtract 1 hour (winter time change)" "No effect,Subtracted"
|
|
bitfld.long 0x00 16. " ADD1H ,Add 1 hour (summer time change)" "No effect,Added"
|
|
newline
|
|
bitfld.long 0x00 15. " TSIE ,Time-stamp interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " WUTIE ,Wakeup timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ALRBIE ,Alarm B interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ALRAIE ,Alarm A interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " TSE ,Timestamp enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " WUTE ,Wakeup timer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ALRBE ,Alarm B enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ALRAE ,Alarm A enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " FMT ,Hour format" "24 hour,AM/PM"
|
|
bitfld.long 0x00 5. " BYPSHAD ,Bypass the shadow registers" "Calendar from shadow,Calendar directly"
|
|
bitfld.long 0x00 4. " REFCKON ,REFIN reference clock detection enable (50 or 60 Hz)" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TSEDGE ,Time-stamp event active edge" "Rising,Falling"
|
|
newline
|
|
rbitfld.long 0x00 0.--2. " WUCKSEL ,Wakeup clock selection" "RTC/16,RTC/8,RTC/4,RTC/2,ck_spre,ck_spre,ck_spre+2^16,ck_spre+2^16"
|
|
elif ((((per.l(ad:0x40002800+0x0C))&0x40)==0x40)&&(((per.l(ad:0x40002800+0x08))&0x400)==0x00)&&(((per.l(ad:0x40002800+0x0C))&0x400)==0x00))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR,RTC Control Register"
|
|
bitfld.long 0x00 24. " ITSE ,Timestamp on internal event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " COE ,Calibration output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " OSEL ,Output selection" "Disabled,AlarmA,AlarmB,Wakeup"
|
|
bitfld.long 0x00 20. " POL ,Output polarity" "High,Low"
|
|
newline
|
|
bitfld.long 0x00 19. " COSEL ,Calibration output selection" "512Hz,1Hz"
|
|
bitfld.long 0x00 18. " BKP ,Backup. DSTC(Daylight Saving Time Change)" "DSTC not performed,DSTC performed"
|
|
bitfld.long 0x00 17. " SUB1H ,Subtract 1 hour (winter time change)" "No effect,Subtracted"
|
|
bitfld.long 0x00 16. " ADD1H ,Add 1 hour (summer time change)" "No effect,Added"
|
|
newline
|
|
bitfld.long 0x00 15. " TSIE ,Time-stamp interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " WUTIE ,Wakeup timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ALRBIE ,Alarm B interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ALRAIE ,Alarm A interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " TSE ,Timestamp enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " WUTE ,Wakeup timer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ALRBE ,Alarm B enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ALRAE ,Alarm A enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " FMT ,Hour format" "24 hour,AM/PM"
|
|
bitfld.long 0x00 5. " BYPSHAD ,Bypass the shadow registers" "Calendar from shadow,Calendar directly"
|
|
bitfld.long 0x00 4. " REFCKON ,REFIN reference clock detection enable (50 or 60 Hz)" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TSEDGE ,Time-stamp event active edge" "Rising,Falling"
|
|
newline
|
|
rbitfld.long 0x00 0.--2. " WUCKSEL ,Wakeup clock selection" "RTC/16,RTC/8,RTC/4,RTC/2,ck_spre,ck_spre,ck_spre+2^16,ck_spre+2^16"
|
|
endif
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ISR,RTC Initialization And Status Register"
|
|
bitfld.long 0x00 17. " ITSF ,Internal time-stamp flag" "No time-stamp event,Time-stamp event"
|
|
rbitfld.long 0x00 16. " RECALPF ,Recalibration pending flag" "CALR unlocked,CALR locked"
|
|
newline
|
|
bitfld.long 0x00 15. " TAMP3F ,TAMP3 detection flag" "No tamper detection,Tamper detection"
|
|
newline
|
|
bitfld.long 0x00 14. " TAMP2F ,TAMP2 detection flag" "No tamper detection,Tamper detection"
|
|
newline
|
|
bitfld.long 0x00 13. " TAMP1F ,TAMP1 detection flag" "No tamper detection,Tamper detection"
|
|
newline
|
|
bitfld.long 0x00 12. " TSOVF ,Time-stamp overflow flag" "TSF not set,TSF already set"
|
|
bitfld.long 0x00 11. " TSF ,Time-stamp flag" "No time-stamp event,Time-stamp event"
|
|
bitfld.long 0x00 10. " WUTF ,Wakeup timer flag" "Counter>0,Counter=0"
|
|
bitfld.long 0x00 9. " ALRBF ,Alarm B flag" "Time/date<>AlarmB,Time/date=AlarmB"
|
|
newline
|
|
bitfld.long 0x00 8. " ALRAF ,Alarm A flag" "Time/date<>AlarmA,Time/date=AlarmA"
|
|
bitfld.long 0x00 7. " INIT ,Initialization mode" "Free running,Initialization"
|
|
rbitfld.long 0x00 6. " INITF ,Initialization flag" "Update not allowed,Update allowed"
|
|
bitfld.long 0x00 5. " RSF ,Registers synchronization flag" "Not synchronized,Synchronized"
|
|
newline
|
|
rbitfld.long 0x00 4. " INITS ,Initialization status flag" "Not initialized,Initialized"
|
|
rbitfld.long 0x00 3. " SHPF ,Shift operation pending" "Not pending,Pending"
|
|
rbitfld.long 0x00 2. " WUTWF ,Wakeup timer write flag" "Update not allowed,Update allowed"
|
|
rbitfld.long 0x00 1. " ALRBWF ,Alarm B write flag" "Update not allowed,Update allowed"
|
|
newline
|
|
rbitfld.long 0x00 0. " ALRAWF ,Alarm A write flag" "Update not allowed,Update allowed"
|
|
if ((per.l(ad:0x40002800+0x0C)&0x80)==0x80)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PRER,RTC Prescaler Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " PREDIV_A ,Asynchronous prescaler factor"
|
|
hexmask.long.word 0x00 0.--14. 1. " PREDIV_S ,Synchronous prescaler factor"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "PRER,RTC Prescaler Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " PREDIV_A ,Asynchronous prescaler factor"
|
|
hexmask.long.word 0x00 0.--14. 1. " PREDIV_S ,Synchronous prescaler factor"
|
|
endif
|
|
if ((per.l(ad:0x40002800+0x0C)&0x800)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "WUTR,RTC Wakeup Timer Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " WUT ,Wakeup auto-reload value bits"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "WUTR,RTC Wakeup Timer Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " WUT ,Wakeup auto-reload value bits"
|
|
endif
|
|
if ((((per.l(ad:0x40002800+0x0C+0x10))&0x30000000)==0x30000000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x00)&&(((per.l(ad:0x40002800+0x1C))&0x300000)==0x200000)&&(((per.l(ad:0x40002800+0x0C+0x10))&0x40000000)==0x00))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ALRMAR,RTC Alarm A Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. " :,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
newline
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date units or day in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Date/day match,Date/day don't care"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif ((((per.l(ad:0x40002800+0x0C+0x10))&0x30000000)!=0x30000000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x00)&&(((per.l(ad:0x40002800+0x1C))&0x300000)==0x200000)&&(((per.l(ad:0x40002800+0x1C))&0x40000000)==0x00))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ALRMAR,RTC Alarm A Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
newline
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date units or day in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Date/day match,Date/day don't care"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif ((((per.l(ad:0x40002800+0x0C+0x10))&0x30000000)==0x30000000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x00)&&(((per.l(ad:0x40002800+0x1C))&0x300000)!=0x200000)&&(((per.l(ad:0x40002800+0x1C))&0x40000000)==0x00))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ALRMAR,RTC Alarm A Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
newline
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date units or day in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Date/day match,Date/day don't care"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif ((((per.l(ad:0x40002800+0x0C+0x10))&0x30000000)!=0x30000000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x00)&&(((per.l(ad:0x40002800+0x1C))&0x300000)!=0x200000)&&(((per.l(ad:0x40002800+0x1C))&0x40000000)==0x00))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ALRMAR,RTC Alarm A Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
newline
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date units or day in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Date/day match,Date/day don't care"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif ((((per.l(ad:0x40002800+0x0C+0x10))&0x300000)!=0x200000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x00)&&(((per.l(ad:0x40002800+0x1C))&0x40000000)==0x40000000))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ALRMAR,RTC Alarm A Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
newline
|
|
bitfld.long 0x00 24.--27. " DU ,Date units or day in BCD format" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Date/day match,Date/day don't care"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif ((((per.l(ad:0x40002800+0x1C))&0x300000)==0x200000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x00)&&(((per.l(ad:0x40002800+0x1C))&0x40000000)==0x40000000))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ALRMAR,RTC Alarm A Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
newline
|
|
bitfld.long 0x00 24.--27. " DU ,Date units or day in BCD format" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Date/day match,Date/day don't care"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif ((((per.l(ad:0x40002800+0x0C+0x10))&0x30000000)==0x30000000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x40)&&(((per.l(ad:0x40002800+0x1C))&0x300000)==0x100000)&&(((per.l(ad:0x40002800+0x1C))&0x40000000)==0x00))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ALRMAR,RTC Alarm A Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM"
|
|
newline
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
newline
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. " ,Date units or day in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Date/day match,Date/day don't care"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif ((((per.l(ad:0x40002800+0x0C+0x10))&0x30000000)!=0x30000000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x40)&&(((per.l(ad:0x40002800+0x1C))&0x300000)==0x100000)&&(((per.l(ad:0x40002800+0x1C))&0x40000000)==0x00))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ALRMAR,RTC Alarm A Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM"
|
|
newline
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
newline
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date units or day in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Date/day match,Date/day don't care"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif ((((per.l(ad:0x40002800+0x0C+0x10))&0x30000000)==0x30000000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x40)&&(((per.l(ad:0x40002800+0x1C))&0x300000)==0x00)&&(((per.l(ad:0x40002800+0x1C))&0x40000000)==0x00))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ALRMAR,RTC Alarm A Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM"
|
|
newline
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
newline
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date units or day in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Date/day match,Date/day don't care"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif ((((per.l(ad:0x40002800+0x0C+0x10))&0x30000000)!=0x30000000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x40)&&(((per.l(ad:0x40002800+0x1C))&0x300000)==0x00)&&(((per.l(ad:0x40002800+0x1C))&0x40000000)==0x00))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ALRMAR,RTC Alarm A Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM"
|
|
newline
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
newline
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date units or day in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Date/day match,Date/day don't care"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif ((((per.l(ad:0x40002800+0x0C+0x10))&0x300000)==0x00)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x40)&&(((per.l(ad:0x40002800+0x1C))&0x40000000)==0x40000000))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ALRMAR,RTC Alarm A Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM"
|
|
newline
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
newline
|
|
bitfld.long 0x00 24.--27. " DU ,Date units or day in BCD format" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Date/day match,Date/day don't care"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif ((((per.l(ad:0x40002800+0x1C))&0x300000)==0x100000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x40)&&(((per.l(ad:0x40002800+0x1C))&0x40000000)==0x40000000))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ALRMAR,RTC Alarm A Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM"
|
|
newline
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
newline
|
|
bitfld.long 0x00 24.--27. " DU ,Date units or day in BCD format" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Date/day match,Date/day don't care"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
endif
|
|
if ((((per.l(ad:0x40002800+0x0C+0x10))&0x30000000)==0x30000000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x00)&&(((per.l(ad:0x40002800+0x20))&0x300000)==0x200000)&&(((per.l(ad:0x40002800+0x0C+0x10))&0x40000000)==0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ALRMBR,RTC Alarm B Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. " :,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
newline
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date units or day in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm B date mask" "Date/day match,Date/day don't care"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm B hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm B minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm B seconds mask" "Not masked,Masked"
|
|
elif ((((per.l(ad:0x40002800+0x0C+0x10))&0x30000000)!=0x30000000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x00)&&(((per.l(ad:0x40002800+0x20))&0x300000)==0x200000)&&(((per.l(ad:0x40002800+0x20))&0x40000000)==0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ALRMBR,RTC Alarm B Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
newline
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date units or day in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm B date mask" "Date/day match,Date/day don't care"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm B hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm B minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm B seconds mask" "Not masked,Masked"
|
|
elif ((((per.l(ad:0x40002800+0x0C+0x10))&0x30000000)==0x30000000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x00)&&(((per.l(ad:0x40002800+0x20))&0x300000)!=0x200000)&&(((per.l(ad:0x40002800+0x20))&0x40000000)==0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ALRMBR,RTC Alarm B Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
newline
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date units or day in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm B date mask" "Date/day match,Date/day don't care"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm B hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm B minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm B seconds mask" "Not masked,Masked"
|
|
elif ((((per.l(ad:0x40002800+0x0C+0x10))&0x30000000)!=0x30000000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x00)&&(((per.l(ad:0x40002800+0x20))&0x300000)!=0x200000)&&(((per.l(ad:0x40002800+0x20))&0x40000000)==0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ALRMBR,RTC Alarm B Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
newline
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date units or day in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm B date mask" "Date/day match,Date/day don't care"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm B hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm B minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm B seconds mask" "Not masked,Masked"
|
|
elif ((((per.l(ad:0x40002800+0x0C+0x10))&0x300000)!=0x200000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x00)&&(((per.l(ad:0x40002800+0x20))&0x40000000)==0x40000000))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ALRMBR,RTC Alarm B Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
newline
|
|
bitfld.long 0x00 24.--27. " DU ,Date units or day in BCD format" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm B date mask" "Date/day match,Date/day don't care"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm B hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm B minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm B seconds mask" "Not masked,Masked"
|
|
elif ((((per.l(ad:0x40002800+0x20))&0x300000)==0x200000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x00)&&(((per.l(ad:0x40002800+0x20))&0x40000000)==0x40000000))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ALRMBR,RTC Alarm B Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
newline
|
|
bitfld.long 0x00 24.--27. " DU ,Date units or day in BCD format" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm B date mask" "Date/day match,Date/day don't care"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm B hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm B minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm B seconds mask" "Not masked,Masked"
|
|
elif ((((per.l(ad:0x40002800+0x0C+0x10))&0x30000000)==0x30000000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x40)&&(((per.l(ad:0x40002800+0x20))&0x300000)==0x100000)&&(((per.l(ad:0x40002800+0x20))&0x40000000)==0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ALRMBR,RTC Alarm B Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM"
|
|
newline
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
newline
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. " ,Date units or day in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm B date mask" "Date/day match,Date/day don't care"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm B hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm B minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm B seconds mask" "Not masked,Masked"
|
|
elif ((((per.l(ad:0x40002800+0x0C+0x10))&0x30000000)!=0x30000000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x40)&&(((per.l(ad:0x40002800+0x20))&0x300000)==0x100000)&&(((per.l(ad:0x40002800+0x20))&0x40000000)==0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ALRMBR,RTC Alarm B Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM"
|
|
newline
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
newline
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date units or day in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm B date mask" "Date/day match,Date/day don't care"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm B hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm B minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm B seconds mask" "Not masked,Masked"
|
|
elif ((((per.l(ad:0x40002800+0x0C+0x10))&0x30000000)==0x30000000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x40)&&(((per.l(ad:0x40002800+0x20))&0x300000)==0x00)&&(((per.l(ad:0x40002800+0x20))&0x40000000)==0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ALRMBR,RTC Alarm B Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM"
|
|
newline
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
newline
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date units or day in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm B date mask" "Date/day match,Date/day don't care"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm B hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm B minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm B seconds mask" "Not masked,Masked"
|
|
elif ((((per.l(ad:0x40002800+0x0C+0x10))&0x30000000)!=0x30000000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x40)&&(((per.l(ad:0x40002800+0x20))&0x300000)==0x00)&&(((per.l(ad:0x40002800+0x20))&0x40000000)==0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ALRMBR,RTC Alarm B Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM"
|
|
newline
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
newline
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date units or day in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm B date mask" "Date/day match,Date/day don't care"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm B hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm B minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm B seconds mask" "Not masked,Masked"
|
|
elif ((((per.l(ad:0x40002800+0x0C+0x10))&0x300000)==0x00)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x40)&&(((per.l(ad:0x40002800+0x20))&0x40000000)==0x40000000))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ALRMBR,RTC Alarm B Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM"
|
|
newline
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
newline
|
|
bitfld.long 0x00 24.--27. " DU ,Date units or day in BCD format" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm B date mask" "Date/day match,Date/day don't care"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm B hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm B minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm B seconds mask" "Not masked,Masked"
|
|
elif ((((per.l(ad:0x40002800+0x20))&0x300000)==0x100000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x40)&&(((per.l(ad:0x40002800+0x20))&0x40000000)==0x40000000))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ALRMBR,RTC Alarm B Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM"
|
|
newline
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
newline
|
|
bitfld.long 0x00 24.--27. " DU ,Date units or day in BCD format" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm B date mask" "Date/day match,Date/day don't care"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm B hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm B minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm B seconds mask" "Not masked,Masked"
|
|
endif
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "WPR,RTC Write Protection Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " KEY ,Write protection key"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "SSR,RTC Sub Second Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SS ,Sub second value"
|
|
wgroup.long 0x2C++0x03
|
|
line.long 0x00 "SHIFTR,RTC Shift Control Register"
|
|
bitfld.long 0x00 31. " ADD1S ,Add one second" "No effect,Added"
|
|
hexmask.long.word 0x00 0.--14. 1. " SUBFS ,Subtract a fraction of a second"
|
|
if ((per.l(ad:0x40002800+0x0C)&0x800)==0x00)
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "TSTR,RTC Time Stamp Time Register"
|
|
elif (((per.l(ad:0x40002800+0x0C)&0x800)==0x800)&&((per.l(ad:0x40002800+0x08)&0x40)==0x00))&&(((per.l(ad:0x40002800+0x30))&0x300000)==0x200000)
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "TSTR,RTC Timestamp Time Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.l(ad:0x40002800+0x0C)&0x800)==0x800)&&((per.l(ad:0x40002800+0x08)&0x40)==0x00))&&(((per.l(ad:0x40002800+0x30))&0x300000)!=0x200000)
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "TSTR,RTC Timestamp Time Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.l(ad:0x40002800+0x0C)&0x800)==0x800)&&((per.l(ad:0x40002800+0x08)&0x40)==0x40))&&(((per.l(ad:0x40002800+0x30))&0x300000)==0x100000)
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "TSTR,RTC Timestamp Time Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM"
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "TSTR,RTC Timestamp Time Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM"
|
|
endif
|
|
if ((per.l(ad:0x40002800+0x0C)&0x800)==0x00)
|
|
hgroup.long 0x34++0x03
|
|
hide.long 0x00 "TSDR,RTC Timestamp Date Register"
|
|
elif ((((per.l(ad:0x40002800+0x34))&0x1000)==0x1000)&&(((per.l(ad:0x40002800+0x34))&0x30)==0x30)&&(((per.l(ad:0x40002800+0x0C))&0x800)==0x800))
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "TSDR,RTC Timestamp Date Register"
|
|
bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12. "/,Month tens in BCD format" "0,1"
|
|
bitfld.long 0x00 8.--11. ",Month units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
elif ((((per.l(ad:0x40002800+0x34))&0x1000)!=0x1000)&&(((per.l(ad:0x40002800+0x34))&0x30)==0x30)&&(((per.l(ad:0x40002800+0x0C))&0x800)==0x800))
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "TSDR,RTC Timestamp Date Register"
|
|
bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12. "/,Month tens in BCD format" "0,1"
|
|
bitfld.long 0x00 8.--11. ",Month units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif ((((per.l(ad:0x40002800+0x34))&0x1000)==0x1000)&&(((per.l(ad:0x40002800+0x34))&0x30)!=0x30)&&(((per.l(ad:0x40002800+0x0C))&0x800)==0x800))
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "TSDR,RTC Timestamp Date Register"
|
|
bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12. "/,Month tens in BCD format" "0,1"
|
|
bitfld.long 0x00 8.--11. ",Month units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
else
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "TSDR,RTC Timestamp Date Register"
|
|
bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12. "/,Month tens in BCD format" "0,1"
|
|
bitfld.long 0x00 8.--11. ",Month units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
endif
|
|
if ((per.l(ad:0x40002800+0x0C)&0x800)==0x800)
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "TSSSR,RTC Time-Stamp Sub Second Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SS ,Sub second value"
|
|
else
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "TSSSR,RTC Time-Stamp Sub Second Register"
|
|
endif
|
|
newline
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CALR,RTC Calibration Register"
|
|
bitfld.long 0x00 15. " CALP ,Increase frequency of RTC by 488.5 ppm" "No pulses,1 pulse every 2^11"
|
|
bitfld.long 0x00 14. " CALW8 ,Use an 8-second calibration cycle period" "No 8 sec calib,8 sec calibration"
|
|
bitfld.long 0x00 13. " CALW16 ,Use an 16-second calibration cycle period" "No 16 sec calib,16 sec calibration"
|
|
hexmask.long.word 0x00 0.--8. 1. " CALM ,Calibration minus"
|
|
if ((per.l(ad:0x40002800+0x40)&0x1800)==0x00)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TAMPCR,RTCTamper Configuration Register"
|
|
bitfld.long 0x00 24. " TAMP3MF ,Tamper 3 mask flag" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " TAMP3NOERASE ,Tamper 3 no erase" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 22. " TAMP3IE ,Tamper 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " TAMP2MF ,Tamper 2 mask flag" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " TAMP2NOERASE ,Tamper 2 no erase" "No,Yes"
|
|
bitfld.long 0x00 19. " TAMP2IE ,Tamper 2 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18. " TAMP1MF ,Tamper 1 mask flag" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " TAMP1NOERASE ,Tamper 1 no erase" "No,Yes"
|
|
bitfld.long 0x00 16. " TAMP1IE ,Tamper 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " TAMPPUDIS ,TAMPx pull-up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--14. " TAMPPRCH ,Tamper precharge duration" "1 cycle,2 cycles,4 cycles,8 cycles"
|
|
bitfld.long 0x00 11.--12. " TAMPFLT ,TAMPx filter count" "On Edge,2 samples,4 samples,8 samples"
|
|
bitfld.long 0x00 8.--10. " TAMPFREQ ,Tamper sampling frequency" "/32768,/16384,/8192,/4096,/2048,/1024,/512,/256"
|
|
bitfld.long 0x00 7. " TAMPTS ,Activate timestamp on tamper detection event" "Not saved,Saved"
|
|
newline
|
|
bitfld.long 0x00 6. " TAMP3TRG ,Active level for TAMP3 input" "Rising,Falling"
|
|
bitfld.long 0x00 5. " TAMP3E ,TAMP3 detection enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TAMP2TRG ,Active level for TAMP2 input" "Rising,Falling"
|
|
bitfld.long 0x00 3. " TAMP2E ,TAMP2 detection enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TAMPIE ,Tamper interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TAMP1TRG ,Active level for TAMP1 input" "Rising,Falling"
|
|
bitfld.long 0x00 0. " TAMP1E ,TAMP1 detection enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TAMPCR,RTCTamper Configuration Register"
|
|
bitfld.long 0x00 24. " TAMP3MF ,Tamper 3 mask flag" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " TAMP3NOERASE ,Tamper 3 no erase" "No,Yes"
|
|
bitfld.long 0x00 22. " TAMP3IE ,Tamper 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " TAMP2MF ,Tamper 2 mask flag" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 20. " TAMP2NOERASE ,Tamper 2 no erase" "No,Yes"
|
|
bitfld.long 0x00 19. " TAMP2IE ,Tamper 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TAMP1MF ,Tamper 1 mask flag" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " TAMP1NOERASE ,Tamper 1 no erase" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 16. " TAMP1IE ,Tamper 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " TAMPPUDIS ,TAMPx pull-up disable" "No,Yes"
|
|
bitfld.long 0x00 13.--14. " TAMPPRCH ,Tamper precharge duration" "1 cycle,2 cycles,4 cycles,8 cycles"
|
|
bitfld.long 0x00 11.--12. " TAMPFLT ,TAMPx filter count" "On Edge,2 samples,4 samples,8 samples"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " TAMPFREQ ,Tamper sampling frequency" "/32768,/16384,/8192,/4096,/2048,/1024,/512,/256"
|
|
bitfld.long 0x00 7. " TAMPTS ,Activate timestamp on tamper detection event" "Not saved,Saved"
|
|
bitfld.long 0x00 6. " TAMP3TRG ,Active level for TAMP3 input" "Low,High"
|
|
bitfld.long 0x00 5. " TAMP3E ,TAMP3 detection enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " TAMP2TRG ,Active level for TAMP2 input" "Low,High"
|
|
bitfld.long 0x00 3. " TAMP2E ,TAMP2 detection enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TAMPIE ,Tamper interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TAMP1TRG ,Active level for TAMP1 input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 0. " TAMP1E ,TAMP1 detection enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.l(ad:0x40002800+0x0C)&0x80)==0x80)||((per.l(ad:0x40002800+0x08)&0x100)==0x00)
|
|
group.long 0x44++0x07
|
|
line.long 0x00 "ALRMASSR,RTC Alarm A Sub Second Register"
|
|
bitfld.long 0x00 24.--27. " MASKSS ,Mask the most-significant bits starting at this bit" "SS[14:0],SS[14:1],SS[14:2],SS[14:3],SS[14:4],SS[14:5],SS[14:6],SS[14:7],SS[14:8],SS[14:9],SS[14:10],SS[14:11],SS[14:12],SS[14:13],SS[14],No mask"
|
|
hexmask.long.word 0x00 0.--14. 1. " SS ,Sub seconds value"
|
|
line.long 0x04 "ALRMBSSR,RTC Alarm B Sub Second Register"
|
|
bitfld.long 0x04 24.--27. " MASKSS ,Mask the most-significant bits" "SS[14:0],SS[14:1],SS[14:2],SS[14:3],SS[14:4],SS[14:5],SS[14:6],SS[14:7],SS[14:8],SS[14:9],SS[14:10],SS[14:11],SS[14:12],SS[14:13],SS[14],No mask"
|
|
hexmask.long.word 0x04 0.--14. 1. " SS ,Sub seconds value"
|
|
else
|
|
rgroup.long 0x44++0x07
|
|
line.long 0x00 "ALRMASSR,RTC Alarm A Sub Second Register"
|
|
bitfld.long 0x00 24.--27. " MASKSS ,Mask the most-significant bits starting at this bit" "No comparison,SS[0] compared,SS[1:0] compared,SS[2:0] compared,SS[3:0] compared,SS[4:0] compared,SS[5:0] compared,SS[6:0] compared,SS[7:0] compared,SS[8:0] compared,SS[9:0] compared,SS[10:0] compared,SS[11:0] compared,SS[12:0] compared,SS[13:0] compared,All bits compared"
|
|
hexmask.long.word 0x00 0.--14. 1. " SS ,Sub seconds value"
|
|
line.long 0x04 "ALRMBSSR,RTC Alarm B Sub Second Register"
|
|
bitfld.long 0x04 24.--27. " MASKSS ,Mask the most-significant bits" "SS[14:0],SS[14:1],SS[14:2],SS[14:3],SS[14:4],SS[14:5],SS[14:6],SS[14:7],SS[14:8],SS[14:9],SS[14:10],SS[14:11],SS[14:12],SS[14:13],SS[14],No mask"
|
|
hexmask.long.word 0x04 0.--14. 1. " SS ,Sub seconds value"
|
|
endif
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "OR,RTC Option Register"
|
|
bitfld.long 0x00 3. " ALARM_TYPE ,ALARM on PC13 output type" "Open-drain,Push-pull"
|
|
bitfld.long 0x00 1.--2. " TSINSEL ,TIMESTAMP mapping" "PC13,PI8,PC1,PC1"
|
|
width 8.
|
|
tree "RTC Backup Registers"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "BKP0R,RTC Backup Register 0"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "BKP1R,RTC Backup Register 1"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "BKP2R,RTC Backup Register 2"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "BKP3R,RTC Backup Register 3"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "BKP4R,RTC Backup Register 4"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "BKP5R,RTC Backup Register 5"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "BKP6R,RTC Backup Register 6"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "BKP7R,RTC Backup Register 7"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "BKP8R,RTC Backup Register 8"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "BKP9R,RTC Backup Register 9"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "BKP10R,RTC Backup Register 10"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "BKP11R,RTC Backup Register 11"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "BKP12R,RTC Backup Register 12"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "BKP13R,RTC Backup Register 13"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "BKP14R,RTC Backup Register 14"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "BKP15R,RTC Backup Register 15"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "BKP16R,RTC Backup Register 16"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "BKP17R,RTC Backup Register 17"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "BKP18R,RTC Backup Register 18"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "BKP19R,RTC Backup Register 19"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "BKP20R,RTC Backup Register 20"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "BKP21R,RTC Backup Register 21"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "BKP22R,RTC Backup Register 22"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "BKP23R,RTC Backup Register 23"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "BKP24R,RTC Backup Register 24"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "BKP25R,RTC Backup Register 25"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "BKP26R,RTC Backup Register 26"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "BKP27R,RTC Backup Register 27"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "BKP28R,RTC Backup Register 28"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "BKP29R,RTC Backup Register 29"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "BKP30R,RTC Backup Register 30"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "BKP31R,RTC Backup Register 31"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "I2C (Inter-Integrated Circuit)"
|
|
tree "I2C 1"
|
|
base ad:0x40005400
|
|
width 10.
|
|
if ((per.l(ad:0x40005400+0x00)&0x100000)==0x00)&&((per.l(ad:0x40005400+0x00)&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
newline
|
|
sif (!cpuis("STM32F7*"))
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40005400+0x00)&0x100000)==0x100000)&&((per.l(ad:0x40005400+0x00)&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
newline
|
|
sif (!cpuis("STM32F7*"))
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40005400+0x00)&0x100000)==0x00)&&((per.l(ad:0x40005400+0x00)&0x01)==0x01)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
newline
|
|
sif (!cpuis("STM32F7*"))
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
rbitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40005400+0x00)&0x100000)==0x100000)&&((per.l(ad:0x40005400+0x00)&0x01)==0x01)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
newline
|
|
sif (!cpuis("STM32F7*"))
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
rbitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40005400+0x04)&0x800)==0x00)&&((per.l(ad:0x40005400)&0x10000)==0x00))
|
|
if ((per.l(ad:0x40005400+0x04)&0x2000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes"
|
|
newline
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
sif cpuis("STM32F730I8")||cpuis("STM32F730R8")||cpuis("STM32F730V8")||cpuis("STM32F730Z8")||cpuis("STM32F750N8")||cpuis("STM32F750V8")||cpuis("STM32F750Z8")
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
newline
|
|
elif (!cpuis("STM32F72*")&&!cpuis("STM32F73*")&&!cpuis("STM32F76*")&&!cpuis("STM32F77*"))
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 0x01 " SADD ,Slave address bit 9:0"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes"
|
|
newline
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
sif cpuis("STM32F730I8")||cpuis("STM32F730R8")||cpuis("STM32F730V8")||cpuis("STM32F730Z8")
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
newline
|
|
elif (!cpuis("STM32F72*")&&!cpuis("STM32F73*")&&!cpuis("STM32F76*")&&!cpuis("STM32F77*"))
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 0x01 " SADD ,Slave address bit 9:0"
|
|
endif
|
|
elif (((per.l(ad:0x40005400+0x04)&0x800)==0x00)&&((per.l(ad:0x40005400)&0x10000)==0x10000))
|
|
if ((per.l(ad:0x40005400+0x04)&0x2000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes"
|
|
newline
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
newline
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
hexmask.long.word 0x00 0.--9. 0x01 " SADD ,Slave address bit 9:0"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes"
|
|
newline
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
newline
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
hexmask.long.word 0x00 0.--9. 0x01 " SADD ,Slave address bit 9:0"
|
|
endif
|
|
elif (((per.l(ad:0x40005400+0x04)&0x800)==0x800)&&((per.l(ad:0x40005400)&0x10000)==0x00))
|
|
if ((per.l(ad:0x40005400+0x04)&0x2000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes"
|
|
newline
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
sif (!cpuis("STM32F72*")&&!cpuis("STM32F73*")&&!cpuis("STM32F76*")&&!cpuis("STM32F77*"))
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 0x01 " SADD ,Slave address bit 9:0"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes"
|
|
newline
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
sif (!cpuis("STM32F72*")&&!cpuis("STM32F73*")&&!cpuis("STM32F76*")&&!cpuis("STM32F77*"))
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 0x01 " SADD ,Slave address bit 9:0"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40005400+0x04)&0x2000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes"
|
|
newline
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
newline
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
hexmask.long.word 0x00 0.--9. 0x01 " SADD ,Slave address bit 9:0"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes"
|
|
newline
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
newline
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
hexmask.long.word 0x00 0.--9. 0x01 " SADD ,Slave address bit 9:0"
|
|
endif
|
|
endif
|
|
if ((per.l(ad:0x40005400+0x08)&0x8000)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "OAR1,Own Address 1 Register"
|
|
bitfld.long 0x00 15. " OA1EN ,Own address 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OA1MODE ,Own address 1 10-bit mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 8.--9. " OA1[9:8] ,Interface address" "0,1,2,3"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " OA1[7:1] ,Interface address"
|
|
newline
|
|
bitfld.long 0x00 0. " OA1[0] ,Interface address" "0,1"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "OAR1,Own Address 1 Register"
|
|
bitfld.long 0x00 15. " OA1EN ,Own address 1 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " OA1MODE ,Own address 1 10-bit mode" "7-bit,10-bit"
|
|
rbitfld.long 0x00 8.--9. " OA1[9:8] ,Interface address" "0,1,2,3"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " OA1[7:1] ,Interface address"
|
|
newline
|
|
rbitfld.long 0x00 0. " OA1[0] ,Interface address" "0,1"
|
|
endif
|
|
if ((per.l(ad:0x40005400+0x0C)&0x8000)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "OAR2,Own Address 2 Register"
|
|
bitfld.long 0x00 15. " OA2EN ,Own address 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " OA2MSK[2:0] ,Own address 2 masks" "No mask,OA2[7:2] compared,OA2[7:3] compared,OA2[7:4] compared,OA2[7:5] compared,OA2[7:6] compared,OA2[7] compared,No comparison"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " OA2[7:1] ,Interface address"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "OAR2,Own Address 2 Register"
|
|
bitfld.long 0x00 15. " OA2EN ,Own address 2 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--10. " OA2MSK[2:0] ,Own address 2 masks" "No mask,OA2[7:2] compared,OA2[7:3] compared,OA2[7:4] compared,OA2[7:5] compared,OA2[7:6] compared,OA2[7] compared,No comparison"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " OA2[7:1] ,Interface address"
|
|
endif
|
|
sif (cpuis("STM32F7*"))||(cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40005400+0x00)&0x01)==0x00))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TIMINGR,Timing Register"
|
|
bitfld.long 0x00 28.--31. " PRESC ,Timing prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " SCLDEL ,Data setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " SDADEL ,Data hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCLH ,SCL high period"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " SCLL ,SCL low period"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TIMINGR,Timing Register"
|
|
bitfld.long 0x00 28.--31. " PRESC ,Timing prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " SCLDEL ,Data setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " SDADEL ,Data hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCLH ,SCL high period"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " SCLL ,SCL low period"
|
|
endif
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TIMINGR,Timing Register"
|
|
bitfld.long 0x00 28.--31. " PRESC ,Timing prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " SCLDEL ,Data setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " SDADEL ,Data hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCLH ,SCL high period"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " SCLL ,SCL low period"
|
|
endif
|
|
if ((per.l(ad:0x40005400+0x14)&0x8000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TIMEOUTR,Timeout Register"
|
|
bitfld.long 0x00 31. " TEXTEN ,Extended clock timeout enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 16.--27. 1. " TIMEOUTB ,Bus timeout B"
|
|
bitfld.long 0x00 15. " TIMOUTEN ,Clock timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " TIDLE ,Idle clock timeout detection" "SCL low,SCL/SDA high"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. " TIMEOUTA ,Bus timeout A"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TIMEOUTR,Timeout Register"
|
|
bitfld.long 0x00 31. " TEXTEN ,Extended clock timeout enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 16.--27. 1. " TIMEOUTB ,Bus timeout B"
|
|
bitfld.long 0x00 15. " TIMOUTEN ,Clock timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. " TIDLE ,Idle clock timeout detection" "SCL low,SCL/SDA high"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. " TIMEOUTA ,Bus timeout A"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ISR,Interrupt And Status Register"
|
|
hexmask.long.byte 0x00 17.--23. 1. " ADDCODE ,Address match code"
|
|
rbitfld.long 0x00 16. " DIR ,Transfer direction" "Write,Read"
|
|
rbitfld.long 0x00 15. " BUSY ,Bus busy" "Idle,Busy"
|
|
rbitfld.long 0x00 13. " ALERT ,SMBus alert" "Not detected,Detected"
|
|
newline
|
|
rbitfld.long 0x00 12. " TIMEOUT ,Timeout or tLOW detection flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 11. " PECERR ,PEC error in reception" "No error,Error"
|
|
rbitfld.long 0x00 10. " OVR ,Overrun/Underrun" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 9. " ARLO ,Arbitration lost" "Not occurred,Occurred"
|
|
newline
|
|
rbitfld.long 0x00 8. " BERR ,Bus error" "No error,Error"
|
|
rbitfld.long 0x00 7. " TCR ,Transfer complete reload" "Not completed,Completed"
|
|
rbitfld.long 0x00 6. " TC ,Transfer complete" "Not completed,Completed"
|
|
rbitfld.long 0x00 5. " STOPF ,Stop detection flag" "Not detected,Detected"
|
|
newline
|
|
rbitfld.long 0x00 4. " NACKF ,Not acknowledge received flag" "Not received,Received"
|
|
rbitfld.long 0x00 3. " ADDR ,Address matched" "Not matched,Matched"
|
|
rbitfld.long 0x00 2. " RXNE ,Receive data register not empty" "No,Yes"
|
|
rbitfld.long 0x00 1. " TXIS ,Transmit interrupt status" "No interrupt,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 0. " TXE ,Transmit data register empty" "Not empty,Empty"
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x00 13. " ALERTCF ,Alert flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 12. " TIMOUTCF ,Timeout detection flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 11. " PECCF ,PEC error flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 10. " OVRCF ,Overrun/Underrun flag clear" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 9. " ARLOCF ,Arbitration lost flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " BERRCF ,Bus error flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 5. " STOPCF ,Stop detection flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " NACKCF ,Not acknowledge flag clear" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 3. " ADDRCF ,Address matched flag clear" "No effect,Clear"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "PECR,PEC Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PEC ,Packet error checking register"
|
|
sif (cpuis("STM32F7*"))
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "RXDR,Receive Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RXDATA ,8-bit receive data"
|
|
else
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "RXDR,Receive Data Register"
|
|
endif
|
|
if ((per.l(ad:0x40005400+0x18)&0x01)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TXDR,Transmit Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,8-bit transmit data"
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "TXDR,Transmit Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,8-bit transmit data"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "I2C 2"
|
|
base ad:0x40005800
|
|
width 10.
|
|
if ((per.l(ad:0x40005800+0x00)&0x100000)==0x00)&&((per.l(ad:0x40005800+0x00)&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
newline
|
|
sif (!cpuis("STM32F7*"))
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40005800+0x00)&0x100000)==0x100000)&&((per.l(ad:0x40005800+0x00)&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
newline
|
|
sif (!cpuis("STM32F7*"))
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40005800+0x00)&0x100000)==0x00)&&((per.l(ad:0x40005800+0x00)&0x01)==0x01)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
newline
|
|
sif (!cpuis("STM32F7*"))
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
rbitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40005800+0x00)&0x100000)==0x100000)&&((per.l(ad:0x40005800+0x00)&0x01)==0x01)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
newline
|
|
sif (!cpuis("STM32F7*"))
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
rbitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40005800+0x04)&0x800)==0x00)&&((per.l(ad:0x40005800)&0x10000)==0x00))
|
|
if ((per.l(ad:0x40005800+0x04)&0x2000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes"
|
|
newline
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
sif cpuis("STM32F730I8")||cpuis("STM32F730R8")||cpuis("STM32F730V8")||cpuis("STM32F730Z8")||cpuis("STM32F750N8")||cpuis("STM32F750V8")||cpuis("STM32F750Z8")
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
newline
|
|
elif (!cpuis("STM32F72*")&&!cpuis("STM32F73*")&&!cpuis("STM32F76*")&&!cpuis("STM32F77*"))
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 0x01 " SADD ,Slave address bit 9:0"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes"
|
|
newline
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
sif cpuis("STM32F730I8")||cpuis("STM32F730R8")||cpuis("STM32F730V8")||cpuis("STM32F730Z8")
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
newline
|
|
elif (!cpuis("STM32F72*")&&!cpuis("STM32F73*")&&!cpuis("STM32F76*")&&!cpuis("STM32F77*"))
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 0x01 " SADD ,Slave address bit 9:0"
|
|
endif
|
|
elif (((per.l(ad:0x40005800+0x04)&0x800)==0x00)&&((per.l(ad:0x40005800)&0x10000)==0x10000))
|
|
if ((per.l(ad:0x40005800+0x04)&0x2000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes"
|
|
newline
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
newline
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
hexmask.long.word 0x00 0.--9. 0x01 " SADD ,Slave address bit 9:0"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes"
|
|
newline
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
newline
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
hexmask.long.word 0x00 0.--9. 0x01 " SADD ,Slave address bit 9:0"
|
|
endif
|
|
elif (((per.l(ad:0x40005800+0x04)&0x800)==0x800)&&((per.l(ad:0x40005800)&0x10000)==0x00))
|
|
if ((per.l(ad:0x40005800+0x04)&0x2000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes"
|
|
newline
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
sif (!cpuis("STM32F72*")&&!cpuis("STM32F73*")&&!cpuis("STM32F76*")&&!cpuis("STM32F77*"))
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 0x01 " SADD ,Slave address bit 9:0"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes"
|
|
newline
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
sif (!cpuis("STM32F72*")&&!cpuis("STM32F73*")&&!cpuis("STM32F76*")&&!cpuis("STM32F77*"))
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 0x01 " SADD ,Slave address bit 9:0"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40005800+0x04)&0x2000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes"
|
|
newline
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
newline
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
hexmask.long.word 0x00 0.--9. 0x01 " SADD ,Slave address bit 9:0"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes"
|
|
newline
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
newline
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
hexmask.long.word 0x00 0.--9. 0x01 " SADD ,Slave address bit 9:0"
|
|
endif
|
|
endif
|
|
if ((per.l(ad:0x40005800+0x08)&0x8000)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "OAR1,Own Address 1 Register"
|
|
bitfld.long 0x00 15. " OA1EN ,Own address 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OA1MODE ,Own address 1 10-bit mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 8.--9. " OA1[9:8] ,Interface address" "0,1,2,3"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " OA1[7:1] ,Interface address"
|
|
newline
|
|
bitfld.long 0x00 0. " OA1[0] ,Interface address" "0,1"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "OAR1,Own Address 1 Register"
|
|
bitfld.long 0x00 15. " OA1EN ,Own address 1 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " OA1MODE ,Own address 1 10-bit mode" "7-bit,10-bit"
|
|
rbitfld.long 0x00 8.--9. " OA1[9:8] ,Interface address" "0,1,2,3"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " OA1[7:1] ,Interface address"
|
|
newline
|
|
rbitfld.long 0x00 0. " OA1[0] ,Interface address" "0,1"
|
|
endif
|
|
if ((per.l(ad:0x40005800+0x0C)&0x8000)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "OAR2,Own Address 2 Register"
|
|
bitfld.long 0x00 15. " OA2EN ,Own address 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " OA2MSK[2:0] ,Own address 2 masks" "No mask,OA2[7:2] compared,OA2[7:3] compared,OA2[7:4] compared,OA2[7:5] compared,OA2[7:6] compared,OA2[7] compared,No comparison"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " OA2[7:1] ,Interface address"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "OAR2,Own Address 2 Register"
|
|
bitfld.long 0x00 15. " OA2EN ,Own address 2 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--10. " OA2MSK[2:0] ,Own address 2 masks" "No mask,OA2[7:2] compared,OA2[7:3] compared,OA2[7:4] compared,OA2[7:5] compared,OA2[7:6] compared,OA2[7] compared,No comparison"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " OA2[7:1] ,Interface address"
|
|
endif
|
|
sif (cpuis("STM32F7*"))||(cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40005800+0x00)&0x01)==0x00))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TIMINGR,Timing Register"
|
|
bitfld.long 0x00 28.--31. " PRESC ,Timing prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " SCLDEL ,Data setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " SDADEL ,Data hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCLH ,SCL high period"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " SCLL ,SCL low period"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TIMINGR,Timing Register"
|
|
bitfld.long 0x00 28.--31. " PRESC ,Timing prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " SCLDEL ,Data setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " SDADEL ,Data hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCLH ,SCL high period"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " SCLL ,SCL low period"
|
|
endif
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TIMINGR,Timing Register"
|
|
bitfld.long 0x00 28.--31. " PRESC ,Timing prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " SCLDEL ,Data setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " SDADEL ,Data hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCLH ,SCL high period"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " SCLL ,SCL low period"
|
|
endif
|
|
if ((per.l(ad:0x40005800+0x14)&0x8000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TIMEOUTR,Timeout Register"
|
|
bitfld.long 0x00 31. " TEXTEN ,Extended clock timeout enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 16.--27. 1. " TIMEOUTB ,Bus timeout B"
|
|
bitfld.long 0x00 15. " TIMOUTEN ,Clock timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " TIDLE ,Idle clock timeout detection" "SCL low,SCL/SDA high"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. " TIMEOUTA ,Bus timeout A"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TIMEOUTR,Timeout Register"
|
|
bitfld.long 0x00 31. " TEXTEN ,Extended clock timeout enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 16.--27. 1. " TIMEOUTB ,Bus timeout B"
|
|
bitfld.long 0x00 15. " TIMOUTEN ,Clock timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. " TIDLE ,Idle clock timeout detection" "SCL low,SCL/SDA high"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. " TIMEOUTA ,Bus timeout A"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ISR,Interrupt And Status Register"
|
|
hexmask.long.byte 0x00 17.--23. 1. " ADDCODE ,Address match code"
|
|
rbitfld.long 0x00 16. " DIR ,Transfer direction" "Write,Read"
|
|
rbitfld.long 0x00 15. " BUSY ,Bus busy" "Idle,Busy"
|
|
rbitfld.long 0x00 13. " ALERT ,SMBus alert" "Not detected,Detected"
|
|
newline
|
|
rbitfld.long 0x00 12. " TIMEOUT ,Timeout or tLOW detection flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 11. " PECERR ,PEC error in reception" "No error,Error"
|
|
rbitfld.long 0x00 10. " OVR ,Overrun/Underrun" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 9. " ARLO ,Arbitration lost" "Not occurred,Occurred"
|
|
newline
|
|
rbitfld.long 0x00 8. " BERR ,Bus error" "No error,Error"
|
|
rbitfld.long 0x00 7. " TCR ,Transfer complete reload" "Not completed,Completed"
|
|
rbitfld.long 0x00 6. " TC ,Transfer complete" "Not completed,Completed"
|
|
rbitfld.long 0x00 5. " STOPF ,Stop detection flag" "Not detected,Detected"
|
|
newline
|
|
rbitfld.long 0x00 4. " NACKF ,Not acknowledge received flag" "Not received,Received"
|
|
rbitfld.long 0x00 3. " ADDR ,Address matched" "Not matched,Matched"
|
|
rbitfld.long 0x00 2. " RXNE ,Receive data register not empty" "No,Yes"
|
|
rbitfld.long 0x00 1. " TXIS ,Transmit interrupt status" "No interrupt,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 0. " TXE ,Transmit data register empty" "Not empty,Empty"
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x00 13. " ALERTCF ,Alert flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 12. " TIMOUTCF ,Timeout detection flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 11. " PECCF ,PEC error flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 10. " OVRCF ,Overrun/Underrun flag clear" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 9. " ARLOCF ,Arbitration lost flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " BERRCF ,Bus error flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 5. " STOPCF ,Stop detection flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " NACKCF ,Not acknowledge flag clear" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 3. " ADDRCF ,Address matched flag clear" "No effect,Clear"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "PECR,PEC Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PEC ,Packet error checking register"
|
|
sif (cpuis("STM32F7*"))
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "RXDR,Receive Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RXDATA ,8-bit receive data"
|
|
else
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "RXDR,Receive Data Register"
|
|
endif
|
|
if ((per.l(ad:0x40005800+0x18)&0x01)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TXDR,Transmit Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,8-bit transmit data"
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "TXDR,Transmit Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,8-bit transmit data"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "I2C 3"
|
|
base ad:0x40005C00
|
|
width 10.
|
|
if ((per.l(ad:0x40005C00+0x00)&0x100000)==0x00)&&((per.l(ad:0x40005C00+0x00)&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
newline
|
|
sif (!cpuis("STM32F7*"))
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40005C00+0x00)&0x100000)==0x100000)&&((per.l(ad:0x40005C00+0x00)&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
newline
|
|
sif (!cpuis("STM32F7*"))
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40005C00+0x00)&0x100000)==0x00)&&((per.l(ad:0x40005C00+0x00)&0x01)==0x01)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
newline
|
|
sif (!cpuis("STM32F7*"))
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
rbitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40005C00+0x00)&0x100000)==0x100000)&&((per.l(ad:0x40005C00+0x00)&0x01)==0x01)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
newline
|
|
sif (!cpuis("STM32F7*"))
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
rbitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40005C00+0x04)&0x800)==0x00)&&((per.l(ad:0x40005C00)&0x10000)==0x00))
|
|
if ((per.l(ad:0x40005C00+0x04)&0x2000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes"
|
|
newline
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
sif cpuis("STM32F730I8")||cpuis("STM32F730R8")||cpuis("STM32F730V8")||cpuis("STM32F730Z8")||cpuis("STM32F750N8")||cpuis("STM32F750V8")||cpuis("STM32F750Z8")
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
newline
|
|
elif (!cpuis("STM32F72*")&&!cpuis("STM32F73*")&&!cpuis("STM32F76*")&&!cpuis("STM32F77*"))
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 0x01 " SADD ,Slave address bit 9:0"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes"
|
|
newline
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
sif cpuis("STM32F730I8")||cpuis("STM32F730R8")||cpuis("STM32F730V8")||cpuis("STM32F730Z8")
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
newline
|
|
elif (!cpuis("STM32F72*")&&!cpuis("STM32F73*")&&!cpuis("STM32F76*")&&!cpuis("STM32F77*"))
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 0x01 " SADD ,Slave address bit 9:0"
|
|
endif
|
|
elif (((per.l(ad:0x40005C00+0x04)&0x800)==0x00)&&((per.l(ad:0x40005C00)&0x10000)==0x10000))
|
|
if ((per.l(ad:0x40005C00+0x04)&0x2000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes"
|
|
newline
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
newline
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
hexmask.long.word 0x00 0.--9. 0x01 " SADD ,Slave address bit 9:0"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes"
|
|
newline
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
newline
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
hexmask.long.word 0x00 0.--9. 0x01 " SADD ,Slave address bit 9:0"
|
|
endif
|
|
elif (((per.l(ad:0x40005C00+0x04)&0x800)==0x800)&&((per.l(ad:0x40005C00)&0x10000)==0x00))
|
|
if ((per.l(ad:0x40005C00+0x04)&0x2000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes"
|
|
newline
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
sif (!cpuis("STM32F72*")&&!cpuis("STM32F73*")&&!cpuis("STM32F76*")&&!cpuis("STM32F77*"))
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 0x01 " SADD ,Slave address bit 9:0"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes"
|
|
newline
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
sif (!cpuis("STM32F72*")&&!cpuis("STM32F73*")&&!cpuis("STM32F76*")&&!cpuis("STM32F77*"))
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 0x01 " SADD ,Slave address bit 9:0"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40005C00+0x04)&0x2000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes"
|
|
newline
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
newline
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
hexmask.long.word 0x00 0.--9. 0x01 " SADD ,Slave address bit 9:0"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes"
|
|
newline
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
newline
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
hexmask.long.word 0x00 0.--9. 0x01 " SADD ,Slave address bit 9:0"
|
|
endif
|
|
endif
|
|
if ((per.l(ad:0x40005C00+0x08)&0x8000)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "OAR1,Own Address 1 Register"
|
|
bitfld.long 0x00 15. " OA1EN ,Own address 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OA1MODE ,Own address 1 10-bit mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 8.--9. " OA1[9:8] ,Interface address" "0,1,2,3"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " OA1[7:1] ,Interface address"
|
|
newline
|
|
bitfld.long 0x00 0. " OA1[0] ,Interface address" "0,1"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "OAR1,Own Address 1 Register"
|
|
bitfld.long 0x00 15. " OA1EN ,Own address 1 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " OA1MODE ,Own address 1 10-bit mode" "7-bit,10-bit"
|
|
rbitfld.long 0x00 8.--9. " OA1[9:8] ,Interface address" "0,1,2,3"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " OA1[7:1] ,Interface address"
|
|
newline
|
|
rbitfld.long 0x00 0. " OA1[0] ,Interface address" "0,1"
|
|
endif
|
|
if ((per.l(ad:0x40005C00+0x0C)&0x8000)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "OAR2,Own Address 2 Register"
|
|
bitfld.long 0x00 15. " OA2EN ,Own address 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " OA2MSK[2:0] ,Own address 2 masks" "No mask,OA2[7:2] compared,OA2[7:3] compared,OA2[7:4] compared,OA2[7:5] compared,OA2[7:6] compared,OA2[7] compared,No comparison"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " OA2[7:1] ,Interface address"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "OAR2,Own Address 2 Register"
|
|
bitfld.long 0x00 15. " OA2EN ,Own address 2 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--10. " OA2MSK[2:0] ,Own address 2 masks" "No mask,OA2[7:2] compared,OA2[7:3] compared,OA2[7:4] compared,OA2[7:5] compared,OA2[7:6] compared,OA2[7] compared,No comparison"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " OA2[7:1] ,Interface address"
|
|
endif
|
|
sif (cpuis("STM32F7*"))||(cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40005C00+0x00)&0x01)==0x00))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TIMINGR,Timing Register"
|
|
bitfld.long 0x00 28.--31. " PRESC ,Timing prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " SCLDEL ,Data setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " SDADEL ,Data hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCLH ,SCL high period"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " SCLL ,SCL low period"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TIMINGR,Timing Register"
|
|
bitfld.long 0x00 28.--31. " PRESC ,Timing prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " SCLDEL ,Data setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " SDADEL ,Data hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCLH ,SCL high period"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " SCLL ,SCL low period"
|
|
endif
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TIMINGR,Timing Register"
|
|
bitfld.long 0x00 28.--31. " PRESC ,Timing prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " SCLDEL ,Data setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " SDADEL ,Data hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCLH ,SCL high period"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " SCLL ,SCL low period"
|
|
endif
|
|
if ((per.l(ad:0x40005C00+0x14)&0x8000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TIMEOUTR,Timeout Register"
|
|
bitfld.long 0x00 31. " TEXTEN ,Extended clock timeout enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 16.--27. 1. " TIMEOUTB ,Bus timeout B"
|
|
bitfld.long 0x00 15. " TIMOUTEN ,Clock timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " TIDLE ,Idle clock timeout detection" "SCL low,SCL/SDA high"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. " TIMEOUTA ,Bus timeout A"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TIMEOUTR,Timeout Register"
|
|
bitfld.long 0x00 31. " TEXTEN ,Extended clock timeout enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 16.--27. 1. " TIMEOUTB ,Bus timeout B"
|
|
bitfld.long 0x00 15. " TIMOUTEN ,Clock timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. " TIDLE ,Idle clock timeout detection" "SCL low,SCL/SDA high"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. " TIMEOUTA ,Bus timeout A"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ISR,Interrupt And Status Register"
|
|
hexmask.long.byte 0x00 17.--23. 1. " ADDCODE ,Address match code"
|
|
rbitfld.long 0x00 16. " DIR ,Transfer direction" "Write,Read"
|
|
rbitfld.long 0x00 15. " BUSY ,Bus busy" "Idle,Busy"
|
|
rbitfld.long 0x00 13. " ALERT ,SMBus alert" "Not detected,Detected"
|
|
newline
|
|
rbitfld.long 0x00 12. " TIMEOUT ,Timeout or tLOW detection flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 11. " PECERR ,PEC error in reception" "No error,Error"
|
|
rbitfld.long 0x00 10. " OVR ,Overrun/Underrun" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 9. " ARLO ,Arbitration lost" "Not occurred,Occurred"
|
|
newline
|
|
rbitfld.long 0x00 8. " BERR ,Bus error" "No error,Error"
|
|
rbitfld.long 0x00 7. " TCR ,Transfer complete reload" "Not completed,Completed"
|
|
rbitfld.long 0x00 6. " TC ,Transfer complete" "Not completed,Completed"
|
|
rbitfld.long 0x00 5. " STOPF ,Stop detection flag" "Not detected,Detected"
|
|
newline
|
|
rbitfld.long 0x00 4. " NACKF ,Not acknowledge received flag" "Not received,Received"
|
|
rbitfld.long 0x00 3. " ADDR ,Address matched" "Not matched,Matched"
|
|
rbitfld.long 0x00 2. " RXNE ,Receive data register not empty" "No,Yes"
|
|
rbitfld.long 0x00 1. " TXIS ,Transmit interrupt status" "No interrupt,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 0. " TXE ,Transmit data register empty" "Not empty,Empty"
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x00 13. " ALERTCF ,Alert flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 12. " TIMOUTCF ,Timeout detection flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 11. " PECCF ,PEC error flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 10. " OVRCF ,Overrun/Underrun flag clear" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 9. " ARLOCF ,Arbitration lost flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " BERRCF ,Bus error flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 5. " STOPCF ,Stop detection flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " NACKCF ,Not acknowledge flag clear" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 3. " ADDRCF ,Address matched flag clear" "No effect,Clear"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "PECR,PEC Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PEC ,Packet error checking register"
|
|
sif (cpuis("STM32F7*"))
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "RXDR,Receive Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RXDATA ,8-bit receive data"
|
|
else
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "RXDR,Receive Data Register"
|
|
endif
|
|
if ((per.l(ad:0x40005C00+0x18)&0x01)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TXDR,Transmit Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,8-bit transmit data"
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "TXDR,Transmit Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,8-bit transmit data"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif !cpuis("STM32F72*")&&!cpuis("STM32F73*")
|
|
tree "I2C 4"
|
|
base ad:0x40006000
|
|
width 10.
|
|
if ((per.l(ad:0x40006000+0x00)&0x100000)==0x00)&&((per.l(ad:0x40006000+0x00)&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
newline
|
|
sif (!cpuis("STM32F7*"))
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40006000+0x00)&0x100000)==0x100000)&&((per.l(ad:0x40006000+0x00)&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
newline
|
|
sif (!cpuis("STM32F7*"))
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40006000+0x00)&0x100000)==0x00)&&((per.l(ad:0x40006000+0x00)&0x01)==0x01)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
newline
|
|
sif (!cpuis("STM32F7*"))
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
rbitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40006000+0x00)&0x100000)==0x100000)&&((per.l(ad:0x40006000+0x00)&0x01)==0x01)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
newline
|
|
sif (!cpuis("STM32F7*"))
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
rbitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40006000+0x04)&0x800)==0x00)&&((per.l(ad:0x40006000)&0x10000)==0x00))
|
|
if ((per.l(ad:0x40006000+0x04)&0x2000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes"
|
|
newline
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
sif cpuis("STM32F730I8")||cpuis("STM32F730R8")||cpuis("STM32F730V8")||cpuis("STM32F730Z8")||cpuis("STM32F750N8")||cpuis("STM32F750V8")||cpuis("STM32F750Z8")
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
newline
|
|
elif (!cpuis("STM32F72*")&&!cpuis("STM32F73*")&&!cpuis("STM32F76*")&&!cpuis("STM32F77*"))
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 0x01 " SADD ,Slave address bit 9:0"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes"
|
|
newline
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
sif cpuis("STM32F730I8")||cpuis("STM32F730R8")||cpuis("STM32F730V8")||cpuis("STM32F730Z8")
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
newline
|
|
elif (!cpuis("STM32F72*")&&!cpuis("STM32F73*")&&!cpuis("STM32F76*")&&!cpuis("STM32F77*"))
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 0x01 " SADD ,Slave address bit 9:0"
|
|
endif
|
|
elif (((per.l(ad:0x40006000+0x04)&0x800)==0x00)&&((per.l(ad:0x40006000)&0x10000)==0x10000))
|
|
if ((per.l(ad:0x40006000+0x04)&0x2000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes"
|
|
newline
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
newline
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
hexmask.long.word 0x00 0.--9. 0x01 " SADD ,Slave address bit 9:0"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes"
|
|
newline
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
newline
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
hexmask.long.word 0x00 0.--9. 0x01 " SADD ,Slave address bit 9:0"
|
|
endif
|
|
elif (((per.l(ad:0x40006000+0x04)&0x800)==0x800)&&((per.l(ad:0x40006000)&0x10000)==0x00))
|
|
if ((per.l(ad:0x40006000+0x04)&0x2000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes"
|
|
newline
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
sif (!cpuis("STM32F72*")&&!cpuis("STM32F73*")&&!cpuis("STM32F76*")&&!cpuis("STM32F77*"))
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 0x01 " SADD ,Slave address bit 9:0"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes"
|
|
newline
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
sif (!cpuis("STM32F72*")&&!cpuis("STM32F73*")&&!cpuis("STM32F76*")&&!cpuis("STM32F77*"))
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 0x01 " SADD ,Slave address bit 9:0"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40006000+0x04)&0x2000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes"
|
|
newline
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
newline
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
hexmask.long.word 0x00 0.--9. 0x01 " SADD ,Slave address bit 9:0"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes"
|
|
newline
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
newline
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
hexmask.long.word 0x00 0.--9. 0x01 " SADD ,Slave address bit 9:0"
|
|
endif
|
|
endif
|
|
if ((per.l(ad:0x40006000+0x08)&0x8000)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "OAR1,Own Address 1 Register"
|
|
bitfld.long 0x00 15. " OA1EN ,Own address 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OA1MODE ,Own address 1 10-bit mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 8.--9. " OA1[9:8] ,Interface address" "0,1,2,3"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " OA1[7:1] ,Interface address"
|
|
newline
|
|
bitfld.long 0x00 0. " OA1[0] ,Interface address" "0,1"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "OAR1,Own Address 1 Register"
|
|
bitfld.long 0x00 15. " OA1EN ,Own address 1 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " OA1MODE ,Own address 1 10-bit mode" "7-bit,10-bit"
|
|
rbitfld.long 0x00 8.--9. " OA1[9:8] ,Interface address" "0,1,2,3"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " OA1[7:1] ,Interface address"
|
|
newline
|
|
rbitfld.long 0x00 0. " OA1[0] ,Interface address" "0,1"
|
|
endif
|
|
if ((per.l(ad:0x40006000+0x0C)&0x8000)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "OAR2,Own Address 2 Register"
|
|
bitfld.long 0x00 15. " OA2EN ,Own address 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " OA2MSK[2:0] ,Own address 2 masks" "No mask,OA2[7:2] compared,OA2[7:3] compared,OA2[7:4] compared,OA2[7:5] compared,OA2[7:6] compared,OA2[7] compared,No comparison"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " OA2[7:1] ,Interface address"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "OAR2,Own Address 2 Register"
|
|
bitfld.long 0x00 15. " OA2EN ,Own address 2 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--10. " OA2MSK[2:0] ,Own address 2 masks" "No mask,OA2[7:2] compared,OA2[7:3] compared,OA2[7:4] compared,OA2[7:5] compared,OA2[7:6] compared,OA2[7] compared,No comparison"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " OA2[7:1] ,Interface address"
|
|
endif
|
|
sif (cpuis("STM32F7*"))||(cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40006000+0x00)&0x01)==0x00))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TIMINGR,Timing Register"
|
|
bitfld.long 0x00 28.--31. " PRESC ,Timing prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " SCLDEL ,Data setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " SDADEL ,Data hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCLH ,SCL high period"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " SCLL ,SCL low period"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TIMINGR,Timing Register"
|
|
bitfld.long 0x00 28.--31. " PRESC ,Timing prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " SCLDEL ,Data setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " SDADEL ,Data hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCLH ,SCL high period"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " SCLL ,SCL low period"
|
|
endif
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TIMINGR,Timing Register"
|
|
bitfld.long 0x00 28.--31. " PRESC ,Timing prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " SCLDEL ,Data setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " SDADEL ,Data hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCLH ,SCL high period"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " SCLL ,SCL low period"
|
|
endif
|
|
if ((per.l(ad:0x40006000+0x14)&0x8000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TIMEOUTR,Timeout Register"
|
|
bitfld.long 0x00 31. " TEXTEN ,Extended clock timeout enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 16.--27. 1. " TIMEOUTB ,Bus timeout B"
|
|
bitfld.long 0x00 15. " TIMOUTEN ,Clock timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " TIDLE ,Idle clock timeout detection" "SCL low,SCL/SDA high"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. " TIMEOUTA ,Bus timeout A"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TIMEOUTR,Timeout Register"
|
|
bitfld.long 0x00 31. " TEXTEN ,Extended clock timeout enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 16.--27. 1. " TIMEOUTB ,Bus timeout B"
|
|
bitfld.long 0x00 15. " TIMOUTEN ,Clock timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. " TIDLE ,Idle clock timeout detection" "SCL low,SCL/SDA high"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. " TIMEOUTA ,Bus timeout A"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ISR,Interrupt And Status Register"
|
|
hexmask.long.byte 0x00 17.--23. 1. " ADDCODE ,Address match code"
|
|
rbitfld.long 0x00 16. " DIR ,Transfer direction" "Write,Read"
|
|
rbitfld.long 0x00 15. " BUSY ,Bus busy" "Idle,Busy"
|
|
rbitfld.long 0x00 13. " ALERT ,SMBus alert" "Not detected,Detected"
|
|
newline
|
|
rbitfld.long 0x00 12. " TIMEOUT ,Timeout or tLOW detection flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 11. " PECERR ,PEC error in reception" "No error,Error"
|
|
rbitfld.long 0x00 10. " OVR ,Overrun/Underrun" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 9. " ARLO ,Arbitration lost" "Not occurred,Occurred"
|
|
newline
|
|
rbitfld.long 0x00 8. " BERR ,Bus error" "No error,Error"
|
|
rbitfld.long 0x00 7. " TCR ,Transfer complete reload" "Not completed,Completed"
|
|
rbitfld.long 0x00 6. " TC ,Transfer complete" "Not completed,Completed"
|
|
rbitfld.long 0x00 5. " STOPF ,Stop detection flag" "Not detected,Detected"
|
|
newline
|
|
rbitfld.long 0x00 4. " NACKF ,Not acknowledge received flag" "Not received,Received"
|
|
rbitfld.long 0x00 3. " ADDR ,Address matched" "Not matched,Matched"
|
|
rbitfld.long 0x00 2. " RXNE ,Receive data register not empty" "No,Yes"
|
|
rbitfld.long 0x00 1. " TXIS ,Transmit interrupt status" "No interrupt,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 0. " TXE ,Transmit data register empty" "Not empty,Empty"
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x00 13. " ALERTCF ,Alert flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 12. " TIMOUTCF ,Timeout detection flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 11. " PECCF ,PEC error flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 10. " OVRCF ,Overrun/Underrun flag clear" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 9. " ARLOCF ,Arbitration lost flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " BERRCF ,Bus error flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 5. " STOPCF ,Stop detection flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " NACKCF ,Not acknowledge flag clear" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 3. " ADDRCF ,Address matched flag clear" "No effect,Clear"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "PECR,PEC Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PEC ,Packet error checking register"
|
|
sif (cpuis("STM32F7*"))
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "RXDR,Receive Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RXDATA ,8-bit receive data"
|
|
else
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "RXDR,Receive Data Register"
|
|
endif
|
|
if ((per.l(ad:0x40006000+0x18)&0x01)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TXDR,Transmit Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,8-bit transmit data"
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "TXDR,Transmit Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,8-bit transmit data"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree.open "USART (Universal Synchronous Asynchronous Receiver Transmitter)"
|
|
tree "USART 1"
|
|
base ad:0x40011000
|
|
width 6.
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40011000))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
sif (cpuis("STM32F7*"))
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver enable de-assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
sif cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
else
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
sif (cpuis("STM32F7*"))
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 16.--20. " DEDT ,Driver enable de-assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
newline
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
sif cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
else
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40011000+0x08))&0x20)==0x20)
|
|
if (((per.l(ad:0x40011000))&0x20000000)==0x20000000)
|
|
if (((per.l(ad:0x40011000))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 31. " RXFFIE ,RXFIFO full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TXFEIE ,TXFIFO empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIFOEN ,FIFO mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
newline
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
newline
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 31. " RXFFIE ,RXFIFO full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TXFEIE ,TXFIFO empty interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " FIFOEN ,FIFO mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
newline
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
newline
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40011000))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 29. " FIFOEN ,FIFO mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
rbitfld.long 0x00 29. " FIFOEN ,FIFO mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40011000))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
newline
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40011000))&0x01)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
if (((per.l(ad:0x40011000))&0x04)==0x00)&&(((per.l(ad:0x40011000+0x04))&0x100000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
elif (((per.l(ad:0x40011000))&0x04)==0x00)&&(((per.l(ad:0x40011000+0x04))&0x100000)==0x100000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
elif (((per.l(ad:0x40011000))&0x04)==0x00)&&(((per.l(ad:0x40011000+0x04))&0x100000)==0x100000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40011000))&0x05)==(0x00||0x04))&&(((per.l(ad:0x40011000+0x04))&0x100000)==0x00)
|
|
if (((per.l(ad:0x40011000))&0x08)==0x08)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
elif ((((per.l(ad:0x40011000))&0x05)==0x05)&&(((per.l(ad:0x40011000+0x04))&0x100000)==0x100000))||((((per.l(ad:0x40011000))&0x05)==0x05)&&(((per.l(ad:0x40011000+0x04))&0x100000)==0x00))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
elif ((((per.l(ad:0x40011000))&0x05)==0x01)&&(((per.l(ad:0x40011000+0x04))&0x100000)==0x100000))||((((per.l(ad:0x40011000))&0x05)==0x01)&&(((per.l(ad:0x40011000+0x04))&0x100000)==0x00))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
elif ((((per.l(ad:0x40011000))&0x05)==(0x00||0x04))&&(((per.l(ad:0x40011000+0x04))&0x100000)==0x100000))
|
|
if (((per.l(ad:0x40011000))&0x08)==0x08)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40011000))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR3,Control Register 3"
|
|
sif cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F75*")||cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
bitfld.long 0x00 24. " TCBGTIE ,Transmission complete before guard time interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 23. " UCESM ,USART clock enable in stop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from low-power mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " WUS ,Wakeup from low-power mode interrupt flag selection" "Address match,,Start bit,RXNE/RXFNE"
|
|
newline
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low"
|
|
bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR3,ControL Register 3"
|
|
sif cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F75*")||cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
bitfld.long 0x00 24. " TCBGTIE ,Transmission complete before guard time interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 23. " UCESM ,USART clock enable in stop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from low-power mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " WUS ,Wakeup from low-power mode interrupt flag selection" "Address match,,Start bit,RXNE/RXFNE"
|
|
newline
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low"
|
|
rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
newline
|
|
rbitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40011000))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR3,Control Register 3"
|
|
bitfld.long 0x00 29.--31. " TXFTCFG ,TXFIFO threshold configuration" "1/8,1/4,1/2,3/4,7/8,Empty,?..."
|
|
bitfld.long 0x00 28. " RXFTIE ,RXFIFO threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--27. " RXFTCFG ,Receive FIFO threshold configuration" "1/8,1/4,1/2,3/4,7/8,Empty,?..."
|
|
bitfld.long 0x00 24. " TCBGTIE ,Transmission complete before guard time interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " TXFTIE ,TXFIFO threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from low-power mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " WUS ,Wakeup from low-power mode interrupt flag selection" "Address match,,Start bit,RXNE/RXFNE"
|
|
newline
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low"
|
|
bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
bitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR3,Control Register 3"
|
|
bitfld.long 0x00 29.--31. " TXFTCFG ,TXFIFO threshold configuration" "1/8,1/4,1/2,3/4,7/8,Empty,?..."
|
|
bitfld.long 0x00 28. " RXFTIE ,RXFIFO threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--27. " RXFTCFG ,Receive FIFO threshold configuration" "1/8,1/4,1/2,3/4,7/8,Empty,?..."
|
|
bitfld.long 0x00 24. " TCBGTIE ,Transmission complete before guard time interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " TXFTIE ,TXFIFO threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from low-power mode interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20.--21. " WUS ,Wakeup from low-power mode interrupt flag selection" "Address match,,Start bit,RXNE/RXFNE"
|
|
newline
|
|
rbitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low"
|
|
rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
rbitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
newline
|
|
rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
sif (cpuis("STM32F7*"))
|
|
if (((per.l((ad:0x40011000)))&0x8001)==0x8000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l((ad:0x40011000)))&0x8001)==0x8001)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l((ad:0x40011000)))&0x8001)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR[3:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR[2:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40011000))&0x01)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR[15:4] ,BRR[15:4]"
|
|
bitfld.long 0x00 0.--3. " [3:0] ,BRR[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR[15:4] ,BRR[15:4]"
|
|
bitfld.long 0x00 0.--3. " [3:0] ,BRR[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40011000))&0x01)==0x00)
|
|
if (((per.l((ad:0x40011000+0x08)))&0x20)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "GTPR,Guard Time And Prescaler Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "GTPR,Guard Time And Prescaler Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
bitfld.long 0x00 0.--4. " PSC ,Prescaler value" ",2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62"
|
|
endif
|
|
else
|
|
if (((per.l((ad:0x40011000+0x08)))&0x20)==0x00)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GTPR,Guard Time And Prescaler Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GTPR,Guard Time And Prescaler Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
bitfld.long 0x00 0.--4. " PSC ,Prescaler value" ",2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62"
|
|
endif
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTOR,Receiver Timeout Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BLEN ,Block length"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " RTO ,Receiver timeout value"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "RQR,Request Register"
|
|
sif (cpuis("STM32F7*"))
|
|
bitfld.long 0x00 4. " TXFRQ ,Transmit data flush request" "No effect,Flush"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 4. " TXFRQ ,Transmit data flush request" "No effect,Flush"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 3. " RXFRQ ,Receive data flush request" "No effect,Flush"
|
|
bitfld.long 0x00 2. " MMRQ ,Mute mode request" "No effect,Mute"
|
|
bitfld.long 0x00 1. " SBKRQ ,Send break request" "No effect,Break"
|
|
bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "No effect,Request"
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40011000+0x08))&0x20)==0x20)
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ISR,Interrupt And Status Register"
|
|
bitfld.long 0x00 27. " TXFT ,TXFIFO threshold flag" "Not reached,Reached"
|
|
bitfld.long 0x00 26. " RXFT ,RXFIFO threshold flag" "Not reached,Reached"
|
|
bitfld.long 0x00 25. " TCBGT ,Transmission complete before guard time flag" "Not completed,Completed"
|
|
bitfld.long 0x00 24. " RXFF ,RXFIFO full" "Not full,Full"
|
|
newline
|
|
bitfld.long 0x00 23. " TXFE ,TXFIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 18. " SBKF ,Send break flag" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy"
|
|
bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "Completed,In progress"
|
|
bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error"
|
|
bitfld.long 0x00 12. " EOBF ,End of block flag" "Not ended,Ended"
|
|
newline
|
|
bitfld.long 0x00 11. " RTOF ,Receiver timeout" "No timeout,Timeout"
|
|
bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset"
|
|
bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " LBDF ,LIN break detection flag" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not empty,Empty"
|
|
bitfld.long 0x00 6. " TC ,Transmission complete" "Not complete,Complete"
|
|
bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes"
|
|
bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error"
|
|
bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " FE ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 0. " PE ,Parity error" "No error,Error"
|
|
else
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ISR,Interrupt And Status Register"
|
|
bitfld.long 0x00 27. " TXFT ,TXFIFO threshold flag" "Not reached,Reached"
|
|
bitfld.long 0x00 26. " RXFT ,RXFIFO threshold flag" "Not reached,Reached"
|
|
bitfld.long 0x00 24. " RXFF ,RXFIFO full" "Not full,Full"
|
|
bitfld.long 0x00 23. " TXFE ,TXFIFO empty" "Not empty,Empty"
|
|
newline
|
|
bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 18. " SBKF ,Send break flag" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy"
|
|
newline
|
|
bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "Completed,In progress"
|
|
bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error"
|
|
bitfld.long 0x00 12. " EOBF ,End of block flag" "Not ended,Ended"
|
|
bitfld.long 0x00 11. " RTOF ,Receiver timeout" "No timeout,Timeout"
|
|
newline
|
|
bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset"
|
|
bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " LBDF ,LIN break detection flag" "Not detected,Detected"
|
|
bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not empty,Empty"
|
|
newline
|
|
bitfld.long 0x00 6. " TC ,Transmission complete" "Not complete,Complete"
|
|
bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes"
|
|
bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected"
|
|
bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " FE ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 0. " PE ,Parity error" "No error,Error"
|
|
endif
|
|
else
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ISR,Interrupt And Status Register"
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 25. " TCBGT ,Transmission complete before guard time flag" "Not completed,Completed"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 22. " REACK ,Receive enable acknowledge flag" "Not acknowledged,Acknowledged"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Not acknowledged,Acknowledged"
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 20. " WUF ,Wakeup from stop mode flag" "Not occurred,Occurred"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 19. " RWU ,Receiver wakeup from mute mode" "Active mode,Mute mode"
|
|
bitfld.long 0x00 18. " SBKF ,Send break flag" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy"
|
|
newline
|
|
bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "Completed,In progress"
|
|
bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error"
|
|
newline
|
|
sif cpuis("STM32F7*")
|
|
bitfld.long 0x00 12. " EOBF ,End of block flag" "Not ended,Ended"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 11. " RTOF ,Receiver timeout" "No timeout,Timeout"
|
|
bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset"
|
|
bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " LBDF ,LIN break detection flag" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not empty,Empty"
|
|
bitfld.long 0x00 6. " TC ,Transmission complete" "Not complete,Complete"
|
|
bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes"
|
|
bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error"
|
|
bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " FE ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 0. " PE ,Parity error" "No error,Error"
|
|
endif
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "ICR,Interrupt Flag Clear Register"
|
|
bitfld.long 0x00 20. " WUCF ,Wakeup from low-power mode clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 13. " UDRCF ,SPI slave underrun clear flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 12. " EOBCF ,End of timeout clear flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 8. " LBDCF ,LIN break detection clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 7. " TCBGTCF ,Transmission complete before guard time clear flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 5. " TXFECF ,TXFIFO empty clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 2. " NECF ,Noise detected clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Clear"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ICR,Interrupt Flag Clear Register"
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
eventfld.long 0x00 20. " WUCF ,Wakeup from stop mode clear flag" "No effect,Clear"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 12. " EOBCF ,End of timeout clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear"
|
|
newline
|
|
eventfld.long 0x00 8. " LBDCF ,LIN break detection clear flag" "No effect,Clear"
|
|
sif (!cpuis("STM32F74*")&&!cpuis("STM32F75*"))
|
|
eventfld.long 0x00 7. " TCBGTCF ,Transmission complete before guard time clear flag" "No effect,Clear"
|
|
endif
|
|
newline
|
|
eventfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Clear"
|
|
newline
|
|
eventfld.long 0x00 2. " NCF ,Noise detected clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Clear"
|
|
endif
|
|
newline
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "RDR,Receive Data Register"
|
|
in
|
|
newline
|
|
if (((per.l(ad:0x40011000))&0x80)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TDR,Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value"
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "TDR,Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value"
|
|
endif
|
|
width 7.
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40011000))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PRESC,Prescaler Register"
|
|
bitfld.long 0x00 0.--3. " PRESCALER ,Clock prescaler" "Not divided,/2,/4,/6,/8,/10,/12,/16,/32,/64,/128,/256,?..."
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "PRESC,Prescaler Register"
|
|
bitfld.long 0x00 0.--3. " PRESCALER ,Clock prescaler" "Not divided,/2,/4,/6,/8,/10,/12,/16,/32,/64,/128,/256,?..."
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "USART 2"
|
|
base ad:0x40004400
|
|
width 6.
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40004400))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
sif (cpuis("STM32F7*"))
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver enable de-assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
sif cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
else
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
sif (cpuis("STM32F7*"))
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 16.--20. " DEDT ,Driver enable de-assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
newline
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
sif cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
else
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40004400+0x08))&0x20)==0x20)
|
|
if (((per.l(ad:0x40004400))&0x20000000)==0x20000000)
|
|
if (((per.l(ad:0x40004400))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 31. " RXFFIE ,RXFIFO full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TXFEIE ,TXFIFO empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIFOEN ,FIFO mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
newline
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
newline
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 31. " RXFFIE ,RXFIFO full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TXFEIE ,TXFIFO empty interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " FIFOEN ,FIFO mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
newline
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
newline
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40004400))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 29. " FIFOEN ,FIFO mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
rbitfld.long 0x00 29. " FIFOEN ,FIFO mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40004400))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
newline
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40004400))&0x01)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
if (((per.l(ad:0x40004400))&0x04)==0x00)&&(((per.l(ad:0x40004400+0x04))&0x100000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
elif (((per.l(ad:0x40004400))&0x04)==0x00)&&(((per.l(ad:0x40004400+0x04))&0x100000)==0x100000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
elif (((per.l(ad:0x40004400))&0x04)==0x00)&&(((per.l(ad:0x40004400+0x04))&0x100000)==0x100000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40004400))&0x05)==(0x00||0x04))&&(((per.l(ad:0x40004400+0x04))&0x100000)==0x00)
|
|
if (((per.l(ad:0x40004400))&0x08)==0x08)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
elif ((((per.l(ad:0x40004400))&0x05)==0x05)&&(((per.l(ad:0x40004400+0x04))&0x100000)==0x100000))||((((per.l(ad:0x40004400))&0x05)==0x05)&&(((per.l(ad:0x40004400+0x04))&0x100000)==0x00))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
elif ((((per.l(ad:0x40004400))&0x05)==0x01)&&(((per.l(ad:0x40004400+0x04))&0x100000)==0x100000))||((((per.l(ad:0x40004400))&0x05)==0x01)&&(((per.l(ad:0x40004400+0x04))&0x100000)==0x00))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
elif ((((per.l(ad:0x40004400))&0x05)==(0x00||0x04))&&(((per.l(ad:0x40004400+0x04))&0x100000)==0x100000))
|
|
if (((per.l(ad:0x40004400))&0x08)==0x08)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40004400))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR3,Control Register 3"
|
|
sif cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F75*")||cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
bitfld.long 0x00 24. " TCBGTIE ,Transmission complete before guard time interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 23. " UCESM ,USART clock enable in stop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from low-power mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " WUS ,Wakeup from low-power mode interrupt flag selection" "Address match,,Start bit,RXNE/RXFNE"
|
|
newline
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low"
|
|
bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR3,ControL Register 3"
|
|
sif cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F75*")||cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
bitfld.long 0x00 24. " TCBGTIE ,Transmission complete before guard time interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 23. " UCESM ,USART clock enable in stop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from low-power mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " WUS ,Wakeup from low-power mode interrupt flag selection" "Address match,,Start bit,RXNE/RXFNE"
|
|
newline
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low"
|
|
rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
newline
|
|
rbitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40004400))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR3,Control Register 3"
|
|
bitfld.long 0x00 29.--31. " TXFTCFG ,TXFIFO threshold configuration" "1/8,1/4,1/2,3/4,7/8,Empty,?..."
|
|
bitfld.long 0x00 28. " RXFTIE ,RXFIFO threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--27. " RXFTCFG ,Receive FIFO threshold configuration" "1/8,1/4,1/2,3/4,7/8,Empty,?..."
|
|
bitfld.long 0x00 24. " TCBGTIE ,Transmission complete before guard time interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " TXFTIE ,TXFIFO threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from low-power mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " WUS ,Wakeup from low-power mode interrupt flag selection" "Address match,,Start bit,RXNE/RXFNE"
|
|
newline
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low"
|
|
bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
bitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR3,Control Register 3"
|
|
bitfld.long 0x00 29.--31. " TXFTCFG ,TXFIFO threshold configuration" "1/8,1/4,1/2,3/4,7/8,Empty,?..."
|
|
bitfld.long 0x00 28. " RXFTIE ,RXFIFO threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--27. " RXFTCFG ,Receive FIFO threshold configuration" "1/8,1/4,1/2,3/4,7/8,Empty,?..."
|
|
bitfld.long 0x00 24. " TCBGTIE ,Transmission complete before guard time interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " TXFTIE ,TXFIFO threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from low-power mode interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20.--21. " WUS ,Wakeup from low-power mode interrupt flag selection" "Address match,,Start bit,RXNE/RXFNE"
|
|
newline
|
|
rbitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low"
|
|
rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
rbitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
newline
|
|
rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
sif (cpuis("STM32F7*"))
|
|
if (((per.l((ad:0x40004400)))&0x8001)==0x8000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l((ad:0x40004400)))&0x8001)==0x8001)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l((ad:0x40004400)))&0x8001)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR[3:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR[2:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40004400))&0x01)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR[15:4] ,BRR[15:4]"
|
|
bitfld.long 0x00 0.--3. " [3:0] ,BRR[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR[15:4] ,BRR[15:4]"
|
|
bitfld.long 0x00 0.--3. " [3:0] ,BRR[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40004400))&0x01)==0x00)
|
|
if (((per.l((ad:0x40004400+0x08)))&0x20)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "GTPR,Guard Time And Prescaler Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "GTPR,Guard Time And Prescaler Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
bitfld.long 0x00 0.--4. " PSC ,Prescaler value" ",2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62"
|
|
endif
|
|
else
|
|
if (((per.l((ad:0x40004400+0x08)))&0x20)==0x00)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GTPR,Guard Time And Prescaler Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GTPR,Guard Time And Prescaler Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
bitfld.long 0x00 0.--4. " PSC ,Prescaler value" ",2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62"
|
|
endif
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTOR,Receiver Timeout Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BLEN ,Block length"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " RTO ,Receiver timeout value"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "RQR,Request Register"
|
|
sif (cpuis("STM32F7*"))
|
|
bitfld.long 0x00 4. " TXFRQ ,Transmit data flush request" "No effect,Flush"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 4. " TXFRQ ,Transmit data flush request" "No effect,Flush"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 3. " RXFRQ ,Receive data flush request" "No effect,Flush"
|
|
bitfld.long 0x00 2. " MMRQ ,Mute mode request" "No effect,Mute"
|
|
bitfld.long 0x00 1. " SBKRQ ,Send break request" "No effect,Break"
|
|
bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "No effect,Request"
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40004400+0x08))&0x20)==0x20)
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ISR,Interrupt And Status Register"
|
|
bitfld.long 0x00 27. " TXFT ,TXFIFO threshold flag" "Not reached,Reached"
|
|
bitfld.long 0x00 26. " RXFT ,RXFIFO threshold flag" "Not reached,Reached"
|
|
bitfld.long 0x00 25. " TCBGT ,Transmission complete before guard time flag" "Not completed,Completed"
|
|
bitfld.long 0x00 24. " RXFF ,RXFIFO full" "Not full,Full"
|
|
newline
|
|
bitfld.long 0x00 23. " TXFE ,TXFIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 18. " SBKF ,Send break flag" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy"
|
|
bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "Completed,In progress"
|
|
bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error"
|
|
bitfld.long 0x00 12. " EOBF ,End of block flag" "Not ended,Ended"
|
|
newline
|
|
bitfld.long 0x00 11. " RTOF ,Receiver timeout" "No timeout,Timeout"
|
|
bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset"
|
|
bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " LBDF ,LIN break detection flag" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not empty,Empty"
|
|
bitfld.long 0x00 6. " TC ,Transmission complete" "Not complete,Complete"
|
|
bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes"
|
|
bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error"
|
|
bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " FE ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 0. " PE ,Parity error" "No error,Error"
|
|
else
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ISR,Interrupt And Status Register"
|
|
bitfld.long 0x00 27. " TXFT ,TXFIFO threshold flag" "Not reached,Reached"
|
|
bitfld.long 0x00 26. " RXFT ,RXFIFO threshold flag" "Not reached,Reached"
|
|
bitfld.long 0x00 24. " RXFF ,RXFIFO full" "Not full,Full"
|
|
bitfld.long 0x00 23. " TXFE ,TXFIFO empty" "Not empty,Empty"
|
|
newline
|
|
bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 18. " SBKF ,Send break flag" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy"
|
|
newline
|
|
bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "Completed,In progress"
|
|
bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error"
|
|
bitfld.long 0x00 12. " EOBF ,End of block flag" "Not ended,Ended"
|
|
bitfld.long 0x00 11. " RTOF ,Receiver timeout" "No timeout,Timeout"
|
|
newline
|
|
bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset"
|
|
bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " LBDF ,LIN break detection flag" "Not detected,Detected"
|
|
bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not empty,Empty"
|
|
newline
|
|
bitfld.long 0x00 6. " TC ,Transmission complete" "Not complete,Complete"
|
|
bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes"
|
|
bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected"
|
|
bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " FE ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 0. " PE ,Parity error" "No error,Error"
|
|
endif
|
|
else
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ISR,Interrupt And Status Register"
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 25. " TCBGT ,Transmission complete before guard time flag" "Not completed,Completed"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 22. " REACK ,Receive enable acknowledge flag" "Not acknowledged,Acknowledged"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Not acknowledged,Acknowledged"
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 20. " WUF ,Wakeup from stop mode flag" "Not occurred,Occurred"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 19. " RWU ,Receiver wakeup from mute mode" "Active mode,Mute mode"
|
|
bitfld.long 0x00 18. " SBKF ,Send break flag" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy"
|
|
newline
|
|
bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "Completed,In progress"
|
|
bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error"
|
|
newline
|
|
sif cpuis("STM32F7*")
|
|
bitfld.long 0x00 12. " EOBF ,End of block flag" "Not ended,Ended"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 11. " RTOF ,Receiver timeout" "No timeout,Timeout"
|
|
bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset"
|
|
bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " LBDF ,LIN break detection flag" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not empty,Empty"
|
|
bitfld.long 0x00 6. " TC ,Transmission complete" "Not complete,Complete"
|
|
bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes"
|
|
bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error"
|
|
bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " FE ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 0. " PE ,Parity error" "No error,Error"
|
|
endif
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "ICR,Interrupt Flag Clear Register"
|
|
bitfld.long 0x00 20. " WUCF ,Wakeup from low-power mode clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 13. " UDRCF ,SPI slave underrun clear flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 12. " EOBCF ,End of timeout clear flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 8. " LBDCF ,LIN break detection clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 7. " TCBGTCF ,Transmission complete before guard time clear flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 5. " TXFECF ,TXFIFO empty clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 2. " NECF ,Noise detected clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Clear"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ICR,Interrupt Flag Clear Register"
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
eventfld.long 0x00 20. " WUCF ,Wakeup from stop mode clear flag" "No effect,Clear"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 12. " EOBCF ,End of timeout clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear"
|
|
newline
|
|
eventfld.long 0x00 8. " LBDCF ,LIN break detection clear flag" "No effect,Clear"
|
|
sif (!cpuis("STM32F74*")&&!cpuis("STM32F75*"))
|
|
eventfld.long 0x00 7. " TCBGTCF ,Transmission complete before guard time clear flag" "No effect,Clear"
|
|
endif
|
|
newline
|
|
eventfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Clear"
|
|
newline
|
|
eventfld.long 0x00 2. " NCF ,Noise detected clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Clear"
|
|
endif
|
|
newline
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "RDR,Receive Data Register"
|
|
in
|
|
newline
|
|
if (((per.l(ad:0x40004400))&0x80)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TDR,Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value"
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "TDR,Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value"
|
|
endif
|
|
width 7.
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40004400))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PRESC,Prescaler Register"
|
|
bitfld.long 0x00 0.--3. " PRESCALER ,Clock prescaler" "Not divided,/2,/4,/6,/8,/10,/12,/16,/32,/64,/128,/256,?..."
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "PRESC,Prescaler Register"
|
|
bitfld.long 0x00 0.--3. " PRESCALER ,Clock prescaler" "Not divided,/2,/4,/6,/8,/10,/12,/16,/32,/64,/128,/256,?..."
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "USART 3"
|
|
base ad:0x40004800
|
|
width 6.
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40004800))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
sif (cpuis("STM32F7*"))
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver enable de-assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
sif cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
else
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
sif (cpuis("STM32F7*"))
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 16.--20. " DEDT ,Driver enable de-assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
newline
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
sif cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
else
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40004800+0x08))&0x20)==0x20)
|
|
if (((per.l(ad:0x40004800))&0x20000000)==0x20000000)
|
|
if (((per.l(ad:0x40004800))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 31. " RXFFIE ,RXFIFO full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TXFEIE ,TXFIFO empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIFOEN ,FIFO mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
newline
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
newline
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 31. " RXFFIE ,RXFIFO full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TXFEIE ,TXFIFO empty interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " FIFOEN ,FIFO mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
newline
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
newline
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40004800))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 29. " FIFOEN ,FIFO mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
rbitfld.long 0x00 29. " FIFOEN ,FIFO mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40004800))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
newline
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40004800))&0x01)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
if (((per.l(ad:0x40004800))&0x04)==0x00)&&(((per.l(ad:0x40004800+0x04))&0x100000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
elif (((per.l(ad:0x40004800))&0x04)==0x00)&&(((per.l(ad:0x40004800+0x04))&0x100000)==0x100000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
elif (((per.l(ad:0x40004800))&0x04)==0x00)&&(((per.l(ad:0x40004800+0x04))&0x100000)==0x100000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40004800))&0x05)==(0x00||0x04))&&(((per.l(ad:0x40004800+0x04))&0x100000)==0x00)
|
|
if (((per.l(ad:0x40004800))&0x08)==0x08)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
elif ((((per.l(ad:0x40004800))&0x05)==0x05)&&(((per.l(ad:0x40004800+0x04))&0x100000)==0x100000))||((((per.l(ad:0x40004800))&0x05)==0x05)&&(((per.l(ad:0x40004800+0x04))&0x100000)==0x00))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
elif ((((per.l(ad:0x40004800))&0x05)==0x01)&&(((per.l(ad:0x40004800+0x04))&0x100000)==0x100000))||((((per.l(ad:0x40004800))&0x05)==0x01)&&(((per.l(ad:0x40004800+0x04))&0x100000)==0x00))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
elif ((((per.l(ad:0x40004800))&0x05)==(0x00||0x04))&&(((per.l(ad:0x40004800+0x04))&0x100000)==0x100000))
|
|
if (((per.l(ad:0x40004800))&0x08)==0x08)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40004800))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR3,Control Register 3"
|
|
sif cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F75*")||cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
bitfld.long 0x00 24. " TCBGTIE ,Transmission complete before guard time interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 23. " UCESM ,USART clock enable in stop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from low-power mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " WUS ,Wakeup from low-power mode interrupt flag selection" "Address match,,Start bit,RXNE/RXFNE"
|
|
newline
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low"
|
|
bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR3,ControL Register 3"
|
|
sif cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F75*")||cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
bitfld.long 0x00 24. " TCBGTIE ,Transmission complete before guard time interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 23. " UCESM ,USART clock enable in stop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from low-power mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " WUS ,Wakeup from low-power mode interrupt flag selection" "Address match,,Start bit,RXNE/RXFNE"
|
|
newline
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low"
|
|
rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
newline
|
|
rbitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40004800))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR3,Control Register 3"
|
|
bitfld.long 0x00 29.--31. " TXFTCFG ,TXFIFO threshold configuration" "1/8,1/4,1/2,3/4,7/8,Empty,?..."
|
|
bitfld.long 0x00 28. " RXFTIE ,RXFIFO threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--27. " RXFTCFG ,Receive FIFO threshold configuration" "1/8,1/4,1/2,3/4,7/8,Empty,?..."
|
|
bitfld.long 0x00 24. " TCBGTIE ,Transmission complete before guard time interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " TXFTIE ,TXFIFO threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from low-power mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " WUS ,Wakeup from low-power mode interrupt flag selection" "Address match,,Start bit,RXNE/RXFNE"
|
|
newline
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low"
|
|
bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
bitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR3,Control Register 3"
|
|
bitfld.long 0x00 29.--31. " TXFTCFG ,TXFIFO threshold configuration" "1/8,1/4,1/2,3/4,7/8,Empty,?..."
|
|
bitfld.long 0x00 28. " RXFTIE ,RXFIFO threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--27. " RXFTCFG ,Receive FIFO threshold configuration" "1/8,1/4,1/2,3/4,7/8,Empty,?..."
|
|
bitfld.long 0x00 24. " TCBGTIE ,Transmission complete before guard time interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " TXFTIE ,TXFIFO threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from low-power mode interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20.--21. " WUS ,Wakeup from low-power mode interrupt flag selection" "Address match,,Start bit,RXNE/RXFNE"
|
|
newline
|
|
rbitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low"
|
|
rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
rbitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
newline
|
|
rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
sif (cpuis("STM32F7*"))
|
|
if (((per.l((ad:0x40004800)))&0x8001)==0x8000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l((ad:0x40004800)))&0x8001)==0x8001)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l((ad:0x40004800)))&0x8001)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR[3:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR[2:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40004800))&0x01)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR[15:4] ,BRR[15:4]"
|
|
bitfld.long 0x00 0.--3. " [3:0] ,BRR[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR[15:4] ,BRR[15:4]"
|
|
bitfld.long 0x00 0.--3. " [3:0] ,BRR[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40004800))&0x01)==0x00)
|
|
if (((per.l((ad:0x40004800+0x08)))&0x20)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "GTPR,Guard Time And Prescaler Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "GTPR,Guard Time And Prescaler Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
bitfld.long 0x00 0.--4. " PSC ,Prescaler value" ",2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62"
|
|
endif
|
|
else
|
|
if (((per.l((ad:0x40004800+0x08)))&0x20)==0x00)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GTPR,Guard Time And Prescaler Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GTPR,Guard Time And Prescaler Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
bitfld.long 0x00 0.--4. " PSC ,Prescaler value" ",2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62"
|
|
endif
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTOR,Receiver Timeout Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BLEN ,Block length"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " RTO ,Receiver timeout value"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "RQR,Request Register"
|
|
sif (cpuis("STM32F7*"))
|
|
bitfld.long 0x00 4. " TXFRQ ,Transmit data flush request" "No effect,Flush"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 4. " TXFRQ ,Transmit data flush request" "No effect,Flush"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 3. " RXFRQ ,Receive data flush request" "No effect,Flush"
|
|
bitfld.long 0x00 2. " MMRQ ,Mute mode request" "No effect,Mute"
|
|
bitfld.long 0x00 1. " SBKRQ ,Send break request" "No effect,Break"
|
|
bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "No effect,Request"
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40004800+0x08))&0x20)==0x20)
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ISR,Interrupt And Status Register"
|
|
bitfld.long 0x00 27. " TXFT ,TXFIFO threshold flag" "Not reached,Reached"
|
|
bitfld.long 0x00 26. " RXFT ,RXFIFO threshold flag" "Not reached,Reached"
|
|
bitfld.long 0x00 25. " TCBGT ,Transmission complete before guard time flag" "Not completed,Completed"
|
|
bitfld.long 0x00 24. " RXFF ,RXFIFO full" "Not full,Full"
|
|
newline
|
|
bitfld.long 0x00 23. " TXFE ,TXFIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 18. " SBKF ,Send break flag" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy"
|
|
bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "Completed,In progress"
|
|
bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error"
|
|
bitfld.long 0x00 12. " EOBF ,End of block flag" "Not ended,Ended"
|
|
newline
|
|
bitfld.long 0x00 11. " RTOF ,Receiver timeout" "No timeout,Timeout"
|
|
bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset"
|
|
bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " LBDF ,LIN break detection flag" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not empty,Empty"
|
|
bitfld.long 0x00 6. " TC ,Transmission complete" "Not complete,Complete"
|
|
bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes"
|
|
bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error"
|
|
bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " FE ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 0. " PE ,Parity error" "No error,Error"
|
|
else
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ISR,Interrupt And Status Register"
|
|
bitfld.long 0x00 27. " TXFT ,TXFIFO threshold flag" "Not reached,Reached"
|
|
bitfld.long 0x00 26. " RXFT ,RXFIFO threshold flag" "Not reached,Reached"
|
|
bitfld.long 0x00 24. " RXFF ,RXFIFO full" "Not full,Full"
|
|
bitfld.long 0x00 23. " TXFE ,TXFIFO empty" "Not empty,Empty"
|
|
newline
|
|
bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 18. " SBKF ,Send break flag" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy"
|
|
newline
|
|
bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "Completed,In progress"
|
|
bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error"
|
|
bitfld.long 0x00 12. " EOBF ,End of block flag" "Not ended,Ended"
|
|
bitfld.long 0x00 11. " RTOF ,Receiver timeout" "No timeout,Timeout"
|
|
newline
|
|
bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset"
|
|
bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " LBDF ,LIN break detection flag" "Not detected,Detected"
|
|
bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not empty,Empty"
|
|
newline
|
|
bitfld.long 0x00 6. " TC ,Transmission complete" "Not complete,Complete"
|
|
bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes"
|
|
bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected"
|
|
bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " FE ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 0. " PE ,Parity error" "No error,Error"
|
|
endif
|
|
else
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ISR,Interrupt And Status Register"
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 25. " TCBGT ,Transmission complete before guard time flag" "Not completed,Completed"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 22. " REACK ,Receive enable acknowledge flag" "Not acknowledged,Acknowledged"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Not acknowledged,Acknowledged"
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 20. " WUF ,Wakeup from stop mode flag" "Not occurred,Occurred"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 19. " RWU ,Receiver wakeup from mute mode" "Active mode,Mute mode"
|
|
bitfld.long 0x00 18. " SBKF ,Send break flag" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy"
|
|
newline
|
|
bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "Completed,In progress"
|
|
bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error"
|
|
newline
|
|
sif cpuis("STM32F7*")
|
|
bitfld.long 0x00 12. " EOBF ,End of block flag" "Not ended,Ended"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 11. " RTOF ,Receiver timeout" "No timeout,Timeout"
|
|
bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset"
|
|
bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " LBDF ,LIN break detection flag" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not empty,Empty"
|
|
bitfld.long 0x00 6. " TC ,Transmission complete" "Not complete,Complete"
|
|
bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes"
|
|
bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error"
|
|
bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " FE ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 0. " PE ,Parity error" "No error,Error"
|
|
endif
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "ICR,Interrupt Flag Clear Register"
|
|
bitfld.long 0x00 20. " WUCF ,Wakeup from low-power mode clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 13. " UDRCF ,SPI slave underrun clear flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 12. " EOBCF ,End of timeout clear flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 8. " LBDCF ,LIN break detection clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 7. " TCBGTCF ,Transmission complete before guard time clear flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 5. " TXFECF ,TXFIFO empty clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 2. " NECF ,Noise detected clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Clear"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ICR,Interrupt Flag Clear Register"
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
eventfld.long 0x00 20. " WUCF ,Wakeup from stop mode clear flag" "No effect,Clear"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 12. " EOBCF ,End of timeout clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear"
|
|
newline
|
|
eventfld.long 0x00 8. " LBDCF ,LIN break detection clear flag" "No effect,Clear"
|
|
sif (!cpuis("STM32F74*")&&!cpuis("STM32F75*"))
|
|
eventfld.long 0x00 7. " TCBGTCF ,Transmission complete before guard time clear flag" "No effect,Clear"
|
|
endif
|
|
newline
|
|
eventfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Clear"
|
|
newline
|
|
eventfld.long 0x00 2. " NCF ,Noise detected clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Clear"
|
|
endif
|
|
newline
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "RDR,Receive Data Register"
|
|
in
|
|
newline
|
|
if (((per.l(ad:0x40004800))&0x80)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TDR,Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value"
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "TDR,Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value"
|
|
endif
|
|
width 7.
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40004800))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PRESC,Prescaler Register"
|
|
bitfld.long 0x00 0.--3. " PRESCALER ,Clock prescaler" "Not divided,/2,/4,/6,/8,/10,/12,/16,/32,/64,/128,/256,?..."
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "PRESC,Prescaler Register"
|
|
bitfld.long 0x00 0.--3. " PRESCALER ,Clock prescaler" "Not divided,/2,/4,/6,/8,/10,/12,/16,/32,/64,/128,/256,?..."
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART 4"
|
|
base ad:0x40004C00
|
|
width 6.
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40004C00))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
sif (cpuis("STM32F7*"))
|
|
else
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver enable de-assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
sif cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
else
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
sif (cpuis("STM32F7*"))
|
|
else
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 16.--20. " DEDT ,Driver enable de-assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
newline
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
sif cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
else
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40004C00+0x08))&0x02)==0x02)||(((per.l(ad:0x40004C00+0x04))&0x4000)==0x4000)
|
|
if (((per.l(ad:0x40004C00))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
newline
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40004C00))&0x20000000)==0x20000000)
|
|
if (((per.l(ad:0x40004C00))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 31. " RXFFIE ,RXFIFO full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TXFEIE ,TXFIFO empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIFOEN ,FIFO mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
newline
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
newline
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 31. " RXFFIE ,RXFIFO full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TXFEIE ,TXFIFO empty interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " FIFOEN ,FIFO mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
newline
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
newline
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40004C00))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 29. " FIFOEN ,FIFO mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
rbitfld.long 0x00 29. " FIFOEN ,FIFO mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
endif
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40004C00))&0x01)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
if (((per.l(ad:0x40004C00))&0x04)==0x00)&&(((per.l(ad:0x40004C00+0x04))&0x100000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
elif (((per.l(ad:0x40004C00))&0x04)==0x00)&&(((per.l(ad:0x40004C00+0x04))&0x100000)==0x100000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
elif (((per.l(ad:0x40004C00))&0x04)==0x00)&&(((per.l(ad:0x40004C00+0x04))&0x100000)==0x100000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40004C00))&0x05)==(0x00||0x04))&&(((per.l(ad:0x40004C00+0x04))&0x100000)==0x00)
|
|
if (((per.l(ad:0x40004C00))&0x08)==0x08)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
elif ((((per.l(ad:0x40004C00))&0x05)==0x05)&&(((per.l(ad:0x40004C00+0x04))&0x100000)==0x100000))||((((per.l(ad:0x40004C00))&0x05)==0x05)&&(((per.l(ad:0x40004C00+0x04))&0x100000)==0x00))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
elif ((((per.l(ad:0x40004C00))&0x05)==0x01)&&(((per.l(ad:0x40004C00+0x04))&0x100000)==0x100000))||((((per.l(ad:0x40004C00))&0x05)==0x01)&&(((per.l(ad:0x40004C00+0x04))&0x100000)==0x00))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
elif ((((per.l(ad:0x40004C00))&0x05)==(0x00||0x04))&&(((per.l(ad:0x40004C00+0x04))&0x100000)==0x100000))
|
|
if (((per.l(ad:0x40004C00))&0x08)==0x08)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40004C00))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR3,Control Register 3"
|
|
sif cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F75*")||cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low"
|
|
bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR3,ControL Register 3"
|
|
sif cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F75*")||cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low"
|
|
rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
newline
|
|
rbitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40004C00))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR3,Control Register 3"
|
|
bitfld.long 0x00 29.--31. " TXFTCFG ,TXFIFO threshold configuration" "1/8,1/4,1/2,3/4,7/8,Empty,?..."
|
|
bitfld.long 0x00 28. " RXFTIE ,RXFIFO threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--27. " RXFTCFG ,Receive FIFO threshold configuration" "1/8,1/4,1/2,3/4,7/8,Empty,?..."
|
|
bitfld.long 0x00 24. " TCBGTIE ,Transmission complete before guard time interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " TXFTIE ,TXFIFO threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from low-power mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " WUS ,Wakeup from low-power mode interrupt flag selection" "Address match,,Start bit,RXNE/RXFNE"
|
|
newline
|
|
bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low"
|
|
bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
bitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR3,Control Register 3"
|
|
bitfld.long 0x00 29.--31. " TXFTCFG ,TXFIFO threshold configuration" "1/8,1/4,1/2,3/4,7/8,Empty,?..."
|
|
bitfld.long 0x00 28. " RXFTIE ,RXFIFO threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--27. " RXFTCFG ,Receive FIFO threshold configuration" "1/8,1/4,1/2,3/4,7/8,Empty,?..."
|
|
bitfld.long 0x00 24. " TCBGTIE ,Transmission complete before guard time interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " TXFTIE ,TXFIFO threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from low-power mode interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20.--21. " WUS ,Wakeup from low-power mode interrupt flag selection" "Address match,,Start bit,RXNE/RXFNE"
|
|
newline
|
|
rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low"
|
|
rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
rbitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
newline
|
|
rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
sif (cpuis("STM32F7*"))
|
|
if (((per.l((ad:0x40004C00)))&0x8001)==0x8000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l((ad:0x40004C00)))&0x8001)==0x8001)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l((ad:0x40004C00)))&0x8001)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR[3:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR[2:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40004C00))&0x01)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR[15:4] ,BRR[15:4]"
|
|
bitfld.long 0x00 0.--3. " [3:0] ,BRR[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR[15:4] ,BRR[15:4]"
|
|
bitfld.long 0x00 0.--3. " [3:0] ,BRR[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40004C00))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "GTPR,Guard Time And Prescaler Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GTPR,Guard Time And Prescaler Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTOR,Receiver Timeout Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BLEN ,Block length"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " RTO ,Receiver timeout value"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "RQR,Request Register"
|
|
sif (cpuis("STM32F7*"))
|
|
else
|
|
bitfld.long 0x00 4. " TXFRQ ,Transmit data flush request" "No effect,Flush"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 3. " RXFRQ ,Receive data flush request" "No effect,Flush"
|
|
bitfld.long 0x00 2. " MMRQ ,Mute mode request" "No effect,Mute"
|
|
bitfld.long 0x00 1. " SBKRQ ,Send break request" "No effect,Break"
|
|
bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "No effect,Request"
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ISR,Interrupt And Status Register"
|
|
bitfld.long 0x00 27. " TXFT ,TXFIFO threshold flag" "Not reached,Reached"
|
|
bitfld.long 0x00 26. " RXFT ,RXFIFO threshold flag" "Not reached,Reached"
|
|
bitfld.long 0x00 24. " RXFF ,RXFIFO full" "Not full,Full"
|
|
bitfld.long 0x00 23. " TXFE ,TXFIFO empty" "Not empty,Empty"
|
|
newline
|
|
bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 18. " SBKF ,Send break flag" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy"
|
|
newline
|
|
bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "Completed,In progress"
|
|
bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error"
|
|
bitfld.long 0x00 11. " RTOF ,Receiver timeout" "No timeout,Timeout"
|
|
bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset"
|
|
newline
|
|
bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " LBDF ,LIN break detection flag" "Not detected,Detected"
|
|
bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not empty,Empty"
|
|
bitfld.long 0x00 6. " TC ,Transmission complete" "Not complete,Complete"
|
|
newline
|
|
bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes"
|
|
bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected"
|
|
bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error"
|
|
bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 1. " FE ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 0. " PE ,Parity error" "No error,Error"
|
|
else
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ISR,Interrupt And Status Register"
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
endif
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 22. " REACK ,Receive enable acknowledge flag" "Not acknowledged,Acknowledged"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Not acknowledged,Acknowledged"
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 20. " WUF ,Wakeup from stop mode flag" "Not occurred,Occurred"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 19. " RWU ,Receiver wakeup from mute mode" "Active mode,Mute mode"
|
|
bitfld.long 0x00 18. " SBKF ,Send break flag" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy"
|
|
newline
|
|
bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "Completed,In progress"
|
|
bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error"
|
|
newline
|
|
sif cpuis("STM32F7*")
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 11. " RTOF ,Receiver timeout" "No timeout,Timeout"
|
|
bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset"
|
|
bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " LBDF ,LIN break detection flag" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not empty,Empty"
|
|
bitfld.long 0x00 6. " TC ,Transmission complete" "Not complete,Complete"
|
|
bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes"
|
|
bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error"
|
|
bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " FE ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 0. " PE ,Parity error" "No error,Error"
|
|
endif
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "ICR,Interrupt Flag Clear Register"
|
|
bitfld.long 0x00 20. " WUCF ,Wakeup from low-power mode clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 13. " UDRCF ,SPI slave underrun clear flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 8. " LBDCF ,LIN break detection clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 7. " TCBGTCF ,Transmission complete before guard time clear flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 5. " TXFECF ,TXFIFO empty clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 2. " NECF ,Noise detected clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Clear"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ICR,Interrupt Flag Clear Register"
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
eventfld.long 0x00 20. " WUCF ,Wakeup from stop mode clear flag" "No effect,Clear"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 12. " EOBCF ,End of timeout clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear"
|
|
newline
|
|
eventfld.long 0x00 8. " LBDCF ,LIN break detection clear flag" "No effect,Clear"
|
|
sif (!cpuis("STM32F74*")&&!cpuis("STM32F75*"))
|
|
endif
|
|
newline
|
|
eventfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Clear"
|
|
newline
|
|
eventfld.long 0x00 2. " NCF ,Noise detected clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Clear"
|
|
endif
|
|
newline
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "RDR,Receive Data Register"
|
|
in
|
|
newline
|
|
if (((per.l(ad:0x40004C00))&0x80)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TDR,Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value"
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "TDR,Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value"
|
|
endif
|
|
width 7.
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40004C00))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PRESC,Prescaler Register"
|
|
bitfld.long 0x00 0.--3. " PRESCALER ,Clock prescaler" "Not divided,/2,/4,/6,/8,/10,/12,/16,/32,/64,/128,/256,?..."
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "PRESC,Prescaler Register"
|
|
bitfld.long 0x00 0.--3. " PRESCALER ,Clock prescaler" "Not divided,/2,/4,/6,/8,/10,/12,/16,/32,/64,/128,/256,?..."
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART 5"
|
|
base ad:0x40005000
|
|
width 6.
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40005000))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
sif (cpuis("STM32F7*"))
|
|
else
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver enable de-assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
sif cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
else
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
sif (cpuis("STM32F7*"))
|
|
else
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 16.--20. " DEDT ,Driver enable de-assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
newline
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
sif cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
else
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40005000+0x08))&0x02)==0x02)||(((per.l(ad:0x40005000+0x04))&0x4000)==0x4000)
|
|
if (((per.l(ad:0x40005000))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
newline
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40005000))&0x20000000)==0x20000000)
|
|
if (((per.l(ad:0x40005000))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 31. " RXFFIE ,RXFIFO full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TXFEIE ,TXFIFO empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIFOEN ,FIFO mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
newline
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
newline
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 31. " RXFFIE ,RXFIFO full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TXFEIE ,TXFIFO empty interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " FIFOEN ,FIFO mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
newline
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
newline
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40005000))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 29. " FIFOEN ,FIFO mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
rbitfld.long 0x00 29. " FIFOEN ,FIFO mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
endif
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40005000))&0x01)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
if (((per.l(ad:0x40005000))&0x04)==0x00)&&(((per.l(ad:0x40005000+0x04))&0x100000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
elif (((per.l(ad:0x40005000))&0x04)==0x00)&&(((per.l(ad:0x40005000+0x04))&0x100000)==0x100000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
elif (((per.l(ad:0x40005000))&0x04)==0x00)&&(((per.l(ad:0x40005000+0x04))&0x100000)==0x100000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40005000))&0x05)==(0x00||0x04))&&(((per.l(ad:0x40005000+0x04))&0x100000)==0x00)
|
|
if (((per.l(ad:0x40005000))&0x08)==0x08)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
elif ((((per.l(ad:0x40005000))&0x05)==0x05)&&(((per.l(ad:0x40005000+0x04))&0x100000)==0x100000))||((((per.l(ad:0x40005000))&0x05)==0x05)&&(((per.l(ad:0x40005000+0x04))&0x100000)==0x00))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
elif ((((per.l(ad:0x40005000))&0x05)==0x01)&&(((per.l(ad:0x40005000+0x04))&0x100000)==0x100000))||((((per.l(ad:0x40005000))&0x05)==0x01)&&(((per.l(ad:0x40005000+0x04))&0x100000)==0x00))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
elif ((((per.l(ad:0x40005000))&0x05)==(0x00||0x04))&&(((per.l(ad:0x40005000+0x04))&0x100000)==0x100000))
|
|
if (((per.l(ad:0x40005000))&0x08)==0x08)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40005000))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR3,Control Register 3"
|
|
sif cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F75*")||cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low"
|
|
bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR3,ControL Register 3"
|
|
sif cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F75*")||cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low"
|
|
rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
newline
|
|
rbitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40005000))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR3,Control Register 3"
|
|
bitfld.long 0x00 29.--31. " TXFTCFG ,TXFIFO threshold configuration" "1/8,1/4,1/2,3/4,7/8,Empty,?..."
|
|
bitfld.long 0x00 28. " RXFTIE ,RXFIFO threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--27. " RXFTCFG ,Receive FIFO threshold configuration" "1/8,1/4,1/2,3/4,7/8,Empty,?..."
|
|
bitfld.long 0x00 24. " TCBGTIE ,Transmission complete before guard time interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " TXFTIE ,TXFIFO threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from low-power mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " WUS ,Wakeup from low-power mode interrupt flag selection" "Address match,,Start bit,RXNE/RXFNE"
|
|
newline
|
|
bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low"
|
|
bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
bitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR3,Control Register 3"
|
|
bitfld.long 0x00 29.--31. " TXFTCFG ,TXFIFO threshold configuration" "1/8,1/4,1/2,3/4,7/8,Empty,?..."
|
|
bitfld.long 0x00 28. " RXFTIE ,RXFIFO threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--27. " RXFTCFG ,Receive FIFO threshold configuration" "1/8,1/4,1/2,3/4,7/8,Empty,?..."
|
|
bitfld.long 0x00 24. " TCBGTIE ,Transmission complete before guard time interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " TXFTIE ,TXFIFO threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from low-power mode interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20.--21. " WUS ,Wakeup from low-power mode interrupt flag selection" "Address match,,Start bit,RXNE/RXFNE"
|
|
newline
|
|
rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low"
|
|
rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
rbitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
newline
|
|
rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
sif (cpuis("STM32F7*"))
|
|
if (((per.l((ad:0x40005000)))&0x8001)==0x8000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l((ad:0x40005000)))&0x8001)==0x8001)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l((ad:0x40005000)))&0x8001)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR[3:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR[2:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40005000))&0x01)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR[15:4] ,BRR[15:4]"
|
|
bitfld.long 0x00 0.--3. " [3:0] ,BRR[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR[15:4] ,BRR[15:4]"
|
|
bitfld.long 0x00 0.--3. " [3:0] ,BRR[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40005000))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "GTPR,Guard Time And Prescaler Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GTPR,Guard Time And Prescaler Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTOR,Receiver Timeout Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BLEN ,Block length"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " RTO ,Receiver timeout value"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "RQR,Request Register"
|
|
sif (cpuis("STM32F7*"))
|
|
else
|
|
bitfld.long 0x00 4. " TXFRQ ,Transmit data flush request" "No effect,Flush"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 3. " RXFRQ ,Receive data flush request" "No effect,Flush"
|
|
bitfld.long 0x00 2. " MMRQ ,Mute mode request" "No effect,Mute"
|
|
bitfld.long 0x00 1. " SBKRQ ,Send break request" "No effect,Break"
|
|
bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "No effect,Request"
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ISR,Interrupt And Status Register"
|
|
bitfld.long 0x00 27. " TXFT ,TXFIFO threshold flag" "Not reached,Reached"
|
|
bitfld.long 0x00 26. " RXFT ,RXFIFO threshold flag" "Not reached,Reached"
|
|
bitfld.long 0x00 24. " RXFF ,RXFIFO full" "Not full,Full"
|
|
bitfld.long 0x00 23. " TXFE ,TXFIFO empty" "Not empty,Empty"
|
|
newline
|
|
bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 18. " SBKF ,Send break flag" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy"
|
|
newline
|
|
bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "Completed,In progress"
|
|
bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error"
|
|
bitfld.long 0x00 11. " RTOF ,Receiver timeout" "No timeout,Timeout"
|
|
bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset"
|
|
newline
|
|
bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " LBDF ,LIN break detection flag" "Not detected,Detected"
|
|
bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not empty,Empty"
|
|
bitfld.long 0x00 6. " TC ,Transmission complete" "Not complete,Complete"
|
|
newline
|
|
bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes"
|
|
bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected"
|
|
bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error"
|
|
bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 1. " FE ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 0. " PE ,Parity error" "No error,Error"
|
|
else
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ISR,Interrupt And Status Register"
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
endif
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 22. " REACK ,Receive enable acknowledge flag" "Not acknowledged,Acknowledged"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Not acknowledged,Acknowledged"
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 20. " WUF ,Wakeup from stop mode flag" "Not occurred,Occurred"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 19. " RWU ,Receiver wakeup from mute mode" "Active mode,Mute mode"
|
|
bitfld.long 0x00 18. " SBKF ,Send break flag" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy"
|
|
newline
|
|
bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "Completed,In progress"
|
|
bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error"
|
|
newline
|
|
sif cpuis("STM32F7*")
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 11. " RTOF ,Receiver timeout" "No timeout,Timeout"
|
|
bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset"
|
|
bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " LBDF ,LIN break detection flag" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not empty,Empty"
|
|
bitfld.long 0x00 6. " TC ,Transmission complete" "Not complete,Complete"
|
|
bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes"
|
|
bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error"
|
|
bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " FE ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 0. " PE ,Parity error" "No error,Error"
|
|
endif
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "ICR,Interrupt Flag Clear Register"
|
|
bitfld.long 0x00 20. " WUCF ,Wakeup from low-power mode clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 13. " UDRCF ,SPI slave underrun clear flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 8. " LBDCF ,LIN break detection clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 7. " TCBGTCF ,Transmission complete before guard time clear flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 5. " TXFECF ,TXFIFO empty clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 2. " NECF ,Noise detected clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Clear"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ICR,Interrupt Flag Clear Register"
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
eventfld.long 0x00 20. " WUCF ,Wakeup from stop mode clear flag" "No effect,Clear"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 12. " EOBCF ,End of timeout clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear"
|
|
newline
|
|
eventfld.long 0x00 8. " LBDCF ,LIN break detection clear flag" "No effect,Clear"
|
|
sif (!cpuis("STM32F74*")&&!cpuis("STM32F75*"))
|
|
endif
|
|
newline
|
|
eventfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Clear"
|
|
newline
|
|
eventfld.long 0x00 2. " NCF ,Noise detected clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Clear"
|
|
endif
|
|
newline
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "RDR,Receive Data Register"
|
|
in
|
|
newline
|
|
if (((per.l(ad:0x40005000))&0x80)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TDR,Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value"
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "TDR,Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value"
|
|
endif
|
|
width 7.
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40005000))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PRESC,Prescaler Register"
|
|
bitfld.long 0x00 0.--3. " PRESCALER ,Clock prescaler" "Not divided,/2,/4,/6,/8,/10,/12,/16,/32,/64,/128,/256,?..."
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "PRESC,Prescaler Register"
|
|
bitfld.long 0x00 0.--3. " PRESCALER ,Clock prescaler" "Not divided,/2,/4,/6,/8,/10,/12,/16,/32,/64,/128,/256,?..."
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "USART 6"
|
|
base ad:0x40011400
|
|
width 6.
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40011400))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
sif (cpuis("STM32F7*"))
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver enable de-assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
sif cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
else
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
sif (cpuis("STM32F7*"))
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 16.--20. " DEDT ,Driver enable de-assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
newline
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
sif cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
else
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40011400+0x08))&0x20)==0x20)
|
|
if (((per.l(ad:0x40011400))&0x20000000)==0x20000000)
|
|
if (((per.l(ad:0x40011400))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 31. " RXFFIE ,RXFIFO full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TXFEIE ,TXFIFO empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIFOEN ,FIFO mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
newline
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
newline
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 31. " RXFFIE ,RXFIFO full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TXFEIE ,TXFIFO empty interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " FIFOEN ,FIFO mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
newline
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
newline
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40011400))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 29. " FIFOEN ,FIFO mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
rbitfld.long 0x00 29. " FIFOEN ,FIFO mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40011400))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
newline
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40011400))&0x01)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
if (((per.l(ad:0x40011400))&0x04)==0x00)&&(((per.l(ad:0x40011400+0x04))&0x100000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
elif (((per.l(ad:0x40011400))&0x04)==0x00)&&(((per.l(ad:0x40011400+0x04))&0x100000)==0x100000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
elif (((per.l(ad:0x40011400))&0x04)==0x00)&&(((per.l(ad:0x40011400+0x04))&0x100000)==0x100000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40011400))&0x05)==(0x00||0x04))&&(((per.l(ad:0x40011400+0x04))&0x100000)==0x00)
|
|
if (((per.l(ad:0x40011400))&0x08)==0x08)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
elif ((((per.l(ad:0x40011400))&0x05)==0x05)&&(((per.l(ad:0x40011400+0x04))&0x100000)==0x100000))||((((per.l(ad:0x40011400))&0x05)==0x05)&&(((per.l(ad:0x40011400+0x04))&0x100000)==0x00))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
elif ((((per.l(ad:0x40011400))&0x05)==0x01)&&(((per.l(ad:0x40011400+0x04))&0x100000)==0x100000))||((((per.l(ad:0x40011400))&0x05)==0x01)&&(((per.l(ad:0x40011400+0x04))&0x100000)==0x00))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
elif ((((per.l(ad:0x40011400))&0x05)==(0x00||0x04))&&(((per.l(ad:0x40011400+0x04))&0x100000)==0x100000))
|
|
if (((per.l(ad:0x40011400))&0x08)==0x08)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40011400))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR3,Control Register 3"
|
|
sif cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F75*")||cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
bitfld.long 0x00 24. " TCBGTIE ,Transmission complete before guard time interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 23. " UCESM ,USART clock enable in stop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from low-power mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " WUS ,Wakeup from low-power mode interrupt flag selection" "Address match,,Start bit,RXNE/RXFNE"
|
|
newline
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low"
|
|
bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR3,ControL Register 3"
|
|
sif cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F75*")||cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
bitfld.long 0x00 24. " TCBGTIE ,Transmission complete before guard time interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 23. " UCESM ,USART clock enable in stop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from low-power mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " WUS ,Wakeup from low-power mode interrupt flag selection" "Address match,,Start bit,RXNE/RXFNE"
|
|
newline
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low"
|
|
rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
newline
|
|
rbitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40011400))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR3,Control Register 3"
|
|
bitfld.long 0x00 29.--31. " TXFTCFG ,TXFIFO threshold configuration" "1/8,1/4,1/2,3/4,7/8,Empty,?..."
|
|
bitfld.long 0x00 28. " RXFTIE ,RXFIFO threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--27. " RXFTCFG ,Receive FIFO threshold configuration" "1/8,1/4,1/2,3/4,7/8,Empty,?..."
|
|
bitfld.long 0x00 24. " TCBGTIE ,Transmission complete before guard time interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " TXFTIE ,TXFIFO threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from low-power mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " WUS ,Wakeup from low-power mode interrupt flag selection" "Address match,,Start bit,RXNE/RXFNE"
|
|
newline
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low"
|
|
bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
bitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR3,Control Register 3"
|
|
bitfld.long 0x00 29.--31. " TXFTCFG ,TXFIFO threshold configuration" "1/8,1/4,1/2,3/4,7/8,Empty,?..."
|
|
bitfld.long 0x00 28. " RXFTIE ,RXFIFO threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--27. " RXFTCFG ,Receive FIFO threshold configuration" "1/8,1/4,1/2,3/4,7/8,Empty,?..."
|
|
bitfld.long 0x00 24. " TCBGTIE ,Transmission complete before guard time interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " TXFTIE ,TXFIFO threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from low-power mode interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20.--21. " WUS ,Wakeup from low-power mode interrupt flag selection" "Address match,,Start bit,RXNE/RXFNE"
|
|
newline
|
|
rbitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low"
|
|
rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
rbitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
newline
|
|
rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
sif (cpuis("STM32F7*"))
|
|
if (((per.l((ad:0x40011400)))&0x8001)==0x8000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l((ad:0x40011400)))&0x8001)==0x8001)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l((ad:0x40011400)))&0x8001)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR[3:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR[2:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40011400))&0x01)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR[15:4] ,BRR[15:4]"
|
|
bitfld.long 0x00 0.--3. " [3:0] ,BRR[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR[15:4] ,BRR[15:4]"
|
|
bitfld.long 0x00 0.--3. " [3:0] ,BRR[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40011400))&0x01)==0x00)
|
|
if (((per.l((ad:0x40011400+0x08)))&0x20)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "GTPR,Guard Time And Prescaler Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "GTPR,Guard Time And Prescaler Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
bitfld.long 0x00 0.--4. " PSC ,Prescaler value" ",2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62"
|
|
endif
|
|
else
|
|
if (((per.l((ad:0x40011400+0x08)))&0x20)==0x00)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GTPR,Guard Time And Prescaler Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GTPR,Guard Time And Prescaler Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
bitfld.long 0x00 0.--4. " PSC ,Prescaler value" ",2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62"
|
|
endif
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTOR,Receiver Timeout Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BLEN ,Block length"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " RTO ,Receiver timeout value"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "RQR,Request Register"
|
|
sif (cpuis("STM32F7*"))
|
|
bitfld.long 0x00 4. " TXFRQ ,Transmit data flush request" "No effect,Flush"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 4. " TXFRQ ,Transmit data flush request" "No effect,Flush"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 3. " RXFRQ ,Receive data flush request" "No effect,Flush"
|
|
bitfld.long 0x00 2. " MMRQ ,Mute mode request" "No effect,Mute"
|
|
bitfld.long 0x00 1. " SBKRQ ,Send break request" "No effect,Break"
|
|
bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "No effect,Request"
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40011400+0x08))&0x20)==0x20)
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ISR,Interrupt And Status Register"
|
|
bitfld.long 0x00 27. " TXFT ,TXFIFO threshold flag" "Not reached,Reached"
|
|
bitfld.long 0x00 26. " RXFT ,RXFIFO threshold flag" "Not reached,Reached"
|
|
bitfld.long 0x00 25. " TCBGT ,Transmission complete before guard time flag" "Not completed,Completed"
|
|
bitfld.long 0x00 24. " RXFF ,RXFIFO full" "Not full,Full"
|
|
newline
|
|
bitfld.long 0x00 23. " TXFE ,TXFIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 18. " SBKF ,Send break flag" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy"
|
|
bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "Completed,In progress"
|
|
bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error"
|
|
bitfld.long 0x00 12. " EOBF ,End of block flag" "Not ended,Ended"
|
|
newline
|
|
bitfld.long 0x00 11. " RTOF ,Receiver timeout" "No timeout,Timeout"
|
|
bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset"
|
|
bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " LBDF ,LIN break detection flag" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not empty,Empty"
|
|
bitfld.long 0x00 6. " TC ,Transmission complete" "Not complete,Complete"
|
|
bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes"
|
|
bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error"
|
|
bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " FE ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 0. " PE ,Parity error" "No error,Error"
|
|
else
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ISR,Interrupt And Status Register"
|
|
bitfld.long 0x00 27. " TXFT ,TXFIFO threshold flag" "Not reached,Reached"
|
|
bitfld.long 0x00 26. " RXFT ,RXFIFO threshold flag" "Not reached,Reached"
|
|
bitfld.long 0x00 24. " RXFF ,RXFIFO full" "Not full,Full"
|
|
bitfld.long 0x00 23. " TXFE ,TXFIFO empty" "Not empty,Empty"
|
|
newline
|
|
bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 18. " SBKF ,Send break flag" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy"
|
|
newline
|
|
bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "Completed,In progress"
|
|
bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error"
|
|
bitfld.long 0x00 12. " EOBF ,End of block flag" "Not ended,Ended"
|
|
bitfld.long 0x00 11. " RTOF ,Receiver timeout" "No timeout,Timeout"
|
|
newline
|
|
bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset"
|
|
bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " LBDF ,LIN break detection flag" "Not detected,Detected"
|
|
bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not empty,Empty"
|
|
newline
|
|
bitfld.long 0x00 6. " TC ,Transmission complete" "Not complete,Complete"
|
|
bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes"
|
|
bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected"
|
|
bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " FE ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 0. " PE ,Parity error" "No error,Error"
|
|
endif
|
|
else
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ISR,Interrupt And Status Register"
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 25. " TCBGT ,Transmission complete before guard time flag" "Not completed,Completed"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 22. " REACK ,Receive enable acknowledge flag" "Not acknowledged,Acknowledged"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Not acknowledged,Acknowledged"
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 20. " WUF ,Wakeup from stop mode flag" "Not occurred,Occurred"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 19. " RWU ,Receiver wakeup from mute mode" "Active mode,Mute mode"
|
|
bitfld.long 0x00 18. " SBKF ,Send break flag" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy"
|
|
newline
|
|
bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "Completed,In progress"
|
|
bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error"
|
|
newline
|
|
sif cpuis("STM32F7*")
|
|
bitfld.long 0x00 12. " EOBF ,End of block flag" "Not ended,Ended"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 11. " RTOF ,Receiver timeout" "No timeout,Timeout"
|
|
bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset"
|
|
bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " LBDF ,LIN break detection flag" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not empty,Empty"
|
|
bitfld.long 0x00 6. " TC ,Transmission complete" "Not complete,Complete"
|
|
bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes"
|
|
bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error"
|
|
bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " FE ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 0. " PE ,Parity error" "No error,Error"
|
|
endif
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "ICR,Interrupt Flag Clear Register"
|
|
bitfld.long 0x00 20. " WUCF ,Wakeup from low-power mode clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 13. " UDRCF ,SPI slave underrun clear flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 12. " EOBCF ,End of timeout clear flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 8. " LBDCF ,LIN break detection clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 7. " TCBGTCF ,Transmission complete before guard time clear flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 5. " TXFECF ,TXFIFO empty clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 2. " NECF ,Noise detected clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Clear"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ICR,Interrupt Flag Clear Register"
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
eventfld.long 0x00 20. " WUCF ,Wakeup from stop mode clear flag" "No effect,Clear"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 12. " EOBCF ,End of timeout clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear"
|
|
newline
|
|
eventfld.long 0x00 8. " LBDCF ,LIN break detection clear flag" "No effect,Clear"
|
|
sif (!cpuis("STM32F74*")&&!cpuis("STM32F75*"))
|
|
eventfld.long 0x00 7. " TCBGTCF ,Transmission complete before guard time clear flag" "No effect,Clear"
|
|
endif
|
|
newline
|
|
eventfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Clear"
|
|
newline
|
|
eventfld.long 0x00 2. " NCF ,Noise detected clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Clear"
|
|
endif
|
|
newline
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "RDR,Receive Data Register"
|
|
in
|
|
newline
|
|
if (((per.l(ad:0x40011400))&0x80)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TDR,Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value"
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "TDR,Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value"
|
|
endif
|
|
width 7.
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40011400))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PRESC,Prescaler Register"
|
|
bitfld.long 0x00 0.--3. " PRESCALER ,Clock prescaler" "Not divided,/2,/4,/6,/8,/10,/12,/16,/32,/64,/128,/256,?..."
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "PRESC,Prescaler Register"
|
|
bitfld.long 0x00 0.--3. " PRESCALER ,Clock prescaler" "Not divided,/2,/4,/6,/8,/10,/12,/16,/32,/64,/128,/256,?..."
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif !cpuis("STM32F72?R*")&&!cpuis("STM32F73?R*")
|
|
tree "UART 7"
|
|
base ad:0x40007800
|
|
width 6.
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40007800))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
sif (cpuis("STM32F7*"))
|
|
else
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver enable de-assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
sif cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
else
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
sif (cpuis("STM32F7*"))
|
|
else
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 16.--20. " DEDT ,Driver enable de-assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
newline
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
sif cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
else
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40007800+0x08))&0x02)==0x02)||(((per.l(ad:0x40007800+0x04))&0x4000)==0x4000)
|
|
if (((per.l(ad:0x40007800))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
newline
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40007800))&0x20000000)==0x20000000)
|
|
if (((per.l(ad:0x40007800))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 31. " RXFFIE ,RXFIFO full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TXFEIE ,TXFIFO empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIFOEN ,FIFO mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
newline
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
newline
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 31. " RXFFIE ,RXFIFO full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TXFEIE ,TXFIFO empty interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " FIFOEN ,FIFO mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
newline
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
newline
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40007800))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 29. " FIFOEN ,FIFO mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
rbitfld.long 0x00 29. " FIFOEN ,FIFO mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
endif
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40007800))&0x01)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
if (((per.l(ad:0x40007800))&0x04)==0x00)&&(((per.l(ad:0x40007800+0x04))&0x100000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
elif (((per.l(ad:0x40007800))&0x04)==0x00)&&(((per.l(ad:0x40007800+0x04))&0x100000)==0x100000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
elif (((per.l(ad:0x40007800))&0x04)==0x00)&&(((per.l(ad:0x40007800+0x04))&0x100000)==0x100000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40007800))&0x05)==(0x00||0x04))&&(((per.l(ad:0x40007800+0x04))&0x100000)==0x00)
|
|
if (((per.l(ad:0x40007800))&0x08)==0x08)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
elif ((((per.l(ad:0x40007800))&0x05)==0x05)&&(((per.l(ad:0x40007800+0x04))&0x100000)==0x100000))||((((per.l(ad:0x40007800))&0x05)==0x05)&&(((per.l(ad:0x40007800+0x04))&0x100000)==0x00))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
elif ((((per.l(ad:0x40007800))&0x05)==0x01)&&(((per.l(ad:0x40007800+0x04))&0x100000)==0x100000))||((((per.l(ad:0x40007800))&0x05)==0x01)&&(((per.l(ad:0x40007800+0x04))&0x100000)==0x00))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
elif ((((per.l(ad:0x40007800))&0x05)==(0x00||0x04))&&(((per.l(ad:0x40007800+0x04))&0x100000)==0x100000))
|
|
if (((per.l(ad:0x40007800))&0x08)==0x08)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40007800))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR3,Control Register 3"
|
|
sif cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F75*")||cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low"
|
|
bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR3,ControL Register 3"
|
|
sif cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F75*")||cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low"
|
|
rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
newline
|
|
rbitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40007800))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR3,Control Register 3"
|
|
bitfld.long 0x00 29.--31. " TXFTCFG ,TXFIFO threshold configuration" "1/8,1/4,1/2,3/4,7/8,Empty,?..."
|
|
bitfld.long 0x00 28. " RXFTIE ,RXFIFO threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--27. " RXFTCFG ,Receive FIFO threshold configuration" "1/8,1/4,1/2,3/4,7/8,Empty,?..."
|
|
bitfld.long 0x00 24. " TCBGTIE ,Transmission complete before guard time interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " TXFTIE ,TXFIFO threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from low-power mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " WUS ,Wakeup from low-power mode interrupt flag selection" "Address match,,Start bit,RXNE/RXFNE"
|
|
newline
|
|
bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low"
|
|
bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
bitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR3,Control Register 3"
|
|
bitfld.long 0x00 29.--31. " TXFTCFG ,TXFIFO threshold configuration" "1/8,1/4,1/2,3/4,7/8,Empty,?..."
|
|
bitfld.long 0x00 28. " RXFTIE ,RXFIFO threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--27. " RXFTCFG ,Receive FIFO threshold configuration" "1/8,1/4,1/2,3/4,7/8,Empty,?..."
|
|
bitfld.long 0x00 24. " TCBGTIE ,Transmission complete before guard time interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " TXFTIE ,TXFIFO threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from low-power mode interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20.--21. " WUS ,Wakeup from low-power mode interrupt flag selection" "Address match,,Start bit,RXNE/RXFNE"
|
|
newline
|
|
rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low"
|
|
rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
rbitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
newline
|
|
rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
sif (cpuis("STM32F7*"))
|
|
if (((per.l((ad:0x40007800)))&0x8001)==0x8000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l((ad:0x40007800)))&0x8001)==0x8001)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l((ad:0x40007800)))&0x8001)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR[3:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR[2:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40007800))&0x01)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR[15:4] ,BRR[15:4]"
|
|
bitfld.long 0x00 0.--3. " [3:0] ,BRR[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR[15:4] ,BRR[15:4]"
|
|
bitfld.long 0x00 0.--3. " [3:0] ,BRR[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40007800))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "GTPR,Guard Time And Prescaler Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GTPR,Guard Time And Prescaler Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTOR,Receiver Timeout Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BLEN ,Block length"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " RTO ,Receiver timeout value"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "RQR,Request Register"
|
|
sif (cpuis("STM32F7*"))
|
|
else
|
|
bitfld.long 0x00 4. " TXFRQ ,Transmit data flush request" "No effect,Flush"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 3. " RXFRQ ,Receive data flush request" "No effect,Flush"
|
|
bitfld.long 0x00 2. " MMRQ ,Mute mode request" "No effect,Mute"
|
|
bitfld.long 0x00 1. " SBKRQ ,Send break request" "No effect,Break"
|
|
bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "No effect,Request"
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ISR,Interrupt And Status Register"
|
|
bitfld.long 0x00 27. " TXFT ,TXFIFO threshold flag" "Not reached,Reached"
|
|
bitfld.long 0x00 26. " RXFT ,RXFIFO threshold flag" "Not reached,Reached"
|
|
bitfld.long 0x00 24. " RXFF ,RXFIFO full" "Not full,Full"
|
|
bitfld.long 0x00 23. " TXFE ,TXFIFO empty" "Not empty,Empty"
|
|
newline
|
|
bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 18. " SBKF ,Send break flag" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy"
|
|
newline
|
|
bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "Completed,In progress"
|
|
bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error"
|
|
bitfld.long 0x00 11. " RTOF ,Receiver timeout" "No timeout,Timeout"
|
|
bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset"
|
|
newline
|
|
bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " LBDF ,LIN break detection flag" "Not detected,Detected"
|
|
bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not empty,Empty"
|
|
bitfld.long 0x00 6. " TC ,Transmission complete" "Not complete,Complete"
|
|
newline
|
|
bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes"
|
|
bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected"
|
|
bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error"
|
|
bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 1. " FE ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 0. " PE ,Parity error" "No error,Error"
|
|
else
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ISR,Interrupt And Status Register"
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
endif
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 22. " REACK ,Receive enable acknowledge flag" "Not acknowledged,Acknowledged"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Not acknowledged,Acknowledged"
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 20. " WUF ,Wakeup from stop mode flag" "Not occurred,Occurred"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 19. " RWU ,Receiver wakeup from mute mode" "Active mode,Mute mode"
|
|
bitfld.long 0x00 18. " SBKF ,Send break flag" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy"
|
|
newline
|
|
bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "Completed,In progress"
|
|
bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error"
|
|
newline
|
|
sif cpuis("STM32F7*")
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 11. " RTOF ,Receiver timeout" "No timeout,Timeout"
|
|
bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset"
|
|
bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " LBDF ,LIN break detection flag" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not empty,Empty"
|
|
bitfld.long 0x00 6. " TC ,Transmission complete" "Not complete,Complete"
|
|
bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes"
|
|
bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error"
|
|
bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " FE ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 0. " PE ,Parity error" "No error,Error"
|
|
endif
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "ICR,Interrupt Flag Clear Register"
|
|
bitfld.long 0x00 20. " WUCF ,Wakeup from low-power mode clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 13. " UDRCF ,SPI slave underrun clear flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 8. " LBDCF ,LIN break detection clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 7. " TCBGTCF ,Transmission complete before guard time clear flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 5. " TXFECF ,TXFIFO empty clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 2. " NECF ,Noise detected clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Clear"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ICR,Interrupt Flag Clear Register"
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
eventfld.long 0x00 20. " WUCF ,Wakeup from stop mode clear flag" "No effect,Clear"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 12. " EOBCF ,End of timeout clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear"
|
|
newline
|
|
eventfld.long 0x00 8. " LBDCF ,LIN break detection clear flag" "No effect,Clear"
|
|
sif (!cpuis("STM32F74*")&&!cpuis("STM32F75*"))
|
|
endif
|
|
newline
|
|
eventfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Clear"
|
|
newline
|
|
eventfld.long 0x00 2. " NCF ,Noise detected clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Clear"
|
|
endif
|
|
newline
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "RDR,Receive Data Register"
|
|
in
|
|
newline
|
|
if (((per.l(ad:0x40007800))&0x80)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TDR,Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value"
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "TDR,Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value"
|
|
endif
|
|
width 7.
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40007800))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PRESC,Prescaler Register"
|
|
bitfld.long 0x00 0.--3. " PRESCALER ,Clock prescaler" "Not divided,/2,/4,/6,/8,/10,/12,/16,/32,/64,/128,/256,?..."
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "PRESC,Prescaler Register"
|
|
bitfld.long 0x00 0.--3. " PRESCALER ,Clock prescaler" "Not divided,/2,/4,/6,/8,/10,/12,/16,/32,/64,/128,/256,?..."
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART 8"
|
|
base ad:0x40007C00
|
|
width 6.
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40007C00))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
sif (cpuis("STM32F7*"))
|
|
else
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver enable de-assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
sif cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
else
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
sif (cpuis("STM32F7*"))
|
|
else
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 16.--20. " DEDT ,Driver enable de-assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
newline
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
sif cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
else
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40007C00+0x08))&0x02)==0x02)||(((per.l(ad:0x40007C00+0x04))&0x4000)==0x4000)
|
|
if (((per.l(ad:0x40007C00))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
newline
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40007C00))&0x20000000)==0x20000000)
|
|
if (((per.l(ad:0x40007C00))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 31. " RXFFIE ,RXFIFO full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TXFEIE ,TXFIFO empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIFOEN ,FIFO mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
newline
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
newline
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 31. " RXFFIE ,RXFIFO full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TXFEIE ,TXFIFO empty interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " FIFOEN ,FIFO mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
newline
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
newline
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40007C00))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 29. " FIFOEN ,FIFO mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
rbitfld.long 0x00 29. " FIFOEN ,FIFO mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 16.--20. " DEDT ,Driver enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UESM ,USART enable in low-power mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
endif
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40007C00))&0x01)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
if (((per.l(ad:0x40007C00))&0x04)==0x00)&&(((per.l(ad:0x40007C00+0x04))&0x100000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
elif (((per.l(ad:0x40007C00))&0x04)==0x00)&&(((per.l(ad:0x40007C00+0x04))&0x100000)==0x100000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
elif (((per.l(ad:0x40007C00))&0x04)==0x00)&&(((per.l(ad:0x40007C00+0x04))&0x100000)==0x100000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40007C00))&0x05)==(0x00||0x04))&&(((per.l(ad:0x40007C00+0x04))&0x100000)==0x00)
|
|
if (((per.l(ad:0x40007C00))&0x08)==0x08)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
elif ((((per.l(ad:0x40007C00))&0x05)==0x05)&&(((per.l(ad:0x40007C00+0x04))&0x100000)==0x100000))||((((per.l(ad:0x40007C00))&0x05)==0x05)&&(((per.l(ad:0x40007C00+0x04))&0x100000)==0x00))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
elif ((((per.l(ad:0x40007C00))&0x05)==0x01)&&(((per.l(ad:0x40007C00+0x04))&0x100000)==0x100000))||((((per.l(ad:0x40007C00))&0x05)==0x01)&&(((per.l(ad:0x40007C00+0x04))&0x100000)==0x00))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
elif ((((per.l(ad:0x40007C00))&0x05)==(0x00||0x04))&&(((per.l(ad:0x40007C00+0x04))&0x100000)==0x100000))
|
|
if (((per.l(ad:0x40007C00))&0x08)==0x08)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
newline
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 bit,0.5 bit,2 bits,1.5 bit"
|
|
newline
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40007C00))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR3,Control Register 3"
|
|
sif cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F75*")||cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low"
|
|
bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR3,ControL Register 3"
|
|
sif cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F75*")||cpuis("STM32F76*")||cpuis("STM32F77*")
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low"
|
|
rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
newline
|
|
rbitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40007C00))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR3,Control Register 3"
|
|
bitfld.long 0x00 29.--31. " TXFTCFG ,TXFIFO threshold configuration" "1/8,1/4,1/2,3/4,7/8,Empty,?..."
|
|
bitfld.long 0x00 28. " RXFTIE ,RXFIFO threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--27. " RXFTCFG ,Receive FIFO threshold configuration" "1/8,1/4,1/2,3/4,7/8,Empty,?..."
|
|
bitfld.long 0x00 24. " TCBGTIE ,Transmission complete before guard time interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " TXFTIE ,TXFIFO threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from low-power mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " WUS ,Wakeup from low-power mode interrupt flag selection" "Address match,,Start bit,RXNE/RXFNE"
|
|
newline
|
|
bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low"
|
|
bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
bitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR3,Control Register 3"
|
|
bitfld.long 0x00 29.--31. " TXFTCFG ,TXFIFO threshold configuration" "1/8,1/4,1/2,3/4,7/8,Empty,?..."
|
|
bitfld.long 0x00 28. " RXFTIE ,RXFIFO threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--27. " RXFTCFG ,Receive FIFO threshold configuration" "1/8,1/4,1/2,3/4,7/8,Empty,?..."
|
|
bitfld.long 0x00 24. " TCBGTIE ,Transmission complete before guard time interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " TXFTIE ,TXFIFO threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from low-power mode interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20.--21. " WUS ,Wakeup from low-power mode interrupt flag selection" "Address match,,Start bit,RXNE/RXFNE"
|
|
newline
|
|
rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low"
|
|
rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
rbitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
newline
|
|
rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
sif (cpuis("STM32F7*"))
|
|
if (((per.l((ad:0x40007C00)))&0x8001)==0x8000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l((ad:0x40007C00)))&0x8001)==0x8001)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l((ad:0x40007C00)))&0x8001)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR[3:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR[2:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40007C00))&0x01)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR[15:4] ,BRR[15:4]"
|
|
bitfld.long 0x00 0.--3. " [3:0] ,BRR[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR[15:4] ,BRR[15:4]"
|
|
bitfld.long 0x00 0.--3. " [3:0] ,BRR[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40007C00))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "GTPR,Guard Time And Prescaler Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GTPR,Guard Time And Prescaler Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTOR,Receiver Timeout Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BLEN ,Block length"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " RTO ,Receiver timeout value"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "RQR,Request Register"
|
|
sif (cpuis("STM32F7*"))
|
|
else
|
|
bitfld.long 0x00 4. " TXFRQ ,Transmit data flush request" "No effect,Flush"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 3. " RXFRQ ,Receive data flush request" "No effect,Flush"
|
|
bitfld.long 0x00 2. " MMRQ ,Mute mode request" "No effect,Mute"
|
|
bitfld.long 0x00 1. " SBKRQ ,Send break request" "No effect,Break"
|
|
bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "No effect,Request"
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ISR,Interrupt And Status Register"
|
|
bitfld.long 0x00 27. " TXFT ,TXFIFO threshold flag" "Not reached,Reached"
|
|
bitfld.long 0x00 26. " RXFT ,RXFIFO threshold flag" "Not reached,Reached"
|
|
bitfld.long 0x00 24. " RXFF ,RXFIFO full" "Not full,Full"
|
|
bitfld.long 0x00 23. " TXFE ,TXFIFO empty" "Not empty,Empty"
|
|
newline
|
|
bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 18. " SBKF ,Send break flag" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy"
|
|
newline
|
|
bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "Completed,In progress"
|
|
bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error"
|
|
bitfld.long 0x00 11. " RTOF ,Receiver timeout" "No timeout,Timeout"
|
|
bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset"
|
|
newline
|
|
bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " LBDF ,LIN break detection flag" "Not detected,Detected"
|
|
bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not empty,Empty"
|
|
bitfld.long 0x00 6. " TC ,Transmission complete" "Not complete,Complete"
|
|
newline
|
|
bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes"
|
|
bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected"
|
|
bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error"
|
|
bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 1. " FE ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 0. " PE ,Parity error" "No error,Error"
|
|
else
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ISR,Interrupt And Status Register"
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
endif
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 22. " REACK ,Receive enable acknowledge flag" "Not acknowledged,Acknowledged"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Not acknowledged,Acknowledged"
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 20. " WUF ,Wakeup from stop mode flag" "Not occurred,Occurred"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 19. " RWU ,Receiver wakeup from mute mode" "Active mode,Mute mode"
|
|
bitfld.long 0x00 18. " SBKF ,Send break flag" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy"
|
|
newline
|
|
bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "Completed,In progress"
|
|
bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error"
|
|
newline
|
|
sif cpuis("STM32F7*")
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 11. " RTOF ,Receiver timeout" "No timeout,Timeout"
|
|
bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset"
|
|
bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " LBDF ,LIN break detection flag" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not empty,Empty"
|
|
bitfld.long 0x00 6. " TC ,Transmission complete" "Not complete,Complete"
|
|
bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes"
|
|
bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error"
|
|
bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " FE ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 0. " PE ,Parity error" "No error,Error"
|
|
endif
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "ICR,Interrupt Flag Clear Register"
|
|
bitfld.long 0x00 20. " WUCF ,Wakeup from low-power mode clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 13. " UDRCF ,SPI slave underrun clear flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 8. " LBDCF ,LIN break detection clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 7. " TCBGTCF ,Transmission complete before guard time clear flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 5. " TXFECF ,TXFIFO empty clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 2. " NECF ,Noise detected clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Clear"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ICR,Interrupt Flag Clear Register"
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
eventfld.long 0x00 20. " WUCF ,Wakeup from stop mode clear flag" "No effect,Clear"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 12. " EOBCF ,End of timeout clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear"
|
|
newline
|
|
eventfld.long 0x00 8. " LBDCF ,LIN break detection clear flag" "No effect,Clear"
|
|
sif (!cpuis("STM32F74*")&&!cpuis("STM32F75*"))
|
|
endif
|
|
newline
|
|
eventfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Clear"
|
|
newline
|
|
eventfld.long 0x00 2. " NCF ,Noise detected clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Clear"
|
|
eventfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Clear"
|
|
endif
|
|
newline
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "RDR,Receive Data Register"
|
|
in
|
|
newline
|
|
if (((per.l(ad:0x40007C00))&0x80)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TDR,Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value"
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "TDR,Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value"
|
|
endif
|
|
width 7.
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40007C00))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PRESC,Prescaler Register"
|
|
bitfld.long 0x00 0.--3. " PRESCALER ,Clock prescaler" "Not divided,/2,/4,/6,/8,/10,/12,/16,/32,/64,/128,/256,?..."
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "PRESC,Prescaler Register"
|
|
bitfld.long 0x00 0.--3. " PRESCALER ,Clock prescaler" "Not divided,/2,/4,/6,/8,/10,/12,/16,/32,/64,/128,/256,?..."
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree.open "SPI (Serial Peripheral Interface)"
|
|
tree "SPI 1 / I2S1"
|
|
base ad:0x40013000
|
|
width 9.
|
|
if (((per.w((ad:0x40013000+0x1C))&0x800)==0x00)&&((per.w((ad:0x40013000+0x04))&0x10)==0x10))
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
newline
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
newline
|
|
newline
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
newline
|
|
elif ((per.w((ad:0x40013000+0x1C))&0x800)==0x00)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
newline
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
newline
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
newline
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame format" "MSB,LSB"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
newline
|
|
bitfld.word 0x00 1. " CPOL ,Clock polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock phase" "First clock=first data,Second clock=first data"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 1. " CPOL ,Clock polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock phase" "First clock=first data,Second clock=first data"
|
|
endif
|
|
if (((per.w((ad:0x40013000+0x1C))&0x800)==0x00)&&((per.w((ad:0x40013000+0x04))&0x10)==0x10))
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "CR2,SPI Control Register 2"
|
|
rbitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
rbitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
newline
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
newline
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
newline
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
newline
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
elif (((per.w((ad:0x40013000+0x1C))&0x800)==0x00)&&((per.w((ad:0x40013000+0x04))&0x10)==0x00))
|
|
if ((per.w((ad:0x40013000))&0x40)==0x00)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "CR2,SPI Control Register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
newline
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
newline
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
newline
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
newline
|
|
bitfld.word 0x00 3. " NSSP ,NSS pulse management" "No NSS,NSS generated"
|
|
bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "CR2,SPI Control Register 2"
|
|
rbitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
rbitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
newline
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
newline
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
newline
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
newline
|
|
rbitfld.word 0x00 3. " NSSP ,NSS pulse management" "No NSS,NSS generated"
|
|
bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if ((per.w((ad:0x40013000+0x04))&0x10)==0x10)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "CR2,SPI Control Register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
newline
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "CR2,SPI Control Register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
newline
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
newline
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "SR,SPI Status Register"
|
|
in
|
|
hgroup.word 0x0C++0x01
|
|
hide.word 0x00 "DR,SPI Data Register"
|
|
in
|
|
newline
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "RCPR,SPI CRC Polynomial Register"
|
|
if (((per.w(ad:0x40013000+0x1C))&0x800)==0x000)
|
|
if (((per.l(ad:0x40013000))&0x80)==0x80)
|
|
hgroup.word 0x14++0x01
|
|
hide.word 0x00 "RXCRCR,SPI Rx CRC Register"
|
|
hgroup.word 0x18++0x01
|
|
hide.word 0x00 "TXCRCR,SPI Tx CRC Register"
|
|
else
|
|
if (((per.l(ad:0x40013000))&0x800)==0x800)
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "RXCRCR,SPI Rx CRC Register"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "TXCRCR,SPI Tx CRC Register"
|
|
else
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "RXCRCR,SPI Rx CRC Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " RXCRC ,Rx CRC register"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "TXCRCR,SPI Tx CRC Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TXCRC ,Tx CRC register"
|
|
endif
|
|
endif
|
|
else
|
|
hgroup.word 0x14++0x01
|
|
hide.word 0x00 "RXCRCR,SPI Rx CRC Register"
|
|
hgroup.word 0x18++0x01
|
|
hide.word 0x00 "TXCRCR,SPI Tx CRC Register"
|
|
endif
|
|
if (((per.w((ad:0x40013000+0x1C)))&0x800)==0x00)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "I2SCFGR,I2S Configuration Register"
|
|
bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
newline
|
|
newline
|
|
newline
|
|
else
|
|
if (((per.w((ad:0x40013000+0x1C)))&0x400)==0x00)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "I2SCFGR,I2S Configuration Register"
|
|
bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
bitfld.word 0x00 10. " I2SE ,I2S enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,Master/Transmit,Master/Receive"
|
|
bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization" "Short,Long"
|
|
newline
|
|
bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Phillips,MSB justified,LSB justified,PCM"
|
|
bitfld.word 0x00 3. " CKPOL ,Steady state clock polarity" "Low,High"
|
|
newline
|
|
bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,Not allowed"
|
|
bitfld.word 0x00 0. " CHLEN ,Channel length" "16-bit,32-bit"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "I2SCFGR,I2S Configuration Register"
|
|
bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
bitfld.word 0x00 10. " I2SE ,I2S enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,Master/Transmit,Master/Receive"
|
|
bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization" "Short,Long"
|
|
newline
|
|
rbitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Phillips,MSB justified,LSB justified,PCM"
|
|
rbitfld.word 0x00 3. " CKPOL ,Steady state clock polarity" "Low,High"
|
|
newline
|
|
rbitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,Not allowed"
|
|
rbitfld.word 0x00 0. " CHLEN ,Channel length" "16-bit,32-bit"
|
|
endif
|
|
endif
|
|
if ((per.w((ad:0x40013000+0x1C)))&0x700)==(0x600||0x700)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "I2SPR,I2S Prescaler Register"
|
|
bitfld.word 0x00 9. " MCKOE ,Master clock output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,(I2SDIV * 2)+1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S linear prescaler"
|
|
else
|
|
hgroup.word 0x20++0x01
|
|
hide.word 0x00 "I2SPR,I2S Prescaler Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "SPI 2 / I2S2"
|
|
base ad:0x40003800
|
|
width 9.
|
|
if (((per.w((ad:0x40003800+0x1C))&0x800)==0x00)&&((per.w((ad:0x40003800+0x04))&0x10)==0x10))
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
newline
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
newline
|
|
newline
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
newline
|
|
elif ((per.w((ad:0x40003800+0x1C))&0x800)==0x00)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
newline
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
newline
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
newline
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame format" "MSB,LSB"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
newline
|
|
bitfld.word 0x00 1. " CPOL ,Clock polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock phase" "First clock=first data,Second clock=first data"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 1. " CPOL ,Clock polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock phase" "First clock=first data,Second clock=first data"
|
|
endif
|
|
if (((per.w((ad:0x40003800+0x1C))&0x800)==0x00)&&((per.w((ad:0x40003800+0x04))&0x10)==0x10))
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "CR2,SPI Control Register 2"
|
|
rbitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
rbitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
newline
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
newline
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
newline
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
newline
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
elif (((per.w((ad:0x40003800+0x1C))&0x800)==0x00)&&((per.w((ad:0x40003800+0x04))&0x10)==0x00))
|
|
if ((per.w((ad:0x40003800))&0x40)==0x00)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "CR2,SPI Control Register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
newline
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
newline
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
newline
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
newline
|
|
bitfld.word 0x00 3. " NSSP ,NSS pulse management" "No NSS,NSS generated"
|
|
bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "CR2,SPI Control Register 2"
|
|
rbitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
rbitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
newline
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
newline
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
newline
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
newline
|
|
rbitfld.word 0x00 3. " NSSP ,NSS pulse management" "No NSS,NSS generated"
|
|
bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if ((per.w((ad:0x40003800+0x04))&0x10)==0x10)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "CR2,SPI Control Register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
newline
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "CR2,SPI Control Register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
newline
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
newline
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "SR,SPI Status Register"
|
|
in
|
|
hgroup.word 0x0C++0x01
|
|
hide.word 0x00 "DR,SPI Data Register"
|
|
in
|
|
newline
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "RCPR,SPI CRC Polynomial Register"
|
|
if (((per.w(ad:0x40003800+0x1C))&0x800)==0x000)
|
|
if (((per.l(ad:0x40003800))&0x80)==0x80)
|
|
hgroup.word 0x14++0x01
|
|
hide.word 0x00 "RXCRCR,SPI Rx CRC Register"
|
|
hgroup.word 0x18++0x01
|
|
hide.word 0x00 "TXCRCR,SPI Tx CRC Register"
|
|
else
|
|
if (((per.l(ad:0x40003800))&0x800)==0x800)
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "RXCRCR,SPI Rx CRC Register"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "TXCRCR,SPI Tx CRC Register"
|
|
else
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "RXCRCR,SPI Rx CRC Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " RXCRC ,Rx CRC register"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "TXCRCR,SPI Tx CRC Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TXCRC ,Tx CRC register"
|
|
endif
|
|
endif
|
|
else
|
|
hgroup.word 0x14++0x01
|
|
hide.word 0x00 "RXCRCR,SPI Rx CRC Register"
|
|
hgroup.word 0x18++0x01
|
|
hide.word 0x00 "TXCRCR,SPI Tx CRC Register"
|
|
endif
|
|
if (((per.w((ad:0x40003800+0x1C)))&0x800)==0x00)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "I2SCFGR,I2S Configuration Register"
|
|
bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
newline
|
|
newline
|
|
newline
|
|
else
|
|
if (((per.w((ad:0x40003800+0x1C)))&0x400)==0x00)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "I2SCFGR,I2S Configuration Register"
|
|
bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
bitfld.word 0x00 10. " I2SE ,I2S enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,Master/Transmit,Master/Receive"
|
|
bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization" "Short,Long"
|
|
newline
|
|
bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Phillips,MSB justified,LSB justified,PCM"
|
|
bitfld.word 0x00 3. " CKPOL ,Steady state clock polarity" "Low,High"
|
|
newline
|
|
bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,Not allowed"
|
|
bitfld.word 0x00 0. " CHLEN ,Channel length" "16-bit,32-bit"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "I2SCFGR,I2S Configuration Register"
|
|
bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
bitfld.word 0x00 10. " I2SE ,I2S enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,Master/Transmit,Master/Receive"
|
|
bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization" "Short,Long"
|
|
newline
|
|
rbitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Phillips,MSB justified,LSB justified,PCM"
|
|
rbitfld.word 0x00 3. " CKPOL ,Steady state clock polarity" "Low,High"
|
|
newline
|
|
rbitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,Not allowed"
|
|
rbitfld.word 0x00 0. " CHLEN ,Channel length" "16-bit,32-bit"
|
|
endif
|
|
endif
|
|
if ((per.w((ad:0x40003800+0x1C)))&0x700)==(0x600||0x700)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "I2SPR,I2S Prescaler Register"
|
|
bitfld.word 0x00 9. " MCKOE ,Master clock output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,(I2SDIV * 2)+1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S linear prescaler"
|
|
else
|
|
hgroup.word 0x20++0x01
|
|
hide.word 0x00 "I2SPR,I2S Prescaler Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "SPI 3 / I2S3"
|
|
base ad:0x40003C00
|
|
width 9.
|
|
if (((per.w((ad:0x40003C00+0x1C))&0x800)==0x00)&&((per.w((ad:0x40003C00+0x04))&0x10)==0x10))
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
newline
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
newline
|
|
newline
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
newline
|
|
elif ((per.w((ad:0x40003C00+0x1C))&0x800)==0x00)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
newline
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
newline
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
newline
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame format" "MSB,LSB"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
newline
|
|
bitfld.word 0x00 1. " CPOL ,Clock polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock phase" "First clock=first data,Second clock=first data"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 1. " CPOL ,Clock polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock phase" "First clock=first data,Second clock=first data"
|
|
endif
|
|
if (((per.w((ad:0x40003C00+0x1C))&0x800)==0x00)&&((per.w((ad:0x40003C00+0x04))&0x10)==0x10))
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "CR2,SPI Control Register 2"
|
|
rbitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
rbitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
newline
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
newline
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
newline
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
newline
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
elif (((per.w((ad:0x40003C00+0x1C))&0x800)==0x00)&&((per.w((ad:0x40003C00+0x04))&0x10)==0x00))
|
|
if ((per.w((ad:0x40003C00))&0x40)==0x00)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "CR2,SPI Control Register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
newline
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
newline
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
newline
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
newline
|
|
bitfld.word 0x00 3. " NSSP ,NSS pulse management" "No NSS,NSS generated"
|
|
bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "CR2,SPI Control Register 2"
|
|
rbitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
rbitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
newline
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
newline
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
newline
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
newline
|
|
rbitfld.word 0x00 3. " NSSP ,NSS pulse management" "No NSS,NSS generated"
|
|
bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if ((per.w((ad:0x40003C00+0x04))&0x10)==0x10)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "CR2,SPI Control Register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
newline
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "CR2,SPI Control Register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
newline
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
newline
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "SR,SPI Status Register"
|
|
in
|
|
hgroup.word 0x0C++0x01
|
|
hide.word 0x00 "DR,SPI Data Register"
|
|
in
|
|
newline
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "RCPR,SPI CRC Polynomial Register"
|
|
if (((per.w(ad:0x40003C00+0x1C))&0x800)==0x000)
|
|
if (((per.l(ad:0x40003C00))&0x80)==0x80)
|
|
hgroup.word 0x14++0x01
|
|
hide.word 0x00 "RXCRCR,SPI Rx CRC Register"
|
|
hgroup.word 0x18++0x01
|
|
hide.word 0x00 "TXCRCR,SPI Tx CRC Register"
|
|
else
|
|
if (((per.l(ad:0x40003C00))&0x800)==0x800)
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "RXCRCR,SPI Rx CRC Register"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "TXCRCR,SPI Tx CRC Register"
|
|
else
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "RXCRCR,SPI Rx CRC Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " RXCRC ,Rx CRC register"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "TXCRCR,SPI Tx CRC Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TXCRC ,Tx CRC register"
|
|
endif
|
|
endif
|
|
else
|
|
hgroup.word 0x14++0x01
|
|
hide.word 0x00 "RXCRCR,SPI Rx CRC Register"
|
|
hgroup.word 0x18++0x01
|
|
hide.word 0x00 "TXCRCR,SPI Tx CRC Register"
|
|
endif
|
|
if (((per.w((ad:0x40003C00+0x1C)))&0x800)==0x00)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "I2SCFGR,I2S Configuration Register"
|
|
bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
newline
|
|
newline
|
|
newline
|
|
else
|
|
if (((per.w((ad:0x40003C00+0x1C)))&0x400)==0x00)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "I2SCFGR,I2S Configuration Register"
|
|
bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
bitfld.word 0x00 10. " I2SE ,I2S enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,Master/Transmit,Master/Receive"
|
|
bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization" "Short,Long"
|
|
newline
|
|
bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Phillips,MSB justified,LSB justified,PCM"
|
|
bitfld.word 0x00 3. " CKPOL ,Steady state clock polarity" "Low,High"
|
|
newline
|
|
bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,Not allowed"
|
|
bitfld.word 0x00 0. " CHLEN ,Channel length" "16-bit,32-bit"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "I2SCFGR,I2S Configuration Register"
|
|
bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
bitfld.word 0x00 10. " I2SE ,I2S enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,Master/Transmit,Master/Receive"
|
|
bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization" "Short,Long"
|
|
newline
|
|
rbitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Phillips,MSB justified,LSB justified,PCM"
|
|
rbitfld.word 0x00 3. " CKPOL ,Steady state clock polarity" "Low,High"
|
|
newline
|
|
rbitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,Not allowed"
|
|
rbitfld.word 0x00 0. " CHLEN ,Channel length" "16-bit,32-bit"
|
|
endif
|
|
endif
|
|
if ((per.w((ad:0x40003C00+0x1C)))&0x700)==(0x600||0x700)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "I2SPR,I2S Prescaler Register"
|
|
bitfld.word 0x00 9. " MCKOE ,Master clock output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,(I2SDIV * 2)+1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S linear prescaler"
|
|
else
|
|
hgroup.word 0x20++0x01
|
|
hide.word 0x00 "I2SPR,I2S Prescaler Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif (!cpuis("STM32F72?R*")&&!cpuis("STM32F73?R*"))
|
|
tree "SPI 4"
|
|
base ad:0x40013400
|
|
width 8.
|
|
if ((per.w((ad:0x40013400))&0x40)==0x00)
|
|
if ((per.w((ad:0x40013400+0x04))&0x10)==0x00)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
newline
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB"
|
|
newline
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
else
|
|
if ((per.w((ad:0x40013400))&0x2000)==0x2000)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
newline
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
newline
|
|
bitfld.word 0x00 1. " CPOL ,Clock polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock phase" "First clock=first data,Second clock=first data"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
newline
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
endif
|
|
endif
|
|
else
|
|
if ((per.w((ad:0x40013400+0x04))&0x10)==0x00)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
rbitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
newline
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB"
|
|
newline
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
newline
|
|
else
|
|
if ((per.w((ad:0x40013400))&0x2000)==0x2000)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
rbitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
newline
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
newline
|
|
bitfld.word 0x00 1. " CPOL ,Clock polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock phase" "First clock=first data,Second clock=first data"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
rbitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
newline
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
endif
|
|
endif
|
|
endif
|
|
if ((per.w((ad:0x40013400))&0x40)==0x00)
|
|
if ((per.w((ad:0x40013400+0x04))&0x10)==0x00)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "CR2,SPI Control Register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
newline
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
newline
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Not masked"
|
|
newline
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
bitfld.word 0x00 3. " NSSP ,NSS pulse management" "Not generated,Generated"
|
|
newline
|
|
bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "CR2,SPI Control Register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
newline
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
newline
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,Rx buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Not masked"
|
|
newline
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if ((per.w((ad:0x40013400+0x04))&0x10)==0x00)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "CR2,SPI Control Register 2"
|
|
rbitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
rbitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
newline
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
newline
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Not masked"
|
|
newline
|
|
rbitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
rbitfld.word 0x00 3. " NSSP ,NSS pulse management" "Not generated,Generated"
|
|
newline
|
|
bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "CR2,SPI Control Register 2"
|
|
rbitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
rbitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
newline
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
newline
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,Rx buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Not masked"
|
|
newline
|
|
rbitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
newline
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "SR,SPI Status Register"
|
|
in
|
|
hgroup.word 0x0C++0x01
|
|
hide.word 0x00 "DR,SPI Data Register"
|
|
in
|
|
newline
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "CRCPR,SPI CRC Polynomial Register"
|
|
if (((per.l(ad:0x40013400))&0x80)==0x80)
|
|
hgroup.word 0x14++0x01
|
|
hide.word 0x00 "RXCRCR,SPI Rx CRC Register"
|
|
hgroup.word 0x18++0x01
|
|
hide.word 0x00 "TXCRCR,SPI Tx CRC Register"
|
|
else
|
|
if (((per.l(ad:0x40013400))&0x800)==0x800)
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "RXCRCR,SPI Rx CRC Register"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "TXCRCR,SPI Tx CRC Register"
|
|
else
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "RXCRCR,SPI Rx CRC Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " RXCRC ,Rx CRC register"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "TXCRCR,SPI Tx CRC Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TXCRC ,Tx CRC register"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F7??Z?")||cpuis("STM32F7??I?")||cpuis("STM32F7??B?")||cpuis("STM32F7??N?")||cpuis("STM32F7??A?")||cpuis("STM32F72*")||cpuis("STM32F73*"))
|
|
sif (!cpuis("STM32F72?R*")&&!cpuis("STM32F73?R*")&&!cpuis("STM32F72?V*")&&!cpuis("STM32F73?V*"))
|
|
tree "SPI 5"
|
|
base ad:0x40015000
|
|
width 8.
|
|
if ((per.w((ad:0x40015000))&0x40)==0x00)
|
|
if ((per.w((ad:0x40015000+0x04))&0x10)==0x00)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
newline
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB"
|
|
newline
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
else
|
|
if ((per.w((ad:0x40015000))&0x2000)==0x2000)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
newline
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
newline
|
|
bitfld.word 0x00 1. " CPOL ,Clock polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock phase" "First clock=first data,Second clock=first data"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
newline
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
endif
|
|
endif
|
|
else
|
|
if ((per.w((ad:0x40015000+0x04))&0x10)==0x00)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
rbitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
newline
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB"
|
|
newline
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
newline
|
|
else
|
|
if ((per.w((ad:0x40015000))&0x2000)==0x2000)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
rbitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
newline
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
newline
|
|
bitfld.word 0x00 1. " CPOL ,Clock polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock phase" "First clock=first data,Second clock=first data"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
rbitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
newline
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
endif
|
|
endif
|
|
endif
|
|
if ((per.w((ad:0x40015000))&0x40)==0x00)
|
|
if ((per.w((ad:0x40015000+0x04))&0x10)==0x00)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "CR2,SPI Control Register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
newline
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
newline
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Not masked"
|
|
newline
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
bitfld.word 0x00 3. " NSSP ,NSS pulse management" "Not generated,Generated"
|
|
newline
|
|
bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "CR2,SPI Control Register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
newline
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
newline
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,Rx buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Not masked"
|
|
newline
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if ((per.w((ad:0x40015000+0x04))&0x10)==0x00)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "CR2,SPI Control Register 2"
|
|
rbitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
rbitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
newline
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
newline
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Not masked"
|
|
newline
|
|
rbitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
rbitfld.word 0x00 3. " NSSP ,NSS pulse management" "Not generated,Generated"
|
|
newline
|
|
bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "CR2,SPI Control Register 2"
|
|
rbitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
rbitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
newline
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
newline
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,Rx buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Not masked"
|
|
newline
|
|
rbitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
newline
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "SR,SPI Status Register"
|
|
in
|
|
hgroup.word 0x0C++0x01
|
|
hide.word 0x00 "DR,SPI Data Register"
|
|
in
|
|
newline
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "CRCPR,SPI CRC Polynomial Register"
|
|
if (((per.l(ad:0x40015000))&0x80)==0x80)
|
|
hgroup.word 0x14++0x01
|
|
hide.word 0x00 "RXCRCR,SPI Rx CRC Register"
|
|
hgroup.word 0x18++0x01
|
|
hide.word 0x00 "TXCRCR,SPI Tx CRC Register"
|
|
else
|
|
if (((per.l(ad:0x40015000))&0x800)==0x800)
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "RXCRCR,SPI Rx CRC Register"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "TXCRCR,SPI Tx CRC Register"
|
|
else
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "RXCRCR,SPI Rx CRC Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " RXCRC ,Rx CRC register"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "TXCRCR,SPI Tx CRC Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TXCRC ,Tx CRC register"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
tree "SPI 6"
|
|
base ad:0x40015400
|
|
width 8.
|
|
if ((per.w((ad:0x40015400))&0x40)==0x00)
|
|
if ((per.w((ad:0x40015400+0x04))&0x10)==0x00)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
newline
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB"
|
|
newline
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
else
|
|
if ((per.w((ad:0x40015400))&0x2000)==0x2000)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
newline
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
newline
|
|
bitfld.word 0x00 1. " CPOL ,Clock polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock phase" "First clock=first data,Second clock=first data"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
newline
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
endif
|
|
endif
|
|
else
|
|
if ((per.w((ad:0x40015400+0x04))&0x10)==0x00)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
rbitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
newline
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB"
|
|
newline
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
newline
|
|
else
|
|
if ((per.w((ad:0x40015400))&0x2000)==0x2000)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
rbitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
newline
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
newline
|
|
bitfld.word 0x00 1. " CPOL ,Clock polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock phase" "First clock=first data,Second clock=first data"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
rbitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
newline
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
endif
|
|
endif
|
|
endif
|
|
if ((per.w((ad:0x40015400))&0x40)==0x00)
|
|
if ((per.w((ad:0x40015400+0x04))&0x10)==0x00)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "CR2,SPI Control Register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
newline
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
newline
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Not masked"
|
|
newline
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
bitfld.word 0x00 3. " NSSP ,NSS pulse management" "Not generated,Generated"
|
|
newline
|
|
bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "CR2,SPI Control Register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
newline
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
newline
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,Rx buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Not masked"
|
|
newline
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if ((per.w((ad:0x40015400+0x04))&0x10)==0x00)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "CR2,SPI Control Register 2"
|
|
rbitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
rbitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
newline
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
newline
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Not masked"
|
|
newline
|
|
rbitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
rbitfld.word 0x00 3. " NSSP ,NSS pulse management" "Not generated,Generated"
|
|
newline
|
|
bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "CR2,SPI Control Register 2"
|
|
rbitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
rbitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
newline
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
newline
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,Rx buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Not masked"
|
|
newline
|
|
rbitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
newline
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "SR,SPI Status Register"
|
|
in
|
|
hgroup.word 0x0C++0x01
|
|
hide.word 0x00 "DR,SPI Data Register"
|
|
in
|
|
newline
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "CRCPR,SPI CRC Polynomial Register"
|
|
if (((per.l(ad:0x40015400))&0x80)==0x80)
|
|
hgroup.word 0x14++0x01
|
|
hide.word 0x00 "RXCRCR,SPI Rx CRC Register"
|
|
hgroup.word 0x18++0x01
|
|
hide.word 0x00 "TXCRCR,SPI Tx CRC Register"
|
|
else
|
|
if (((per.l(ad:0x40015400))&0x800)==0x800)
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "RXCRCR,SPI Rx CRC Register"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "TXCRCR,SPI Tx CRC Register"
|
|
else
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "RXCRCR,SPI Rx CRC Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " RXCRC ,Rx CRC register"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "TXCRCR,SPI Tx CRC Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TXCRC ,Tx CRC register"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree.open "SAI (Serial Audio Interface)"
|
|
tree "SAI 1"
|
|
tree "Block A"
|
|
base ad:0x40015800
|
|
width 9.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GCR,Global Configuration Register"
|
|
bitfld.long 0x00 4.--5. " SYNCOUT ,Synchronization outputs" "No synchronization,Block A,Block B,?..."
|
|
bitfld.long 0x00 0.--1. " SYNCIN ,Synchronization inputs" ",SAI2 sync,?..."
|
|
if (((per.l(ad:0x40015800+0x04))&0x10000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1_A,SAI A Configuration Register 1"
|
|
bitfld.long 0x00 20.--23. " MCKDIV ,Master clock divider" "/1,/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15"
|
|
bitfld.long 0x00 19. " NODIV ,No divider" "No,Yes"
|
|
bitfld.long 0x00 17. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " SAIAEN ,Audio block enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " OUTDRIV ,Output drive" "On SAIAEN,Immediately"
|
|
bitfld.long 0x00 12. " MONO ,Mono mode" "Stereo,Mono"
|
|
bitfld.long 0x00 10.--11. " SYNCEN ,Synchronization enable" "Asynchronous,Synchronous (int),Synchronous (ext),?..."
|
|
newline
|
|
bitfld.long 0x00 9. " CKSTR ,Clock strobing edge" "Falling,Rising"
|
|
bitfld.long 0x00 8. " LSBFIRST ,Least significant bit first" "MSB,LSB"
|
|
bitfld.long 0x00 5.--7. " DS ,Data size" ",,8-bit,10-bit,16-bit,20-bit,24-bit,32-bit"
|
|
bitfld.long 0x00 2.--3. " PRTCFG ,Protocol configuration" "Free,SPDIF,AC97,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--1. " MODE ,Audio block mode" "Master transmitter,Master receiver,Slave transmitter,Slave receiver"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1_A,SAI A Configuration Register 1"
|
|
rbitfld.long 0x00 20.--23. " MCKDIV ,Master clock divider" "/1,/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15"
|
|
bitfld.long 0x00 19. " NODIV ,No divider" "No,Yes"
|
|
bitfld.long 0x00 17. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " SAIAEN ,Audio block enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " OUTDRIV ,Output drive" "On SAIAEN,Immediately"
|
|
bitfld.long 0x00 12. " MONO ,Mono mode" "Stereo,Mono"
|
|
rbitfld.long 0x00 10.--11. " SYNCEN ,Synchronization enable" "Asynchronous,Synchronous (int),Synchronous (ext),?..."
|
|
newline
|
|
rbitfld.long 0x00 9. " CKSTR ,Clock strobing edge" "Falling,Rising"
|
|
rbitfld.long 0x00 8. " LSBFIRST ,Least significant bit first" "MSB,LSB"
|
|
rbitfld.long 0x00 5.--7. " DS ,Data size" ",,8-bit,10-bit,16-bit,20-bit,24-bit,32-bit"
|
|
rbitfld.long 0x00 2.--3. " PRTCFG ,Protocol configuration" "Free,SPDIF,AC97,?..."
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " MODE ,Audio block mode" "Master transmitter,Master receiver,Slave transmitter,Slave receiver"
|
|
endif
|
|
if (((per.l(ad:0x40015800+0x04))&0x03)==(0x01||0x03))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR2_A,SAI A ConfIguration Register 2"
|
|
bitfld.long 0x00 14.--15. " COMP ,Companding mode" "No companding,,U-Law,A-Law"
|
|
bitfld.long 0x00 13. " CPL ,Complement bit" "1s complement,2s complement"
|
|
bitfld.long 0x00 7.--12. " MUTECNT ,Mute counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6. " MUTEVAL ,Mute value" "Bit value 0,Last values"
|
|
bitfld.long 0x00 5. " MUTE ,Mute" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRIS ,Tristate management on data line" "Driven,Released"
|
|
newline
|
|
bitfld.long 0x00 3. " FFLUSH ,FIFO flush" "Not flushed,Flushed"
|
|
bitfld.long 0x00 0.--2. " FTH ,FIFO threshold" "Empty,1/4 FIFO,1/2 FIFO,3/4 FIFO,Full,?..."
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR2_A,SAI A Configuration Register 2"
|
|
bitfld.long 0x00 14.--15. " COMP ,Companding mode" "No companding,,U-Law,A-Law"
|
|
bitfld.long 0x00 13. " CPL ,Complement bit" "1s complement,2s complement"
|
|
newline
|
|
bitfld.long 0x00 6. " MUTEVAL ,Mute value" "Bit value 0,Last values"
|
|
bitfld.long 0x00 5. " MUTE ,Mute" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRIS ,Tristate management on data line" "Driven,Released"
|
|
newline
|
|
bitfld.long 0x00 3. " FFLUSH ,FIFO flush" "Not flushed,Flushed"
|
|
bitfld.long 0x00 0.--2. " FTH ,FIFO threshold" "Empty,1/4 FIFO,1/2 FIFO,3/4 FIFO,Full,?..."
|
|
endif
|
|
if (((per.l(ad:0x40015800+0x04))&0x0C)!=(0x04||0x08))
|
|
if (((per.l(ad:0x40015800+0x04))&0x10000)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FRCR_A,Frame Configuration Register"
|
|
bitfld.long 0x00 18. " FSOFF ,Frame synchronization offset" "First bit,One bit before"
|
|
bitfld.long 0x00 17. " FSPOL ,Frame synchronization polarity" "Low/Falling,High/Rising"
|
|
rbitfld.long 0x00 16. " FSDEF ,Frame synchronization definition" "Start frame,Start frame+channel"
|
|
hexmask.long.byte 0x00 8.--14. 1. " FSALL ,Frame synchronization active level length"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " FRL ,Frame length"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FRCR_A,Frame Configuration Register"
|
|
rbitfld.long 0x00 18. " FSOFF ,Frame synchronization offset" "First bit,One bit before"
|
|
rbitfld.long 0x00 17. " FSPOL ,Frame synchronization polarity" "Low/Falling,High/Rising"
|
|
rbitfld.long 0x00 16. " FSDEF ,Frame synchronization definition" "Start frame,Start frame+channel"
|
|
hexmask.long.byte 0x00 8.--14. 1. " FSALL ,Frame synchronization active level length"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " FRL ,Frame length"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SLOTR_A,Slot Register"
|
|
bitfld.long 0x00 31. " SLOTEN[15] ,Slot 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [14] ,Slot 14 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [13] ,Slot 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [12] ,Slot 12 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " [11] ,Slot 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [10] ,Slot 10 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [9] ,Slot 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [8] ,Slot 8 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [7] ,Slot 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [6] ,Slot 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [5] ,Slot 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [4] ,Slot 4 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [3] ,Slot 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [2] ,Slot 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [1] ,Slot 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,Slot 0 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NBSLOT ,Number of slots in an audio frame" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 6.--7. " SLOTSZ ,Slot size" "Data size,16b,32b,?..."
|
|
bitfld.long 0x00 0.--4. " FBOFF ,First bit offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "FRCR_A,Frame Configuration Register"
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SLOTR_A,Slot Register"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "IM_A,SAI A Interrupt Mask Register 2"
|
|
bitfld.long 0x00 6. " LFSDETIE ,Late frame synchronization detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " AFSDETIE ,Anticipated frame synchronization detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CNRDYIE ,Codec not ready interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " FREQIE ,FIFO request interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " WCKCFGIE ,Wrong clock configuration interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MUTEDETIE ,Mute detection interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " OVRUDRIE ,Overrun/Underrun interrupt enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40015800+0x04))&0x01)==0x00)
|
|
if (((per.l(ad:0x40015800+0x04))&0x0C)==0x00)
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "SR_A,SAI A Status Register"
|
|
bitfld.long 0x00 16.--18. " FLVL ,FIFO level threshold" "Empty,FIFO <= 1/4,1/4 < FIFO <= 1/2,1/2 < FIFO <= 3/4,3/4 < FIFO,Full,?..."
|
|
bitfld.long 0x00 6. " LFSDET ,Late frame synchronization detection" "No error,Error"
|
|
bitfld.long 0x00 5. " AFSDET ,Anticipated frame synchronization detection" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct"
|
|
newline
|
|
bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error"
|
|
else
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "SR_A,SAI A Status Register"
|
|
bitfld.long 0x00 16.--18. " FLVL ,FIFO level threshold" "Empty,FIFO <= 1/4,1/4 < FIFO <= 1/2,1/2 < FIFO <= 3/4,3/4 < FIFO,Full,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct"
|
|
newline
|
|
bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015800+0x04))&0x0C)==0x00)
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "SR_A,SAI A Status Register"
|
|
bitfld.long 0x00 16.--18. " FLVL ,FIFO level threshold" "Empty,FIFO < 1/4,1/4 <= FIFO < 1/2,1/2 <= FIFO < 3/4,3/4 <= FIFO,Full,?..."
|
|
bitfld.long 0x00 6. " LFSDET ,Late frame synchronization detection" "No error,Error"
|
|
bitfld.long 0x00 5. " AFSDET ,Anticipated frame synchronization detection" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct"
|
|
newline
|
|
bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error"
|
|
elif (((per.l(ad:0x40015800+0x04))&0x0C)==0x08)
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "SR_A,SAI A Status Register"
|
|
bitfld.long 0x00 16.--18. " FLVL ,FIFO level threshold" "Empty,FIFO < 1/4,1/4 <= FIFO < 1/2,1/2 <= FIFO < 3/4,3/4 <= FIFO,Full,?..."
|
|
newline
|
|
bitfld.long 0x00 4. " CNRDY ,Codec not ready" "Ready,Not ready"
|
|
bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct"
|
|
newline
|
|
bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error"
|
|
else
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "SR_A,SAI A Status Register"
|
|
bitfld.long 0x00 16.--18. " FLVL ,FIFO level threshold" "Empty,FIFO < 1/4,1/4 <= FIFO < 1/2,1/2 <= FIFO < 3/4,3/4 <= FIFO,Full,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct"
|
|
newline
|
|
bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error"
|
|
endif
|
|
endif
|
|
if ((per.l((ad:0x40015800+0x04))&0x0C)==0x00)
|
|
if ((per.l(ad:0x40015800+0x04)&0x80003)==(0x00||0x01))
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "CLRFR_A,SAI A Clear Flag Register"
|
|
bitfld.long 0x00 6. " CLFSDET ,Clear late frame synchronization detection flag" "No effect,Clear"
|
|
bitfld.long 0x00 5. " CAFSDET ,Clear anticipated frame synchronization detection flag" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CWCKCFG ,Clear wrong clock configuration flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 1. " CMUTEDET ,Clear mute detection flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " COVRUDR ,Clear overrun/underrun" "No effect,Clear"
|
|
else
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "CLRFR_A,SAI A Clear Flag Register"
|
|
bitfld.long 0x00 6. " CLFSDET ,Clear late frame synchronization detection flag" "No effect,Clear"
|
|
bitfld.long 0x00 5. " CAFSDET ,Clear anticipated frame synchronization detection flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 1. " CMUTEDET ,Clear mute detection flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " COVRUDR ,Clear overrun/underrun" "No effect,Clear"
|
|
endif
|
|
elif ((per.l((ad:0x40015800+0x04))&0x0C)==0x08)
|
|
if ((per.l(ad:0x40015800+0x04)&0x80003)==(0x00||0x01))
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "CLRFR_A,SAI A Clear Flag Register"
|
|
bitfld.long 0x00 4. " CCNRDY ,Clear codec not ready flag" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CWCKCFG ,Clear wrong clock configuration flag" "No effect,Clear"
|
|
bitfld.long 0x00 1. " CMUTEDET ,Clear mute detection flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 0. " COVRUDR ,Clear overrun/underrun" "No effect,Clear"
|
|
else
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "CLRFR_A,SAI A Clear Flag Register"
|
|
bitfld.long 0x00 4. " CCNRDY ,Clear codec not ready flag" "No effect,Clear"
|
|
bitfld.long 0x00 1. " CMUTEDET ,Clear mute detection flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " COVRUDR ,Clear overrun/underrun" "No effect,Clear"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40015800+0x04)&0x80003)==(0x00||0x01))
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "CLRFR_A,SAI A Clear Flag Register"
|
|
bitfld.long 0x00 2. " CWCKCFG ,Clear wrong clock configuration flag" "No effect,Clear"
|
|
bitfld.long 0x00 1. " CMUTEDET ,Clear mute detection flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " COVRUDR ,Clear overrun/underrun" "No effect,Clear"
|
|
else
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "CLRFR_A,SAI A Clear Flag Register"
|
|
bitfld.long 0x00 1. " CMUTEDET ,Clear mute detection flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " COVRUDR ,Clear overrun/underrun" "No effect,Clear"
|
|
endif
|
|
endif
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "DR_A,SAI A Data Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Block B"
|
|
base ad:0x40015820
|
|
width 9.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GCR,Global Configuration Register"
|
|
bitfld.long 0x00 4.--5. " SYNCOUT ,Synchronization outputs" "No synchronization,Block A,Block B,?..."
|
|
bitfld.long 0x00 0.--1. " SYNCIN ,Synchronization inputs" ",SAI2 sync,?..."
|
|
if (((per.l(ad:0x40015820+0x04))&0x10000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1_B,SAI B Configuration Register 1"
|
|
bitfld.long 0x00 20.--23. " MCKDIV ,Master clock divider" "/1,/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15"
|
|
bitfld.long 0x00 19. " NODIV ,No divider" "No,Yes"
|
|
bitfld.long 0x00 17. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " SAIBEN ,Audio block enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " OUTDRIV ,Output drive" "On SAIBEN,Immediately"
|
|
bitfld.long 0x00 12. " MONO ,Mono mode" "Stereo,Mono"
|
|
bitfld.long 0x00 10.--11. " SYNCEN ,Synchronization enable" "Asynchronous,Synchronous (int),Synchronous (ext),?..."
|
|
newline
|
|
bitfld.long 0x00 9. " CKSTR ,Clock strobing edge" "Falling,Rising"
|
|
bitfld.long 0x00 8. " LSBFIRST ,Least significant bit first" "MSB,LSB"
|
|
bitfld.long 0x00 5.--7. " DS ,Data size" ",,8-bit,10-bit,16-bit,20-bit,24-bit,32-bit"
|
|
bitfld.long 0x00 2.--3. " PRTCFG ,Protocol configuration" "Free,SPDIF,AC97,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--1. " MODE ,Audio block mode" "Master transmitter,Master receiver,Slave transmitter,Slave receiver"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1_B,SAI B Configuration Register 1"
|
|
rbitfld.long 0x00 20.--23. " MCKDIV ,Master clock divider" "/1,/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15"
|
|
bitfld.long 0x00 19. " NODIV ,No divider" "No,Yes"
|
|
bitfld.long 0x00 17. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " SAIBEN ,Audio block enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " OUTDRIV ,Output drive" "On SAIBEN,Immediately"
|
|
bitfld.long 0x00 12. " MONO ,Mono mode" "Stereo,Mono"
|
|
rbitfld.long 0x00 10.--11. " SYNCEN ,Synchronization enable" "Asynchronous,Synchronous (int),Synchronous (ext),?..."
|
|
newline
|
|
rbitfld.long 0x00 9. " CKSTR ,Clock strobing edge" "Falling,Rising"
|
|
rbitfld.long 0x00 8. " LSBFIRST ,Least significant bit first" "MSB,LSB"
|
|
rbitfld.long 0x00 5.--7. " DS ,Data size" ",,8-bit,10-bit,16-bit,20-bit,24-bit,32-bit"
|
|
rbitfld.long 0x00 2.--3. " PRTCFG ,Protocol configuration" "Free,SPDIF,AC97,?..."
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " MODE ,Audio block mode" "Master transmitter,Master receiver,Slave transmitter,Slave receiver"
|
|
endif
|
|
if (((per.l(ad:0x40015820+0x04))&0x03)==(0x01||0x03))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR2_B,SAI B ConfIguration Register 2"
|
|
bitfld.long 0x00 14.--15. " COMP ,Companding mode" "No companding,,U-Law,A-Law"
|
|
bitfld.long 0x00 13. " CPL ,Complement bit" "1s complement,2s complement"
|
|
bitfld.long 0x00 7.--12. " MUTECNT ,Mute counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6. " MUTEVAL ,Mute value" "Bit value 0,Last values"
|
|
bitfld.long 0x00 5. " MUTE ,Mute" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRIS ,Tristate management on data line" "Driven,Released"
|
|
newline
|
|
bitfld.long 0x00 3. " FFLUSH ,FIFO flush" "Not flushed,Flushed"
|
|
bitfld.long 0x00 0.--2. " FTH ,FIFO threshold" "Empty,1/4 FIFO,1/2 FIFO,3/4 FIFO,Full,?..."
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR2_B,SAI B Configuration Register 2"
|
|
bitfld.long 0x00 14.--15. " COMP ,Companding mode" "No companding,,U-Law,A-Law"
|
|
bitfld.long 0x00 13. " CPL ,Complement bit" "1s complement,2s complement"
|
|
newline
|
|
bitfld.long 0x00 6. " MUTEVAL ,Mute value" "Bit value 0,Last values"
|
|
bitfld.long 0x00 5. " MUTE ,Mute" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRIS ,Tristate management on data line" "Driven,Released"
|
|
newline
|
|
bitfld.long 0x00 3. " FFLUSH ,FIFO flush" "Not flushed,Flushed"
|
|
bitfld.long 0x00 0.--2. " FTH ,FIFO threshold" "Empty,1/4 FIFO,1/2 FIFO,3/4 FIFO,Full,?..."
|
|
endif
|
|
if (((per.l(ad:0x40015820+0x04))&0x0C)!=(0x04||0x08))
|
|
if (((per.l(ad:0x40015820+0x04))&0x10000)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FRCR_B,Frame Configuration Register"
|
|
bitfld.long 0x00 18. " FSOFF ,Frame synchronization offset" "First bit,One bit before"
|
|
bitfld.long 0x00 17. " FSPOL ,Frame synchronization polarity" "Low/Falling,High/Rising"
|
|
rbitfld.long 0x00 16. " FSDEF ,Frame synchronization definition" "Start frame,Start frame+channel"
|
|
hexmask.long.byte 0x00 8.--14. 1. " FSALL ,Frame synchronization active level length"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " FRL ,Frame length"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FRCR_B,Frame Configuration Register"
|
|
rbitfld.long 0x00 18. " FSOFF ,Frame synchronization offset" "First bit,One bit before"
|
|
rbitfld.long 0x00 17. " FSPOL ,Frame synchronization polarity" "Low/Falling,High/Rising"
|
|
rbitfld.long 0x00 16. " FSDEF ,Frame synchronization definition" "Start frame,Start frame+channel"
|
|
hexmask.long.byte 0x00 8.--14. 1. " FSALL ,Frame synchronization active level length"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " FRL ,Frame length"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SLOTR_B,Slot Register"
|
|
bitfld.long 0x00 31. " SLOTEN[15] ,Slot 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [14] ,Slot 14 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [13] ,Slot 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [12] ,Slot 12 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " [11] ,Slot 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [10] ,Slot 10 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [9] ,Slot 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [8] ,Slot 8 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [7] ,Slot 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [6] ,Slot 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [5] ,Slot 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [4] ,Slot 4 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [3] ,Slot 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [2] ,Slot 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [1] ,Slot 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,Slot 0 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NBSLOT ,Number of slots in an audio frame" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 6.--7. " SLOTSZ ,Slot size" "Data size,16b,32b,?..."
|
|
bitfld.long 0x00 0.--4. " FBOFF ,First bit offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "FRCR_B,Frame Configuration Register"
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SLOTR_B,Slot Register"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "IM_B,SAI B Interrupt Mask Register 2"
|
|
bitfld.long 0x00 6. " LFSDETIE ,Late frame synchronization detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " AFSDETIE ,Anticipated frame synchronization detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CNRDYIE ,Codec not ready interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " FREQIE ,FIFO request interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " WCKCFGIE ,Wrong clock configuration interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MUTEDETIE ,Mute detection interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " OVRUDRIE ,Overrun/Underrun interrupt enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40015820+0x04))&0x01)==0x00)
|
|
if (((per.l(ad:0x40015820+0x04))&0x0C)==0x00)
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "SR_B,SAI B Status Register"
|
|
bitfld.long 0x00 16.--18. " FLVL ,FIFO level threshold" "Empty,FIFO <= 1/4,1/4 < FIFO <= 1/2,1/2 < FIFO <= 3/4,3/4 < FIFO,Full,?..."
|
|
bitfld.long 0x00 6. " LFSDET ,Late frame synchronization detection" "No error,Error"
|
|
bitfld.long 0x00 5. " AFSDET ,Anticipated frame synchronization detection" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct"
|
|
newline
|
|
bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error"
|
|
else
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "SR_B,SAI B Status Register"
|
|
bitfld.long 0x00 16.--18. " FLVL ,FIFO level threshold" "Empty,FIFO <= 1/4,1/4 < FIFO <= 1/2,1/2 < FIFO <= 3/4,3/4 < FIFO,Full,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct"
|
|
newline
|
|
bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015820+0x04))&0x0C)==0x00)
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "SR_B,SAI B Status Register"
|
|
bitfld.long 0x00 16.--18. " FLVL ,FIFO level threshold" "Empty,FIFO < 1/4,1/4 <= FIFO < 1/2,1/2 <= FIFO < 3/4,3/4 <= FIFO,Full,?..."
|
|
bitfld.long 0x00 6. " LFSDET ,Late frame synchronization detection" "No error,Error"
|
|
bitfld.long 0x00 5. " AFSDET ,Anticipated frame synchronization detection" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct"
|
|
newline
|
|
bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error"
|
|
elif (((per.l(ad:0x40015820+0x04))&0x0C)==0x08)
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "SR_B,SAI B Status Register"
|
|
bitfld.long 0x00 16.--18. " FLVL ,FIFO level threshold" "Empty,FIFO < 1/4,1/4 <= FIFO < 1/2,1/2 <= FIFO < 3/4,3/4 <= FIFO,Full,?..."
|
|
newline
|
|
bitfld.long 0x00 4. " CNRDY ,Codec not ready" "Ready,Not ready"
|
|
bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct"
|
|
newline
|
|
bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error"
|
|
else
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "SR_B,SAI B Status Register"
|
|
bitfld.long 0x00 16.--18. " FLVL ,FIFO level threshold" "Empty,FIFO < 1/4,1/4 <= FIFO < 1/2,1/2 <= FIFO < 3/4,3/4 <= FIFO,Full,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct"
|
|
newline
|
|
bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error"
|
|
endif
|
|
endif
|
|
if ((per.l((ad:0x40015820+0x04))&0x0C)==0x00)
|
|
if ((per.l(ad:0x40015820+0x04)&0x80003)==(0x00||0x01))
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "CLRFR_B,SAI B Clear Flag Register"
|
|
bitfld.long 0x00 6. " CLFSDET ,Clear late frame synchronization detection flag" "No effect,Clear"
|
|
bitfld.long 0x00 5. " CAFSDET ,Clear anticipated frame synchronization detection flag" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CWCKCFG ,Clear wrong clock configuration flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 1. " CMUTEDET ,Clear mute detection flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " COVRUDR ,Clear overrun/underrun" "No effect,Clear"
|
|
else
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "CLRFR_B,SAI B Clear Flag Register"
|
|
bitfld.long 0x00 6. " CLFSDET ,Clear late frame synchronization detection flag" "No effect,Clear"
|
|
bitfld.long 0x00 5. " CAFSDET ,Clear anticipated frame synchronization detection flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 1. " CMUTEDET ,Clear mute detection flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " COVRUDR ,Clear overrun/underrun" "No effect,Clear"
|
|
endif
|
|
elif ((per.l((ad:0x40015820+0x04))&0x0C)==0x08)
|
|
if ((per.l(ad:0x40015820+0x04)&0x80003)==(0x00||0x01))
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "CLRFR_B,SAI B Clear Flag Register"
|
|
bitfld.long 0x00 4. " CCNRDY ,Clear codec not ready flag" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CWCKCFG ,Clear wrong clock configuration flag" "No effect,Clear"
|
|
bitfld.long 0x00 1. " CMUTEDET ,Clear mute detection flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 0. " COVRUDR ,Clear overrun/underrun" "No effect,Clear"
|
|
else
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "CLRFR_B,SAI B Clear Flag Register"
|
|
bitfld.long 0x00 4. " CCNRDY ,Clear codec not ready flag" "No effect,Clear"
|
|
bitfld.long 0x00 1. " CMUTEDET ,Clear mute detection flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " COVRUDR ,Clear overrun/underrun" "No effect,Clear"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40015820+0x04)&0x80003)==(0x00||0x01))
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "CLRFR_B,SAI B Clear Flag Register"
|
|
bitfld.long 0x00 2. " CWCKCFG ,Clear wrong clock configuration flag" "No effect,Clear"
|
|
bitfld.long 0x00 1. " CMUTEDET ,Clear mute detection flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " COVRUDR ,Clear overrun/underrun" "No effect,Clear"
|
|
else
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "CLRFR_B,SAI B Clear Flag Register"
|
|
bitfld.long 0x00 1. " CMUTEDET ,Clear mute detection flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " COVRUDR ,Clear overrun/underrun" "No effect,Clear"
|
|
endif
|
|
endif
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "DR_B,SAI B Data Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "SAI 2"
|
|
tree "Block A"
|
|
base ad:0x40015C00
|
|
width 9.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GCR,Global Configuration Register"
|
|
bitfld.long 0x00 4.--5. " SYNCOUT ,Synchronization outputs" "No synchronization,Block A,Block B,?..."
|
|
bitfld.long 0x00 0.--1. " SYNCIN ,Synchronization inputs" "SAI1 sync,?..."
|
|
if (((per.l(ad:0x40015C00+0x04))&0x10000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1_A,SAI A Configuration Register 1"
|
|
bitfld.long 0x00 20.--23. " MCKDIV ,Master clock divider" "/1,/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15"
|
|
bitfld.long 0x00 19. " NODIV ,No divider" "No,Yes"
|
|
bitfld.long 0x00 17. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " SAIAEN ,Audio block enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " OUTDRIV ,Output drive" "On SAIAEN,Immediately"
|
|
bitfld.long 0x00 12. " MONO ,Mono mode" "Stereo,Mono"
|
|
bitfld.long 0x00 10.--11. " SYNCEN ,Synchronization enable" "Asynchronous,Synchronous (int),Synchronous (ext),?..."
|
|
newline
|
|
bitfld.long 0x00 9. " CKSTR ,Clock strobing edge" "Falling,Rising"
|
|
bitfld.long 0x00 8. " LSBFIRST ,Least significant bit first" "MSB,LSB"
|
|
bitfld.long 0x00 5.--7. " DS ,Data size" ",,8-bit,10-bit,16-bit,20-bit,24-bit,32-bit"
|
|
bitfld.long 0x00 2.--3. " PRTCFG ,Protocol configuration" "Free,SPDIF,AC97,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--1. " MODE ,Audio block mode" "Master transmitter,Master receiver,Slave transmitter,Slave receiver"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1_A,SAI A Configuration Register 1"
|
|
rbitfld.long 0x00 20.--23. " MCKDIV ,Master clock divider" "/1,/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15"
|
|
bitfld.long 0x00 19. " NODIV ,No divider" "No,Yes"
|
|
bitfld.long 0x00 17. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " SAIAEN ,Audio block enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " OUTDRIV ,Output drive" "On SAIAEN,Immediately"
|
|
bitfld.long 0x00 12. " MONO ,Mono mode" "Stereo,Mono"
|
|
rbitfld.long 0x00 10.--11. " SYNCEN ,Synchronization enable" "Asynchronous,Synchronous (int),Synchronous (ext),?..."
|
|
newline
|
|
rbitfld.long 0x00 9. " CKSTR ,Clock strobing edge" "Falling,Rising"
|
|
rbitfld.long 0x00 8. " LSBFIRST ,Least significant bit first" "MSB,LSB"
|
|
rbitfld.long 0x00 5.--7. " DS ,Data size" ",,8-bit,10-bit,16-bit,20-bit,24-bit,32-bit"
|
|
rbitfld.long 0x00 2.--3. " PRTCFG ,Protocol configuration" "Free,SPDIF,AC97,?..."
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " MODE ,Audio block mode" "Master transmitter,Master receiver,Slave transmitter,Slave receiver"
|
|
endif
|
|
if (((per.l(ad:0x40015C00+0x04))&0x03)==(0x01||0x03))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR2_A,SAI A ConfIguration Register 2"
|
|
bitfld.long 0x00 14.--15. " COMP ,Companding mode" "No companding,,U-Law,A-Law"
|
|
bitfld.long 0x00 13. " CPL ,Complement bit" "1s complement,2s complement"
|
|
bitfld.long 0x00 7.--12. " MUTECNT ,Mute counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6. " MUTEVAL ,Mute value" "Bit value 0,Last values"
|
|
bitfld.long 0x00 5. " MUTE ,Mute" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRIS ,Tristate management on data line" "Driven,Released"
|
|
newline
|
|
bitfld.long 0x00 3. " FFLUSH ,FIFO flush" "Not flushed,Flushed"
|
|
bitfld.long 0x00 0.--2. " FTH ,FIFO threshold" "Empty,1/4 FIFO,1/2 FIFO,3/4 FIFO,Full,?..."
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR2_A,SAI A Configuration Register 2"
|
|
bitfld.long 0x00 14.--15. " COMP ,Companding mode" "No companding,,U-Law,A-Law"
|
|
bitfld.long 0x00 13. " CPL ,Complement bit" "1s complement,2s complement"
|
|
newline
|
|
bitfld.long 0x00 6. " MUTEVAL ,Mute value" "Bit value 0,Last values"
|
|
bitfld.long 0x00 5. " MUTE ,Mute" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRIS ,Tristate management on data line" "Driven,Released"
|
|
newline
|
|
bitfld.long 0x00 3. " FFLUSH ,FIFO flush" "Not flushed,Flushed"
|
|
bitfld.long 0x00 0.--2. " FTH ,FIFO threshold" "Empty,1/4 FIFO,1/2 FIFO,3/4 FIFO,Full,?..."
|
|
endif
|
|
if (((per.l(ad:0x40015C00+0x04))&0x0C)!=(0x04||0x08))
|
|
if (((per.l(ad:0x40015C00+0x04))&0x10000)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FRCR_A,Frame Configuration Register"
|
|
bitfld.long 0x00 18. " FSOFF ,Frame synchronization offset" "First bit,One bit before"
|
|
bitfld.long 0x00 17. " FSPOL ,Frame synchronization polarity" "Low/Falling,High/Rising"
|
|
rbitfld.long 0x00 16. " FSDEF ,Frame synchronization definition" "Start frame,Start frame+channel"
|
|
hexmask.long.byte 0x00 8.--14. 1. " FSALL ,Frame synchronization active level length"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " FRL ,Frame length"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FRCR_A,Frame Configuration Register"
|
|
rbitfld.long 0x00 18. " FSOFF ,Frame synchronization offset" "First bit,One bit before"
|
|
rbitfld.long 0x00 17. " FSPOL ,Frame synchronization polarity" "Low/Falling,High/Rising"
|
|
rbitfld.long 0x00 16. " FSDEF ,Frame synchronization definition" "Start frame,Start frame+channel"
|
|
hexmask.long.byte 0x00 8.--14. 1. " FSALL ,Frame synchronization active level length"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " FRL ,Frame length"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SLOTR_A,Slot Register"
|
|
bitfld.long 0x00 31. " SLOTEN[15] ,Slot 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [14] ,Slot 14 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [13] ,Slot 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [12] ,Slot 12 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " [11] ,Slot 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [10] ,Slot 10 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [9] ,Slot 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [8] ,Slot 8 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [7] ,Slot 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [6] ,Slot 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [5] ,Slot 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [4] ,Slot 4 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [3] ,Slot 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [2] ,Slot 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [1] ,Slot 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,Slot 0 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NBSLOT ,Number of slots in an audio frame" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 6.--7. " SLOTSZ ,Slot size" "Data size,16b,32b,?..."
|
|
bitfld.long 0x00 0.--4. " FBOFF ,First bit offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "FRCR_A,Frame Configuration Register"
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SLOTR_A,Slot Register"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "IM_A,SAI A Interrupt Mask Register 2"
|
|
bitfld.long 0x00 6. " LFSDETIE ,Late frame synchronization detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " AFSDETIE ,Anticipated frame synchronization detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CNRDYIE ,Codec not ready interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " FREQIE ,FIFO request interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " WCKCFGIE ,Wrong clock configuration interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MUTEDETIE ,Mute detection interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " OVRUDRIE ,Overrun/Underrun interrupt enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40015C00+0x04))&0x01)==0x00)
|
|
if (((per.l(ad:0x40015C00+0x04))&0x0C)==0x00)
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "SR_A,SAI A Status Register"
|
|
bitfld.long 0x00 16.--18. " FLVL ,FIFO level threshold" "Empty,FIFO <= 1/4,1/4 < FIFO <= 1/2,1/2 < FIFO <= 3/4,3/4 < FIFO,Full,?..."
|
|
bitfld.long 0x00 6. " LFSDET ,Late frame synchronization detection" "No error,Error"
|
|
bitfld.long 0x00 5. " AFSDET ,Anticipated frame synchronization detection" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct"
|
|
newline
|
|
bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error"
|
|
else
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "SR_A,SAI A Status Register"
|
|
bitfld.long 0x00 16.--18. " FLVL ,FIFO level threshold" "Empty,FIFO <= 1/4,1/4 < FIFO <= 1/2,1/2 < FIFO <= 3/4,3/4 < FIFO,Full,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct"
|
|
newline
|
|
bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015C00+0x04))&0x0C)==0x00)
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "SR_A,SAI A Status Register"
|
|
bitfld.long 0x00 16.--18. " FLVL ,FIFO level threshold" "Empty,FIFO < 1/4,1/4 <= FIFO < 1/2,1/2 <= FIFO < 3/4,3/4 <= FIFO,Full,?..."
|
|
bitfld.long 0x00 6. " LFSDET ,Late frame synchronization detection" "No error,Error"
|
|
bitfld.long 0x00 5. " AFSDET ,Anticipated frame synchronization detection" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct"
|
|
newline
|
|
bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error"
|
|
elif (((per.l(ad:0x40015C00+0x04))&0x0C)==0x08)
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "SR_A,SAI A Status Register"
|
|
bitfld.long 0x00 16.--18. " FLVL ,FIFO level threshold" "Empty,FIFO < 1/4,1/4 <= FIFO < 1/2,1/2 <= FIFO < 3/4,3/4 <= FIFO,Full,?..."
|
|
newline
|
|
bitfld.long 0x00 4. " CNRDY ,Codec not ready" "Ready,Not ready"
|
|
bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct"
|
|
newline
|
|
bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error"
|
|
else
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "SR_A,SAI A Status Register"
|
|
bitfld.long 0x00 16.--18. " FLVL ,FIFO level threshold" "Empty,FIFO < 1/4,1/4 <= FIFO < 1/2,1/2 <= FIFO < 3/4,3/4 <= FIFO,Full,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct"
|
|
newline
|
|
bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error"
|
|
endif
|
|
endif
|
|
if ((per.l((ad:0x40015C00+0x04))&0x0C)==0x00)
|
|
if ((per.l(ad:0x40015C00+0x04)&0x80003)==(0x00||0x01))
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "CLRFR_A,SAI A Clear Flag Register"
|
|
bitfld.long 0x00 6. " CLFSDET ,Clear late frame synchronization detection flag" "No effect,Clear"
|
|
bitfld.long 0x00 5. " CAFSDET ,Clear anticipated frame synchronization detection flag" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CWCKCFG ,Clear wrong clock configuration flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 1. " CMUTEDET ,Clear mute detection flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " COVRUDR ,Clear overrun/underrun" "No effect,Clear"
|
|
else
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "CLRFR_A,SAI A Clear Flag Register"
|
|
bitfld.long 0x00 6. " CLFSDET ,Clear late frame synchronization detection flag" "No effect,Clear"
|
|
bitfld.long 0x00 5. " CAFSDET ,Clear anticipated frame synchronization detection flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 1. " CMUTEDET ,Clear mute detection flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " COVRUDR ,Clear overrun/underrun" "No effect,Clear"
|
|
endif
|
|
elif ((per.l((ad:0x40015C00+0x04))&0x0C)==0x08)
|
|
if ((per.l(ad:0x40015C00+0x04)&0x80003)==(0x00||0x01))
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "CLRFR_A,SAI A Clear Flag Register"
|
|
bitfld.long 0x00 4. " CCNRDY ,Clear codec not ready flag" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CWCKCFG ,Clear wrong clock configuration flag" "No effect,Clear"
|
|
bitfld.long 0x00 1. " CMUTEDET ,Clear mute detection flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 0. " COVRUDR ,Clear overrun/underrun" "No effect,Clear"
|
|
else
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "CLRFR_A,SAI A Clear Flag Register"
|
|
bitfld.long 0x00 4. " CCNRDY ,Clear codec not ready flag" "No effect,Clear"
|
|
bitfld.long 0x00 1. " CMUTEDET ,Clear mute detection flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " COVRUDR ,Clear overrun/underrun" "No effect,Clear"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40015C00+0x04)&0x80003)==(0x00||0x01))
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "CLRFR_A,SAI A Clear Flag Register"
|
|
bitfld.long 0x00 2. " CWCKCFG ,Clear wrong clock configuration flag" "No effect,Clear"
|
|
bitfld.long 0x00 1. " CMUTEDET ,Clear mute detection flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " COVRUDR ,Clear overrun/underrun" "No effect,Clear"
|
|
else
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "CLRFR_A,SAI A Clear Flag Register"
|
|
bitfld.long 0x00 1. " CMUTEDET ,Clear mute detection flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " COVRUDR ,Clear overrun/underrun" "No effect,Clear"
|
|
endif
|
|
endif
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "DR_A,SAI A Data Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Block B"
|
|
base ad:0x40015C20
|
|
width 9.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GCR,Global Configuration Register"
|
|
bitfld.long 0x00 4.--5. " SYNCOUT ,Synchronization outputs" "No synchronization,Block A,Block B,?..."
|
|
bitfld.long 0x00 0.--1. " SYNCIN ,Synchronization inputs" "SAI1 sync,?..."
|
|
if (((per.l(ad:0x40015C20+0x04))&0x10000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1_B,SAI B Configuration Register 1"
|
|
bitfld.long 0x00 20.--23. " MCKDIV ,Master clock divider" "/1,/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15"
|
|
bitfld.long 0x00 19. " NODIV ,No divider" "No,Yes"
|
|
bitfld.long 0x00 17. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " SAIBEN ,Audio block enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " OUTDRIV ,Output drive" "On SAIBEN,Immediately"
|
|
bitfld.long 0x00 12. " MONO ,Mono mode" "Stereo,Mono"
|
|
bitfld.long 0x00 10.--11. " SYNCEN ,Synchronization enable" "Asynchronous,Synchronous (int),Synchronous (ext),?..."
|
|
newline
|
|
bitfld.long 0x00 9. " CKSTR ,Clock strobing edge" "Falling,Rising"
|
|
bitfld.long 0x00 8. " LSBFIRST ,Least significant bit first" "MSB,LSB"
|
|
bitfld.long 0x00 5.--7. " DS ,Data size" ",,8-bit,10-bit,16-bit,20-bit,24-bit,32-bit"
|
|
bitfld.long 0x00 2.--3. " PRTCFG ,Protocol configuration" "Free,SPDIF,AC97,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--1. " MODE ,Audio block mode" "Master transmitter,Master receiver,Slave transmitter,Slave receiver"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR1_B,SAI B Configuration Register 1"
|
|
rbitfld.long 0x00 20.--23. " MCKDIV ,Master clock divider" "/1,/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15"
|
|
bitfld.long 0x00 19. " NODIV ,No divider" "No,Yes"
|
|
bitfld.long 0x00 17. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " SAIBEN ,Audio block enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " OUTDRIV ,Output drive" "On SAIBEN,Immediately"
|
|
bitfld.long 0x00 12. " MONO ,Mono mode" "Stereo,Mono"
|
|
rbitfld.long 0x00 10.--11. " SYNCEN ,Synchronization enable" "Asynchronous,Synchronous (int),Synchronous (ext),?..."
|
|
newline
|
|
rbitfld.long 0x00 9. " CKSTR ,Clock strobing edge" "Falling,Rising"
|
|
rbitfld.long 0x00 8. " LSBFIRST ,Least significant bit first" "MSB,LSB"
|
|
rbitfld.long 0x00 5.--7. " DS ,Data size" ",,8-bit,10-bit,16-bit,20-bit,24-bit,32-bit"
|
|
rbitfld.long 0x00 2.--3. " PRTCFG ,Protocol configuration" "Free,SPDIF,AC97,?..."
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " MODE ,Audio block mode" "Master transmitter,Master receiver,Slave transmitter,Slave receiver"
|
|
endif
|
|
if (((per.l(ad:0x40015C20+0x04))&0x03)==(0x01||0x03))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR2_B,SAI B ConfIguration Register 2"
|
|
bitfld.long 0x00 14.--15. " COMP ,Companding mode" "No companding,,U-Law,A-Law"
|
|
bitfld.long 0x00 13. " CPL ,Complement bit" "1s complement,2s complement"
|
|
bitfld.long 0x00 7.--12. " MUTECNT ,Mute counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6. " MUTEVAL ,Mute value" "Bit value 0,Last values"
|
|
bitfld.long 0x00 5. " MUTE ,Mute" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRIS ,Tristate management on data line" "Driven,Released"
|
|
newline
|
|
bitfld.long 0x00 3. " FFLUSH ,FIFO flush" "Not flushed,Flushed"
|
|
bitfld.long 0x00 0.--2. " FTH ,FIFO threshold" "Empty,1/4 FIFO,1/2 FIFO,3/4 FIFO,Full,?..."
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR2_B,SAI B Configuration Register 2"
|
|
bitfld.long 0x00 14.--15. " COMP ,Companding mode" "No companding,,U-Law,A-Law"
|
|
bitfld.long 0x00 13. " CPL ,Complement bit" "1s complement,2s complement"
|
|
newline
|
|
bitfld.long 0x00 6. " MUTEVAL ,Mute value" "Bit value 0,Last values"
|
|
bitfld.long 0x00 5. " MUTE ,Mute" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRIS ,Tristate management on data line" "Driven,Released"
|
|
newline
|
|
bitfld.long 0x00 3. " FFLUSH ,FIFO flush" "Not flushed,Flushed"
|
|
bitfld.long 0x00 0.--2. " FTH ,FIFO threshold" "Empty,1/4 FIFO,1/2 FIFO,3/4 FIFO,Full,?..."
|
|
endif
|
|
if (((per.l(ad:0x40015C20+0x04))&0x0C)!=(0x04||0x08))
|
|
if (((per.l(ad:0x40015C20+0x04))&0x10000)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FRCR_B,Frame Configuration Register"
|
|
bitfld.long 0x00 18. " FSOFF ,Frame synchronization offset" "First bit,One bit before"
|
|
bitfld.long 0x00 17. " FSPOL ,Frame synchronization polarity" "Low/Falling,High/Rising"
|
|
rbitfld.long 0x00 16. " FSDEF ,Frame synchronization definition" "Start frame,Start frame+channel"
|
|
hexmask.long.byte 0x00 8.--14. 1. " FSALL ,Frame synchronization active level length"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " FRL ,Frame length"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FRCR_B,Frame Configuration Register"
|
|
rbitfld.long 0x00 18. " FSOFF ,Frame synchronization offset" "First bit,One bit before"
|
|
rbitfld.long 0x00 17. " FSPOL ,Frame synchronization polarity" "Low/Falling,High/Rising"
|
|
rbitfld.long 0x00 16. " FSDEF ,Frame synchronization definition" "Start frame,Start frame+channel"
|
|
hexmask.long.byte 0x00 8.--14. 1. " FSALL ,Frame synchronization active level length"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " FRL ,Frame length"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SLOTR_B,Slot Register"
|
|
bitfld.long 0x00 31. " SLOTEN[15] ,Slot 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [14] ,Slot 14 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [13] ,Slot 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [12] ,Slot 12 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " [11] ,Slot 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [10] ,Slot 10 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [9] ,Slot 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [8] ,Slot 8 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [7] ,Slot 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [6] ,Slot 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [5] ,Slot 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [4] ,Slot 4 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [3] ,Slot 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [2] ,Slot 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [1] ,Slot 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,Slot 0 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " NBSLOT ,Number of slots in an audio frame" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 6.--7. " SLOTSZ ,Slot size" "Data size,16b,32b,?..."
|
|
bitfld.long 0x00 0.--4. " FBOFF ,First bit offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "FRCR_B,Frame Configuration Register"
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SLOTR_B,Slot Register"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "IM_B,SAI B Interrupt Mask Register 2"
|
|
bitfld.long 0x00 6. " LFSDETIE ,Late frame synchronization detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " AFSDETIE ,Anticipated frame synchronization detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CNRDYIE ,Codec not ready interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " FREQIE ,FIFO request interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " WCKCFGIE ,Wrong clock configuration interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MUTEDETIE ,Mute detection interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " OVRUDRIE ,Overrun/Underrun interrupt enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40015C20+0x04))&0x01)==0x00)
|
|
if (((per.l(ad:0x40015C20+0x04))&0x0C)==0x00)
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "SR_B,SAI B Status Register"
|
|
bitfld.long 0x00 16.--18. " FLVL ,FIFO level threshold" "Empty,FIFO <= 1/4,1/4 < FIFO <= 1/2,1/2 < FIFO <= 3/4,3/4 < FIFO,Full,?..."
|
|
bitfld.long 0x00 6. " LFSDET ,Late frame synchronization detection" "No error,Error"
|
|
bitfld.long 0x00 5. " AFSDET ,Anticipated frame synchronization detection" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct"
|
|
newline
|
|
bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error"
|
|
else
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "SR_B,SAI B Status Register"
|
|
bitfld.long 0x00 16.--18. " FLVL ,FIFO level threshold" "Empty,FIFO <= 1/4,1/4 < FIFO <= 1/2,1/2 < FIFO <= 3/4,3/4 < FIFO,Full,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct"
|
|
newline
|
|
bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40015C20+0x04))&0x0C)==0x00)
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "SR_B,SAI B Status Register"
|
|
bitfld.long 0x00 16.--18. " FLVL ,FIFO level threshold" "Empty,FIFO < 1/4,1/4 <= FIFO < 1/2,1/2 <= FIFO < 3/4,3/4 <= FIFO,Full,?..."
|
|
bitfld.long 0x00 6. " LFSDET ,Late frame synchronization detection" "No error,Error"
|
|
bitfld.long 0x00 5. " AFSDET ,Anticipated frame synchronization detection" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct"
|
|
newline
|
|
bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error"
|
|
elif (((per.l(ad:0x40015C20+0x04))&0x0C)==0x08)
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "SR_B,SAI B Status Register"
|
|
bitfld.long 0x00 16.--18. " FLVL ,FIFO level threshold" "Empty,FIFO < 1/4,1/4 <= FIFO < 1/2,1/2 <= FIFO < 3/4,3/4 <= FIFO,Full,?..."
|
|
newline
|
|
bitfld.long 0x00 4. " CNRDY ,Codec not ready" "Ready,Not ready"
|
|
bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct"
|
|
newline
|
|
bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error"
|
|
else
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "SR_B,SAI B Status Register"
|
|
bitfld.long 0x00 16.--18. " FLVL ,FIFO level threshold" "Empty,FIFO < 1/4,1/4 <= FIFO < 1/2,1/2 <= FIFO < 3/4,3/4 <= FIFO,Full,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct"
|
|
newline
|
|
bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error"
|
|
endif
|
|
endif
|
|
if ((per.l((ad:0x40015C20+0x04))&0x0C)==0x00)
|
|
if ((per.l(ad:0x40015C20+0x04)&0x80003)==(0x00||0x01))
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "CLRFR_B,SAI B Clear Flag Register"
|
|
bitfld.long 0x00 6. " CLFSDET ,Clear late frame synchronization detection flag" "No effect,Clear"
|
|
bitfld.long 0x00 5. " CAFSDET ,Clear anticipated frame synchronization detection flag" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CWCKCFG ,Clear wrong clock configuration flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 1. " CMUTEDET ,Clear mute detection flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " COVRUDR ,Clear overrun/underrun" "No effect,Clear"
|
|
else
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "CLRFR_B,SAI B Clear Flag Register"
|
|
bitfld.long 0x00 6. " CLFSDET ,Clear late frame synchronization detection flag" "No effect,Clear"
|
|
bitfld.long 0x00 5. " CAFSDET ,Clear anticipated frame synchronization detection flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 1. " CMUTEDET ,Clear mute detection flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " COVRUDR ,Clear overrun/underrun" "No effect,Clear"
|
|
endif
|
|
elif ((per.l((ad:0x40015C20+0x04))&0x0C)==0x08)
|
|
if ((per.l(ad:0x40015C20+0x04)&0x80003)==(0x00||0x01))
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "CLRFR_B,SAI B Clear Flag Register"
|
|
bitfld.long 0x00 4. " CCNRDY ,Clear codec not ready flag" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CWCKCFG ,Clear wrong clock configuration flag" "No effect,Clear"
|
|
bitfld.long 0x00 1. " CMUTEDET ,Clear mute detection flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 0. " COVRUDR ,Clear overrun/underrun" "No effect,Clear"
|
|
else
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "CLRFR_B,SAI B Clear Flag Register"
|
|
bitfld.long 0x00 4. " CCNRDY ,Clear codec not ready flag" "No effect,Clear"
|
|
bitfld.long 0x00 1. " CMUTEDET ,Clear mute detection flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " COVRUDR ,Clear overrun/underrun" "No effect,Clear"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40015C20+0x04)&0x80003)==(0x00||0x01))
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "CLRFR_B,SAI B Clear Flag Register"
|
|
bitfld.long 0x00 2. " CWCKCFG ,Clear wrong clock configuration flag" "No effect,Clear"
|
|
bitfld.long 0x00 1. " CMUTEDET ,Clear mute detection flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " COVRUDR ,Clear overrun/underrun" "No effect,Clear"
|
|
else
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "CLRFR_B,SAI B Clear Flag Register"
|
|
bitfld.long 0x00 1. " CMUTEDET ,Clear mute detection flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " COVRUDR ,Clear overrun/underrun" "No effect,Clear"
|
|
endif
|
|
endif
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "DR_B,SAI B Data Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
sif (!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
tree "SPDIFRX (SPDIF Receiver Interface)"
|
|
base ad:0x40004000
|
|
width 6.
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32F767BI"))
|
|
if (((per.l(ad:0x40004000))&0x03)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 21. " CKSBKPEN ,Backup symbol clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CKSEN ,Symbol clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " INSEL ,SPDIFRX input selection" "IN1,IN2,IN3,IN4,?..."
|
|
newline
|
|
bitfld.long 0x00 14. " WFA ,Wait for activity" "No,Yes"
|
|
bitfld.long 0x00 12.--13. " NBTR ,Maximum allowed re-tries during synchronization phase" "0,3,15,63"
|
|
bitfld.long 0x00 11. " CHSEL ,Channel selection" "Channel A,Channel B"
|
|
newline
|
|
bitfld.long 0x00 10. " CBDMAEN ,Control buffer DMA enable for control flow" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PTMSK ,Mask of preamble type bits" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " CUMSK ,Mask of channel status and user bits" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 7. " VMSK ,Mask of validity bit" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " PMSK ,Mask parity error bit" "Not masked,Masked"
|
|
bitfld.long 0x00 4.--5. " DRFMT ,RX data format" "LSB,MSB,32-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " RXSTEO ,Stereo mode" "MONO,STEREO"
|
|
bitfld.long 0x00 2. " RXDMAEN ,Receiver DMA enable for data flow" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " SPDIFRXEN ,Peripheral block enable" "Disabled,Enabled SPDIFRX synchronization,,Enabled SPDIF receiver"
|
|
elif (((per.l(ad:0x40004000))&0x03)==0x01)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 21. " CKSBKPEN ,Backup symbol clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CKSEN ,Symbol clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " INSEL ,SPDIFRX input selection" "IN1,IN2,IN3,IN4,?..."
|
|
newline
|
|
rbitfld.long 0x00 14. " WFA ,Wait for activity" "No,Yes"
|
|
rbitfld.long 0x00 12.--13. " NBTR ,Maximum allowed re-tries during synchronization phase" "0,3,15,63"
|
|
rbitfld.long 0x00 11. " CHSEL ,Channel selection" "Channel A,Channel B"
|
|
newline
|
|
bitfld.long 0x00 10. " CBDMAEN ,Control buffer DMA enable for control flow" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PTMSK ,Mask of preamble type bits" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " CUMSK ,Mask of channel status and user bits" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 7. " VMSK ,Mask of validity bit" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " PMSK ,Mask parity error bit" "Not masked,Masked"
|
|
bitfld.long 0x00 4.--5. " DRFMT ,RX data format" "LSB,MSB,32-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " RXSTEO ,Stereo mode" "MONO,STEREO"
|
|
bitfld.long 0x00 2. " RXDMAEN ,Receiver DMA enable for data flow" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " SPDIFRXEN ,Peripheral block enable" "Disabled,Enabled SPDIFRX synchronization,,Enabled SPDIF receiver"
|
|
elif (((per.l(ad:0x40004000))&0x03)==0x03)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 21. " CKSBKPEN ,Backup symbol clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CKSEN ,Symbol clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " INSEL ,SPDIFRX input selection" "IN1,IN2,IN3,IN4,?..."
|
|
newline
|
|
rbitfld.long 0x00 14. " WFA ,Wait for activity" "No,Yes"
|
|
rbitfld.long 0x00 12.--13. " NBTR ,Maximum allowed re-tries during synchronization phase" "0,3,15,63"
|
|
rbitfld.long 0x00 11. " CHSEL ,Channel selection" "Channel A,Channel B"
|
|
newline
|
|
bitfld.long 0x00 10. " CBDMAEN ,Control buffer DMA enable for control flow" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PTMSK ,Mask of preamble type bits" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " CUMSK ,Mask of channel status and user bits" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 7. " VMSK ,Mask of validity bit" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " PMSK ,Mask parity error bit" "Not masked,Masked"
|
|
rbitfld.long 0x00 4.--5. " DRFMT ,RX data format" "LSB,MSB,32-bit,?..."
|
|
newline
|
|
rbitfld.long 0x00 3. " RXSTEO ,Stereo mode" "MONO,STEREO"
|
|
bitfld.long 0x00 2. " RXDMAEN ,Receiver DMA enable for data flow" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " SPDIFRXEN ,Peripheral block enable" "Disabled,Enabled SPDIFRX synchronization,,Enabled SPDIF receiver"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 21. " CKSBKPEN ,Backup symbol clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CKSEN ,Symbol clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " SPDIFRXEN ,Peripheral block enable" "Disabled,Enabled SPDIFRX synchronization,,Enabled SPDIF receiver"
|
|
endif
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 16.--18. " INSEL ,SPDIFRX input selection" "IN1,IN2,IN3,IN4,?..."
|
|
bitfld.long 0x00 14. " WFA ,Wait for activity" "No,Yes"
|
|
bitfld.long 0x00 12.--13. " NBTR ,Maximum allowed re-tries during synchronization phase" "0,3,15,63"
|
|
newline
|
|
bitfld.long 0x00 11. " CHSEL ,Channel selection" "Channel A,Channel B"
|
|
bitfld.long 0x00 10. " CBDMAEN ,Control buffer DMA enable for control flow" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PTMSK ,Mask of preamble type bits" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 8. " CUMSK ,Mask of channel status and user bits" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " VMSK ,Mask of validity bit" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " PMSK ,Mask parity error bit" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " DRFMT ,RX data format" "LSB,MSB,2*16-bit -> 32-bit,?..."
|
|
bitfld.long 0x00 3. " RXSTEO ,Stereo mode" "MONO,STEREO"
|
|
bitfld.long 0x00 2. " RXDMAEN ,Receiver DMA enable for data flow" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " SPDIFRXEN ,Peripheral block enable" "Disabled,Enabled SPDIFRX synchronization,,Enabled SPDIF receiver"
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x00 6. " IFEIE ,Serial interface error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SYNCDIE ,Synchronization done interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SBLKIE ,Synchronization block detected interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " OVRIE ,Overrun error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PERRIE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CSRNEIE ,Control buffer ready interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
hexmask.long.word 0x00 16.--30. 1. " WIDTH5 ,Duration of 5 symbols counted with CLK"
|
|
bitfld.long 0x00 8. " TERR ,Time-out error" "No error,Error"
|
|
bitfld.long 0x00 7. " SERR ,Synchronization error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 6. " FERR ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 5. " SYNCD ,Synchronization done" "Not completed,Completed"
|
|
bitfld.long 0x00 4. " SBD ,Synchronization block detected" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 3. " OVR ,Overrun error" "No overrun,Overrun"
|
|
bitfld.long 0x00 2. " PERR ,Parity error" "No error,Error"
|
|
bitfld.long 0x00 1. " CSRNE ,The control buffer register is not empty" "Empty,Not empty"
|
|
newline
|
|
bitfld.long 0x00 0. " RXNE ,Read data register not empty" "Empty,Not empty"
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "IFCR,Interrupt Flag Clear Register"
|
|
bitfld.long 0x00 5. " SYNCDCF ,Clears the synchronization done flag" "No effect,Clear"
|
|
bitfld.long 0x00 4. " SBDCF ,Clears the synchronization block detected flag" "No effect,Clear"
|
|
bitfld.long 0x00 3. " OVRCF ,Clears the overrun error flag" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 2. " PERRCF ,Clears the parity error flag" "No effect,Clear"
|
|
if ((per.l(ad:0x40004000)&0x30)==0x00)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "DR,Data Input Register"
|
|
bitfld.long 0x00 28.--29. " PT ,Preamble type received" "Not used,Preamble B,Preamble M,Preamble W"
|
|
bitfld.long 0x00 27. " C ,Channel status bit" "0,1"
|
|
bitfld.long 0x00 26. " U ,User bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. " V ,Validity bit" "0,1"
|
|
bitfld.long 0x00 24. " PE ,Parity error bit" "0,1"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " DR ,Data value"
|
|
elif ((per.l(ad:0x40004000)&0x30)==0x10)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "DR,Data Input Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " DR ,Data value"
|
|
bitfld.long 0x00 4.--5. " PT ,Preamble type received" "Not used,Preamble B,Preamble M,Preamble W"
|
|
bitfld.long 0x00 3. " C ,Channel status bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. " U ,User bit" "0,1"
|
|
bitfld.long 0x00 1. " V ,Validity bit" "0,1"
|
|
bitfld.long 0x00 0. " PE ,Parity error bit" "0,1"
|
|
elif ((per.l(ad:0x40004000)&0x30)==0x20)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "DR,Data Input Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DRNL2 ,Data value (Channel A)"
|
|
hexmask.long.word 0x00 0.--15. 1. " DRNL1 ,Data value (Channel B)"
|
|
endif
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "CSR,Channel Status Register"
|
|
bitfld.long 0x00 24. " SOB ,Start of block (CS[0] correspond)" "Not first,First"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CS ,Channel A status information"
|
|
hexmask.long.word 0x00 0.--15. 1. " USR ,User data information"
|
|
line.long 0x04 "DIR,Debug Information Register"
|
|
hexmask.long.word 0x04 16.--28. 1. " TLO ,Threshold LOW"
|
|
hexmask.long.word 0x04 0.--12. 1. " THI ,Threshold HIGH"
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
rgroup.long 0x3F4++0x0B
|
|
line.long 0x00 "VERR,SPDIFRX Version Register"
|
|
bitfld.long 0x00 4.--7. " MAJREV ,Major revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " MINREV ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "IDR,SPDIFRX Identification Register"
|
|
line.long 0x08 "SIDR,SPDIFRX Size Identification Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
tree "MDIO"
|
|
base ad:0x40017800
|
|
width 13.
|
|
if ((per.l(ad:0x40017800)&0x01)==0x01)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MDIOS_CR,MDIOS Configuration Register"
|
|
hexmask.long.byte 0x00 8.--12. 0x01 " PORT_ADDRESS ,Slave's address"
|
|
rbitfld.long 0x00 7. " DPC ,Disable preamble check" "No,Yes"
|
|
bitfld.long 0x00 3. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RDIE ,Register read interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " WRIE ,Register write interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Peripheral enable" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MDIOS_CR,MDIOS Configuration Register"
|
|
hexmask.long.byte 0x00 8.--12. 0x01 " PORT_ADDRESS ,Slave's address"
|
|
bitfld.long 0x00 7. " DPC ,Disable preamble check" "No,Yes"
|
|
bitfld.long 0x00 3. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RDIE ,Register read interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " WRIE ,Register write interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Peripheral enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MDIOS_WRFR,MDIOS Write Flag Register"
|
|
bitfld.long 0x00 31. " WRF[31] ,MDIO register 31 write flag" "No write,Write"
|
|
bitfld.long 0x00 30. " [30] ,MDIO register 30 write flag" "No write,Write"
|
|
bitfld.long 0x00 29. " [29] ,MDIO register 29 write flag" "No write,Write"
|
|
bitfld.long 0x00 28. " [28] ,MDIO register 28 write flag" "No write,Write"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,MDIO register 27 write flag" "No write,Write"
|
|
bitfld.long 0x00 26. " [26] ,MDIO register 26 write flag" "No write,Write"
|
|
bitfld.long 0x00 25. " [25] ,MDIO register 25 write flag" "No write,Write"
|
|
bitfld.long 0x00 24. " [24] ,MDIO register 24 write flag" "No write,Write"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,MDIO register 23 write flag" "No write,Write"
|
|
bitfld.long 0x00 22. " [22] ,MDIO register 22 write flag" "No write,Write"
|
|
bitfld.long 0x00 21. " [21] ,MDIO register 21 write flag" "No write,Write"
|
|
bitfld.long 0x00 20. " [20] ,MDIO register 20 write flag" "No write,Write"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,MDIO register 19 write flag" "No write,Write"
|
|
bitfld.long 0x00 18. " [18] ,MDIO register 18 write flag" "No write,Write"
|
|
bitfld.long 0x00 17. " [17] ,MDIO register 17 write flag" "No write,Write"
|
|
bitfld.long 0x00 16. " [16] ,MDIO register 16 write flag" "No write,Write"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,MDIO register 15 write flag" "No write,Write"
|
|
bitfld.long 0x00 14. " [14] ,MDIO register 14 write flag" "No write,Write"
|
|
bitfld.long 0x00 13. " [13] ,MDIO register 13 write flag" "No write,Write"
|
|
bitfld.long 0x00 12. " [12] ,MDIO register 12 write flag" "No write,Write"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,MDIO register 11 write flag" "No write,Write"
|
|
bitfld.long 0x00 10. " [10] ,MDIO register 10 write flag" "No write,Write"
|
|
bitfld.long 0x00 9. " [9] ,MDIO register 9 write flag" "No write,Write"
|
|
bitfld.long 0x00 8. " [8] ,MDIO register 8 write flag" "No write,Write"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,MDIO register 7 write flag" "No write,Write"
|
|
bitfld.long 0x00 6. " [6] ,MDIO register 6 write flag" "No write,Write"
|
|
bitfld.long 0x00 5. " [5] ,MDIO register 5 write flag" "No write,Write"
|
|
bitfld.long 0x00 4. " [4] ,MDIO register 4 write flag" "No write,Write"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,MDIO register 3 write flag" "No write,Write"
|
|
bitfld.long 0x00 2. " [2] ,MDIO register 2 write flag" "No write,Write"
|
|
bitfld.long 0x00 1. " [1] ,MDIO register 1 write flag" "No write,Write"
|
|
bitfld.long 0x00 0. " [0] ,MDIO register 0 write flag" "No write,Write"
|
|
newline
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "MDIOS_CWRFR,MDIOS Clear Write Flag Register"
|
|
eventfld.long 0x00 31. " CWRF[31] ,Clear MDIO register 31 write flag" "No effect,Clear"
|
|
eventfld.long 0x00 30. " [30] ,Clear MDIO register 30 write flag" "No effect,Clear"
|
|
eventfld.long 0x00 29. " [29] ,Clear MDIO register 29 write flag" "No effect,Clear"
|
|
eventfld.long 0x00 28. " [28] ,Clear MDIO register 28 write flag" "No effect,Clear"
|
|
newline
|
|
eventfld.long 0x00 27. " [27] ,Clear MDIO register 27 write flag" "No effect,Clear"
|
|
eventfld.long 0x00 26. " [26] ,Clear MDIO register 26 write flag" "No effect,Clear"
|
|
eventfld.long 0x00 25. " [25] ,Clear MDIO register 25 write flag" "No effect,Clear"
|
|
eventfld.long 0x00 24. " [24] ,Clear MDIO register 24 write flag" "No effect,Clear"
|
|
newline
|
|
eventfld.long 0x00 23. " [23] ,Clear MDIO register 23 write flag" "No effect,Clear"
|
|
eventfld.long 0x00 22. " [22] ,Clear MDIO register 22 write flag" "No effect,Clear"
|
|
eventfld.long 0x00 21. " [21] ,Clear MDIO register 21 write flag" "No effect,Clear"
|
|
eventfld.long 0x00 20. " [20] ,Clear MDIO register 20 write flag" "No effect,Clear"
|
|
newline
|
|
eventfld.long 0x00 19. " [19] ,Clear MDIO register 19 write flag" "No effect,Clear"
|
|
eventfld.long 0x00 18. " [18] ,Clear MDIO register 18 write flag" "No effect,Clear"
|
|
eventfld.long 0x00 17. " [17] ,Clear MDIO register 17 write flag" "No effect,Clear"
|
|
eventfld.long 0x00 16. " [16] ,Clear MDIO register 16 write flag" "No effect,Clear"
|
|
newline
|
|
eventfld.long 0x00 15. " [15] ,Clear MDIO register 15 write flag" "No effect,Clear"
|
|
eventfld.long 0x00 14. " [14] ,Clear MDIO register 14 write flag" "No effect,Clear"
|
|
eventfld.long 0x00 13. " [13] ,Clear MDIO register 13 write flag" "No effect,Clear"
|
|
eventfld.long 0x00 12. " [12] ,Clear MDIO register 12 write flag" "No effect,Clear"
|
|
newline
|
|
eventfld.long 0x00 11. " [11] ,Clear MDIO register 11 write flag" "No effect,Clear"
|
|
eventfld.long 0x00 10. " [10] ,Clear MDIO register 10 write flag" "No effect,Clear"
|
|
eventfld.long 0x00 9. " [9] ,Clear MDIO register 9 write flag" "No effect,Clear"
|
|
eventfld.long 0x00 8. " [8] ,Clear MDIO register 8 write flag" "No effect,Clear"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,Clear MDIO register 7 write flag" "No effect,Clear"
|
|
eventfld.long 0x00 6. " [6] ,Clear MDIO register 6 write flag" "No effect,Clear"
|
|
eventfld.long 0x00 5. " [5] ,Clear MDIO register 5 write flag" "No effect,Clear"
|
|
eventfld.long 0x00 4. " [4] ,Clear MDIO register 4 write flag" "No effect,Clear"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,Clear MDIO register 3 write flag" "No effect,Clear"
|
|
eventfld.long 0x00 2. " [2] ,Clear MDIO register 2 write flag" "No effect,Clear"
|
|
eventfld.long 0x00 1. " [1] ,Clear MDIO register 1 write flag" "No effect,Clear"
|
|
eventfld.long 0x00 0. " [0] ,Clear MDIO register 0 write flag" "No effect,Clear"
|
|
newline
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "MDIOS_RDFR,MDIOS Read Flag Register"
|
|
bitfld.long 0x00 31. " RDF[31] ,MDIO register 31 read flag" "No read,Read"
|
|
bitfld.long 0x00 30. " [30] ,MDIO register 30 read flag" "No read,Read"
|
|
bitfld.long 0x00 29. " [29] ,MDIO register 29 read flag" "No read,Read"
|
|
bitfld.long 0x00 28. " [28] ,MDIO register 28 read flag" "No read,Read"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,MDIO register 27 read flag" "No read,Read"
|
|
bitfld.long 0x00 26. " [26] ,MDIO register 26 read flag" "No read,Read"
|
|
bitfld.long 0x00 25. " [25] ,MDIO register 25 read flag" "No read,Read"
|
|
bitfld.long 0x00 24. " [24] ,MDIO register 24 read flag" "No read,Read"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,MDIO register 23 read flag" "No read,Read"
|
|
bitfld.long 0x00 22. " [22] ,MDIO register 22 read flag" "No read,Read"
|
|
bitfld.long 0x00 21. " [21] ,MDIO register 21 read flag" "No read,Read"
|
|
bitfld.long 0x00 20. " [20] ,MDIO register 20 read flag" "No read,Read"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,MDIO register 19 read flag" "No read,Read"
|
|
bitfld.long 0x00 18. " [18] ,MDIO register 18 read flag" "No read,Read"
|
|
bitfld.long 0x00 17. " [17] ,MDIO register 17 read flag" "No read,Read"
|
|
bitfld.long 0x00 16. " [16] ,MDIO register 16 read flag" "No read,Read"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,MDIO register 15 read flag" "No read,Read"
|
|
bitfld.long 0x00 14. " [14] ,MDIO register 14 read flag" "No read,Read"
|
|
bitfld.long 0x00 13. " [13] ,MDIO register 13 read flag" "No read,Read"
|
|
bitfld.long 0x00 12. " [12] ,MDIO register 12 read flag" "No read,Read"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,MDIO register 11 read flag" "No read,Read"
|
|
bitfld.long 0x00 10. " [10] ,MDIO register 10 read flag" "No read,Read"
|
|
bitfld.long 0x00 9. " [9] ,MDIO register 9 read flag" "No read,Read"
|
|
bitfld.long 0x00 8. " [8] ,MDIO register 8 read flag" "No read,Read"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,MDIO register 7 read flag" "No read,Read"
|
|
bitfld.long 0x00 6. " [6] ,MDIO register 6 read flag" "No read,Read"
|
|
bitfld.long 0x00 5. " [5] ,MDIO register 5 read flag" "No read,Read"
|
|
bitfld.long 0x00 4. " [4] ,MDIO register 4 read flag" "No read,Read"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,MDIO register 3 read flag" "No read,Read"
|
|
bitfld.long 0x00 2. " [2] ,MDIO register 2 read flag" "No read,Read"
|
|
bitfld.long 0x00 1. " [1] ,MDIO register 1 read flag" "No read,Read"
|
|
bitfld.long 0x00 0. " [0] ,MDIO register 0 read flag" "No read,Read"
|
|
newline
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MDIOS_CRDFR,MDIOS Clear Read Flag Register"
|
|
eventfld.long 0x00 31. " CRDF[31] ,Clear MDIO register 31 read flag" "No effect,Clear"
|
|
eventfld.long 0x00 30. " [30] ,Clear MDIO register 30 read flag" "No effect,Clear"
|
|
eventfld.long 0x00 29. " [29] ,Clear MDIO register 29 read flag" "No effect,Clear"
|
|
eventfld.long 0x00 28. " [28] ,Clear MDIO register 28 read flag" "No effect,Clear"
|
|
newline
|
|
eventfld.long 0x00 27. " [27] ,Clear MDIO register 27 read flag" "No effect,Clear"
|
|
eventfld.long 0x00 26. " [26] ,Clear MDIO register 26 read flag" "No effect,Clear"
|
|
eventfld.long 0x00 25. " [25] ,Clear MDIO register 25 read flag" "No effect,Clear"
|
|
eventfld.long 0x00 24. " [24] ,Clear MDIO register 24 read flag" "No effect,Clear"
|
|
newline
|
|
eventfld.long 0x00 23. " [23] ,Clear MDIO register 23 read flag" "No effect,Clear"
|
|
eventfld.long 0x00 22. " [22] ,Clear MDIO register 22 read flag" "No effect,Clear"
|
|
eventfld.long 0x00 21. " [21] ,Clear MDIO register 21 read flag" "No effect,Clear"
|
|
eventfld.long 0x00 20. " [20] ,Clear MDIO register 20 read flag" "No effect,Clear"
|
|
newline
|
|
eventfld.long 0x00 19. " [19] ,Clear MDIO register 19 read flag" "No effect,Clear"
|
|
eventfld.long 0x00 18. " [18] ,Clear MDIO register 18 read flag" "No effect,Clear"
|
|
eventfld.long 0x00 17. " [17] ,Clear MDIO register 17 read flag" "No effect,Clear"
|
|
eventfld.long 0x00 16. " [16] ,Clear MDIO register 16 read flag" "No effect,Clear"
|
|
newline
|
|
eventfld.long 0x00 15. " [15] ,Clear MDIO register 15 read flag" "No effect,Clear"
|
|
eventfld.long 0x00 14. " [14] ,Clear MDIO register 14 read flag" "No effect,Clear"
|
|
eventfld.long 0x00 13. " [13] ,Clear MDIO register 13 read flag" "No effect,Clear"
|
|
eventfld.long 0x00 12. " [12] ,Clear MDIO register 12 read flag" "No effect,Clear"
|
|
newline
|
|
eventfld.long 0x00 11. " [11] ,Clear MDIO register 11 read flag" "No effect,Clear"
|
|
eventfld.long 0x00 10. " [10] ,Clear MDIO register 10 read flag" "No effect,Clear"
|
|
eventfld.long 0x00 9. " [9] ,Clear MDIO register 9 read flag" "No effect,Clear"
|
|
eventfld.long 0x00 8. " [8] ,Clear MDIO register 8 read flag" "No effect,Clear"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,Clear MDIO register 7 read flag" "No effect,Clear"
|
|
eventfld.long 0x00 6. " [6] ,Clear MDIO register 6 read flag" "No effect,Clear"
|
|
eventfld.long 0x00 5. " [5] ,Clear MDIO register 5 read flag" "No effect,Clear"
|
|
eventfld.long 0x00 4. " [4] ,Clear MDIO register 4 read flag" "No effect,Clear"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,Clear MDIO register 3 read flag" "No effect,Clear"
|
|
eventfld.long 0x00 2. " [2] ,Clear MDIO register 2 read flag" "No effect,Clear"
|
|
eventfld.long 0x00 1. " [1] ,Clear MDIO register 1 read flag" "No effect,Clear"
|
|
eventfld.long 0x00 0. " [0] ,Clear MDIO register 0 read flag" "No effect,Clear"
|
|
newline
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MDIOS_SR,MDIOS Status Register"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " TERF ,Turnaround error flag" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " SERF ,Start error flag" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " PERF ,Preamble error flag" "Not occurred,Occurred"
|
|
width 15.
|
|
tree "MDIOS Data Registers"
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "MDIOS_DINR0,MDIOS Input Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIN0 ,Input data received from MDIO master during write frames"
|
|
group.long (0x100+0x80)++0x03
|
|
line.long 0x00 "MDIOS_DOUTR0,MDIOS Output Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DOUT0 ,Output data sent to MDIO master during read frames"
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 "MDIOS_DINR1,MDIOS Input Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIN1 ,Input data received from MDIO master during write frames"
|
|
group.long (0x104+0x80)++0x03
|
|
line.long 0x00 "MDIOS_DOUTR1,MDIOS Output Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DOUT1 ,Output data sent to MDIO master during read frames"
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "MDIOS_DINR2,MDIOS Input Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIN2 ,Input data received from MDIO master during write frames"
|
|
group.long (0x108+0x80)++0x03
|
|
line.long 0x00 "MDIOS_DOUTR2,MDIOS Output Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DOUT2 ,Output data sent to MDIO master during read frames"
|
|
rgroup.long 0x10C++0x03
|
|
line.long 0x00 "MDIOS_DINR3,MDIOS Input Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIN3 ,Input data received from MDIO master during write frames"
|
|
group.long (0x10C+0x80)++0x03
|
|
line.long 0x00 "MDIOS_DOUTR3,MDIOS Output Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DOUT3 ,Output data sent to MDIO master during read frames"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "MDIOS_DINR4,MDIOS Input Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIN4 ,Input data received from MDIO master during write frames"
|
|
group.long (0x110+0x80)++0x03
|
|
line.long 0x00 "MDIOS_DOUTR4,MDIOS Output Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DOUT4 ,Output data sent to MDIO master during read frames"
|
|
rgroup.long 0x114++0x03
|
|
line.long 0x00 "MDIOS_DINR5,MDIOS Input Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIN5 ,Input data received from MDIO master during write frames"
|
|
group.long (0x114+0x80)++0x03
|
|
line.long 0x00 "MDIOS_DOUTR5,MDIOS Output Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DOUT5 ,Output data sent to MDIO master during read frames"
|
|
rgroup.long 0x118++0x03
|
|
line.long 0x00 "MDIOS_DINR6,MDIOS Input Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIN6 ,Input data received from MDIO master during write frames"
|
|
group.long (0x118+0x80)++0x03
|
|
line.long 0x00 "MDIOS_DOUTR6,MDIOS Output Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DOUT6 ,Output data sent to MDIO master during read frames"
|
|
rgroup.long 0x11C++0x03
|
|
line.long 0x00 "MDIOS_DINR7,MDIOS Input Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIN7 ,Input data received from MDIO master during write frames"
|
|
group.long (0x11C+0x80)++0x03
|
|
line.long 0x00 "MDIOS_DOUTR7,MDIOS Output Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DOUT7 ,Output data sent to MDIO master during read frames"
|
|
rgroup.long 0x120++0x03
|
|
line.long 0x00 "MDIOS_DINR8,MDIOS Input Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIN8 ,Input data received from MDIO master during write frames"
|
|
group.long (0x120+0x80)++0x03
|
|
line.long 0x00 "MDIOS_DOUTR8,MDIOS Output Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DOUT8 ,Output data sent to MDIO master during read frames"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "MDIOS_DINR9,MDIOS Input Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIN9 ,Input data received from MDIO master during write frames"
|
|
group.long (0x124+0x80)++0x03
|
|
line.long 0x00 "MDIOS_DOUTR9,MDIOS Output Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DOUT9 ,Output data sent to MDIO master during read frames"
|
|
rgroup.long 0x128++0x03
|
|
line.long 0x00 "MDIOS_DINR10,MDIOS Input Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIN10 ,Input data received from MDIO master during write frames"
|
|
group.long (0x128+0x80)++0x03
|
|
line.long 0x00 "MDIOS_DOUTR10,MDIOS Output Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DOUT10 ,Output data sent to MDIO master during read frames"
|
|
rgroup.long 0x12C++0x03
|
|
line.long 0x00 "MDIOS_DINR11,MDIOS Input Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIN11 ,Input data received from MDIO master during write frames"
|
|
group.long (0x12C+0x80)++0x03
|
|
line.long 0x00 "MDIOS_DOUTR11,MDIOS Output Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DOUT11 ,Output data sent to MDIO master during read frames"
|
|
rgroup.long 0x130++0x03
|
|
line.long 0x00 "MDIOS_DINR12,MDIOS Input Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIN12 ,Input data received from MDIO master during write frames"
|
|
group.long (0x130+0x80)++0x03
|
|
line.long 0x00 "MDIOS_DOUTR12,MDIOS Output Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DOUT12 ,Output data sent to MDIO master during read frames"
|
|
rgroup.long 0x134++0x03
|
|
line.long 0x00 "MDIOS_DINR13,MDIOS Input Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIN13 ,Input data received from MDIO master during write frames"
|
|
group.long (0x134+0x80)++0x03
|
|
line.long 0x00 "MDIOS_DOUTR13,MDIOS Output Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DOUT13 ,Output data sent to MDIO master during read frames"
|
|
rgroup.long 0x138++0x03
|
|
line.long 0x00 "MDIOS_DINR14,MDIOS Input Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIN14 ,Input data received from MDIO master during write frames"
|
|
group.long (0x138+0x80)++0x03
|
|
line.long 0x00 "MDIOS_DOUTR14,MDIOS Output Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DOUT14 ,Output data sent to MDIO master during read frames"
|
|
rgroup.long 0x13C++0x03
|
|
line.long 0x00 "MDIOS_DINR15,MDIOS Input Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIN15 ,Input data received from MDIO master during write frames"
|
|
group.long (0x13C+0x80)++0x03
|
|
line.long 0x00 "MDIOS_DOUTR15,MDIOS Output Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DOUT15 ,Output data sent to MDIO master during read frames"
|
|
rgroup.long 0x140++0x03
|
|
line.long 0x00 "MDIOS_DINR16,MDIOS Input Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIN16 ,Input data received from MDIO master during write frames"
|
|
group.long (0x140+0x80)++0x03
|
|
line.long 0x00 "MDIOS_DOUTR16,MDIOS Output Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DOUT16 ,Output data sent to MDIO master during read frames"
|
|
rgroup.long 0x144++0x03
|
|
line.long 0x00 "MDIOS_DINR17,MDIOS Input Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIN17 ,Input data received from MDIO master during write frames"
|
|
group.long (0x144+0x80)++0x03
|
|
line.long 0x00 "MDIOS_DOUTR17,MDIOS Output Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DOUT17 ,Output data sent to MDIO master during read frames"
|
|
rgroup.long 0x148++0x03
|
|
line.long 0x00 "MDIOS_DINR18,MDIOS Input Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIN18 ,Input data received from MDIO master during write frames"
|
|
group.long (0x148+0x80)++0x03
|
|
line.long 0x00 "MDIOS_DOUTR18,MDIOS Output Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DOUT18 ,Output data sent to MDIO master during read frames"
|
|
rgroup.long 0x14C++0x03
|
|
line.long 0x00 "MDIOS_DINR19,MDIOS Input Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIN19 ,Input data received from MDIO master during write frames"
|
|
group.long (0x14C+0x80)++0x03
|
|
line.long 0x00 "MDIOS_DOUTR19,MDIOS Output Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DOUT19 ,Output data sent to MDIO master during read frames"
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "MDIOS_DINR20,MDIOS Input Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIN20 ,Input data received from MDIO master during write frames"
|
|
group.long (0x150+0x80)++0x03
|
|
line.long 0x00 "MDIOS_DOUTR20,MDIOS Output Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DOUT20 ,Output data sent to MDIO master during read frames"
|
|
rgroup.long 0x154++0x03
|
|
line.long 0x00 "MDIOS_DINR21,MDIOS Input Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIN21 ,Input data received from MDIO master during write frames"
|
|
group.long (0x154+0x80)++0x03
|
|
line.long 0x00 "MDIOS_DOUTR21,MDIOS Output Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DOUT21 ,Output data sent to MDIO master during read frames"
|
|
rgroup.long 0x158++0x03
|
|
line.long 0x00 "MDIOS_DINR22,MDIOS Input Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIN22 ,Input data received from MDIO master during write frames"
|
|
group.long (0x158+0x80)++0x03
|
|
line.long 0x00 "MDIOS_DOUTR22,MDIOS Output Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DOUT22 ,Output data sent to MDIO master during read frames"
|
|
rgroup.long 0x15C++0x03
|
|
line.long 0x00 "MDIOS_DINR23,MDIOS Input Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIN23 ,Input data received from MDIO master during write frames"
|
|
group.long (0x15C+0x80)++0x03
|
|
line.long 0x00 "MDIOS_DOUTR23,MDIOS Output Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DOUT23 ,Output data sent to MDIO master during read frames"
|
|
rgroup.long 0x160++0x03
|
|
line.long 0x00 "MDIOS_DINR24,MDIOS Input Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIN24 ,Input data received from MDIO master during write frames"
|
|
group.long (0x160+0x80)++0x03
|
|
line.long 0x00 "MDIOS_DOUTR24,MDIOS Output Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DOUT24 ,Output data sent to MDIO master during read frames"
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "MDIOS_DINR25,MDIOS Input Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIN25 ,Input data received from MDIO master during write frames"
|
|
group.long (0x164+0x80)++0x03
|
|
line.long 0x00 "MDIOS_DOUTR25,MDIOS Output Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DOUT25 ,Output data sent to MDIO master during read frames"
|
|
rgroup.long 0x168++0x03
|
|
line.long 0x00 "MDIOS_DINR26,MDIOS Input Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIN26 ,Input data received from MDIO master during write frames"
|
|
group.long (0x168+0x80)++0x03
|
|
line.long 0x00 "MDIOS_DOUTR26,MDIOS Output Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DOUT26 ,Output data sent to MDIO master during read frames"
|
|
rgroup.long 0x16C++0x03
|
|
line.long 0x00 "MDIOS_DINR27,MDIOS Input Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIN27 ,Input data received from MDIO master during write frames"
|
|
group.long (0x16C+0x80)++0x03
|
|
line.long 0x00 "MDIOS_DOUTR27,MDIOS Output Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DOUT27 ,Output data sent to MDIO master during read frames"
|
|
rgroup.long 0x170++0x03
|
|
line.long 0x00 "MDIOS_DINR28,MDIOS Input Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIN28 ,Input data received from MDIO master during write frames"
|
|
group.long (0x170+0x80)++0x03
|
|
line.long 0x00 "MDIOS_DOUTR28,MDIOS Output Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DOUT28 ,Output data sent to MDIO master during read frames"
|
|
rgroup.long 0x174++0x03
|
|
line.long 0x00 "MDIOS_DINR29,MDIOS Input Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIN29 ,Input data received from MDIO master during write frames"
|
|
group.long (0x174+0x80)++0x03
|
|
line.long 0x00 "MDIOS_DOUTR29,MDIOS Output Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DOUT29 ,Output data sent to MDIO master during read frames"
|
|
rgroup.long 0x178++0x03
|
|
line.long 0x00 "MDIOS_DINR30,MDIOS Input Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIN30 ,Input data received from MDIO master during write frames"
|
|
group.long (0x178+0x80)++0x03
|
|
line.long 0x00 "MDIOS_DOUTR30,MDIOS Output Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DOUT30 ,Output data sent to MDIO master during read frames"
|
|
rgroup.long 0x17C++0x03
|
|
line.long 0x00 "MDIOS_DINR31,MDIOS Input Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIN31 ,Input data received from MDIO master during write frames"
|
|
group.long (0x17C+0x80)++0x03
|
|
line.long 0x00 "MDIOS_DOUTR31,MDIOS Output Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DOUT31 ,Output data sent to MDIO master during read frames"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.open "SDMMC (SD/SDIO/MMC Card Host Interface)"
|
|
tree "SDMMC1"
|
|
base ad:0x40012C00
|
|
width 9.
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40012C00)&0x03)==0x00))
|
|
if (((per.l(ad:0x40012C00+0x0C)&0x1000)==0x1000))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "POWER,SDMMC Power Control Register"
|
|
bitfld.long 0x00 4. " DIRPOL ,Data and command direction signals polarity selection" "Low,High"
|
|
rbitfld.long 0x00 3. " VSWITCHEN ,Voltage switch procedure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " VSWITCH ,Voltage switch sequence start" "Not started,Started"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " PWRCTRL ,SDMMC state control bits" "Reset,,Power-cycle,Power-on"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "POWER,SDMMC Power Control Register"
|
|
bitfld.long 0x00 4. " DIRPOL ,Data and command direction signals polarity selection" "Low,High"
|
|
bitfld.long 0x00 3. " VSWITCHEN ,Voltage switch procedure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " VSWITCH ,Voltage switch sequence start" "Not started,Started"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " PWRCTRL ,SDMMC state control bits" "Reset,,Power-cycle,Power-on"
|
|
endif
|
|
elif (((per.l(ad:0x40012C00)&0x03)==(0x01||0x02)))
|
|
if (((per.l(ad:0x40012C00+0x0C)&0x1000)==0x1000))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "POWER,SDMMC Power Control Register"
|
|
rbitfld.long 0x00 4. " DIRPOL ,Data and command direction signals polarity selection" "Low,High"
|
|
rbitfld.long 0x00 3. " VSWITCHEN ,Voltage switch procedure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " VSWITCH ,Voltage switch sequence start" "Not started,Started"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " PWRCTRL ,SDMMC state control bits" "Reset,,Power-cycle,Power-on"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "POWER,SDMMC Power Control Register"
|
|
rbitfld.long 0x00 4. " DIRPOL ,Data and command direction signals polarity selection" "Low,High"
|
|
bitfld.long 0x00 3. " VSWITCHEN ,Voltage switch procedure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " VSWITCH ,Voltage switch sequence start" "Not started,Started"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " PWRCTRL ,SDMMC state control bits" "Reset,,Power-cycle,Power-on"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40012C00+0x0C)&0x1000)==0x1000))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "POWER,SDMMC Power Control Register"
|
|
rbitfld.long 0x00 4. " DIRPOL ,Data and command direction signals polarity selection" "Low,High"
|
|
rbitfld.long 0x00 3. " VSWITCHEN ,Voltage switch procedure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " VSWITCH ,Voltage switch sequence start" "Not started,Started"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " PWRCTRL ,SDMMC state control bits" "Reset,,Power-cycle,Power-on"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "POWER,SDMMC Power Control Register"
|
|
rbitfld.long 0x00 4. " DIRPOL ,Data and command direction signals polarity selection" "Low,High"
|
|
bitfld.long 0x00 3. " VSWITCHEN ,Voltage switch procedure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " VSWITCH ,Voltage switch sequence start" "Not started,Started"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " PWRCTRL ,SDMMC state control bits" "Reset,,Power-cycle,Power-on"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40012C00+0x0C)&0x1000)==0x1000))&&(((per.l(ad:0x40012C00+0x34)&0x1000)==0x1000))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CLKCR,SDMMC Clock Control Register"
|
|
bitfld.long 0x00 20.--21. " SELCLKRX ,Receive clock selection" "IO_IN_CK,CKIN,FB_CK,?..."
|
|
bitfld.long 0x00 19. " BUSSPEED ,Bus speed mode selection between DS HS SDR12 SDR25 and SDR50 DDR50 SDR104" "DS/HS/SDR12/SDR25,SDR50/DDR50/SDR104"
|
|
bitfld.long 0x00 18. " DDR ,Data rate signaling selection" "Single,Double"
|
|
newline
|
|
bitfld.long 0x00 17. " HWFC_EN ,Hardware flow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " NEGEDGE ,CK dephasing selection bit for data and command" "0,1"
|
|
bitfld.long 0x00 14.--15. " WIDBUS ,Wide bus mode enable bit" "1-bit wide,4-bit wide,8-bit wide,?..."
|
|
newline
|
|
bitfld.long 0x00 12. " PWRSAV ,Power saving configuration bit" "Always enabled,Enabled on bus active"
|
|
hexmask.long.word 0x00 0.--9. 1. " CLKDIV ,Clock divide factor"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "CLKCR,SDMMC Clock Control Register"
|
|
bitfld.long 0x00 20.--21. " SELCLKRX ,Receive clock selection" "IO_IN_CK,CKIN,FB_CK,?..."
|
|
bitfld.long 0x00 19. " BUSSPEED ,Bus speed mode selection between DS HS SDR12 SDR25 and SDR50 DDR50 SDR104" "DS/HS/SDR12/SDR25,SDR50/DDR50/SDR104"
|
|
bitfld.long 0x00 18. " DDR ,Data rate signaling selection" "Single,Double"
|
|
newline
|
|
bitfld.long 0x00 17. " HWFC_EN ,Hardware flow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " NEGEDGE ,CK dephasing selection bit for data and command" "0,1"
|
|
bitfld.long 0x00 14.--15. " WIDBUS ,Wide bus mode enable bit" "1-bit wide,4-bit wide,8-bit wide,?..."
|
|
newline
|
|
bitfld.long 0x00 12. " PWRSAV ,Power saving configuration bit" "Always enabled,Enabled on bus active"
|
|
hexmask.long.word 0x00 0.--9. 1. " CLKDIV ,Clock divide factor"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ARG,SDMMC Argument Register"
|
|
if (((per.l(ad:0x40012C00+0x0C)&0x1000)==0x1000))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CMD,SDMMC Command Register"
|
|
rbitfld.long 0x00 16. " CMDSUSPEND ,The CPSM treats the command as a suspend or resume command and signals interrupt period start/end" "Suspended,Resumed"
|
|
bitfld.long 0x00 15. " BOOTEN ,Enable boot mode procedure" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " BOOTMODE ,Select the boot mode procedure to be used" "Normal,Alternative"
|
|
newline
|
|
bitfld.long 0x00 13. " DTHOLD ,Hold new data block transmission and reception in the DPSM" "Not held,Held"
|
|
bitfld.long 0x00 12. " CPSMEN ,Command path state machine (CPSM) enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " WAITPEND ,CPSM waits for ends of data transfer (CmdPend internal signal)" "No wait,Wait"
|
|
newline
|
|
bitfld.long 0x00 10. " WAITINT ,CPSM waits for interrupt request" "No wait,Wait"
|
|
rbitfld.long 0x00 8.--9. " WAITRESP ,Wait for response bits" "No resp(CMDSENT),Short(CMDREND||CCRCFAIL),No resp(CMDSENT),Long(CMDREND||CCRCFAIL)"
|
|
rbitfld.long 0x00 7. " CMDSTOP ,The CPSM treats the command as a stop transmission command and signals abort to the DPSM" "No abort signal issued,Abort signal issued"
|
|
newline
|
|
rbitfld.long 0x00 6. " CMDTRANS ,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "No end of interrupt period,Interrupt period"
|
|
rbitfld.long 0x00 0.--5. " CMDINDEX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CMD,SDMMC Command Register"
|
|
bitfld.long 0x00 16. " CMDSUSPEND ,The CPSM treats the command as a suspend or resume command and signals interrupt period start/end" "Suspended,Resumed"
|
|
bitfld.long 0x00 15. " BOOTEN ,Enable boot mode procedure" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BOOTMODE ,Select the boot mode procedure to be used" "Normal,Alternative"
|
|
newline
|
|
bitfld.long 0x00 13. " DTHOLD ,Hold new data block transmission and reception in the DPSM" "Not held,Held"
|
|
bitfld.long 0x00 12. " CPSMEN ,Command path state machine (CPSM) enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " WAITPEND ,CPSM waits for ends of data transfer (CmdPend internal signal)" "No wait,Wait"
|
|
newline
|
|
bitfld.long 0x00 10. " WAITINT ,CPSM waits for interrupt request" "No wait,Wait"
|
|
bitfld.long 0x00 8.--9. " WAITRESP ,Wait for response bits" "No resp(CMDSENT),Short(CMDREND||CCRCFAIL),No resp(CMDSENT),Long(CMDREND||CCRCFAIL)"
|
|
bitfld.long 0x00 7. " CMDSTOP ,The CPSM treats the command as a stop transmission command and signals abort to the DPSM" "No abort signal issued,Abort signal issued"
|
|
newline
|
|
bitfld.long 0x00 6. " CMDTRANS ,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "No end of interrupt period,Interrupt period"
|
|
bitfld.long 0x00 0.--5. " CMDINDEX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
else
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "POWER,SDMMC Power Control Register"
|
|
bitfld.long 0x00 0.--1. " PWRCTRL ,Power supply control bits" "Power off,,Power-up,Power-on"
|
|
line.long 0x04 "CLKCR,SDMMC Clock Control Register"
|
|
bitfld.long 0x04 14. " HWFC_EN ,HW flow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " NEGEDGE ,CK dephasing selection bit" "Rising edge,Falling edge"
|
|
bitfld.long 0x04 11.--12. " WIDBUS ,Wide bus mode enable bit" "Default,4-wide,8-wide,?..."
|
|
newline
|
|
bitfld.long 0x04 10. " BYPASS ,Clock divider bypass enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " PWRSAV ,Power saving configuration bit" "Always enabled,Only when bus active"
|
|
bitfld.long 0x04 8. " CLKEN ,Clock enable bit" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. " CLKDIV ,Clock divide factor"
|
|
line.long 0x08 "ARG,SDMMC Argument Register"
|
|
if ((per.l((ad:0x40012C00+0x2C))&0x04)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CMD,SDMMC Command Register"
|
|
bitfld.long 0x00 11. " SDIOSUSPEND ,SD I/O suspend command" "Others,Suspend command"
|
|
bitfld.long 0x00 10. " CPSMEN ,Command path state machine (CPSM) enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " WAITINT ,CPSM waits for interrupt request" "No wait,Wait"
|
|
bitfld.long 0x00 6.--7. " WAITRESP ,Wait for response bits" "No resp(CMDSENT),Short(CMDREND||CCRCFAIL),No resp(CMDSENT),Long(CMDREND||CCRCFAIL)"
|
|
bitfld.long 0x00 0.--5. " CMDINDEX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CMD,SDMMC Command Register"
|
|
bitfld.long 0x00 11. " SDIOSUSPEND ,SD I/O suspend command" "Others,Suspend command"
|
|
bitfld.long 0x00 10. " CPSMEN ,Command path state machine (CPSM) enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " WAITPEND ,CPSM waits for ends of data transfer" "No wait,Wait"
|
|
newline
|
|
bitfld.long 0x00 8. " WAITINT ,CPSM waits for interrupt request" "No wait,Wait"
|
|
bitfld.long 0x00 6.--7. " WAITRESP ,Wait for response bits" "No resp(CMDSENT),Short(CMDREND||CCRCFAIL),No resp(CMDSENT),Long(CMDREND||CCRCFAIL)"
|
|
bitfld.long 0x00 0.--5. " CMDINDEX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "RESPCMD,SDMMC Command Response Register"
|
|
bitfld.long 0x00 0.--5. " RESPCMD ,Response command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
if ((per.l((ad:0x40012C00+0x0C))&0xC0)==0x40)
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "RESP1,SDMMC Response 1 Register"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "RESP2,SDMMC Response 2 Register"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "RESP3,SDMMC Response 3 Register"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "RESP4,SDMMC Response 4 Register"
|
|
elif ((per.l((ad:0x40012C00+0x0C))&0xC0)==0xC0)
|
|
rgroup.long 0x14++0x0F
|
|
line.long 0x00 "RESP1,SDMMC Response 1 Register"
|
|
line.long 0x04 "RESP2,SDMMC Response 2 Register"
|
|
line.long 0x08 "RESP3,SDMMC Response 3 Register"
|
|
line.long 0x0C "RESP4,SDMMC Response 4 Register"
|
|
else
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "RESP1,SDMMC Response 1 Register"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "RESP2,SDMMC Response 2 Register"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "RESP3,SDMMC Response 3 Register"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "RESP4,SDMMC Response 4 Register"
|
|
endif
|
|
group.long 0x24++0x07
|
|
line.long 0x00 "DTIMER,SDMMC Data Timer Register"
|
|
line.long 0x04 "DLEN,SDMMC Data Length Register"
|
|
hexmask.long 0x04 0.--24. 1. " DATALENGTH ,Data length value"
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40012C00+0x34)&0x1000)==0x1000))&&(((per.l(ad:0x40012C00+0x50)&0x01)==0x00))
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DCTRL,SDMMC Data Control Register"
|
|
bitfld.long 0x00 13. " FIFORST ,FIFO reset will flush any remaining data" "Not affected,Flushed"
|
|
rbitfld.long 0x00 12. " BOOTACKEN ,Enable the reception of the boot acknowledgment" "Disabled,Enabled"
|
|
rbitfld.long 0x00 11. " SDIOEN ,SD I/O enable functions" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 10. " RWMOD ,Read wait mode" "Using D2,Stopping CK"
|
|
bitfld.long 0x00 9. " RWSTOP ,Read wait stop" "In progress,Stopped"
|
|
bitfld.long 0x00 8. " RWSTART ,Read wait start" "Stopped,Started"
|
|
newline
|
|
rbitfld.long 0x00 4.--7. " DBLOCKSIZE ,Data block size" "1byte,2bytes,4bytes,8bytes,16bytes,32bytes,64bytes,128bytes,256bytes,512bytes,1024bytes,2048bytes,4096bytes,8192bytes,16384bytes,?..."
|
|
rbitfld.long 0x00 2.--3. " DTMODE ,Data transfer mode selection" "Block(ending on block cnt),SDIO,MMC,Block(ending on STOP_TRANSMISSION cmd)"
|
|
rbitfld.long 0x00 1. " DTDIR ,Data transfer direction selection" "Host->Card,Card->Host"
|
|
newline
|
|
rbitfld.long 0x00 0. " DTEN ,Data transfer enabled bit" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40012C00+0x34)&0x1000)==0x1000))&&(((per.l(ad:0x40012C00+0x50)&0x01)==0x01))
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DCTRL,SDMMC Data Control Register"
|
|
rbitfld.long 0x00 13. " FIFORST ,FIFO reset will flush any remaining data" "Not affected,Flushed"
|
|
rbitfld.long 0x00 12. " BOOTACKEN ,Enable the reception of the boot acknowledgment" "Disabled,Enabled"
|
|
rbitfld.long 0x00 11. " SDIOEN ,SD I/O enable functions" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 10. " RWMOD ,Read wait mode" "Using D2,Stopping CK"
|
|
bitfld.long 0x00 9. " RWSTOP ,Read wait stop" "In progress,Stopped"
|
|
bitfld.long 0x00 8. " RWSTART ,Read wait start" "Stopped,Started"
|
|
newline
|
|
rbitfld.long 0x00 4.--7. " DBLOCKSIZE ,Data block size" "1byte,2bytes,4bytes,8bytes,16bytes,32bytes,64bytes,128bytes,256bytes,512bytes,1024bytes,2048bytes,4096bytes,8192bytes,16384bytes,?..."
|
|
rbitfld.long 0x00 2.--3. " DTMODE ,Data transfer mode selection" "Block(ending on block cnt),SDIO,MMC,Block(ending on STOP_TRANSMISSION cmd)"
|
|
rbitfld.long 0x00 1. " DTDIR ,Data transfer direction selection" "Host->Card,Card->Host"
|
|
newline
|
|
rbitfld.long 0x00 0. " DTEN ,Data transfer enabled bit" "Disabled,Enabled"
|
|
else
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DCTRL,SDMMC Data Control Register"
|
|
rbitfld.long 0x00 13. " FIFORST ,FIFO reset will flush any remaining data" "Not affected,Flushed"
|
|
bitfld.long 0x00 12. " BOOTACKEN ,Enable the reception of the boot acknowledgment" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SDIOEN ,SD I/O enable functions" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " RWMOD ,Read wait mode" "Using D2,Stopping CK"
|
|
bitfld.long 0x00 9. " RWSTOP ,Read wait stop" "In progress,Stopped"
|
|
bitfld.long 0x00 8. " RWSTART ,Read wait start" "Stopped,Started"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " DBLOCKSIZE ,Data block size" "1byte,2bytes,4bytes,8bytes,16bytes,32bytes,64bytes,128bytes,256bytes,512bytes,1024bytes,2048bytes,4096bytes,8192bytes,16384bytes,?..."
|
|
bitfld.long 0x00 2.--3. " DTMODE ,Data transfer mode selection" "Block(ending on block cnt),SDIO,MMC,Block(ending on STOP_TRANSMISSION cmd)"
|
|
bitfld.long 0x00 1. " DTDIR ,Data transfer direction selection" "Host->Card,Card->Host"
|
|
newline
|
|
bitfld.long 0x00 0. " DTEN ,Data transfer enabled bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40012C00+0x2C))&0x800)==0x800)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DCTRL,SDMMC Data Control Register"
|
|
bitfld.long 0x00 11. " SDIOEN ,SD I/O enable functions" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RWMOD ,Read wait mode" "Stopping D2,Using CK"
|
|
bitfld.long 0x00 9. " RWSTOP ,Read wait stop" "In progress,Stopped"
|
|
newline
|
|
bitfld.long 0x00 8. " RWSTART ,Read wait stop" "Stopped,Started"
|
|
bitfld.long 0x00 4.--7. " DBLOCKSIZE ,Data block size" "1byte,2bytes,4bytes,8bytes,16bytes,32bytes,64bytes,128bytes,256bytes,512bytes,1024bytes,2048bytes,4096bytes,8192bytes,16384bytes,?..."
|
|
bitfld.long 0x00 3. " DMAEN ,DMA enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " DTMODE ,Data transfer mode selection" "Block,Stream or SDIO multibyte"
|
|
bitfld.long 0x00 1. " DTDIR ,Data transfer direction selection" "Controller->Card,Card->Controller"
|
|
bitfld.long 0x00 0. " DTEN ,Data transfer enabled bit" "Disabled,Enabled"
|
|
else
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DCTRL,SDMMC Data Control Register"
|
|
bitfld.long 0x00 11. " SDIOEN ,SD I/O enable functions" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RWMOD ,Read wait mode" "Stopping D2,Using CK"
|
|
bitfld.long 0x00 9. " RWSTOP ,Read wait stop" "In progress,Stopped"
|
|
newline
|
|
bitfld.long 0x00 8. " RWSTART ,Read wait stop" "Stopped,Started"
|
|
bitfld.long 0x00 4.--7. " DBLOCKSIZE ,Data block size" "1byte,2bytes,4bytes,8bytes,16bytes,32bytes,64bytes,128bytes,256bytes,512bytes,1024bytes,2048bytes,4096bytes,8192bytes,16384bytes,?..."
|
|
bitfld.long 0x00 3. " DMAEN ,DMA enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " DTMODE ,Data transfer mode selection" "Block,MultiMediaCard stream"
|
|
bitfld.long 0x00 1. " DTDIR ,Data transfer direction selection" "Controller->Card,Card->Controller"
|
|
bitfld.long 0x00 0. " DTEN ,Data transfer enabled bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.long 0x30++0x07
|
|
line.long 0x00 "DCOUNT,SDMMC Data Counter Register"
|
|
hexmask.long 0x00 0.--24. 1. " DATACOUNT ,Data count value"
|
|
line.long 0x04 "STA,SDMMC Status Register"
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
bitfld.long 0x04 28. " IDMABTC ,IDMA buffer transfer complete" "Not completed,Completed"
|
|
bitfld.long 0x04 27. " IDMATE ,IDMA transfer error" "No error,Error"
|
|
bitfld.long 0x04 26. " CKSTOP ,CK stopped in voltage switch procedure" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x04 25. " VSWEND ,Voltage switch critical timing section completion" "Not completed,Completed"
|
|
bitfld.long 0x04 24. " ACKTIMEOUT ,Boot acknowledgment timeout" "Not timed-out,Timed-out"
|
|
bitfld.long 0x04 23. " ACKFAIL ,Boot acknowledgment received" "Not received,Received"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 22. " SDIOIT ,SDIO interrupt received" "Not received,Received"
|
|
newline
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
bitfld.long 0x04 21. " BUSYD0END ,End of D0 busy following a CMD response detected" "Not detected,Detected"
|
|
bitfld.long 0x04 20. " BUSYD0 ,Card signals busy on D0 indicator" "Not busy,Busy"
|
|
else
|
|
bitfld.long 0x04 21. " RXDAVL ,Data available in receive FIFO" "No data,Data available"
|
|
bitfld.long 0x04 20. " TXDAVL ,Data available in transmit FIFO" "No data,Data available"
|
|
endif
|
|
newline
|
|
bitfld.long 0x04 19. " RXFIFOE ,Receive FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x04 18. " TXFIFOE ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x04 17. " RXFIFOF ,Receive FIFO full" "Not full,Full"
|
|
newline
|
|
bitfld.long 0x04 16. " TXFIFOF ,Transmit FIFO full" "Not full,Full"
|
|
bitfld.long 0x04 15. " RXFIFOHF ,Receive FIFO half full: there are at least 8 words in the FIFO" "Not half full,Half full"
|
|
bitfld.long 0x04 14. " TXFIFOHE ,Transmit FIFO half empty: there are at least 8 words in the FIFO" "Not half empty,Half empty"
|
|
newline
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
bitfld.long 0x04 13. " CPSMACT ,Command path state machine active" "Not active,Active"
|
|
bitfld.long 0x04 12. " DPSMACT ,Data path state machine active" "Not active,Active"
|
|
bitfld.long 0x04 11. " DABORT ,Data transfer aborted by CMD12" "Not aborted,Aborted"
|
|
newline
|
|
else
|
|
bitfld.long 0x04 13. " RXACT ,Data receive in progress" "Done,In progress"
|
|
bitfld.long 0x04 12. " TXACT ,Data transmit in progress" "Done,In progress"
|
|
bitfld.long 0x04 11. " CMDACT ,Command transfer in progress" "Done,In progress"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 10. " DBCKEND ,Data block sent/received" "Sending/Receiving,Sent/Received"
|
|
newline
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
bitfld.long 0x04 9. " DHOLD ,Data transfer hold" "Not held,Held"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 8. " DATAEND ,Data end" "No data end,Data end"
|
|
bitfld.long 0x04 7. " CMDSENT ,Command sent" "Not sent,Sent"
|
|
bitfld.long 0x04 6. " CMDREND ,Command response received" "Not received,Received"
|
|
newline
|
|
bitfld.long 0x04 5. " RXOVERR ,Received FIFO overrun error" "No error,Error"
|
|
bitfld.long 0x04 4. " TXUNDERR ,Transmit FIFO underrun error" "No error,Error"
|
|
bitfld.long 0x04 3. " DTIMEOUT ,Data timeout" "No timeout,Timeout"
|
|
newline
|
|
bitfld.long 0x04 2. " CTIMEOUT ,Command response timeout" "No timeout,Timeout"
|
|
bitfld.long 0x04 1. " DCRCFAIL ,Data block sent/received" "Sending/Receiving,Sent/Received"
|
|
bitfld.long 0x04 0. " CCRCFAIL ,Command response received" "Not received,Received"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "ICR,SDMMC Interrupt Clear Register"
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
bitfld.long 0x00 28. " IDMABTCC ,IDMA buffer transfer complete clear bit" "Not cleared,Clear"
|
|
bitfld.long 0x00 27. " IDMATEC ,IDMA transfer error clear bit" "Not cleared,Clear"
|
|
bitfld.long 0x00 26. " CKSTOPC ,CKSTOP flag clear bit" "Not cleared,Clear"
|
|
newline
|
|
bitfld.long 0x00 25. " VSWENDC ,VSWEND flag clear bit" "Not cleared,Clear"
|
|
bitfld.long 0x00 24. " ACKTIMEOUTC ,ACKTIMEOUT flag clear bit" "Not cleared,Clear"
|
|
bitfld.long 0x00 23. " ACKFAILC ,ACKFAIL flag clear bit" "Not cleared,Clear"
|
|
newline
|
|
bitfld.long 0x00 22. " SDIOITC ,SDIOIT flag clear bit" "Not cleared,Clear"
|
|
bitfld.long 0x00 21. " BUSYD0ENDC ,BUSYD0END flag clear bit" "Not cleared,Clear"
|
|
bitfld.long 0x00 11. " DABORTC ,DABORT flag clear bit" "Not cleared,Clear"
|
|
newline
|
|
bitfld.long 0x00 10. " DBCKENDC ,DBCKEND flag clear bit" "Not cleared,Clear"
|
|
bitfld.long 0x00 9. " DHOLDC ,DHOLD flag clear bit" "Not cleared,Clear"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 22. " SDIOITC ,SDIOIT flag clear bit" "Not cleared,Clear"
|
|
bitfld.long 0x00 10. " DBCKENDC ,DBCKEND flag clear bit" "Not cleared,Clear"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 8. " DATAENDC ,DATAEND flag clear bit" "Not cleared,Clear"
|
|
bitfld.long 0x00 7. " CMDSENTC ,CMDSENT flag clear bit" "Not cleared,Clear"
|
|
bitfld.long 0x00 6. " CMDRENDC ,CMDREND flag clear bit" "Not cleared,Clear"
|
|
newline
|
|
bitfld.long 0x00 5. " RXOVERRC ,RXOVERR flag clear bit" "Not cleared,Clear"
|
|
bitfld.long 0x00 4. " TXUNDERRC ,TXUNDERR flag clear bit" "Not cleared,Clear"
|
|
bitfld.long 0x00 3. " DTIMEOUTC ,DTIMEOUT flag clear bit" "Not cleared,Clear"
|
|
newline
|
|
bitfld.long 0x00 2. " CTIMEOUTC ,CTIMEOUT flag clear bit" "Not cleared,Clear"
|
|
bitfld.long 0x00 1. " DCRCFAILC ,DCRCFAIL flag clear bit" "Not cleared,Clear"
|
|
bitfld.long 0x00 0. " CCRCFAILC ,CCRCFAIL flag clear bit" "Not cleared,Clear"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "MASK,SDMMC Mask Register"
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
bitfld.long 0x00 28. " IDMABTCIE ,IDMA buffer transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " CKSTOPIE ,Voltage switch clock stopped interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " VSWENDIE ,Voltage switch critical timing section completion interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24. " ACKTIMEOUTIE ,Acknowledgment timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " ACKFAILIE ,Acknowledgment fail interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " SDIOITIE ,SDIO interrupt received interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. " BUSYD0ENDIE ,BUSYD0END interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 22. " SDIOITIE ,SDIO interrupt received interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RXDAVLIE ,Data available in receive FIFO interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TXDAVLIE ,Data available in transmit FIFO interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " RXFIFOEIE ,Receive FIFO empty interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 18. " TXFIFOEIE ,Transmit FIFO empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RXFIFOFIE ,Receive FIFO full interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
bitfld.long 0x00 16. " TXFIFOFIE ,Transmit FIFO full interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15. " RXFIFOHFIE ,Receive FIFO half full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXFIFOHEIE ,Transmit FIFO half empty interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
bitfld.long 0x00 13. " RXACTIE ,Data receive in progress interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " TXACTIE ,Data transmit in progress interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " CMDACTIE ,Command transfer in progress interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " DBCKENDIE ,Data block sent/received interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 11. " DABORTIE ,Data transfer aborted interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DBCKENDIE ,Data block sent/received interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " DHOLDIE ,Data hold interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 8. " DATAENDIE ,Data end interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CMDSENTIE ,Command sent interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CMDRENDIE ,Command response received interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " RXOVERRIE ,Received FIFO overrun error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TXUNDERRIE ,Transmit FIFO underrun error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DTIMEOUTIE ,Data timeout interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CTIMEOUTIE ,Command response timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DCRCFAILIE ,Data block sent/received interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCRCFAILIE ,Command response received interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
width 10.
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "FIFOCNT,SDMMC FIFO Counter Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " FIFOCOUNT ,Remaining number of words to be written to or read from the FIFO"
|
|
else
|
|
if (((per.l(ad:0x40012C00+0x0C)&0x1000)==0x1000))
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "ACKTIMER,SDMMC Acknowledgment Timer Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ACKTIME ,Boot acknowledgment timeout period"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "ACKTIMER,SDMMC Acknowledgment Timer Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ACKTIME ,Boot acknowledgment timeout period"
|
|
endif
|
|
endif
|
|
newline
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
hgroup.long 0x80++0x03
|
|
hide.long 0x00 "FIFO0,SDMMC Data FIFO Register 0"
|
|
in
|
|
hgroup.long 0x84++0x03
|
|
hide.long 0x00 "FIFO1,SDMMC Data FIFO Register 1"
|
|
in
|
|
hgroup.long 0x88++0x03
|
|
hide.long 0x00 "FIFO2,SDMMC Data FIFO Register 2"
|
|
in
|
|
hgroup.long 0x8C++0x03
|
|
hide.long 0x00 "FIFO3,SDMMC Data FIFO Register 3"
|
|
in
|
|
hgroup.long 0x90++0x03
|
|
hide.long 0x00 "FIFO4,SDMMC Data FIFO Register 4"
|
|
in
|
|
hgroup.long 0x94++0x03
|
|
hide.long 0x00 "FIFO5,SDMMC Data FIFO Register 5"
|
|
in
|
|
hgroup.long 0x98++0x03
|
|
hide.long 0x00 "FIFO6,SDMMC Data FIFO Register 6"
|
|
in
|
|
hgroup.long 0x9C++0x03
|
|
hide.long 0x00 "FIFO7,SDMMC Data FIFO Register 7"
|
|
in
|
|
hgroup.long 0xA0++0x03
|
|
hide.long 0x00 "FIFO8,SDMMC Data FIFO Register 8"
|
|
in
|
|
hgroup.long 0xA4++0x03
|
|
hide.long 0x00 "FIFO9,SDMMC Data FIFO Register 9"
|
|
in
|
|
hgroup.long 0xA8++0x03
|
|
hide.long 0x00 "FIFO10,SDMMC Data FIFO Register 10"
|
|
in
|
|
hgroup.long 0xAC++0x03
|
|
hide.long 0x00 "FIFO11,SDMMC Data FIFO Register 11"
|
|
in
|
|
hgroup.long 0xB0++0x03
|
|
hide.long 0x00 "FIFO12,SDMMC Data FIFO Register 12"
|
|
in
|
|
hgroup.long 0xB4++0x03
|
|
hide.long 0x00 "FIFO13,SDMMC Data FIFO Register 13"
|
|
in
|
|
hgroup.long 0xB8++0x03
|
|
hide.long 0x00 "FIFO14,SDMMC Data FIFO Register 14"
|
|
in
|
|
hgroup.long 0xBC++0x03
|
|
hide.long 0x00 "FIFO15,SDMMC Data FIFO Register 15"
|
|
in
|
|
hgroup.long 0xC0++0x03
|
|
hide.long 0x00 "FIFO16,SDMMC Data FIFO Register 16"
|
|
in
|
|
hgroup.long 0xC4++0x03
|
|
hide.long 0x00 "FIFO17,SDMMC Data FIFO Register 17"
|
|
in
|
|
hgroup.long 0xC8++0x03
|
|
hide.long 0x00 "FIFO18,SDMMC Data FIFO Register 18"
|
|
in
|
|
hgroup.long 0xCC++0x03
|
|
hide.long 0x00 "FIFO19,SDMMC Data FIFO Register 19"
|
|
in
|
|
hgroup.long 0xD0++0x03
|
|
hide.long 0x00 "FIFO20,SDMMC Data FIFO Register 20"
|
|
in
|
|
hgroup.long 0xD4++0x03
|
|
hide.long 0x00 "FIFO21,SDMMC Data FIFO Register 21"
|
|
in
|
|
hgroup.long 0xD8++0x03
|
|
hide.long 0x00 "FIFO22,SDMMC Data FIFO Register 22"
|
|
in
|
|
hgroup.long 0xDC++0x03
|
|
hide.long 0x00 "FIFO23,SDMMC Data FIFO Register 23"
|
|
in
|
|
hgroup.long 0xE0++0x03
|
|
hide.long 0x00 "FIFO24,SDMMC Data FIFO Register 24"
|
|
in
|
|
hgroup.long 0xE4++0x03
|
|
hide.long 0x00 "FIFO25,SDMMC Data FIFO Register 25"
|
|
in
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "FIFO26,SDMMC Data FIFO Register 26"
|
|
in
|
|
hgroup.long 0xEC++0x03
|
|
hide.long 0x00 "FIFO27,SDMMC Data FIFO Register 27"
|
|
in
|
|
hgroup.long 0xF0++0x03
|
|
hide.long 0x00 "FIFO28,SDMMC Data FIFO Register 28"
|
|
in
|
|
hgroup.long 0xF4++0x03
|
|
hide.long 0x00 "FIFO29,SDMMC Data FIFO Register 29"
|
|
in
|
|
hgroup.long 0xF8++0x03
|
|
hide.long 0x00 "FIFO30,SDMMC Data FIFO Register 30"
|
|
in
|
|
hgroup.long 0xFC++0x03
|
|
hide.long 0x00 "FIFO31,SDMMC Data FIFO Register 31"
|
|
in
|
|
else
|
|
hgroup.long 0x80++0x03
|
|
hide.long 0x00 "FIFO0,SDMMC Data FIFO Register 0"
|
|
in
|
|
hgroup.long 0x84++0x03
|
|
hide.long 0x00 "FIFO1,SDMMC Data FIFO Register 1"
|
|
in
|
|
hgroup.long 0x88++0x03
|
|
hide.long 0x00 "FIFO2,SDMMC Data FIFO Register 2"
|
|
in
|
|
hgroup.long 0x8C++0x03
|
|
hide.long 0x00 "FIFO3,SDMMC Data FIFO Register 3"
|
|
in
|
|
hgroup.long 0x90++0x03
|
|
hide.long 0x00 "FIFO4,SDMMC Data FIFO Register 4"
|
|
in
|
|
hgroup.long 0x94++0x03
|
|
hide.long 0x00 "FIFO5,SDMMC Data FIFO Register 5"
|
|
in
|
|
hgroup.long 0x98++0x03
|
|
hide.long 0x00 "FIFO6,SDMMC Data FIFO Register 6"
|
|
in
|
|
hgroup.long 0x9C++0x03
|
|
hide.long 0x00 "FIFO7,SDMMC Data FIFO Register 7"
|
|
in
|
|
hgroup.long 0xA0++0x03
|
|
hide.long 0x00 "FIFO8,SDMMC Data FIFO Register 8"
|
|
in
|
|
hgroup.long 0xA4++0x03
|
|
hide.long 0x00 "FIFO9,SDMMC Data FIFO Register 9"
|
|
in
|
|
hgroup.long 0xA8++0x03
|
|
hide.long 0x00 "FIFO10,SDMMC Data FIFO Register 10"
|
|
in
|
|
hgroup.long 0xAC++0x03
|
|
hide.long 0x00 "FIFO11,SDMMC Data FIFO Register 11"
|
|
in
|
|
hgroup.long 0xB0++0x03
|
|
hide.long 0x00 "FIFO12,SDMMC Data FIFO Register 12"
|
|
in
|
|
hgroup.long 0xB4++0x03
|
|
hide.long 0x00 "FIFO13,SDMMC Data FIFO Register 13"
|
|
in
|
|
hgroup.long 0xB8++0x03
|
|
hide.long 0x00 "FIFO14,SDMMC Data FIFO Register 14"
|
|
in
|
|
hgroup.long 0xBC++0x03
|
|
hide.long 0x00 "FIFO15,SDMMC Data FIFO Register 15"
|
|
in
|
|
endif
|
|
newline
|
|
width 12.
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40012C00+0x34)&0x1000)==0x1000))
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "IDMACTRLR,SDMMC DMA Control Register"
|
|
bitfld.long 0x00 2. " IDMABACT ,Double buffer mode active buffer indication" "Buffer0 && IDMABASE0 prohibited,Buffer1 && IDMABASE1 prohibited"
|
|
bitfld.long 0x00 1. " IDMABMODE ,Buffer mode selection" "Single,Double"
|
|
bitfld.long 0x00 0. " IDMAEN ,IDMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "IDMACTRLR,SDMMC DMA Control Register"
|
|
bitfld.long 0x00 2. " IDMABACT ,Double buffer mode active buffer indication" "Buffer0 && IDMABASE0 prohibited,Buffer1 && IDMABASE1 prohibited"
|
|
bitfld.long 0x00 1. " IDMABMODE ,Buffer mode selection" "Single,Double"
|
|
bitfld.long 0x00 0. " IDMAEN ,IDMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x54++0x0B
|
|
line.long 0x00 "IDMABSIZER,SDMMC IDMA Buffer Size Register"
|
|
hexmask.long.word 0x00 5.--12. 1. " IDMABNDT ,Number of transfers per buffer"
|
|
line.long 0x04 "IDMABASE0R,SDMMC IDMA Buffer 0 Base Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IDMABASE0[31:2] ,Buffer 0 memory base address bits [31:2]"
|
|
rbitfld.long 0x04 0.--1. " IDMABASE0[1:0] ,Buffer 0 memory base address bits [1:0]" "0,1,2,3"
|
|
line.long 0x08 "IDMABASE1R,SDMMC IDMA Buffer 1 Base Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " IDMABASE1[31:2] ,Buffer 1 memory base address bits [31:2]"
|
|
rbitfld.long 0x08 0.--1. " IDMABASE1[1:0] ,Buffer 1 memory base address bits [1:0]" "0,1,2,3"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32F72*")||cpuis("STM32F73*")
|
|
sif !cpuis("STM32F72?R*")&&!cpuis("STM32F73?R*")&&!cpuis("STM32F723V*")&&!cpuis("STM32F733V*")
|
|
tree "SDMMC2"
|
|
base ad:0x40011C00
|
|
width 9.
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40011C00)&0x03)==0x00))
|
|
if (((per.l(ad:0x40011C00+0x0C)&0x1000)==0x1000))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "POWER,SDMMC Power Control Register"
|
|
bitfld.long 0x00 4. " DIRPOL ,Data and command direction signals polarity selection" "Low,High"
|
|
rbitfld.long 0x00 3. " VSWITCHEN ,Voltage switch procedure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " VSWITCH ,Voltage switch sequence start" "Not started,Started"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " PWRCTRL ,SDMMC state control bits" "Reset,,Power-cycle,Power-on"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "POWER,SDMMC Power Control Register"
|
|
bitfld.long 0x00 4. " DIRPOL ,Data and command direction signals polarity selection" "Low,High"
|
|
bitfld.long 0x00 3. " VSWITCHEN ,Voltage switch procedure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " VSWITCH ,Voltage switch sequence start" "Not started,Started"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " PWRCTRL ,SDMMC state control bits" "Reset,,Power-cycle,Power-on"
|
|
endif
|
|
elif (((per.l(ad:0x40011C00)&0x03)==(0x01||0x02)))
|
|
if (((per.l(ad:0x40011C00+0x0C)&0x1000)==0x1000))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "POWER,SDMMC Power Control Register"
|
|
rbitfld.long 0x00 4. " DIRPOL ,Data and command direction signals polarity selection" "Low,High"
|
|
rbitfld.long 0x00 3. " VSWITCHEN ,Voltage switch procedure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " VSWITCH ,Voltage switch sequence start" "Not started,Started"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " PWRCTRL ,SDMMC state control bits" "Reset,,Power-cycle,Power-on"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "POWER,SDMMC Power Control Register"
|
|
rbitfld.long 0x00 4. " DIRPOL ,Data and command direction signals polarity selection" "Low,High"
|
|
bitfld.long 0x00 3. " VSWITCHEN ,Voltage switch procedure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " VSWITCH ,Voltage switch sequence start" "Not started,Started"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " PWRCTRL ,SDMMC state control bits" "Reset,,Power-cycle,Power-on"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40011C00+0x0C)&0x1000)==0x1000))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "POWER,SDMMC Power Control Register"
|
|
rbitfld.long 0x00 4. " DIRPOL ,Data and command direction signals polarity selection" "Low,High"
|
|
rbitfld.long 0x00 3. " VSWITCHEN ,Voltage switch procedure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " VSWITCH ,Voltage switch sequence start" "Not started,Started"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " PWRCTRL ,SDMMC state control bits" "Reset,,Power-cycle,Power-on"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "POWER,SDMMC Power Control Register"
|
|
rbitfld.long 0x00 4. " DIRPOL ,Data and command direction signals polarity selection" "Low,High"
|
|
bitfld.long 0x00 3. " VSWITCHEN ,Voltage switch procedure enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " VSWITCH ,Voltage switch sequence start" "Not started,Started"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. " PWRCTRL ,SDMMC state control bits" "Reset,,Power-cycle,Power-on"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40011C00+0x0C)&0x1000)==0x1000))&&(((per.l(ad:0x40011C00+0x34)&0x1000)==0x1000))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CLKCR,SDMMC Clock Control Register"
|
|
bitfld.long 0x00 20.--21. " SELCLKRX ,Receive clock selection" "IO_IN_CK,CKIN,FB_CK,?..."
|
|
bitfld.long 0x00 19. " BUSSPEED ,Bus speed mode selection between DS HS SDR12 SDR25 and SDR50 DDR50 SDR104" "DS/HS/SDR12/SDR25,SDR50/DDR50/SDR104"
|
|
bitfld.long 0x00 18. " DDR ,Data rate signaling selection" "Single,Double"
|
|
newline
|
|
bitfld.long 0x00 17. " HWFC_EN ,Hardware flow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " NEGEDGE ,CK dephasing selection bit for data and command" "0,1"
|
|
bitfld.long 0x00 14.--15. " WIDBUS ,Wide bus mode enable bit" "1-bit wide,4-bit wide,8-bit wide,?..."
|
|
newline
|
|
bitfld.long 0x00 12. " PWRSAV ,Power saving configuration bit" "Always enabled,Enabled on bus active"
|
|
hexmask.long.word 0x00 0.--9. 1. " CLKDIV ,Clock divide factor"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "CLKCR,SDMMC Clock Control Register"
|
|
bitfld.long 0x00 20.--21. " SELCLKRX ,Receive clock selection" "IO_IN_CK,CKIN,FB_CK,?..."
|
|
bitfld.long 0x00 19. " BUSSPEED ,Bus speed mode selection between DS HS SDR12 SDR25 and SDR50 DDR50 SDR104" "DS/HS/SDR12/SDR25,SDR50/DDR50/SDR104"
|
|
bitfld.long 0x00 18. " DDR ,Data rate signaling selection" "Single,Double"
|
|
newline
|
|
bitfld.long 0x00 17. " HWFC_EN ,Hardware flow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " NEGEDGE ,CK dephasing selection bit for data and command" "0,1"
|
|
bitfld.long 0x00 14.--15. " WIDBUS ,Wide bus mode enable bit" "1-bit wide,4-bit wide,8-bit wide,?..."
|
|
newline
|
|
bitfld.long 0x00 12. " PWRSAV ,Power saving configuration bit" "Always enabled,Enabled on bus active"
|
|
hexmask.long.word 0x00 0.--9. 1. " CLKDIV ,Clock divide factor"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ARG,SDMMC Argument Register"
|
|
if (((per.l(ad:0x40011C00+0x0C)&0x1000)==0x1000))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CMD,SDMMC Command Register"
|
|
rbitfld.long 0x00 16. " CMDSUSPEND ,The CPSM treats the command as a suspend or resume command and signals interrupt period start/end" "Suspended,Resumed"
|
|
bitfld.long 0x00 15. " BOOTEN ,Enable boot mode procedure" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " BOOTMODE ,Select the boot mode procedure to be used" "Normal,Alternative"
|
|
newline
|
|
bitfld.long 0x00 13. " DTHOLD ,Hold new data block transmission and reception in the DPSM" "Not held,Held"
|
|
bitfld.long 0x00 12. " CPSMEN ,Command path state machine (CPSM) enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " WAITPEND ,CPSM waits for ends of data transfer (CmdPend internal signal)" "No wait,Wait"
|
|
newline
|
|
bitfld.long 0x00 10. " WAITINT ,CPSM waits for interrupt request" "No wait,Wait"
|
|
rbitfld.long 0x00 8.--9. " WAITRESP ,Wait for response bits" "No resp(CMDSENT),Short(CMDREND||CCRCFAIL),No resp(CMDSENT),Long(CMDREND||CCRCFAIL)"
|
|
rbitfld.long 0x00 7. " CMDSTOP ,The CPSM treats the command as a stop transmission command and signals abort to the DPSM" "No abort signal issued,Abort signal issued"
|
|
newline
|
|
rbitfld.long 0x00 6. " CMDTRANS ,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "No end of interrupt period,Interrupt period"
|
|
rbitfld.long 0x00 0.--5. " CMDINDEX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CMD,SDMMC Command Register"
|
|
bitfld.long 0x00 16. " CMDSUSPEND ,The CPSM treats the command as a suspend or resume command and signals interrupt period start/end" "Suspended,Resumed"
|
|
bitfld.long 0x00 15. " BOOTEN ,Enable boot mode procedure" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BOOTMODE ,Select the boot mode procedure to be used" "Normal,Alternative"
|
|
newline
|
|
bitfld.long 0x00 13. " DTHOLD ,Hold new data block transmission and reception in the DPSM" "Not held,Held"
|
|
bitfld.long 0x00 12. " CPSMEN ,Command path state machine (CPSM) enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " WAITPEND ,CPSM waits for ends of data transfer (CmdPend internal signal)" "No wait,Wait"
|
|
newline
|
|
bitfld.long 0x00 10. " WAITINT ,CPSM waits for interrupt request" "No wait,Wait"
|
|
bitfld.long 0x00 8.--9. " WAITRESP ,Wait for response bits" "No resp(CMDSENT),Short(CMDREND||CCRCFAIL),No resp(CMDSENT),Long(CMDREND||CCRCFAIL)"
|
|
bitfld.long 0x00 7. " CMDSTOP ,The CPSM treats the command as a stop transmission command and signals abort to the DPSM" "No abort signal issued,Abort signal issued"
|
|
newline
|
|
bitfld.long 0x00 6. " CMDTRANS ,The CPSM treats the command as a data transfer command stops the interrupt period and signals DataEnable to the DPSM" "No end of interrupt period,Interrupt period"
|
|
bitfld.long 0x00 0.--5. " CMDINDEX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
else
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "POWER,SDMMC Power Control Register"
|
|
bitfld.long 0x00 0.--1. " PWRCTRL ,Power supply control bits" "Power off,,Power-up,Power-on"
|
|
line.long 0x04 "CLKCR,SDMMC Clock Control Register"
|
|
bitfld.long 0x04 14. " HWFC_EN ,HW flow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " NEGEDGE ,CK dephasing selection bit" "Rising edge,Falling edge"
|
|
bitfld.long 0x04 11.--12. " WIDBUS ,Wide bus mode enable bit" "Default,4-wide,8-wide,?..."
|
|
newline
|
|
bitfld.long 0x04 10. " BYPASS ,Clock divider bypass enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " PWRSAV ,Power saving configuration bit" "Always enabled,Only when bus active"
|
|
bitfld.long 0x04 8. " CLKEN ,Clock enable bit" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. " CLKDIV ,Clock divide factor"
|
|
line.long 0x08 "ARG,SDMMC Argument Register"
|
|
if ((per.l((ad:0x40011C00+0x2C))&0x04)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CMD,SDMMC Command Register"
|
|
bitfld.long 0x00 11. " SDIOSUSPEND ,SD I/O suspend command" "Others,Suspend command"
|
|
bitfld.long 0x00 10. " CPSMEN ,Command path state machine (CPSM) enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " WAITINT ,CPSM waits for interrupt request" "No wait,Wait"
|
|
bitfld.long 0x00 6.--7. " WAITRESP ,Wait for response bits" "No resp(CMDSENT),Short(CMDREND||CCRCFAIL),No resp(CMDSENT),Long(CMDREND||CCRCFAIL)"
|
|
bitfld.long 0x00 0.--5. " CMDINDEX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CMD,SDMMC Command Register"
|
|
bitfld.long 0x00 11. " SDIOSUSPEND ,SD I/O suspend command" "Others,Suspend command"
|
|
bitfld.long 0x00 10. " CPSMEN ,Command path state machine (CPSM) enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " WAITPEND ,CPSM waits for ends of data transfer" "No wait,Wait"
|
|
newline
|
|
bitfld.long 0x00 8. " WAITINT ,CPSM waits for interrupt request" "No wait,Wait"
|
|
bitfld.long 0x00 6.--7. " WAITRESP ,Wait for response bits" "No resp(CMDSENT),Short(CMDREND||CCRCFAIL),No resp(CMDSENT),Long(CMDREND||CCRCFAIL)"
|
|
bitfld.long 0x00 0.--5. " CMDINDEX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "RESPCMD,SDMMC Command Response Register"
|
|
bitfld.long 0x00 0.--5. " RESPCMD ,Response command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
if ((per.l((ad:0x40011C00+0x0C))&0xC0)==0x40)
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "RESP1,SDMMC Response 1 Register"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "RESP2,SDMMC Response 2 Register"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "RESP3,SDMMC Response 3 Register"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "RESP4,SDMMC Response 4 Register"
|
|
elif ((per.l((ad:0x40011C00+0x0C))&0xC0)==0xC0)
|
|
rgroup.long 0x14++0x0F
|
|
line.long 0x00 "RESP1,SDMMC Response 1 Register"
|
|
line.long 0x04 "RESP2,SDMMC Response 2 Register"
|
|
line.long 0x08 "RESP3,SDMMC Response 3 Register"
|
|
line.long 0x0C "RESP4,SDMMC Response 4 Register"
|
|
else
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "RESP1,SDMMC Response 1 Register"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "RESP2,SDMMC Response 2 Register"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "RESP3,SDMMC Response 3 Register"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "RESP4,SDMMC Response 4 Register"
|
|
endif
|
|
group.long 0x24++0x07
|
|
line.long 0x00 "DTIMER,SDMMC Data Timer Register"
|
|
line.long 0x04 "DLEN,SDMMC Data Length Register"
|
|
hexmask.long 0x04 0.--24. 1. " DATALENGTH ,Data length value"
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40011C00+0x34)&0x1000)==0x1000))&&(((per.l(ad:0x40011C00+0x50)&0x01)==0x00))
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DCTRL,SDMMC Data Control Register"
|
|
bitfld.long 0x00 13. " FIFORST ,FIFO reset will flush any remaining data" "Not affected,Flushed"
|
|
rbitfld.long 0x00 12. " BOOTACKEN ,Enable the reception of the boot acknowledgment" "Disabled,Enabled"
|
|
rbitfld.long 0x00 11. " SDIOEN ,SD I/O enable functions" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 10. " RWMOD ,Read wait mode" "Using D2,Stopping CK"
|
|
bitfld.long 0x00 9. " RWSTOP ,Read wait stop" "In progress,Stopped"
|
|
bitfld.long 0x00 8. " RWSTART ,Read wait start" "Stopped,Started"
|
|
newline
|
|
rbitfld.long 0x00 4.--7. " DBLOCKSIZE ,Data block size" "1byte,2bytes,4bytes,8bytes,16bytes,32bytes,64bytes,128bytes,256bytes,512bytes,1024bytes,2048bytes,4096bytes,8192bytes,16384bytes,?..."
|
|
rbitfld.long 0x00 2.--3. " DTMODE ,Data transfer mode selection" "Block(ending on block cnt),SDIO,MMC,Block(ending on STOP_TRANSMISSION cmd)"
|
|
rbitfld.long 0x00 1. " DTDIR ,Data transfer direction selection" "Host->Card,Card->Host"
|
|
newline
|
|
rbitfld.long 0x00 0. " DTEN ,Data transfer enabled bit" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40011C00+0x34)&0x1000)==0x1000))&&(((per.l(ad:0x40011C00+0x50)&0x01)==0x01))
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DCTRL,SDMMC Data Control Register"
|
|
rbitfld.long 0x00 13. " FIFORST ,FIFO reset will flush any remaining data" "Not affected,Flushed"
|
|
rbitfld.long 0x00 12. " BOOTACKEN ,Enable the reception of the boot acknowledgment" "Disabled,Enabled"
|
|
rbitfld.long 0x00 11. " SDIOEN ,SD I/O enable functions" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 10. " RWMOD ,Read wait mode" "Using D2,Stopping CK"
|
|
bitfld.long 0x00 9. " RWSTOP ,Read wait stop" "In progress,Stopped"
|
|
bitfld.long 0x00 8. " RWSTART ,Read wait start" "Stopped,Started"
|
|
newline
|
|
rbitfld.long 0x00 4.--7. " DBLOCKSIZE ,Data block size" "1byte,2bytes,4bytes,8bytes,16bytes,32bytes,64bytes,128bytes,256bytes,512bytes,1024bytes,2048bytes,4096bytes,8192bytes,16384bytes,?..."
|
|
rbitfld.long 0x00 2.--3. " DTMODE ,Data transfer mode selection" "Block(ending on block cnt),SDIO,MMC,Block(ending on STOP_TRANSMISSION cmd)"
|
|
rbitfld.long 0x00 1. " DTDIR ,Data transfer direction selection" "Host->Card,Card->Host"
|
|
newline
|
|
rbitfld.long 0x00 0. " DTEN ,Data transfer enabled bit" "Disabled,Enabled"
|
|
else
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DCTRL,SDMMC Data Control Register"
|
|
rbitfld.long 0x00 13. " FIFORST ,FIFO reset will flush any remaining data" "Not affected,Flushed"
|
|
bitfld.long 0x00 12. " BOOTACKEN ,Enable the reception of the boot acknowledgment" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SDIOEN ,SD I/O enable functions" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " RWMOD ,Read wait mode" "Using D2,Stopping CK"
|
|
bitfld.long 0x00 9. " RWSTOP ,Read wait stop" "In progress,Stopped"
|
|
bitfld.long 0x00 8. " RWSTART ,Read wait start" "Stopped,Started"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " DBLOCKSIZE ,Data block size" "1byte,2bytes,4bytes,8bytes,16bytes,32bytes,64bytes,128bytes,256bytes,512bytes,1024bytes,2048bytes,4096bytes,8192bytes,16384bytes,?..."
|
|
bitfld.long 0x00 2.--3. " DTMODE ,Data transfer mode selection" "Block(ending on block cnt),SDIO,MMC,Block(ending on STOP_TRANSMISSION cmd)"
|
|
bitfld.long 0x00 1. " DTDIR ,Data transfer direction selection" "Host->Card,Card->Host"
|
|
newline
|
|
bitfld.long 0x00 0. " DTEN ,Data transfer enabled bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40011C00+0x2C))&0x800)==0x800)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DCTRL,SDMMC Data Control Register"
|
|
bitfld.long 0x00 11. " SDIOEN ,SD I/O enable functions" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RWMOD ,Read wait mode" "Stopping D2,Using CK"
|
|
bitfld.long 0x00 9. " RWSTOP ,Read wait stop" "In progress,Stopped"
|
|
newline
|
|
bitfld.long 0x00 8. " RWSTART ,Read wait stop" "Stopped,Started"
|
|
bitfld.long 0x00 4.--7. " DBLOCKSIZE ,Data block size" "1byte,2bytes,4bytes,8bytes,16bytes,32bytes,64bytes,128bytes,256bytes,512bytes,1024bytes,2048bytes,4096bytes,8192bytes,16384bytes,?..."
|
|
bitfld.long 0x00 3. " DMAEN ,DMA enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " DTMODE ,Data transfer mode selection" "Block,Stream or SDIO multibyte"
|
|
bitfld.long 0x00 1. " DTDIR ,Data transfer direction selection" "Controller->Card,Card->Controller"
|
|
bitfld.long 0x00 0. " DTEN ,Data transfer enabled bit" "Disabled,Enabled"
|
|
else
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DCTRL,SDMMC Data Control Register"
|
|
bitfld.long 0x00 11. " SDIOEN ,SD I/O enable functions" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RWMOD ,Read wait mode" "Stopping D2,Using CK"
|
|
bitfld.long 0x00 9. " RWSTOP ,Read wait stop" "In progress,Stopped"
|
|
newline
|
|
bitfld.long 0x00 8. " RWSTART ,Read wait stop" "Stopped,Started"
|
|
bitfld.long 0x00 4.--7. " DBLOCKSIZE ,Data block size" "1byte,2bytes,4bytes,8bytes,16bytes,32bytes,64bytes,128bytes,256bytes,512bytes,1024bytes,2048bytes,4096bytes,8192bytes,16384bytes,?..."
|
|
bitfld.long 0x00 3. " DMAEN ,DMA enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " DTMODE ,Data transfer mode selection" "Block,MultiMediaCard stream"
|
|
bitfld.long 0x00 1. " DTDIR ,Data transfer direction selection" "Controller->Card,Card->Controller"
|
|
bitfld.long 0x00 0. " DTEN ,Data transfer enabled bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.long 0x30++0x07
|
|
line.long 0x00 "DCOUNT,SDMMC Data Counter Register"
|
|
hexmask.long 0x00 0.--24. 1. " DATACOUNT ,Data count value"
|
|
line.long 0x04 "STA,SDMMC Status Register"
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
bitfld.long 0x04 28. " IDMABTC ,IDMA buffer transfer complete" "Not completed,Completed"
|
|
bitfld.long 0x04 27. " IDMATE ,IDMA transfer error" "No error,Error"
|
|
bitfld.long 0x04 26. " CKSTOP ,CK stopped in voltage switch procedure" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x04 25. " VSWEND ,Voltage switch critical timing section completion" "Not completed,Completed"
|
|
bitfld.long 0x04 24. " ACKTIMEOUT ,Boot acknowledgment timeout" "Not timed-out,Timed-out"
|
|
bitfld.long 0x04 23. " ACKFAIL ,Boot acknowledgment received" "Not received,Received"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 22. " SDIOIT ,SDIO interrupt received" "Not received,Received"
|
|
newline
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
bitfld.long 0x04 21. " BUSYD0END ,End of D0 busy following a CMD response detected" "Not detected,Detected"
|
|
bitfld.long 0x04 20. " BUSYD0 ,Card signals busy on D0 indicator" "Not busy,Busy"
|
|
else
|
|
bitfld.long 0x04 21. " RXDAVL ,Data available in receive FIFO" "No data,Data available"
|
|
bitfld.long 0x04 20. " TXDAVL ,Data available in transmit FIFO" "No data,Data available"
|
|
endif
|
|
newline
|
|
bitfld.long 0x04 19. " RXFIFOE ,Receive FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x04 18. " TXFIFOE ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x04 17. " RXFIFOF ,Receive FIFO full" "Not full,Full"
|
|
newline
|
|
bitfld.long 0x04 16. " TXFIFOF ,Transmit FIFO full" "Not full,Full"
|
|
bitfld.long 0x04 15. " RXFIFOHF ,Receive FIFO half full: there are at least 8 words in the FIFO" "Not half full,Half full"
|
|
bitfld.long 0x04 14. " TXFIFOHE ,Transmit FIFO half empty: there are at least 8 words in the FIFO" "Not half empty,Half empty"
|
|
newline
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
bitfld.long 0x04 13. " CPSMACT ,Command path state machine active" "Not active,Active"
|
|
bitfld.long 0x04 12. " DPSMACT ,Data path state machine active" "Not active,Active"
|
|
bitfld.long 0x04 11. " DABORT ,Data transfer aborted by CMD12" "Not aborted,Aborted"
|
|
newline
|
|
else
|
|
bitfld.long 0x04 13. " RXACT ,Data receive in progress" "Done,In progress"
|
|
bitfld.long 0x04 12. " TXACT ,Data transmit in progress" "Done,In progress"
|
|
bitfld.long 0x04 11. " CMDACT ,Command transfer in progress" "Done,In progress"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 10. " DBCKEND ,Data block sent/received" "Sending/Receiving,Sent/Received"
|
|
newline
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
bitfld.long 0x04 9. " DHOLD ,Data transfer hold" "Not held,Held"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 8. " DATAEND ,Data end" "No data end,Data end"
|
|
bitfld.long 0x04 7. " CMDSENT ,Command sent" "Not sent,Sent"
|
|
bitfld.long 0x04 6. " CMDREND ,Command response received" "Not received,Received"
|
|
newline
|
|
bitfld.long 0x04 5. " RXOVERR ,Received FIFO overrun error" "No error,Error"
|
|
bitfld.long 0x04 4. " TXUNDERR ,Transmit FIFO underrun error" "No error,Error"
|
|
bitfld.long 0x04 3. " DTIMEOUT ,Data timeout" "No timeout,Timeout"
|
|
newline
|
|
bitfld.long 0x04 2. " CTIMEOUT ,Command response timeout" "No timeout,Timeout"
|
|
bitfld.long 0x04 1. " DCRCFAIL ,Data block sent/received" "Sending/Receiving,Sent/Received"
|
|
bitfld.long 0x04 0. " CCRCFAIL ,Command response received" "Not received,Received"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "ICR,SDMMC Interrupt Clear Register"
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
bitfld.long 0x00 28. " IDMABTCC ,IDMA buffer transfer complete clear bit" "Not cleared,Clear"
|
|
bitfld.long 0x00 27. " IDMATEC ,IDMA transfer error clear bit" "Not cleared,Clear"
|
|
bitfld.long 0x00 26. " CKSTOPC ,CKSTOP flag clear bit" "Not cleared,Clear"
|
|
newline
|
|
bitfld.long 0x00 25. " VSWENDC ,VSWEND flag clear bit" "Not cleared,Clear"
|
|
bitfld.long 0x00 24. " ACKTIMEOUTC ,ACKTIMEOUT flag clear bit" "Not cleared,Clear"
|
|
bitfld.long 0x00 23. " ACKFAILC ,ACKFAIL flag clear bit" "Not cleared,Clear"
|
|
newline
|
|
bitfld.long 0x00 22. " SDIOITC ,SDIOIT flag clear bit" "Not cleared,Clear"
|
|
bitfld.long 0x00 21. " BUSYD0ENDC ,BUSYD0END flag clear bit" "Not cleared,Clear"
|
|
bitfld.long 0x00 11. " DABORTC ,DABORT flag clear bit" "Not cleared,Clear"
|
|
newline
|
|
bitfld.long 0x00 10. " DBCKENDC ,DBCKEND flag clear bit" "Not cleared,Clear"
|
|
bitfld.long 0x00 9. " DHOLDC ,DHOLD flag clear bit" "Not cleared,Clear"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 22. " SDIOITC ,SDIOIT flag clear bit" "Not cleared,Clear"
|
|
bitfld.long 0x00 10. " DBCKENDC ,DBCKEND flag clear bit" "Not cleared,Clear"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 8. " DATAENDC ,DATAEND flag clear bit" "Not cleared,Clear"
|
|
bitfld.long 0x00 7. " CMDSENTC ,CMDSENT flag clear bit" "Not cleared,Clear"
|
|
bitfld.long 0x00 6. " CMDRENDC ,CMDREND flag clear bit" "Not cleared,Clear"
|
|
newline
|
|
bitfld.long 0x00 5. " RXOVERRC ,RXOVERR flag clear bit" "Not cleared,Clear"
|
|
bitfld.long 0x00 4. " TXUNDERRC ,TXUNDERR flag clear bit" "Not cleared,Clear"
|
|
bitfld.long 0x00 3. " DTIMEOUTC ,DTIMEOUT flag clear bit" "Not cleared,Clear"
|
|
newline
|
|
bitfld.long 0x00 2. " CTIMEOUTC ,CTIMEOUT flag clear bit" "Not cleared,Clear"
|
|
bitfld.long 0x00 1. " DCRCFAILC ,DCRCFAIL flag clear bit" "Not cleared,Clear"
|
|
bitfld.long 0x00 0. " CCRCFAILC ,CCRCFAIL flag clear bit" "Not cleared,Clear"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "MASK,SDMMC Mask Register"
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
bitfld.long 0x00 28. " IDMABTCIE ,IDMA buffer transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " CKSTOPIE ,Voltage switch clock stopped interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " VSWENDIE ,Voltage switch critical timing section completion interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24. " ACKTIMEOUTIE ,Acknowledgment timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " ACKFAILIE ,Acknowledgment fail interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " SDIOITIE ,SDIO interrupt received interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. " BUSYD0ENDIE ,BUSYD0END interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 22. " SDIOITIE ,SDIO interrupt received interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " RXDAVLIE ,Data available in receive FIFO interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TXDAVLIE ,Data available in transmit FIFO interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " RXFIFOEIE ,Receive FIFO empty interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 18. " TXFIFOEIE ,Transmit FIFO empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RXFIFOFIE ,Receive FIFO full interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
bitfld.long 0x00 16. " TXFIFOFIE ,Transmit FIFO full interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15. " RXFIFOHFIE ,Receive FIFO half full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXFIFOHEIE ,Transmit FIFO half empty interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
bitfld.long 0x00 13. " RXACTIE ,Data receive in progress interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " TXACTIE ,Data transmit in progress interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " CMDACTIE ,Command transfer in progress interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " DBCKENDIE ,Data block sent/received interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 11. " DABORTIE ,Data transfer aborted interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DBCKENDIE ,Data block sent/received interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " DHOLDIE ,Data hold interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 8. " DATAENDIE ,Data end interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CMDSENTIE ,Command sent interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CMDRENDIE ,Command response received interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " RXOVERRIE ,Received FIFO overrun error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TXUNDERRIE ,Transmit FIFO underrun error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DTIMEOUTIE ,Data timeout interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CTIMEOUTIE ,Command response timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DCRCFAILIE ,Data block sent/received interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CCRCFAILIE ,Command response received interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
width 10.
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "FIFOCNT,SDMMC FIFO Counter Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " FIFOCOUNT ,Remaining number of words to be written to or read from the FIFO"
|
|
else
|
|
if (((per.l(ad:0x40011C00+0x0C)&0x1000)==0x1000))
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "ACKTIMER,SDMMC Acknowledgment Timer Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ACKTIME ,Boot acknowledgment timeout period"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "ACKTIMER,SDMMC Acknowledgment Timer Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ACKTIME ,Boot acknowledgment timeout period"
|
|
endif
|
|
endif
|
|
newline
|
|
sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*"))
|
|
hgroup.long 0x80++0x03
|
|
hide.long 0x00 "FIFO0,SDMMC Data FIFO Register 0"
|
|
in
|
|
hgroup.long 0x84++0x03
|
|
hide.long 0x00 "FIFO1,SDMMC Data FIFO Register 1"
|
|
in
|
|
hgroup.long 0x88++0x03
|
|
hide.long 0x00 "FIFO2,SDMMC Data FIFO Register 2"
|
|
in
|
|
hgroup.long 0x8C++0x03
|
|
hide.long 0x00 "FIFO3,SDMMC Data FIFO Register 3"
|
|
in
|
|
hgroup.long 0x90++0x03
|
|
hide.long 0x00 "FIFO4,SDMMC Data FIFO Register 4"
|
|
in
|
|
hgroup.long 0x94++0x03
|
|
hide.long 0x00 "FIFO5,SDMMC Data FIFO Register 5"
|
|
in
|
|
hgroup.long 0x98++0x03
|
|
hide.long 0x00 "FIFO6,SDMMC Data FIFO Register 6"
|
|
in
|
|
hgroup.long 0x9C++0x03
|
|
hide.long 0x00 "FIFO7,SDMMC Data FIFO Register 7"
|
|
in
|
|
hgroup.long 0xA0++0x03
|
|
hide.long 0x00 "FIFO8,SDMMC Data FIFO Register 8"
|
|
in
|
|
hgroup.long 0xA4++0x03
|
|
hide.long 0x00 "FIFO9,SDMMC Data FIFO Register 9"
|
|
in
|
|
hgroup.long 0xA8++0x03
|
|
hide.long 0x00 "FIFO10,SDMMC Data FIFO Register 10"
|
|
in
|
|
hgroup.long 0xAC++0x03
|
|
hide.long 0x00 "FIFO11,SDMMC Data FIFO Register 11"
|
|
in
|
|
hgroup.long 0xB0++0x03
|
|
hide.long 0x00 "FIFO12,SDMMC Data FIFO Register 12"
|
|
in
|
|
hgroup.long 0xB4++0x03
|
|
hide.long 0x00 "FIFO13,SDMMC Data FIFO Register 13"
|
|
in
|
|
hgroup.long 0xB8++0x03
|
|
hide.long 0x00 "FIFO14,SDMMC Data FIFO Register 14"
|
|
in
|
|
hgroup.long 0xBC++0x03
|
|
hide.long 0x00 "FIFO15,SDMMC Data FIFO Register 15"
|
|
in
|
|
hgroup.long 0xC0++0x03
|
|
hide.long 0x00 "FIFO16,SDMMC Data FIFO Register 16"
|
|
in
|
|
hgroup.long 0xC4++0x03
|
|
hide.long 0x00 "FIFO17,SDMMC Data FIFO Register 17"
|
|
in
|
|
hgroup.long 0xC8++0x03
|
|
hide.long 0x00 "FIFO18,SDMMC Data FIFO Register 18"
|
|
in
|
|
hgroup.long 0xCC++0x03
|
|
hide.long 0x00 "FIFO19,SDMMC Data FIFO Register 19"
|
|
in
|
|
hgroup.long 0xD0++0x03
|
|
hide.long 0x00 "FIFO20,SDMMC Data FIFO Register 20"
|
|
in
|
|
hgroup.long 0xD4++0x03
|
|
hide.long 0x00 "FIFO21,SDMMC Data FIFO Register 21"
|
|
in
|
|
hgroup.long 0xD8++0x03
|
|
hide.long 0x00 "FIFO22,SDMMC Data FIFO Register 22"
|
|
in
|
|
hgroup.long 0xDC++0x03
|
|
hide.long 0x00 "FIFO23,SDMMC Data FIFO Register 23"
|
|
in
|
|
hgroup.long 0xE0++0x03
|
|
hide.long 0x00 "FIFO24,SDMMC Data FIFO Register 24"
|
|
in
|
|
hgroup.long 0xE4++0x03
|
|
hide.long 0x00 "FIFO25,SDMMC Data FIFO Register 25"
|
|
in
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "FIFO26,SDMMC Data FIFO Register 26"
|
|
in
|
|
hgroup.long 0xEC++0x03
|
|
hide.long 0x00 "FIFO27,SDMMC Data FIFO Register 27"
|
|
in
|
|
hgroup.long 0xF0++0x03
|
|
hide.long 0x00 "FIFO28,SDMMC Data FIFO Register 28"
|
|
in
|
|
hgroup.long 0xF4++0x03
|
|
hide.long 0x00 "FIFO29,SDMMC Data FIFO Register 29"
|
|
in
|
|
hgroup.long 0xF8++0x03
|
|
hide.long 0x00 "FIFO30,SDMMC Data FIFO Register 30"
|
|
in
|
|
hgroup.long 0xFC++0x03
|
|
hide.long 0x00 "FIFO31,SDMMC Data FIFO Register 31"
|
|
in
|
|
else
|
|
hgroup.long 0x80++0x03
|
|
hide.long 0x00 "FIFO0,SDMMC Data FIFO Register 0"
|
|
in
|
|
hgroup.long 0x84++0x03
|
|
hide.long 0x00 "FIFO1,SDMMC Data FIFO Register 1"
|
|
in
|
|
hgroup.long 0x88++0x03
|
|
hide.long 0x00 "FIFO2,SDMMC Data FIFO Register 2"
|
|
in
|
|
hgroup.long 0x8C++0x03
|
|
hide.long 0x00 "FIFO3,SDMMC Data FIFO Register 3"
|
|
in
|
|
hgroup.long 0x90++0x03
|
|
hide.long 0x00 "FIFO4,SDMMC Data FIFO Register 4"
|
|
in
|
|
hgroup.long 0x94++0x03
|
|
hide.long 0x00 "FIFO5,SDMMC Data FIFO Register 5"
|
|
in
|
|
hgroup.long 0x98++0x03
|
|
hide.long 0x00 "FIFO6,SDMMC Data FIFO Register 6"
|
|
in
|
|
hgroup.long 0x9C++0x03
|
|
hide.long 0x00 "FIFO7,SDMMC Data FIFO Register 7"
|
|
in
|
|
hgroup.long 0xA0++0x03
|
|
hide.long 0x00 "FIFO8,SDMMC Data FIFO Register 8"
|
|
in
|
|
hgroup.long 0xA4++0x03
|
|
hide.long 0x00 "FIFO9,SDMMC Data FIFO Register 9"
|
|
in
|
|
hgroup.long 0xA8++0x03
|
|
hide.long 0x00 "FIFO10,SDMMC Data FIFO Register 10"
|
|
in
|
|
hgroup.long 0xAC++0x03
|
|
hide.long 0x00 "FIFO11,SDMMC Data FIFO Register 11"
|
|
in
|
|
hgroup.long 0xB0++0x03
|
|
hide.long 0x00 "FIFO12,SDMMC Data FIFO Register 12"
|
|
in
|
|
hgroup.long 0xB4++0x03
|
|
hide.long 0x00 "FIFO13,SDMMC Data FIFO Register 13"
|
|
in
|
|
hgroup.long 0xB8++0x03
|
|
hide.long 0x00 "FIFO14,SDMMC Data FIFO Register 14"
|
|
in
|
|
hgroup.long 0xBC++0x03
|
|
hide.long 0x00 "FIFO15,SDMMC Data FIFO Register 15"
|
|
in
|
|
endif
|
|
newline
|
|
width 12.
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40011C00+0x34)&0x1000)==0x1000))
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "IDMACTRLR,SDMMC DMA Control Register"
|
|
bitfld.long 0x00 2. " IDMABACT ,Double buffer mode active buffer indication" "Buffer0 && IDMABASE0 prohibited,Buffer1 && IDMABASE1 prohibited"
|
|
bitfld.long 0x00 1. " IDMABMODE ,Buffer mode selection" "Single,Double"
|
|
bitfld.long 0x00 0. " IDMAEN ,IDMA enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "IDMACTRLR,SDMMC DMA Control Register"
|
|
bitfld.long 0x00 2. " IDMABACT ,Double buffer mode active buffer indication" "Buffer0 && IDMABASE0 prohibited,Buffer1 && IDMABASE1 prohibited"
|
|
bitfld.long 0x00 1. " IDMABMODE ,Buffer mode selection" "Single,Double"
|
|
bitfld.long 0x00 0. " IDMAEN ,IDMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x54++0x0B
|
|
line.long 0x00 "IDMABSIZER,SDMMC IDMA Buffer Size Register"
|
|
hexmask.long.word 0x00 5.--12. 1. " IDMABNDT ,Number of transfers per buffer"
|
|
line.long 0x04 "IDMABASE0R,SDMMC IDMA Buffer 0 Base Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " IDMABASE0[31:2] ,Buffer 0 memory base address bits [31:2]"
|
|
rbitfld.long 0x04 0.--1. " IDMABASE0[1:0] ,Buffer 0 memory base address bits [1:0]" "0,1,2,3"
|
|
line.long 0x08 "IDMABASE1R,SDMMC IDMA Buffer 1 Base Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " IDMABASE1[31:2] ,Buffer 1 memory base address bits [31:2]"
|
|
rbitfld.long 0x08 0.--1. " IDMABASE1[1:0] ,Buffer 1 memory base address bits [1:0]" "0,1,2,3"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree.open "CAN (Controller Area Network)"
|
|
tree "CAN 1"
|
|
base ad:0x40006400
|
|
width 7.
|
|
group.long 0x00++0x1F
|
|
line.long 0x00 "MCR,CAN Master Control Register"
|
|
bitfld.long 0x00 16. " DBF ,Debug freeze" "Not frozen,Frozen"
|
|
bitfld.long 0x00 15. " RESET ,bxCAN software master reset" "No reset,Reset"
|
|
bitfld.long 0x00 7. " TTCM ,Time triggered communication mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ABOM ,Automatic bus-off management" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " AWUM ,Automatic wake-up mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NART ,No automatic retransmission" "Retransmitted,Transmitted once"
|
|
bitfld.long 0x00 3. " RFLM ,Receive FIFO locked mode" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " TXFP ,Transmit FIFO priority" "Identifier,Request order"
|
|
newline
|
|
bitfld.long 0x00 1. " SLEEP ,SLEEP mode request" "Normal mode,Sleep mode"
|
|
bitfld.long 0x00 0. " INRQ ,Initialization request" "No effect,Initialize"
|
|
line.long 0x04 "MSR,CAN Master Status Register"
|
|
rbitfld.long 0x04 11. " RX ,CAN Rx signal" "0,1"
|
|
rbitfld.long 0x04 10. " SAMP ,Last sample point" "0,1"
|
|
rbitfld.long 0x04 9. " RXM ,Receive mode" "Not receiving,Receiving"
|
|
rbitfld.long 0x04 8. " TXM ,Transmit mode" "Not transmitting,Transmitting"
|
|
newline
|
|
eventfld.long 0x04 4. " SLAKI ,SLEEP acknowledge interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 3. " WKUI ,Wake-Up interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 2. " ERRI ,Error interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x04 1. " SLAK ,SLEEP acknowledge" "No sleep,Sleep"
|
|
newline
|
|
rbitfld.long 0x04 0. " INAK ,Initialization acknowledge" "No initialization,Initialization"
|
|
line.long 0x08 "TSR,CAN Transmit Status Register"
|
|
rbitfld.long 0x08 31. " LOW2 ,Lowest priority flag for mailbox 2" "Not lowest,Lowest"
|
|
rbitfld.long 0x08 30. " LOW1 ,Lowest priority flag for mailbox 1" "Not lowest,Lowest"
|
|
rbitfld.long 0x08 29. " LOW0 ,Lowest priority flag for mailbox 0" "Not lowest,Lowest"
|
|
rbitfld.long 0x08 28. " TME2 ,Transmit mailbox 2 empty" "Not empty,Empty"
|
|
newline
|
|
rbitfld.long 0x08 27. " TME1 ,Transmit mailbox 1 empty" "Not empty,Empty"
|
|
rbitfld.long 0x08 26. " TME0 ,Transmit mailbox 0 empty" "Not empty,Empty"
|
|
rbitfld.long 0x08 24.--25. " CODE ,Mailbox code" "0,1,2,3"
|
|
bitfld.long 0x08 23. " ABRQ2 ,Abort request for mailbox 2" "Not requested,Requested"
|
|
newline
|
|
eventfld.long 0x08 19. " TERR2 ,Transmission error of mailbox 2" "No error,Error"
|
|
eventfld.long 0x08 18. " ALST2 ,Arbitration lost for mailbox 2" "Not lost,Lost"
|
|
eventfld.long 0x08 17. " TXOK2 ,Transmission OK of mailbox 2" "Failed,Successful"
|
|
eventfld.long 0x08 16. " RQCP2 ,Request completed mailbox 2" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x08 15. " ABRQ1 ,Abort request for mailbox 1" "Not requested,Requested"
|
|
eventfld.long 0x08 11. " TERR1 ,Transmission error of mailbox 1" "No error,Error"
|
|
eventfld.long 0x08 10. " ALST1 ,Arbitration lost for mailbox 1" "Not lost,Lost"
|
|
eventfld.long 0x08 9. " TXOK1 ,Transmission OK of mailbox 1" "Failed,Successful"
|
|
newline
|
|
eventfld.long 0x08 8. " RQCP1 ,Request completed mailbox 1" "Not completed,Completed"
|
|
bitfld.long 0x08 7. " ABRQ0 ,Abort request for mailbox 0" "Not requested,Requested"
|
|
eventfld.long 0x08 3. " TERR0 ,Transmission error of mailbox 0" "No error,Error"
|
|
eventfld.long 0x08 2. " ALST0 ,Arbitration lost for mailbox 0" "Not lost,Lost"
|
|
newline
|
|
eventfld.long 0x08 1. " TXOK0 ,Transmission OK of mailbox 0" "Failed,Successful"
|
|
eventfld.long 0x08 0. " RQCP0 ,Request completed mailbox 0" "Not completed,Completed"
|
|
line.long 0x0C "RF0R,CAN Receive FIFO 0 Register"
|
|
bitfld.long 0x0C 5. " RFOM0 ,Release FIFO 0 output mailbox" "No effect,Release"
|
|
eventfld.long 0x0C 4. " FOVR0 ,FIFO 0 overrun" "No overrun,Overrun"
|
|
eventfld.long 0x0C 3. " FULL0 ,FIFO 0 full" "Not full,Full"
|
|
rbitfld.long 0x0C 0.--1. " FMP0 ,FIFO 0 message pending" "0,1,2,3"
|
|
line.long 0x10 "RF1R,CAN Receive FIFO 1 Register"
|
|
bitfld.long 0x10 5. " RFOM1 ,Release FIFO 1 output mailbox" "No effect,Release"
|
|
eventfld.long 0x10 4. " FOVR1 ,FIFO 1 overrun" "No overrun,Overrun"
|
|
eventfld.long 0x10 3. " FULL1 ,FIFO 1 full" "Not full,Full"
|
|
rbitfld.long 0x10 0.--1. " FMP1 ,FIFO 1 message pending" "0,1,2,3"
|
|
line.long 0x14 "IER,CAN Interrupt Enable Register"
|
|
bitfld.long 0x14 17. " SLKIE ,SLEEP interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 16. " WKUIE ,Wake-Up interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 15. " ERRIE ,Error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 11. " LECIE ,Last error code interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 10. " BOFIE ,Bus-Off interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 9. " EPVIE ,Error passive interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " EWGIE ,Error warning interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " FOVIE1 ,FIFO overrun interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 5. " FFIE1 ,FIFO full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " FMPIE1 ,FIFO message pending interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 3. " FOVIE0 ,FIFO overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " FFIE0 ,FIFO full interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 1. " FMPIE0 ,FIFO message pending interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " TMEIE ,Transmit mailbox empty interrupt enable" "Disabled,Enabled"
|
|
line.long 0x18 "ESR,CAN Error Status Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " REC ,Receive error counter"
|
|
hexmask.long.byte 0x18 16.--23. 1. " TEC ,Least significant byte of the 9-bit transmit error counter"
|
|
bitfld.long 0x18 4.--6. " LEC ,Last error code" "No error,Stuff,Form,Acknowledgment,Bit recessive,Bit dominant,CRC,Set by software"
|
|
rbitfld.long 0x18 2. " BOFF ,Bus-off flag" "Not occurred,Occurred"
|
|
newline
|
|
rbitfld.long 0x18 1. " EPVF ,Error passive flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x18 0. " EWGF ,Error warning flag" "Not occurred,Occurred"
|
|
line.long 0x1C "BTR,CAN Bit Timing Register"
|
|
bitfld.long 0x1C 31. " SILM ,Silent mode" "Normal,Silent"
|
|
bitfld.long 0x1C 30. " LBKM ,Loop back mode" "Disabled,Enabled"
|
|
bitfld.long 0x1C 24.--25. " SJW ,Resynchronization jump width" "0,1,2,3"
|
|
bitfld.long 0x1C 20.--22. " TS2 ,Time segment 2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x1C 16.--19. " TS1 ,Time segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x1C 0.--9. 1. " BRP ,Baud rate prescaler"
|
|
tree "T0 Mailbox"
|
|
if (((per.l(ad:0x40006400+0x08))&(1.<<26.))==0x0)
|
|
if (((per.l((ad:0x40006400+0x180)))&0x4)==0x04)
|
|
rgroup.long 0x180++0x03
|
|
line.long 0x00 "TI0R,TX Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested"
|
|
else
|
|
rgroup.long 0x180++0x03
|
|
line.long 0x00 "TI0R,TX Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested"
|
|
endif
|
|
rgroup.long (0x180+0x04)++0x0B
|
|
line.long 0x00 "TDT0R,Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp"
|
|
bitfld.long 0x00 8. " TGT ,Transmit global time" "Not sent,Sent"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..."
|
|
line.long 0x04 "TDL0R,Mailbox Data Low Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data byte 0"
|
|
line.long 0x08 "TDH0R,Mailbox Data High Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data byte 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data byte 4"
|
|
else
|
|
if (((per.l((ad:0x40006400+0x180)))&0x4)==0x04)
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "TI0R,TX Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested"
|
|
else
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "TI0R,TX Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested"
|
|
endif
|
|
group.long (0x180+0x04)++0x0B
|
|
line.long 0x00 "TDT0R,Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp"
|
|
bitfld.long 0x00 8. " TGT ,Transmit global time" "Not sent,Sent"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..."
|
|
line.long 0x04 "TDL0R,Mailbox Data Low Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data byte 0"
|
|
line.long 0x08 "TDH0R,Mailbox Data High Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data byte 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data byte 4"
|
|
endif
|
|
tree.end
|
|
tree "T1 Mailbox"
|
|
if (((per.l(ad:0x40006400+0x08))&(1.<<27.))==0x0)
|
|
if (((per.l((ad:0x40006400+0x190)))&0x4)==0x04)
|
|
rgroup.long 0x190++0x03
|
|
line.long 0x00 "TI1R,TX Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested"
|
|
else
|
|
rgroup.long 0x190++0x03
|
|
line.long 0x00 "TI1R,TX Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested"
|
|
endif
|
|
rgroup.long (0x190+0x04)++0x0B
|
|
line.long 0x00 "TDT1R,Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp"
|
|
bitfld.long 0x00 8. " TGT ,Transmit global time" "Not sent,Sent"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..."
|
|
line.long 0x04 "TDL1R,Mailbox Data Low Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data byte 0"
|
|
line.long 0x08 "TDH1R,Mailbox Data High Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data byte 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data byte 4"
|
|
else
|
|
if (((per.l((ad:0x40006400+0x190)))&0x4)==0x04)
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "TI1R,TX Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested"
|
|
else
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "TI1R,TX Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested"
|
|
endif
|
|
group.long (0x190+0x04)++0x0B
|
|
line.long 0x00 "TDT1R,Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp"
|
|
bitfld.long 0x00 8. " TGT ,Transmit global time" "Not sent,Sent"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..."
|
|
line.long 0x04 "TDL1R,Mailbox Data Low Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data byte 0"
|
|
line.long 0x08 "TDH1R,Mailbox Data High Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data byte 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data byte 4"
|
|
endif
|
|
tree.end
|
|
tree "T2 Mailbox"
|
|
if (((per.l(ad:0x40006400+0x08))&(1.<<28.))==0x0)
|
|
if (((per.l((ad:0x40006400+0x1A0)))&0x4)==0x04)
|
|
rgroup.long 0x1A0++0x03
|
|
line.long 0x00 "TI2R,TX Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested"
|
|
else
|
|
rgroup.long 0x1A0++0x03
|
|
line.long 0x00 "TI2R,TX Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested"
|
|
endif
|
|
rgroup.long (0x1A0+0x04)++0x0B
|
|
line.long 0x00 "TDT2R,Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp"
|
|
bitfld.long 0x00 8. " TGT ,Transmit global time" "Not sent,Sent"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..."
|
|
line.long 0x04 "TDL2R,Mailbox Data Low Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data byte 0"
|
|
line.long 0x08 "TDH2R,Mailbox Data High Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data byte 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data byte 4"
|
|
else
|
|
if (((per.l((ad:0x40006400+0x1A0)))&0x4)==0x04)
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "TI2R,TX Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested"
|
|
else
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "TI2R,TX Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested"
|
|
endif
|
|
group.long (0x1A0+0x04)++0x0B
|
|
line.long 0x00 "TDT2R,Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp"
|
|
bitfld.long 0x00 8. " TGT ,Transmit global time" "Not sent,Sent"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..."
|
|
line.long 0x04 "TDL2R,Mailbox Data Low Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data byte 0"
|
|
line.long 0x08 "TDH2R,Mailbox Data High Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data byte 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data byte 4"
|
|
endif
|
|
tree.end
|
|
tree "FIFO 0"
|
|
if (((per.l((ad:0x40006400+0x1B0)))&0x4)==0x4)
|
|
rgroup.long 0x1B0++0x03
|
|
line.long 0x00 "RI0R,Rx FIFO Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
else
|
|
rgroup.long 0x1B0++0x03
|
|
line.long 0x00 "RI0R,Rx FIFO Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
endif
|
|
rgroup.long (0x1B0+0x04)++0x03
|
|
line.long 0x00 "RDT0R,Receive FIFO Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp"
|
|
hexmask.long.byte 0x00 8.--15. 1. " FMI ,Filter match index"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..."
|
|
newline
|
|
hgroup.long (0x1B0+0x08)++0x03
|
|
hide.long 0x00 "RDL0R,CAN Receive FIFO Mailbox Data Low Register"
|
|
in
|
|
hgroup.long (0x1B0+0x0C)++0x03
|
|
hide.long 0x00 "RDH0R,CAN Receive FIFO Mailbox Data High Register"
|
|
in
|
|
tree.end
|
|
tree "FIFO 1"
|
|
if (((per.l((ad:0x40006400+0x1C0)))&0x4)==0x4)
|
|
rgroup.long 0x1C0++0x03
|
|
line.long 0x00 "RI1R,Rx FIFO Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
else
|
|
rgroup.long 0x1C0++0x03
|
|
line.long 0x00 "RI1R,Rx FIFO Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
endif
|
|
rgroup.long (0x1C0+0x04)++0x03
|
|
line.long 0x00 "RDT1R,Receive FIFO Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp"
|
|
hexmask.long.byte 0x00 8.--15. 1. " FMI ,Filter match index"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..."
|
|
newline
|
|
hgroup.long (0x1C0+0x08)++0x03
|
|
hide.long 0x00 "RDL1R,CAN Receive FIFO Mailbox Data Low Register"
|
|
in
|
|
hgroup.long (0x1C0+0x0C)++0x03
|
|
hide.long 0x00 "RDH1R,CAN Receive FIFO Mailbox Data High Register"
|
|
in
|
|
tree.end
|
|
tree "Filter Registers"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "FMR,CAN Filter Master Register"
|
|
sif (!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
hexmask.long.byte 0x00 8.--13. 1. " CAN2SB ,CAN2 start bank"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 0. " FINIT ,Filter init mode" "Active mode,Initialization"
|
|
if ((per.l(ad:0x40006400+0x200)&0x01)==0x01)
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "FM1R,CAN Filter Mode Register"
|
|
sif (!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
bitfld.long 0x00 27. " FBM[27] ,Filter bank 27 mode" "Mask,List"
|
|
bitfld.long 0x00 26. " [26] ,Filter bank 26 mode" "Mask,List"
|
|
bitfld.long 0x00 25. " [25] ,Filter bank 25 mode" "Mask,List"
|
|
bitfld.long 0x00 24. " [24] ,Filter bank 24 mode" "Mask,List"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bank 23 mode" "Mask,List"
|
|
bitfld.long 0x00 22. " [22] ,Filter bank 22 mode" "Mask,List"
|
|
bitfld.long 0x00 21. " [21] ,Filter bank 21 mode" "Mask,List"
|
|
bitfld.long 0x00 20. " [20] ,Filter bank 20 mode" "Mask,List"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bank 19 mode" "Mask,List"
|
|
bitfld.long 0x00 18. " [18] ,Filter bank 18 mode" "Mask,List"
|
|
bitfld.long 0x00 17. " [17] ,Filter bank 17 mode" "Mask,List"
|
|
bitfld.long 0x00 16. " [16] ,Filter bank 16 mode" "Mask,List"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bank 15 mode" "Mask,List"
|
|
bitfld.long 0x00 14. " [14] ,Filter bank 14 mode" "Mask,List"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 13. " FBM[13] ,Filter bank 13 mode" "Mask,List"
|
|
bitfld.long 0x00 12. " [12] ,Filter bank 12 mode" "Mask,List"
|
|
bitfld.long 0x00 11. " [11] ,Filter bank 11 mode" "Mask,List"
|
|
bitfld.long 0x00 10. " [10] ,Filter bank 10 mode" "Mask,List"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Filter bank 9 mode" "Mask,List"
|
|
bitfld.long 0x00 8. " [8] ,Filter bank 8 mode" "Mask,List"
|
|
bitfld.long 0x00 7. " [7] ,Filter bank 7 mode" "Mask,List"
|
|
bitfld.long 0x00 6. " [6] ,Filter bank 6 mode" "Mask,List"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Filter bank 5 mode" "Mask,List"
|
|
bitfld.long 0x00 4. " [4] ,Filter bank 4 mode" "Mask,List"
|
|
bitfld.long 0x00 3. " [3] ,Filter bank 3 mode" "Mask,List"
|
|
bitfld.long 0x00 2. " [2] ,Filter bank 2 mode" "Mask,List"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Filter bank 1 mode" "Mask,List"
|
|
bitfld.long 0x00 0. " [0] ,Filter bank 0 mode" "Mask,List"
|
|
newline
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "FS1R,CAN Filter Scale Register"
|
|
sif (!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
bitfld.long 0x00 27. " FSC[27] ,Filter 27 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 26. " [26] ,Filter 26 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 25. " [25] ,Filter 25 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 24. " [24] ,Filter 24 scale configuration" "Dual,Single"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter 23 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 22. " [22] ,Filter 22 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 21. " [21] ,Filter 21 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 20. " [20] ,Filter 20 scale configuration" "Dual,Single"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter 19 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 18. " [18] ,Filter 18 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 17. " [17] ,Filter 17 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 16. " [16] ,Filter 16 scale configuration" "Dual,Single"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter 15 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 14. " [14] ,Filter 14 scale configuration" "Dual,Single"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 13. " FSC[13] ,Filter 13 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 12. " [12] ,Filter 12 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 11. " [11] ,Filter 11 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 10. " [10] ,Filter 10 scale configuration" "Dual,Single"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Filter 9 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 8. " [8] ,Filter 8 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 7. " [7] ,Filter 7 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 6. " [6] ,Filter 6 scale configuration" "Dual,Single"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Filter 5 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 4. " [4] ,Filter 4 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 3. " [3] ,Filter 3 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 2. " [2] ,Filter 2 scale configuration" "Dual,Single"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Filter 1 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 0. " [0] ,Filter 0 scale configuration" "Dual,Single"
|
|
newline
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "FFA1R,CAN Filter FIFO Assignment Register"
|
|
sif (!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
bitfld.long 0x00 27. " FFA[27] ,Filter FIFO assignment for filter 27" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 26. " [26] ,Filter FIFO assignment for filter 26" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 25. " [25] ,Filter FIFO assignment for filter 25" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 24. " [24] ,Filter FIFO assignment for filter 24" "FIFO0,FIFO1"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter FIFO assignment for filter 23" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 22. " [22] ,Filter FIFO assignment for filter 22" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 21. " [21] ,Filter FIFO assignment for filter 21" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 20. " [20] ,Filter FIFO assignment for filter 20" "FIFO0,FIFO1"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter FIFO assignment for filter 19" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 18. " [18] ,Filter FIFO assignment for filter 18" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 17. " [17] ,Filter FIFO assignment for filter 17" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 16. " [16] ,Filter FIFO assignment for filter 16" "FIFO0,FIFO1"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter FIFO assignment for filter 15" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 14. " [14] ,Filter FIFO assignment for filter 14" "FIFO0,FIFO1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 13. " FFA[13] ,Filter FIFO assignment for filter 13" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 12. " [12] ,Filter FIFO assignment for filter 12" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 11. " [11] ,Filter FIFO assignment for filter 11" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 10. " [10] ,Filter FIFO assignment for filter 10" "FIFO0,FIFO1"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Filter FIFO assignment for filter 9" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 8. " [8] ,Filter FIFO assignment for filter 8" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 7. " [7] ,Filter FIFO assignment for filter 7" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 6. " [6] ,Filter FIFO assignment for filter 6" "FIFO0,FIFO1"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Filter FIFO assignment for filter 5" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 4. " [4] ,Filter FIFO assignment for filter 4" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 3. " [3] ,Filter FIFO assignment for filter 3" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 2. " [2] ,Filter FIFO assignment for filter 2" "FIFO0,FIFO1"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Filter FIFO assignment for filter 1" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 0. " [0] ,Filter FIFO assignment for filter 0" "FIFO0,FIFO1"
|
|
newline
|
|
else
|
|
rgroup.long 0x204++0x03
|
|
line.long 0x00 "FM1R,CAN Filter Mode Register"
|
|
sif (!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
bitfld.long 0x00 27. " FBM[27] ,Filter bank 27 mode" "Mask,List"
|
|
bitfld.long 0x00 26. " [26] ,Filter bank 26 mode" "Mask,List"
|
|
bitfld.long 0x00 25. " [25] ,Filter bank 25 mode" "Mask,List"
|
|
bitfld.long 0x00 24. " [24] ,Filter bank 24 mode" "Mask,List"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bank 23 mode" "Mask,List"
|
|
bitfld.long 0x00 22. " [22] ,Filter bank 22 mode" "Mask,List"
|
|
bitfld.long 0x00 21. " [21] ,Filter bank 21 mode" "Mask,List"
|
|
bitfld.long 0x00 20. " [20] ,Filter bank 20 mode" "Mask,List"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bank 19 mode" "Mask,List"
|
|
bitfld.long 0x00 18. " [18] ,Filter bank 18 mode" "Mask,List"
|
|
bitfld.long 0x00 17. " [17] ,Filter bank 17 mode" "Mask,List"
|
|
bitfld.long 0x00 16. " [16] ,Filter bank 16 mode" "Mask,List"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bank 15 mode" "Mask,List"
|
|
bitfld.long 0x00 14. " [14] ,Filter bank 14 mode" "Mask,List"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 13. " FBM[13] ,Filter bank 13 mode" "Mask,List"
|
|
bitfld.long 0x00 12. " [12] ,Filter bank 12 mode" "Mask,List"
|
|
bitfld.long 0x00 11. " [11] ,Filter bank 11 mode" "Mask,List"
|
|
bitfld.long 0x00 10. " [10] ,Filter bank 10 mode" "Mask,List"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Filter bank 9 mode" "Mask,List"
|
|
bitfld.long 0x00 8. " [8] ,Filter bank 8 mode" "Mask,List"
|
|
bitfld.long 0x00 7. " [7] ,Filter bank 7 mode" "Mask,List"
|
|
bitfld.long 0x00 6. " [6] ,Filter bank 6 mode" "Mask,List"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Filter bank 5 mode" "Mask,List"
|
|
bitfld.long 0x00 4. " [4] ,Filter bank 4 mode" "Mask,List"
|
|
bitfld.long 0x00 3. " [3] ,Filter bank 3 mode" "Mask,List"
|
|
bitfld.long 0x00 2. " [2] ,Filter bank 2 mode" "Mask,List"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Filter bank 1 mode" "Mask,List"
|
|
bitfld.long 0x00 0. " [0] ,Filter bank 0 mode" "Mask,List"
|
|
newline
|
|
rgroup.long 0x20C++0x03
|
|
line.long 0x00 "FS1R,CAN Filter Scale Register"
|
|
sif (!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
bitfld.long 0x00 27. " FSC[27] ,Filter 27 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 26. " [26] ,Filter 26 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 25. " [25] ,Filter 25 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 24. " [24] ,Filter 24 scale configuration" "Dual,Single"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter 23 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 22. " [22] ,Filter 22 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 21. " [21] ,Filter 21 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 20. " [20] ,Filter 20 scale configuration" "Dual,Single"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter 19 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 18. " [18] ,Filter 18 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 17. " [17] ,Filter 17 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 16. " [16] ,Filter 16 scale configuration" "Dual,Single"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter 15 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 14. " [14] ,Filter 14 scale configuration" "Dual,Single"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 13. " FSC[13] ,Filter 13 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 12. " [12] ,Filter 12 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 11. " [11] ,Filter 11 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 10. " [10] ,Filter 10 scale configuration" "Dual,Single"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Filter 9 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 8. " [8] ,Filter 8 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 7. " [7] ,Filter 7 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 6. " [6] ,Filter 6 scale configuration" "Dual,Single"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Filter 5 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 4. " [4] ,Filter 4 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 3. " [3] ,Filter 3 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 2. " [2] ,Filter 2 scale configuration" "Dual,Single"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Filter 1 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 0. " [0] ,Filter 0 scale configuration" "Dual,Single"
|
|
newline
|
|
rgroup.long 0x214++0x03
|
|
line.long 0x00 "FFA1R,CAN Filter FIFO Assignment Register"
|
|
sif (!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
bitfld.long 0x00 27. " FFA[27] ,Filter FIFO assignment for filter 27" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 26. " [26] ,Filter FIFO assignment for filter 26" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 25. " [25] ,Filter FIFO assignment for filter 25" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 24. " [24] ,Filter FIFO assignment for filter 24" "FIFO0,FIFO1"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter FIFO assignment for filter 23" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 22. " [22] ,Filter FIFO assignment for filter 22" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 21. " [21] ,Filter FIFO assignment for filter 21" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 20. " [20] ,Filter FIFO assignment for filter 20" "FIFO0,FIFO1"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter FIFO assignment for filter 19" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 18. " [18] ,Filter FIFO assignment for filter 18" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 17. " [17] ,Filter FIFO assignment for filter 17" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 16. " [16] ,Filter FIFO assignment for filter 16" "FIFO0,FIFO1"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter FIFO assignment for filter 15" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 14. " [14] ,Filter FIFO assignment for filter 14" "FIFO0,FIFO1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 13. " FFA[13] ,Filter FIFO assignment for filter 13" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 12. " [12] ,Filter FIFO assignment for filter 12" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 11. " [11] ,Filter FIFO assignment for filter 11" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 10. " [10] ,Filter FIFO assignment for filter 10" "FIFO0,FIFO1"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Filter FIFO assignment for filter 9" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 8. " [8] ,Filter FIFO assignment for filter 8" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 7. " [7] ,Filter FIFO assignment for filter 7" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 6. " [6] ,Filter FIFO assignment for filter 6" "FIFO0,FIFO1"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Filter FIFO assignment for filter 5" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 4. " [4] ,Filter FIFO assignment for filter 4" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 3. " [3] ,Filter FIFO assignment for filter 3" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 2. " [2] ,Filter FIFO assignment for filter 2" "FIFO0,FIFO1"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Filter FIFO assignment for filter 1" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 0. " [0] ,Filter FIFO assignment for filter 0" "FIFO0,FIFO1"
|
|
newline
|
|
endif
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "FA1R,CAN Filter Activation Register"
|
|
sif (!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
bitfld.long 0x00 27. " FACT[27] ,Filter 27 active" "Not active,Active"
|
|
bitfld.long 0x00 26. " [26] ,Filter 26 active" "Not active,Active"
|
|
bitfld.long 0x00 25. " [25] ,Filter 25 active" "Not active,Active"
|
|
bitfld.long 0x00 24. " [24] ,Filter 24 active" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter 23 active" "Not active,Active"
|
|
bitfld.long 0x00 22. " [22] ,Filter 22 active" "Not active,Active"
|
|
bitfld.long 0x00 21. " [21] ,Filter 21 active" "Not active,Active"
|
|
bitfld.long 0x00 20. " [20] ,Filter 20 active" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter 19 active" "Not active,Active"
|
|
bitfld.long 0x00 18. " [18] ,Filter 18 active" "Not active,Active"
|
|
bitfld.long 0x00 17. " [17] ,Filter 17 active" "Not active,Active"
|
|
bitfld.long 0x00 16. " [16] ,Filter 16 active" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter 15 active" "Not active,Active"
|
|
bitfld.long 0x00 14. " [14] ,Filter 14 active" "Not active,Active"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 13. " FACT[13] ,Filter 13 active" "Not active,Active"
|
|
bitfld.long 0x00 12. " [12] ,Filter 12 active" "Not active,Active"
|
|
bitfld.long 0x00 11. " [11] ,Filter 11 active" "Not active,Active"
|
|
bitfld.long 0x00 10. " [10] ,Filter 10 active" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Filter 9 active" "Not active,Active"
|
|
bitfld.long 0x00 8. " [8] ,Filter 8 active" "Not active,Active"
|
|
bitfld.long 0x00 7. " [7] ,Filter 7 active" "Not active,Active"
|
|
bitfld.long 0x00 6. " [6] ,Filter 6 active" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Filter 5 active" "Not active,Active"
|
|
bitfld.long 0x00 4. " [4] ,Filter 4 active" "Not active,Active"
|
|
bitfld.long 0x00 3. " [3] ,Filter 3 active" "Not active,Active"
|
|
bitfld.long 0x00 2. " [2] ,Filter 2 active" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Filter 1 active" "Not active,Active"
|
|
bitfld.long 0x00 0. " [0] ,Filter 0 active" "Not active,Active"
|
|
newline
|
|
tree "Filter Bank Registers"
|
|
if ((per.l(ad:0x40006400+0x200)&0x01)==0x01)&&((per.l(ad:0x40006400+0x21C)&(0x01<<0.))==0x00)
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "F0R1,Filter Bank 0 Register 1 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x240++0x03
|
|
line.long 0x00 "F0R1,Filter Bank 0 Register 1 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((per.l(ad:0x40006400+0x200)&0x01)==0x01)&&((per.l(ad:0x40006400+0x21C)&(0x01<<1.))==0x00)
|
|
group.long 0x244++0x03
|
|
line.long 0x00 "F0R2,Filter Bank 0 Register 2 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x244++0x03
|
|
line.long 0x00 "F0R2,Filter Bank 0 Register 2 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((per.l(ad:0x40006400+0x200)&0x01)==0x01)&&((per.l(ad:0x40006400+0x21C)&(0x01<<2.))==0x00)
|
|
group.long 0x248++0x03
|
|
line.long 0x00 "F1R1,Filter Bank 1 Register 1 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x248++0x03
|
|
line.long 0x00 "F1R1,Filter Bank 1 Register 1 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((per.l(ad:0x40006400+0x200)&0x01)==0x01)&&((per.l(ad:0x40006400+0x21C)&(0x01<<3.))==0x00)
|
|
group.long 0x24C++0x03
|
|
line.long 0x00 "F1R2,Filter Bank 1 Register 2 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x24C++0x03
|
|
line.long 0x00 "F1R2,Filter Bank 1 Register 2 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((per.l(ad:0x40006400+0x200)&0x01)==0x01)&&((per.l(ad:0x40006400+0x21C)&(0x01<<4.))==0x00)
|
|
group.long 0x250++0x03
|
|
line.long 0x00 "F2R1,Filter Bank 2 Register 1 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x250++0x03
|
|
line.long 0x00 "F2R1,Filter Bank 2 Register 1 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((per.l(ad:0x40006400+0x200)&0x01)==0x01)&&((per.l(ad:0x40006400+0x21C)&(0x01<<5.))==0x00)
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "F2R2,Filter Bank 2 Register 2 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x254++0x03
|
|
line.long 0x00 "F2R2,Filter Bank 2 Register 2 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((per.l(ad:0x40006400+0x200)&0x01)==0x01)&&((per.l(ad:0x40006400+0x21C)&(0x01<<6.))==0x00)
|
|
group.long 0x258++0x03
|
|
line.long 0x00 "F3R1,Filter Bank 3 Register 1 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x258++0x03
|
|
line.long 0x00 "F3R1,Filter Bank 3 Register 1 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((per.l(ad:0x40006400+0x200)&0x01)==0x01)&&((per.l(ad:0x40006400+0x21C)&(0x01<<7.))==0x00)
|
|
group.long 0x25C++0x03
|
|
line.long 0x00 "F3R2,Filter Bank 3 Register 2 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x25C++0x03
|
|
line.long 0x00 "F3R2,Filter Bank 3 Register 2 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((per.l(ad:0x40006400+0x200)&0x01)==0x01)&&((per.l(ad:0x40006400+0x21C)&(0x01<<8.))==0x00)
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "F4R1,Filter Bank 4 Register 1 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x260++0x03
|
|
line.long 0x00 "F4R1,Filter Bank 4 Register 1 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((per.l(ad:0x40006400+0x200)&0x01)==0x01)&&((per.l(ad:0x40006400+0x21C)&(0x01<<9.))==0x00)
|
|
group.long 0x264++0x03
|
|
line.long 0x00 "F4R2,Filter Bank 4 Register 2 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x264++0x03
|
|
line.long 0x00 "F4R2,Filter Bank 4 Register 2 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((per.l(ad:0x40006400+0x200)&0x01)==0x01)&&((per.l(ad:0x40006400+0x21C)&(0x01<<10.))==0x00)
|
|
group.long 0x268++0x03
|
|
line.long 0x00 "F5R1,Filter Bank 5 Register 1 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x268++0x03
|
|
line.long 0x00 "F5R1,Filter Bank 5 Register 1 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((per.l(ad:0x40006400+0x200)&0x01)==0x01)&&((per.l(ad:0x40006400+0x21C)&(0x01<<11.))==0x00)
|
|
group.long 0x26C++0x03
|
|
line.long 0x00 "F5R2,Filter Bank 5 Register 2 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x26C++0x03
|
|
line.long 0x00 "F5R2,Filter Bank 5 Register 2 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((per.l(ad:0x40006400+0x200)&0x01)==0x01)&&((per.l(ad:0x40006400+0x21C)&(0x01<<12.))==0x00)
|
|
group.long 0x270++0x03
|
|
line.long 0x00 "F6R1,Filter Bank 6 Register 1 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x270++0x03
|
|
line.long 0x00 "F6R1,Filter Bank 6 Register 1 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((per.l(ad:0x40006400+0x200)&0x01)==0x01)&&((per.l(ad:0x40006400+0x21C)&(0x01<<13.))==0x00)
|
|
group.long 0x274++0x03
|
|
line.long 0x00 "F6R2,Filter Bank 6 Register 2 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x274++0x03
|
|
line.long 0x00 "F6R2,Filter Bank 6 Register 2 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((per.l(ad:0x40006400+0x200)&0x01)==0x01)&&((per.l(ad:0x40006400+0x21C)&(0x01<<14.))==0x00)
|
|
group.long 0x278++0x03
|
|
line.long 0x00 "F7R1,Filter Bank 7 Register 1 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x278++0x03
|
|
line.long 0x00 "F7R1,Filter Bank 7 Register 1 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((per.l(ad:0x40006400+0x200)&0x01)==0x01)&&((per.l(ad:0x40006400+0x21C)&(0x01<<15.))==0x00)
|
|
group.long 0x27C++0x03
|
|
line.long 0x00 "F7R2,Filter Bank 7 Register 2 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x27C++0x03
|
|
line.long 0x00 "F7R2,Filter Bank 7 Register 2 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((per.l(ad:0x40006400+0x200)&0x01)==0x01)&&((per.l(ad:0x40006400+0x21C)&(0x01<<16.))==0x00)
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "F8R1,Filter Bank 8 Register 1 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x280++0x03
|
|
line.long 0x00 "F8R1,Filter Bank 8 Register 1 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((per.l(ad:0x40006400+0x200)&0x01)==0x01)&&((per.l(ad:0x40006400+0x21C)&(0x01<<17.))==0x00)
|
|
group.long 0x284++0x03
|
|
line.long 0x00 "F8R2,Filter Bank 8 Register 2 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x284++0x03
|
|
line.long 0x00 "F8R2,Filter Bank 8 Register 2 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((per.l(ad:0x40006400+0x200)&0x01)==0x01)&&((per.l(ad:0x40006400+0x21C)&(0x01<<18.))==0x00)
|
|
group.long 0x288++0x03
|
|
line.long 0x00 "F9R1,Filter Bank 9 Register 1 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x288++0x03
|
|
line.long 0x00 "F9R1,Filter Bank 9 Register 1 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((per.l(ad:0x40006400+0x200)&0x01)==0x01)&&((per.l(ad:0x40006400+0x21C)&(0x01<<19.))==0x00)
|
|
group.long 0x28C++0x03
|
|
line.long 0x00 "F9R2,Filter Bank 9 Register 2 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x28C++0x03
|
|
line.long 0x00 "F9R2,Filter Bank 9 Register 2 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((per.l(ad:0x40006400+0x200)&0x01)==0x01)&&((per.l(ad:0x40006400+0x21C)&(0x01<<20.))==0x00)
|
|
group.long 0x290++0x03
|
|
line.long 0x00 "F10R1,Filter Bank 10 Register 1 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x290++0x03
|
|
line.long 0x00 "F10R1,Filter Bank 10 Register 1 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((per.l(ad:0x40006400+0x200)&0x01)==0x01)&&((per.l(ad:0x40006400+0x21C)&(0x01<<21.))==0x00)
|
|
group.long 0x294++0x03
|
|
line.long 0x00 "F10R2,Filter Bank 10 Register 2 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x294++0x03
|
|
line.long 0x00 "F10R2,Filter Bank 10 Register 2 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((per.l(ad:0x40006400+0x200)&0x01)==0x01)&&((per.l(ad:0x40006400+0x21C)&(0x01<<22.))==0x00)
|
|
group.long 0x298++0x03
|
|
line.long 0x00 "F11R1,Filter Bank 11 Register 1 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x298++0x03
|
|
line.long 0x00 "F11R1,Filter Bank 11 Register 1 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((per.l(ad:0x40006400+0x200)&0x01)==0x01)&&((per.l(ad:0x40006400+0x21C)&(0x01<<23.))==0x00)
|
|
group.long 0x29C++0x03
|
|
line.long 0x00 "F11R2,Filter Bank 11 Register 2 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x29C++0x03
|
|
line.long 0x00 "F11R2,Filter Bank 11 Register 2 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((per.l(ad:0x40006400+0x200)&0x01)==0x01)&&((per.l(ad:0x40006400+0x21C)&(0x01<<24.))==0x00)
|
|
group.long 0x2A0++0x03
|
|
line.long 0x00 "F12R1,Filter Bank 12 Register 1 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2A0++0x03
|
|
line.long 0x00 "F12R1,Filter Bank 12 Register 1 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((per.l(ad:0x40006400+0x200)&0x01)==0x01)&&((per.l(ad:0x40006400+0x21C)&(0x01<<25.))==0x00)
|
|
group.long 0x2A4++0x03
|
|
line.long 0x00 "F12R2,Filter Bank 12 Register 2 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2A4++0x03
|
|
line.long 0x00 "F12R2,Filter Bank 12 Register 2 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((per.l(ad:0x40006400+0x200)&0x01)==0x01)&&((per.l(ad:0x40006400+0x21C)&(0x01<<26.))==0x00)
|
|
group.long 0x2A8++0x03
|
|
line.long 0x00 "F13R1,Filter Bank 13 Register 1 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2A8++0x03
|
|
line.long 0x00 "F13R1,Filter Bank 13 Register 1 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((per.l(ad:0x40006400+0x200)&0x01)==0x01)&&((per.l(ad:0x40006400+0x21C)&(0x01<<27.))==0x00)
|
|
group.long 0x2AC++0x03
|
|
line.long 0x00 "F13R2,Filter Bank 13 Register 2 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2AC++0x03
|
|
line.long 0x00 "F13R2,Filter Bank 13 Register 2 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
sif (!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
tree "CAN 2"
|
|
base ad:0x40006800
|
|
width 7.
|
|
group.long 0x00++0x1F
|
|
line.long 0x00 "MCR,CAN Master Control Register"
|
|
bitfld.long 0x00 16. " DBF ,Debug freeze" "Not frozen,Frozen"
|
|
bitfld.long 0x00 15. " RESET ,bxCAN software master reset" "No reset,Reset"
|
|
bitfld.long 0x00 7. " TTCM ,Time triggered communication mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ABOM ,Automatic bus-off management" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " AWUM ,Automatic wake-up mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NART ,No automatic retransmission" "Retransmitted,Transmitted once"
|
|
bitfld.long 0x00 3. " RFLM ,Receive FIFO locked mode" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " TXFP ,Transmit FIFO priority" "Identifier,Request order"
|
|
newline
|
|
bitfld.long 0x00 1. " SLEEP ,SLEEP mode request" "Normal mode,Sleep mode"
|
|
bitfld.long 0x00 0. " INRQ ,Initialization request" "No effect,Initialize"
|
|
line.long 0x04 "MSR,CAN Master Status Register"
|
|
rbitfld.long 0x04 11. " RX ,CAN Rx signal" "0,1"
|
|
rbitfld.long 0x04 10. " SAMP ,Last sample point" "0,1"
|
|
rbitfld.long 0x04 9. " RXM ,Receive mode" "Not receiving,Receiving"
|
|
rbitfld.long 0x04 8. " TXM ,Transmit mode" "Not transmitting,Transmitting"
|
|
newline
|
|
eventfld.long 0x04 4. " SLAKI ,SLEEP acknowledge interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 3. " WKUI ,Wake-Up interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 2. " ERRI ,Error interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x04 1. " SLAK ,SLEEP acknowledge" "No sleep,Sleep"
|
|
newline
|
|
rbitfld.long 0x04 0. " INAK ,Initialization acknowledge" "No initialization,Initialization"
|
|
line.long 0x08 "TSR,CAN Transmit Status Register"
|
|
rbitfld.long 0x08 31. " LOW2 ,Lowest priority flag for mailbox 2" "Not lowest,Lowest"
|
|
rbitfld.long 0x08 30. " LOW1 ,Lowest priority flag for mailbox 1" "Not lowest,Lowest"
|
|
rbitfld.long 0x08 29. " LOW0 ,Lowest priority flag for mailbox 0" "Not lowest,Lowest"
|
|
rbitfld.long 0x08 28. " TME2 ,Transmit mailbox 2 empty" "Not empty,Empty"
|
|
newline
|
|
rbitfld.long 0x08 27. " TME1 ,Transmit mailbox 1 empty" "Not empty,Empty"
|
|
rbitfld.long 0x08 26. " TME0 ,Transmit mailbox 0 empty" "Not empty,Empty"
|
|
rbitfld.long 0x08 24.--25. " CODE ,Mailbox code" "0,1,2,3"
|
|
bitfld.long 0x08 23. " ABRQ2 ,Abort request for mailbox 2" "Not requested,Requested"
|
|
newline
|
|
eventfld.long 0x08 19. " TERR2 ,Transmission error of mailbox 2" "No error,Error"
|
|
eventfld.long 0x08 18. " ALST2 ,Arbitration lost for mailbox 2" "Not lost,Lost"
|
|
eventfld.long 0x08 17. " TXOK2 ,Transmission OK of mailbox 2" "Failed,Successful"
|
|
eventfld.long 0x08 16. " RQCP2 ,Request completed mailbox 2" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x08 15. " ABRQ1 ,Abort request for mailbox 1" "Not requested,Requested"
|
|
eventfld.long 0x08 11. " TERR1 ,Transmission error of mailbox 1" "No error,Error"
|
|
eventfld.long 0x08 10. " ALST1 ,Arbitration lost for mailbox 1" "Not lost,Lost"
|
|
eventfld.long 0x08 9. " TXOK1 ,Transmission OK of mailbox 1" "Failed,Successful"
|
|
newline
|
|
eventfld.long 0x08 8. " RQCP1 ,Request completed mailbox 1" "Not completed,Completed"
|
|
bitfld.long 0x08 7. " ABRQ0 ,Abort request for mailbox 0" "Not requested,Requested"
|
|
eventfld.long 0x08 3. " TERR0 ,Transmission error of mailbox 0" "No error,Error"
|
|
eventfld.long 0x08 2. " ALST0 ,Arbitration lost for mailbox 0" "Not lost,Lost"
|
|
newline
|
|
eventfld.long 0x08 1. " TXOK0 ,Transmission OK of mailbox 0" "Failed,Successful"
|
|
eventfld.long 0x08 0. " RQCP0 ,Request completed mailbox 0" "Not completed,Completed"
|
|
line.long 0x0C "RF0R,CAN Receive FIFO 0 Register"
|
|
bitfld.long 0x0C 5. " RFOM0 ,Release FIFO 0 output mailbox" "No effect,Release"
|
|
eventfld.long 0x0C 4. " FOVR0 ,FIFO 0 overrun" "No overrun,Overrun"
|
|
eventfld.long 0x0C 3. " FULL0 ,FIFO 0 full" "Not full,Full"
|
|
rbitfld.long 0x0C 0.--1. " FMP0 ,FIFO 0 message pending" "0,1,2,3"
|
|
line.long 0x10 "RF1R,CAN Receive FIFO 1 Register"
|
|
bitfld.long 0x10 5. " RFOM1 ,Release FIFO 1 output mailbox" "No effect,Release"
|
|
eventfld.long 0x10 4. " FOVR1 ,FIFO 1 overrun" "No overrun,Overrun"
|
|
eventfld.long 0x10 3. " FULL1 ,FIFO 1 full" "Not full,Full"
|
|
rbitfld.long 0x10 0.--1. " FMP1 ,FIFO 1 message pending" "0,1,2,3"
|
|
line.long 0x14 "IER,CAN Interrupt Enable Register"
|
|
bitfld.long 0x14 17. " SLKIE ,SLEEP interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 16. " WKUIE ,Wake-Up interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 15. " ERRIE ,Error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 11. " LECIE ,Last error code interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 10. " BOFIE ,Bus-Off interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 9. " EPVIE ,Error passive interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " EWGIE ,Error warning interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " FOVIE1 ,FIFO overrun interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 5. " FFIE1 ,FIFO full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " FMPIE1 ,FIFO message pending interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 3. " FOVIE0 ,FIFO overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " FFIE0 ,FIFO full interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 1. " FMPIE0 ,FIFO message pending interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " TMEIE ,Transmit mailbox empty interrupt enable" "Disabled,Enabled"
|
|
line.long 0x18 "ESR,CAN Error Status Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " REC ,Receive error counter"
|
|
hexmask.long.byte 0x18 16.--23. 1. " TEC ,Least significant byte of the 9-bit transmit error counter"
|
|
bitfld.long 0x18 4.--6. " LEC ,Last error code" "No error,Stuff,Form,Acknowledgment,Bit recessive,Bit dominant,CRC,Set by software"
|
|
rbitfld.long 0x18 2. " BOFF ,Bus-off flag" "Not occurred,Occurred"
|
|
newline
|
|
rbitfld.long 0x18 1. " EPVF ,Error passive flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x18 0. " EWGF ,Error warning flag" "Not occurred,Occurred"
|
|
line.long 0x1C "BTR,CAN Bit Timing Register"
|
|
bitfld.long 0x1C 31. " SILM ,Silent mode" "Normal,Silent"
|
|
bitfld.long 0x1C 30. " LBKM ,Loop back mode" "Disabled,Enabled"
|
|
bitfld.long 0x1C 24.--25. " SJW ,Resynchronization jump width" "0,1,2,3"
|
|
bitfld.long 0x1C 20.--22. " TS2 ,Time segment 2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x1C 16.--19. " TS1 ,Time segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x1C 0.--9. 1. " BRP ,Baud rate prescaler"
|
|
tree "T0 Mailbox"
|
|
if (((per.l(ad:0x40006800+0x08))&(1.<<26.))==0x0)
|
|
if (((per.l((ad:0x40006800+0x180)))&0x4)==0x04)
|
|
rgroup.long 0x180++0x03
|
|
line.long 0x00 "TI0R,TX Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested"
|
|
else
|
|
rgroup.long 0x180++0x03
|
|
line.long 0x00 "TI0R,TX Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested"
|
|
endif
|
|
rgroup.long (0x180+0x04)++0x0B
|
|
line.long 0x00 "TDT0R,Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp"
|
|
bitfld.long 0x00 8. " TGT ,Transmit global time" "Not sent,Sent"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..."
|
|
line.long 0x04 "TDL0R,Mailbox Data Low Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data byte 0"
|
|
line.long 0x08 "TDH0R,Mailbox Data High Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data byte 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data byte 4"
|
|
else
|
|
if (((per.l((ad:0x40006800+0x180)))&0x4)==0x04)
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "TI0R,TX Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested"
|
|
else
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "TI0R,TX Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested"
|
|
endif
|
|
group.long (0x180+0x04)++0x0B
|
|
line.long 0x00 "TDT0R,Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp"
|
|
bitfld.long 0x00 8. " TGT ,Transmit global time" "Not sent,Sent"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..."
|
|
line.long 0x04 "TDL0R,Mailbox Data Low Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data byte 0"
|
|
line.long 0x08 "TDH0R,Mailbox Data High Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data byte 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data byte 4"
|
|
endif
|
|
tree.end
|
|
tree "T1 Mailbox"
|
|
if (((per.l(ad:0x40006800+0x08))&(1.<<27.))==0x0)
|
|
if (((per.l((ad:0x40006800+0x190)))&0x4)==0x04)
|
|
rgroup.long 0x190++0x03
|
|
line.long 0x00 "TI1R,TX Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested"
|
|
else
|
|
rgroup.long 0x190++0x03
|
|
line.long 0x00 "TI1R,TX Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested"
|
|
endif
|
|
rgroup.long (0x190+0x04)++0x0B
|
|
line.long 0x00 "TDT1R,Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp"
|
|
bitfld.long 0x00 8. " TGT ,Transmit global time" "Not sent,Sent"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..."
|
|
line.long 0x04 "TDL1R,Mailbox Data Low Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data byte 0"
|
|
line.long 0x08 "TDH1R,Mailbox Data High Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data byte 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data byte 4"
|
|
else
|
|
if (((per.l((ad:0x40006800+0x190)))&0x4)==0x04)
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "TI1R,TX Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested"
|
|
else
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "TI1R,TX Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested"
|
|
endif
|
|
group.long (0x190+0x04)++0x0B
|
|
line.long 0x00 "TDT1R,Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp"
|
|
bitfld.long 0x00 8. " TGT ,Transmit global time" "Not sent,Sent"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..."
|
|
line.long 0x04 "TDL1R,Mailbox Data Low Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data byte 0"
|
|
line.long 0x08 "TDH1R,Mailbox Data High Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data byte 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data byte 4"
|
|
endif
|
|
tree.end
|
|
tree "T2 Mailbox"
|
|
if (((per.l(ad:0x40006800+0x08))&(1.<<28.))==0x0)
|
|
if (((per.l((ad:0x40006800+0x1A0)))&0x4)==0x04)
|
|
rgroup.long 0x1A0++0x03
|
|
line.long 0x00 "TI2R,TX Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested"
|
|
else
|
|
rgroup.long 0x1A0++0x03
|
|
line.long 0x00 "TI2R,TX Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested"
|
|
endif
|
|
rgroup.long (0x1A0+0x04)++0x0B
|
|
line.long 0x00 "TDT2R,Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp"
|
|
bitfld.long 0x00 8. " TGT ,Transmit global time" "Not sent,Sent"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..."
|
|
line.long 0x04 "TDL2R,Mailbox Data Low Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data byte 0"
|
|
line.long 0x08 "TDH2R,Mailbox Data High Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data byte 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data byte 4"
|
|
else
|
|
if (((per.l((ad:0x40006800+0x1A0)))&0x4)==0x04)
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "TI2R,TX Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested"
|
|
else
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "TI2R,TX Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested"
|
|
endif
|
|
group.long (0x1A0+0x04)++0x0B
|
|
line.long 0x00 "TDT2R,Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp"
|
|
bitfld.long 0x00 8. " TGT ,Transmit global time" "Not sent,Sent"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..."
|
|
line.long 0x04 "TDL2R,Mailbox Data Low Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data byte 0"
|
|
line.long 0x08 "TDH2R,Mailbox Data High Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data byte 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data byte 4"
|
|
endif
|
|
tree.end
|
|
tree "FIFO 0"
|
|
if (((per.l((ad:0x40006800+0x1B0)))&0x4)==0x4)
|
|
rgroup.long 0x1B0++0x03
|
|
line.long 0x00 "RI0R,Rx FIFO Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
else
|
|
rgroup.long 0x1B0++0x03
|
|
line.long 0x00 "RI0R,Rx FIFO Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
endif
|
|
rgroup.long (0x1B0+0x04)++0x03
|
|
line.long 0x00 "RDT0R,Receive FIFO Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp"
|
|
hexmask.long.byte 0x00 8.--15. 1. " FMI ,Filter match index"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..."
|
|
newline
|
|
hgroup.long (0x1B0+0x08)++0x03
|
|
hide.long 0x00 "RDL0R,CAN Receive FIFO Mailbox Data Low Register"
|
|
in
|
|
hgroup.long (0x1B0+0x0C)++0x03
|
|
hide.long 0x00 "RDH0R,CAN Receive FIFO Mailbox Data High Register"
|
|
in
|
|
tree.end
|
|
tree "FIFO 1"
|
|
if (((per.l((ad:0x40006800+0x1C0)))&0x4)==0x4)
|
|
rgroup.long 0x1C0++0x03
|
|
line.long 0x00 "RI1R,Rx FIFO Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
else
|
|
rgroup.long 0x1C0++0x03
|
|
line.long 0x00 "RI1R,Rx FIFO Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
endif
|
|
rgroup.long (0x1C0+0x04)++0x03
|
|
line.long 0x00 "RDT1R,Receive FIFO Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp"
|
|
hexmask.long.byte 0x00 8.--15. 1. " FMI ,Filter match index"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..."
|
|
newline
|
|
hgroup.long (0x1C0+0x08)++0x03
|
|
hide.long 0x00 "RDL1R,CAN Receive FIFO Mailbox Data Low Register"
|
|
in
|
|
hgroup.long (0x1C0+0x0C)++0x03
|
|
hide.long 0x00 "RDH1R,CAN Receive FIFO Mailbox Data High Register"
|
|
in
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
tree "CAN 3"
|
|
base ad:0x40003400
|
|
width 7.
|
|
group.long 0x00++0x1F
|
|
line.long 0x00 "MCR,CAN Master Control Register"
|
|
bitfld.long 0x00 16. " DBF ,Debug freeze" "Not frozen,Frozen"
|
|
bitfld.long 0x00 15. " RESET ,bxCAN software master reset" "No reset,Reset"
|
|
bitfld.long 0x00 7. " TTCM ,Time triggered communication mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ABOM ,Automatic bus-off management" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " AWUM ,Automatic wake-up mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NART ,No automatic retransmission" "Retransmitted,Transmitted once"
|
|
bitfld.long 0x00 3. " RFLM ,Receive FIFO locked mode" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " TXFP ,Transmit FIFO priority" "Identifier,Request order"
|
|
newline
|
|
bitfld.long 0x00 1. " SLEEP ,SLEEP mode request" "Normal mode,Sleep mode"
|
|
bitfld.long 0x00 0. " INRQ ,Initialization request" "No effect,Initialize"
|
|
line.long 0x04 "MSR,CAN Master Status Register"
|
|
rbitfld.long 0x04 11. " RX ,CAN Rx signal" "0,1"
|
|
rbitfld.long 0x04 10. " SAMP ,Last sample point" "0,1"
|
|
rbitfld.long 0x04 9. " RXM ,Receive mode" "Not receiving,Receiving"
|
|
rbitfld.long 0x04 8. " TXM ,Transmit mode" "Not transmitting,Transmitting"
|
|
newline
|
|
eventfld.long 0x04 4. " SLAKI ,SLEEP acknowledge interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 3. " WKUI ,Wake-Up interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 2. " ERRI ,Error interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x04 1. " SLAK ,SLEEP acknowledge" "No sleep,Sleep"
|
|
newline
|
|
rbitfld.long 0x04 0. " INAK ,Initialization acknowledge" "No initialization,Initialization"
|
|
line.long 0x08 "TSR,CAN Transmit Status Register"
|
|
rbitfld.long 0x08 31. " LOW2 ,Lowest priority flag for mailbox 2" "Not lowest,Lowest"
|
|
rbitfld.long 0x08 30. " LOW1 ,Lowest priority flag for mailbox 1" "Not lowest,Lowest"
|
|
rbitfld.long 0x08 29. " LOW0 ,Lowest priority flag for mailbox 0" "Not lowest,Lowest"
|
|
rbitfld.long 0x08 28. " TME2 ,Transmit mailbox 2 empty" "Not empty,Empty"
|
|
newline
|
|
rbitfld.long 0x08 27. " TME1 ,Transmit mailbox 1 empty" "Not empty,Empty"
|
|
rbitfld.long 0x08 26. " TME0 ,Transmit mailbox 0 empty" "Not empty,Empty"
|
|
rbitfld.long 0x08 24.--25. " CODE ,Mailbox code" "0,1,2,3"
|
|
bitfld.long 0x08 23. " ABRQ2 ,Abort request for mailbox 2" "Not requested,Requested"
|
|
newline
|
|
eventfld.long 0x08 19. " TERR2 ,Transmission error of mailbox 2" "No error,Error"
|
|
eventfld.long 0x08 18. " ALST2 ,Arbitration lost for mailbox 2" "Not lost,Lost"
|
|
eventfld.long 0x08 17. " TXOK2 ,Transmission OK of mailbox 2" "Failed,Successful"
|
|
eventfld.long 0x08 16. " RQCP2 ,Request completed mailbox 2" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x08 15. " ABRQ1 ,Abort request for mailbox 1" "Not requested,Requested"
|
|
eventfld.long 0x08 11. " TERR1 ,Transmission error of mailbox 1" "No error,Error"
|
|
eventfld.long 0x08 10. " ALST1 ,Arbitration lost for mailbox 1" "Not lost,Lost"
|
|
eventfld.long 0x08 9. " TXOK1 ,Transmission OK of mailbox 1" "Failed,Successful"
|
|
newline
|
|
eventfld.long 0x08 8. " RQCP1 ,Request completed mailbox 1" "Not completed,Completed"
|
|
bitfld.long 0x08 7. " ABRQ0 ,Abort request for mailbox 0" "Not requested,Requested"
|
|
eventfld.long 0x08 3. " TERR0 ,Transmission error of mailbox 0" "No error,Error"
|
|
eventfld.long 0x08 2. " ALST0 ,Arbitration lost for mailbox 0" "Not lost,Lost"
|
|
newline
|
|
eventfld.long 0x08 1. " TXOK0 ,Transmission OK of mailbox 0" "Failed,Successful"
|
|
eventfld.long 0x08 0. " RQCP0 ,Request completed mailbox 0" "Not completed,Completed"
|
|
line.long 0x0C "RF0R,CAN Receive FIFO 0 Register"
|
|
bitfld.long 0x0C 5. " RFOM0 ,Release FIFO 0 output mailbox" "No effect,Release"
|
|
eventfld.long 0x0C 4. " FOVR0 ,FIFO 0 overrun" "No overrun,Overrun"
|
|
eventfld.long 0x0C 3. " FULL0 ,FIFO 0 full" "Not full,Full"
|
|
rbitfld.long 0x0C 0.--1. " FMP0 ,FIFO 0 message pending" "0,1,2,3"
|
|
line.long 0x10 "RF1R,CAN Receive FIFO 1 Register"
|
|
bitfld.long 0x10 5. " RFOM1 ,Release FIFO 1 output mailbox" "No effect,Release"
|
|
eventfld.long 0x10 4. " FOVR1 ,FIFO 1 overrun" "No overrun,Overrun"
|
|
eventfld.long 0x10 3. " FULL1 ,FIFO 1 full" "Not full,Full"
|
|
rbitfld.long 0x10 0.--1. " FMP1 ,FIFO 1 message pending" "0,1,2,3"
|
|
line.long 0x14 "IER,CAN Interrupt Enable Register"
|
|
bitfld.long 0x14 17. " SLKIE ,SLEEP interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 16. " WKUIE ,Wake-Up interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 15. " ERRIE ,Error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 11. " LECIE ,Last error code interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 10. " BOFIE ,Bus-Off interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 9. " EPVIE ,Error passive interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " EWGIE ,Error warning interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " FOVIE1 ,FIFO overrun interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 5. " FFIE1 ,FIFO full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " FMPIE1 ,FIFO message pending interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 3. " FOVIE0 ,FIFO overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " FFIE0 ,FIFO full interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 1. " FMPIE0 ,FIFO message pending interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " TMEIE ,Transmit mailbox empty interrupt enable" "Disabled,Enabled"
|
|
line.long 0x18 "ESR,CAN Error Status Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " REC ,Receive error counter"
|
|
hexmask.long.byte 0x18 16.--23. 1. " TEC ,Least significant byte of the 9-bit transmit error counter"
|
|
bitfld.long 0x18 4.--6. " LEC ,Last error code" "No error,Stuff,Form,Acknowledgment,Bit recessive,Bit dominant,CRC,Set by software"
|
|
rbitfld.long 0x18 2. " BOFF ,Bus-off flag" "Not occurred,Occurred"
|
|
newline
|
|
rbitfld.long 0x18 1. " EPVF ,Error passive flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x18 0. " EWGF ,Error warning flag" "Not occurred,Occurred"
|
|
line.long 0x1C "BTR,CAN Bit Timing Register"
|
|
bitfld.long 0x1C 31. " SILM ,Silent mode" "Normal,Silent"
|
|
bitfld.long 0x1C 30. " LBKM ,Loop back mode" "Disabled,Enabled"
|
|
bitfld.long 0x1C 24.--25. " SJW ,Resynchronization jump width" "0,1,2,3"
|
|
bitfld.long 0x1C 20.--22. " TS2 ,Time segment 2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x1C 16.--19. " TS1 ,Time segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x1C 0.--9. 1. " BRP ,Baud rate prescaler"
|
|
tree "T0 Mailbox"
|
|
if (((per.l(ad:0x40003400+0x08))&(1.<<26.))==0x0)
|
|
if (((per.l((ad:0x40003400+0x180)))&0x4)==0x04)
|
|
rgroup.long 0x180++0x03
|
|
line.long 0x00 "TI0R,TX Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested"
|
|
else
|
|
rgroup.long 0x180++0x03
|
|
line.long 0x00 "TI0R,TX Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested"
|
|
endif
|
|
rgroup.long (0x180+0x04)++0x0B
|
|
line.long 0x00 "TDT0R,Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp"
|
|
bitfld.long 0x00 8. " TGT ,Transmit global time" "Not sent,Sent"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..."
|
|
line.long 0x04 "TDL0R,Mailbox Data Low Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data byte 0"
|
|
line.long 0x08 "TDH0R,Mailbox Data High Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data byte 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data byte 4"
|
|
else
|
|
if (((per.l((ad:0x40003400+0x180)))&0x4)==0x04)
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "TI0R,TX Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested"
|
|
else
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "TI0R,TX Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested"
|
|
endif
|
|
group.long (0x180+0x04)++0x0B
|
|
line.long 0x00 "TDT0R,Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp"
|
|
bitfld.long 0x00 8. " TGT ,Transmit global time" "Not sent,Sent"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..."
|
|
line.long 0x04 "TDL0R,Mailbox Data Low Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data byte 0"
|
|
line.long 0x08 "TDH0R,Mailbox Data High Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data byte 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data byte 4"
|
|
endif
|
|
tree.end
|
|
tree "T1 Mailbox"
|
|
if (((per.l(ad:0x40003400+0x08))&(1.<<27.))==0x0)
|
|
if (((per.l((ad:0x40003400+0x190)))&0x4)==0x04)
|
|
rgroup.long 0x190++0x03
|
|
line.long 0x00 "TI1R,TX Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested"
|
|
else
|
|
rgroup.long 0x190++0x03
|
|
line.long 0x00 "TI1R,TX Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested"
|
|
endif
|
|
rgroup.long (0x190+0x04)++0x0B
|
|
line.long 0x00 "TDT1R,Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp"
|
|
bitfld.long 0x00 8. " TGT ,Transmit global time" "Not sent,Sent"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..."
|
|
line.long 0x04 "TDL1R,Mailbox Data Low Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data byte 0"
|
|
line.long 0x08 "TDH1R,Mailbox Data High Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data byte 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data byte 4"
|
|
else
|
|
if (((per.l((ad:0x40003400+0x190)))&0x4)==0x04)
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "TI1R,TX Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested"
|
|
else
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "TI1R,TX Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested"
|
|
endif
|
|
group.long (0x190+0x04)++0x0B
|
|
line.long 0x00 "TDT1R,Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp"
|
|
bitfld.long 0x00 8. " TGT ,Transmit global time" "Not sent,Sent"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..."
|
|
line.long 0x04 "TDL1R,Mailbox Data Low Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data byte 0"
|
|
line.long 0x08 "TDH1R,Mailbox Data High Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data byte 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data byte 4"
|
|
endif
|
|
tree.end
|
|
tree "T2 Mailbox"
|
|
if (((per.l(ad:0x40003400+0x08))&(1.<<28.))==0x0)
|
|
if (((per.l((ad:0x40003400+0x1A0)))&0x4)==0x04)
|
|
rgroup.long 0x1A0++0x03
|
|
line.long 0x00 "TI2R,TX Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested"
|
|
else
|
|
rgroup.long 0x1A0++0x03
|
|
line.long 0x00 "TI2R,TX Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested"
|
|
endif
|
|
rgroup.long (0x1A0+0x04)++0x0B
|
|
line.long 0x00 "TDT2R,Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp"
|
|
bitfld.long 0x00 8. " TGT ,Transmit global time" "Not sent,Sent"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..."
|
|
line.long 0x04 "TDL2R,Mailbox Data Low Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data byte 0"
|
|
line.long 0x08 "TDH2R,Mailbox Data High Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data byte 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data byte 4"
|
|
else
|
|
if (((per.l((ad:0x40003400+0x1A0)))&0x4)==0x04)
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "TI2R,TX Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested"
|
|
else
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "TI2R,TX Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested"
|
|
endif
|
|
group.long (0x1A0+0x04)++0x0B
|
|
line.long 0x00 "TDT2R,Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp"
|
|
bitfld.long 0x00 8. " TGT ,Transmit global time" "Not sent,Sent"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..."
|
|
line.long 0x04 "TDL2R,Mailbox Data Low Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data byte 0"
|
|
line.long 0x08 "TDH2R,Mailbox Data High Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data byte 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data byte 4"
|
|
endif
|
|
tree.end
|
|
tree "FIFO 0"
|
|
if (((per.l((ad:0x40003400+0x1B0)))&0x4)==0x4)
|
|
rgroup.long 0x1B0++0x03
|
|
line.long 0x00 "RI0R,Rx FIFO Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
else
|
|
rgroup.long 0x1B0++0x03
|
|
line.long 0x00 "RI0R,Rx FIFO Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
endif
|
|
rgroup.long (0x1B0+0x04)++0x03
|
|
line.long 0x00 "RDT0R,Receive FIFO Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp"
|
|
hexmask.long.byte 0x00 8.--15. 1. " FMI ,Filter match index"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..."
|
|
newline
|
|
hgroup.long (0x1B0+0x08)++0x03
|
|
hide.long 0x00 "RDL0R,CAN Receive FIFO Mailbox Data Low Register"
|
|
in
|
|
hgroup.long (0x1B0+0x0C)++0x03
|
|
hide.long 0x00 "RDH0R,CAN Receive FIFO Mailbox Data High Register"
|
|
in
|
|
tree.end
|
|
tree "FIFO 1"
|
|
if (((per.l((ad:0x40003400+0x1C0)))&0x4)==0x4)
|
|
rgroup.long 0x1C0++0x03
|
|
line.long 0x00 "RI1R,Rx FIFO Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
else
|
|
rgroup.long 0x1C0++0x03
|
|
line.long 0x00 "RI1R,Rx FIFO Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended identifier" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data,Remote"
|
|
endif
|
|
rgroup.long (0x1C0+0x04)++0x03
|
|
line.long 0x00 "RDT1R,Receive FIFO Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp"
|
|
hexmask.long.byte 0x00 8.--15. 1. " FMI ,Filter match index"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..."
|
|
newline
|
|
hgroup.long (0x1C0+0x08)++0x03
|
|
hide.long 0x00 "RDL1R,CAN Receive FIFO Mailbox Data Low Register"
|
|
in
|
|
hgroup.long (0x1C0+0x0C)++0x03
|
|
hide.long 0x00 "RDH1R,CAN Receive FIFO Mailbox Data High Register"
|
|
in
|
|
tree.end
|
|
tree "Filter Registers"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "FMR,CAN Filter Master Register"
|
|
bitfld.long 0x00 0. " FINIT ,Filter init mode" "Active mode,Initialization"
|
|
if ((per.l(ad:0x40003400+0x200)&0x01)==0x01)
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "FM1R,CAN Filter Mode Register"
|
|
bitfld.long 0x00 13. " FBM[13] ,Filter bank 13 mode" "Mask,List"
|
|
bitfld.long 0x00 12. " [12] ,Filter bank 12 mode" "Mask,List"
|
|
bitfld.long 0x00 11. " [11] ,Filter bank 11 mode" "Mask,List"
|
|
bitfld.long 0x00 10. " [10] ,Filter bank 10 mode" "Mask,List"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Filter bank 9 mode" "Mask,List"
|
|
bitfld.long 0x00 8. " [8] ,Filter bank 8 mode" "Mask,List"
|
|
bitfld.long 0x00 7. " [7] ,Filter bank 7 mode" "Mask,List"
|
|
bitfld.long 0x00 6. " [6] ,Filter bank 6 mode" "Mask,List"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Filter bank 5 mode" "Mask,List"
|
|
bitfld.long 0x00 4. " [4] ,Filter bank 4 mode" "Mask,List"
|
|
bitfld.long 0x00 3. " [3] ,Filter bank 3 mode" "Mask,List"
|
|
bitfld.long 0x00 2. " [2] ,Filter bank 2 mode" "Mask,List"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Filter bank 1 mode" "Mask,List"
|
|
bitfld.long 0x00 0. " [0] ,Filter bank 0 mode" "Mask,List"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "FS1R,CAN Filter Scale Register"
|
|
bitfld.long 0x00 13. " FSC[13] ,Filter 13 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 12. " [12] ,Filter 12 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 11. " [11] ,Filter 11 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 10. " [10] ,Filter 10 scale configuration" "Dual,Single"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Filter 9 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 8. " [8] ,Filter 8 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 7. " [7] ,Filter 7 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 6. " [6] ,Filter 6 scale configuration" "Dual,Single"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Filter 5 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 4. " [4] ,Filter 4 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 3. " [3] ,Filter 3 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 2. " [2] ,Filter 2 scale configuration" "Dual,Single"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Filter 1 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 0. " [0] ,Filter 0 scale configuration" "Dual,Single"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "FFA1R,CAN Filter FIFO Assignment Register"
|
|
bitfld.long 0x00 13. " FFA[13] ,Filter FIFO assignment for filter 13" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 12. " [12] ,Filter FIFO assignment for filter 12" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 11. " [11] ,Filter FIFO assignment for filter 11" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 10. " [10] ,Filter FIFO assignment for filter 10" "FIFO0,FIFO1"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Filter FIFO assignment for filter 9" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 8. " [8] ,Filter FIFO assignment for filter 8" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 7. " [7] ,Filter FIFO assignment for filter 7" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 6. " [6] ,Filter FIFO assignment for filter 6" "FIFO0,FIFO1"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Filter FIFO assignment for filter 5" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 4. " [4] ,Filter FIFO assignment for filter 4" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 3. " [3] ,Filter FIFO assignment for filter 3" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 2. " [2] ,Filter FIFO assignment for filter 2" "FIFO0,FIFO1"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Filter FIFO assignment for filter 1" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 0. " [0] ,Filter FIFO assignment for filter 0" "FIFO0,FIFO1"
|
|
else
|
|
rgroup.long 0x204++0x03
|
|
line.long 0x00 "FM1R,CAN Filter Mode Register"
|
|
bitfld.long 0x00 13. " FBM[13] ,Filter bank 13 mode" "Mask,List"
|
|
bitfld.long 0x00 12. " [12] ,Filter bank 12 mode" "Mask,List"
|
|
bitfld.long 0x00 11. " [11] ,Filter bank 11 mode" "Mask,List"
|
|
bitfld.long 0x00 10. " [10] ,Filter bank 10 mode" "Mask,List"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Filter bank 9 mode" "Mask,List"
|
|
bitfld.long 0x00 8. " [8] ,Filter bank 8 mode" "Mask,List"
|
|
bitfld.long 0x00 7. " [7] ,Filter bank 7 mode" "Mask,List"
|
|
bitfld.long 0x00 6. " [6] ,Filter bank 6 mode" "Mask,List"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Filter bank 5 mode" "Mask,List"
|
|
bitfld.long 0x00 4. " [4] ,Filter bank 4 mode" "Mask,List"
|
|
bitfld.long 0x00 3. " [3] ,Filter bank 3 mode" "Mask,List"
|
|
bitfld.long 0x00 2. " [2] ,Filter bank 2 mode" "Mask,List"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Filter bank 1 mode" "Mask,List"
|
|
bitfld.long 0x00 0. " [0] ,Filter bank 0 mode" "Mask,List"
|
|
rgroup.long 0x20C++0x03
|
|
line.long 0x00 "FS1R,CAN Filter Scale Register"
|
|
bitfld.long 0x00 13. " FSC[13] ,Filter 13 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 12. " [12] ,Filter 12 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 11. " [11] ,Filter 11 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 10. " [10] ,Filter 10 scale configuration" "Dual,Single"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Filter 9 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 8. " [8] ,Filter 8 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 7. " [7] ,Filter 7 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 6. " [6] ,Filter 6 scale configuration" "Dual,Single"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Filter 5 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 4. " [4] ,Filter 4 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 3. " [3] ,Filter 3 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 2. " [2] ,Filter 2 scale configuration" "Dual,Single"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Filter 1 scale configuration" "Dual,Single"
|
|
bitfld.long 0x00 0. " [0] ,Filter 0 scale configuration" "Dual,Single"
|
|
rgroup.long 0x214++0x03
|
|
line.long 0x00 "FFA1R,CAN Filter FIFO Assignment Register"
|
|
bitfld.long 0x00 13. " FFA[13] ,Filter FIFO assignment for filter 13" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 12. " [12] ,Filter FIFO assignment for filter 12" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 11. " [11] ,Filter FIFO assignment for filter 11" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 10. " [10] ,Filter FIFO assignment for filter 10" "FIFO0,FIFO1"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Filter FIFO assignment for filter 9" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 8. " [8] ,Filter FIFO assignment for filter 8" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 7. " [7] ,Filter FIFO assignment for filter 7" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 6. " [6] ,Filter FIFO assignment for filter 6" "FIFO0,FIFO1"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Filter FIFO assignment for filter 5" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 4. " [4] ,Filter FIFO assignment for filter 4" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 3. " [3] ,Filter FIFO assignment for filter 3" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 2. " [2] ,Filter FIFO assignment for filter 2" "FIFO0,FIFO1"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Filter FIFO assignment for filter 1" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 0. " [0] ,Filter FIFO assignment for filter 0" "FIFO0,FIFO1"
|
|
endif
|
|
newline
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "FA1R,CAN Filter Activation Register"
|
|
bitfld.long 0x00 13. " FACT[13] ,Filter 13 active" "Not active,Active"
|
|
bitfld.long 0x00 12. " [12] ,Filter 12 active" "Not active,Active"
|
|
bitfld.long 0x00 11. " [11] ,Filter 11 active" "Not active,Active"
|
|
bitfld.long 0x00 10. " [10] ,Filter 10 active" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Filter 9 active" "Not active,Active"
|
|
bitfld.long 0x00 8. " [8] ,Filter 8 active" "Not active,Active"
|
|
bitfld.long 0x00 7. " [7] ,Filter 7 active" "Not active,Active"
|
|
bitfld.long 0x00 6. " [6] ,Filter 6 active" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Filter 5 active" "Not active,Active"
|
|
bitfld.long 0x00 4. " [4] ,Filter 4 active" "Not active,Active"
|
|
bitfld.long 0x00 3. " [3] ,Filter 3 active" "Not active,Active"
|
|
bitfld.long 0x00 2. " [2] ,Filter 2 active" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Filter 1 active" "Not active,Active"
|
|
bitfld.long 0x00 0. " [0] ,Filter 0 active" "Not active,Active"
|
|
tree "Filter Bank Registers"
|
|
if ((per.l(ad:0x40003400+0x200)&0x01)==0x01)&&((per.l(ad:0x40003400+0x21C)&(0x01<<0.))==0x00)
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "F0R1,Filter Bank 0 Register 1(Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x240++0x03
|
|
line.long 0x00 "F0R1,Filter Bank 0 Register 1 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((per.l(ad:0x40003400+0x200)&0x01)==0x01)&&((per.l(ad:0x40003400+0x21C)&(0x01<<1.))==0x00)
|
|
group.long 0x244++0x03
|
|
line.long 0x00 "F1R2,Filter Bank 1 Register 2(Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x244++0x03
|
|
line.long 0x00 "F1R2,Filter Bank 1 Register 2 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((per.l(ad:0x40003400+0x200)&0x01)==0x01)&&((per.l(ad:0x40003400+0x21C)&(0x01<<2.))==0x00)
|
|
group.long 0x248++0x03
|
|
line.long 0x00 "F2R1,Filter Bank 2 Register 1(Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x248++0x03
|
|
line.long 0x00 "F2R1,Filter Bank 2 Register 1 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((per.l(ad:0x40003400+0x200)&0x01)==0x01)&&((per.l(ad:0x40003400+0x21C)&(0x01<<3.))==0x00)
|
|
group.long 0x24C++0x03
|
|
line.long 0x00 "F3R2,Filter Bank 3 Register 2(Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x24C++0x03
|
|
line.long 0x00 "F3R2,Filter Bank 3 Register 2 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((per.l(ad:0x40003400+0x200)&0x01)==0x01)&&((per.l(ad:0x40003400+0x21C)&(0x01<<4.))==0x00)
|
|
group.long 0x250++0x03
|
|
line.long 0x00 "F4R1,Filter Bank 4 Register 1(Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x250++0x03
|
|
line.long 0x00 "F4R1,Filter Bank 4 Register 1 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((per.l(ad:0x40003400+0x200)&0x01)==0x01)&&((per.l(ad:0x40003400+0x21C)&(0x01<<5.))==0x00)
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "F5R2,Filter Bank 5 Register 2(Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x254++0x03
|
|
line.long 0x00 "F5R2,Filter Bank 5 Register 2 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((per.l(ad:0x40003400+0x200)&0x01)==0x01)&&((per.l(ad:0x40003400+0x21C)&(0x01<<6.))==0x00)
|
|
group.long 0x258++0x03
|
|
line.long 0x00 "F6R1,Filter Bank 6 Register 1(Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x258++0x03
|
|
line.long 0x00 "F6R1,Filter Bank 6 Register 1 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((per.l(ad:0x40003400+0x200)&0x01)==0x01)&&((per.l(ad:0x40003400+0x21C)&(0x01<<7.))==0x00)
|
|
group.long 0x25C++0x03
|
|
line.long 0x00 "F7R2,Filter Bank 7 Register 2(Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x25C++0x03
|
|
line.long 0x00 "F7R2,Filter Bank 7 Register 2 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((per.l(ad:0x40003400+0x200)&0x01)==0x01)&&((per.l(ad:0x40003400+0x21C)&(0x01<<8.))==0x00)
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "F8R1,Filter Bank 8 Register 1(Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x260++0x03
|
|
line.long 0x00 "F8R1,Filter Bank 8 Register 1 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((per.l(ad:0x40003400+0x200)&0x01)==0x01)&&((per.l(ad:0x40003400+0x21C)&(0x01<<9.))==0x00)
|
|
group.long 0x264++0x03
|
|
line.long 0x00 "F9R2,Filter Bank 9 Register 2(Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x264++0x03
|
|
line.long 0x00 "F9R2,Filter Bank 9 Register 2 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((per.l(ad:0x40003400+0x200)&0x01)==0x01)&&((per.l(ad:0x40003400+0x21C)&(0x01<<10.))==0x00)
|
|
group.long 0x268++0x03
|
|
line.long 0x00 "F10R1,Filter Bank 10 Register 1(Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x268++0x03
|
|
line.long 0x00 "F10R1,Filter Bank 10 Register 1 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((per.l(ad:0x40003400+0x200)&0x01)==0x01)&&((per.l(ad:0x40003400+0x21C)&(0x01<<11.))==0x00)
|
|
group.long 0x26C++0x03
|
|
line.long 0x00 "F11R2,Filter Bank 11 Register 2(Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x26C++0x03
|
|
line.long 0x00 "F11R2,Filter Bank 11 Register 2 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((per.l(ad:0x40003400+0x200)&0x01)==0x01)&&((per.l(ad:0x40003400+0x21C)&(0x01<<12.))==0x00)
|
|
group.long 0x270++0x03
|
|
line.long 0x00 "F12R1,Filter Bank 12 Register 1(Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x270++0x03
|
|
line.long 0x00 "F12R1,Filter Bank 12 Register 1 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((per.l(ad:0x40003400+0x200)&0x01)==0x01)&&((per.l(ad:0x40003400+0x21C)&(0x01<<13.))==0x00)
|
|
group.long 0x274++0x03
|
|
line.long 0x00 "F13R2,Filter Bank 13 Register 2(Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x274++0x03
|
|
line.long 0x00 "F13R2,Filter Bank 13 Register 2 (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " [30] ,Filter bit 30" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 29. " [29] ,Filter bit 29" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " [28] ,Filter bit 28" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Filter bit 27" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " [26] ,Filter bit 26" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 25. " [25] ,Filter bit 25" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " [24] ,Filter bit 24" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Filter bit 23" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " [22] ,Filter bit 22" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 21. " [21] ,Filter bit 21" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " [20] ,Filter bit 20" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Filter bit 19" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " [18] ,Filter bit 18" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 17. " [17] ,Filter bit 17" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " [16] ,Filter bit 16" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Filter bits 15" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " [14] ,Filter bits 14" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 13. " [13] ,Filter bits 13" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " [12] ,Filter bits 12" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Filter bit 11" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " [10] ,Filter bit 10" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 9. " [9] ,Filter bit 9" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " [8] ,Filter bit 8" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Filter bit 7" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " [6] ,Filter bit 6" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 5. " [5] ,Filter bit 5" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " [4] ,Filter bit 4" "Dominant/Not used,Recessive/Matched"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Filter bit 3" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " [2] ,Filter bit 2" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 1. " [1] ,Filter bit 1" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " [0] ,Filter bit 0" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "USB_OTG_FS (USB on-the-go full-speed)"
|
|
base ad:0x50000000
|
|
width 11.
|
|
tree "OTG_FS Global Registers"
|
|
if (((per.l((ad:0x50000000+0x014)))&0x01)==0x01)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GOTGCTL,OTG_FS Control And Status Register"
|
|
rbitfld.long 0x00 21. " CURMOD ,Current mode of operation" "Device mode,Host mode"
|
|
newline
|
|
bitfld.long 0x00 20. " OTGVER ,OTG version" "Ver. 1.3,Ver. 2.0"
|
|
rbitfld.long 0x00 18. " ASVLD ,A-session valid" "Not valid,Valid"
|
|
rbitfld.long 0x00 17. " DBCT ,Long/short debounce time" "Long,Short"
|
|
rbitfld.long 0x00 16. " CIDSTS ,Connector ID status" "A-Device,B-Device"
|
|
newline
|
|
bitfld.long 0x00 12. " EHEN ,Embedded host enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " HSHNPEN ,Host set HNP enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " AVALOVAL ,A-peripheral session valid override value" "Invalid,Valid"
|
|
bitfld.long 0x00 4. " AVALOEN ,A-peripheral session valid override enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " VBVALOVAL ,VBUS valid override value" "Invalid,Valid"
|
|
bitfld.long 0x00 2. " VBVALOEN ,VBUS valid override enable" "Disabled,Enabled"
|
|
if (((per.l((ad:0x50000000+0x0C)))&0x300)!=0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "GOTGINT,OTG_FS Interrupt Register"
|
|
eventfld.long 0x00 20. " IDCHNG ,Indicates change in the value of the ID input pin" "Not changed,Changed"
|
|
eventfld.long 0x00 19. " DBCDNE ,Debounce done" "Not done,Done"
|
|
eventfld.long 0x00 18. " ADTOCHG ,A-device timeout change" "Not changed,Changed"
|
|
eventfld.long 0x00 17. " HNGDET ,Host negotiation detected" "Not detected,Detected"
|
|
newline
|
|
eventfld.long 0x00 9. " HNSSCHG ,Host negotiation success status change" "Not changed,Changed"
|
|
eventfld.long 0x00 8. " SRSSCHG ,Session request success status change" "Not changed,Changed"
|
|
eventfld.long 0x00 2. " SEDET ,Session end detected" "Not detected,Detected"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "GOTGINT,OTG_FS Interrupt Register"
|
|
eventfld.long 0x00 20. " IDCHNG ,Change in the value of the ID input pin" "Not changed,Changed"
|
|
eventfld.long 0x00 18. " ADTOCHG ,A-device timeout change" "Not changed,Changed"
|
|
eventfld.long 0x00 17. " HNGDET ,Host negotiation detected" "Not detected,Detected"
|
|
newline
|
|
eventfld.long 0x00 9. " HNSSCHG ,Host negotiation success status change" "Not changed,Changed"
|
|
eventfld.long 0x00 8. " SRSSCHG ,Session request success status change" "Not changed,Changed"
|
|
eventfld.long 0x00 2. " SEDET ,Session end detected" "Not detected,Detected"
|
|
endif
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "GAHBCFG,OTG_FS AHB Configuration Register"
|
|
bitfld.long 0x00 8. " PTXFELVL ,Periodic TxFIFO empty level" "Half empty,Empty"
|
|
bitfld.long 0x00 7. " TXFELVL ,Nonperiodic Tx FIFO empty level" "Half empty,Empty"
|
|
bitfld.long 0x00 0. " GINTMSK ,Global interrupt mask" "Masked,Unmasked"
|
|
line.long 0x04 "GUSBCFG,OTG_FS USB Configuration Register"
|
|
bitfld.long 0x04 30. " FDMOD ,Force device mode" "Normal,Forced"
|
|
bitfld.long 0x04 29. " FHMOD ,Force host mode" "Normal,Forced"
|
|
bitfld.long 0x04 9. " HNPCAP ,HNP-capable" "Not capable,Capable"
|
|
newline
|
|
bitfld.long 0x04 8. " SRPCAP ,SRP-capable" "Not capable,Capable"
|
|
rbitfld.long 0x04 6. " PHSEL ,Full speed serial transceiver select" "USB 2.0 HS,USB 1.1 FS"
|
|
bitfld.long 0x04 0.--2. " TOCAL ,FS timeout calibration" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "GRSTCTL,OTG_FS Reset Register"
|
|
rbitfld.long 0x08 31. " AHBIDL ,AHB master idle" "Low,High"
|
|
bitfld.long 0x08 6.--10. " TXFNUM ,TxFIFO number" "Non-periodic TxFIFO,Periodic TxFIFO,,,,,,,,,,,,,,,All TxFIFOs,?..."
|
|
bitfld.long 0x08 5. " TXFFLSH ,TxFIFO flush" "No effect,Flush"
|
|
bitfld.long 0x08 4. " RXFFLSH ,RxFIFO flush" "No effect,Flush"
|
|
newline
|
|
bitfld.long 0x08 2. " FCRST ,Host frame counter reset" "No reset,Reset"
|
|
bitfld.long 0x08 1. " PSRST ,Partial soft reset" "No reset,Reset"
|
|
bitfld.long 0x08 0. " CSRST ,Core soft reset" "No reset,Reset"
|
|
if ((per.l(ad:0x50000000+0x54)&0x01)==0x01)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GINTSTS,OTG_FS Core Interrupt Register"
|
|
eventfld.long 0x00 31. " WKUPINT ,Resume wakeup detected interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " SRQINT ,Session request detected interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 29. " DISCINT ,Disconnect detected interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 28. " CIDSCHG ,Connector ID status change" "Not changed,Changed"
|
|
rbitfld.long 0x00 26. " PTXFE ,Periodic TxFIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 25. " HCINT ,Host channels interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 24. " HPRTINT ,Host port interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 21. " IPXFR ,Incomplete periodic transfer" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 5. " NPTXFE ,Non-periodic TxFIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 4. " RXFLVL ,RxFIFO non-empty" "Empty,Not empty"
|
|
newline
|
|
eventfld.long 0x00 3. " SOF ,Start of frame" "Not started,Started"
|
|
rbitfld.long 0x00 2. " OTGINT ,OTG interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " MMIS ,Mode mismatch interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 0. " CMOD ,Current mode of operation" "Device mode,Host mode"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GINTSTS,OTG_FS Core Interrupt Register"
|
|
eventfld.long 0x00 31. " WKUPINT ,Resume wakeup detected interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " SRQINT ,Session request detected interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 29. " DISCINT ,Disconnect detected interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 28. " CIDSCHG ,Connector ID status change" "Not changed,Changed"
|
|
rbitfld.long 0x00 26. " PTXFE ,Periodic TxFIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 25. " HCINT ,Host channels interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 24. " HPRTINT ,Host port interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 21. " IPXFR ,Incomplete periodic transfer" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 5. " NPTXFE ,Non-periodic TxFIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 4. " RXFLVL ,RxFIFO non-empty" "Empty,Not empty"
|
|
eventfld.long 0x00 3. " SOF ,Start of frame" "Not started,Started"
|
|
newline
|
|
rbitfld.long 0x00 2. " OTGINT ,OTG interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " MMIS ,Mode mismatch interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 0. " CMOD ,Current mode of operation" "Device mode,Host mode"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "GINTMSK,OTG_FS Interrupt Mask Register"
|
|
bitfld.long 0x00 31. " WUIM ,Resume wakeup detected interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 30. " SRQIM ,New session detected interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 28. " CIDSCHGM ,Connector ID status change mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 27. " LPMINTM ,LPM interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x00 26. " PTXFEM ,Periodic TxFIFO empty mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 25. " HCIM ,Host channels interrupt mask" "Masked,Unmasked"
|
|
rbitfld.long 0x00 24. " PRTIM ,Host port interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 21. " IPXFRM ,Incomplete periodic transfer mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x00 5. " NPTXFEM ,Non-periodic TxFIFO empty mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 4. " RXFLVLM ,Receive FIFO non-empty mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 3. " SOFM ,Start of frame mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 2. " OTGINT ,OTG interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x00 1. " MMISM ,Mode mismatch interrupt mask" "Masked,Unmasked"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "GOTGCTL,OTG_FS Control And Status Register"
|
|
rbitfld.long 0x00 21. " CURMOD ,Current mode of operation" "Device mode,Host mode"
|
|
newline
|
|
bitfld.long 0x00 20. " OTGVER ,OTG version" "Ver. 1.3,Ver. 2.0"
|
|
rbitfld.long 0x00 19. " BSVLD ,B-session valid" "Not valid,Valid"
|
|
rbitfld.long 0x00 16. " CIDSTS ,Connector ID status" "A-Device,B-Device"
|
|
bitfld.long 0x00 12. " EHEN ,Embedded host enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " DHNPEN ,Device HNP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " HNPRQ ,HNP request" "Not requested,Requested"
|
|
rbitfld.long 0x00 8. " HNGSCS ,Host negotiation success" "Failed,Successful"
|
|
bitfld.long 0x00 7. " BVALOVAL ,B-peripheral session valid override value" "Invalid,Valid"
|
|
newline
|
|
bitfld.long 0x00 6. " BVALOEN ,B-peripheral session valid override enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SRQ ,Session request" "Not requested,Requested"
|
|
rbitfld.long 0x00 0. " SRQSCS ,Session request success" "Failed,Successful"
|
|
line.long 0x04 "GOTGINT,OTG_FS Interrupt Register"
|
|
eventfld.long 0x04 20. " IDCHNG ,Indicates change in the value of the ID input pin" "Not changed,Changed"
|
|
eventfld.long 0x04 18. " ADTOCHG ,A-device timeout change" "Not changed,Changed"
|
|
eventfld.long 0x04 17. " HNGDET ,Host negotiation detected" "Not detected,Detected"
|
|
newline
|
|
eventfld.long 0x04 9. " HNSSCHG ,Host negotiation success status change" "Not changed,Changed"
|
|
eventfld.long 0x04 8. " SRSSCHG ,Session request success status change" "Not changed,Changed"
|
|
eventfld.long 0x04 2. " SEDET ,Session end detected" "Not detected,Detected"
|
|
line.long 0x08 "GAHBCFG,OTG_FS AHB Configuration Register"
|
|
bitfld.long 0x08 7. " TXFELVL ,IN endpoint txfifo empty level" "Half empty,Empty"
|
|
bitfld.long 0x08 0. " GINTMSK ,Global interrupt mask" "Masked,Unmasked"
|
|
line.long 0x0C "GUSBCFG,OTG_FS USB Configuration Register"
|
|
bitfld.long 0x0C 30. " FDMOD ,Force device mode" "Normal,Forced"
|
|
bitfld.long 0x0C 29. " FHMOD ,Force host mode" "Normal,Forced"
|
|
bitfld.long 0x0C 10.--13. " TRDT ,USB turnaround time" ",,,,,,32MHz,27.5MHz - 32MHz,24MHz - 27.5MHz,21.8MHz - 24MHz,20MHz - 21.8MHz,18.5MHz - 20MHz,17.2MHz - 18.5MHz,16MHz - 17.2MHz,15MHz - 16MHz,14.2MHz - 15MHz"
|
|
bitfld.long 0x0C 9. " HNPCAP ,HNP-capable" "Not capable,Capable"
|
|
newline
|
|
bitfld.long 0x0C 8. " SRPCAP ,SRP-capable" "Not capable,Capable"
|
|
rbitfld.long 0x0C 6. " PHSEL ,Full speed serial transceiver select" "USB 2.0 HS,USB 1.1 FS"
|
|
bitfld.long 0x0C 0.--2. " TOCAL ,FS timeout calibration" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "GRSTCTL,OTG_FS Reset Register"
|
|
rbitfld.long 0x10 31. " AHBIDL ,AHB master idle" "Low,High"
|
|
bitfld.long 0x10 6.--10. " TXFNUM ,TxFIFO number" "TxFIFO 0,TxFIFO 1,TxFIFO 2,TxFIFO 3,TxFIFO 4,TxFIFO 5,TxFIFO 6,TxFIFO 7,TxFIFO 8,TxFIFO 9,TxFIFO 10,TxFIFO 11,TxFIFO 12,TxFIFO 13,TxFIFO 14,TxFIFO 15,All TxFIFOs,?..."
|
|
bitfld.long 0x10 5. " TXFFLSH ,TxFIFO flush" "No effect,Flush"
|
|
newline
|
|
bitfld.long 0x10 4. " RXFFLSH ,RxFIFO flush" "No effect,Flush"
|
|
bitfld.long 0x10 1. " PSRST ,Partial soft reset" "No reset,Reset"
|
|
bitfld.long 0x10 0. " CSRST ,Core soft reset" "No reset,Reset"
|
|
if ((per.l(ad:0x50000000+0x54)&0x01)==0x01)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GINTSTS,OTG_FS Core Interrupt Register"
|
|
eventfld.long 0x00 31. " WKUPINT ,Remote wakeup detected interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " SRQINT ,New session detected interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 28. " CIDSCHG ,Connector ID status change" "Not changed,Changed"
|
|
newline
|
|
eventfld.long 0x00 27. " LPMINT ,LPM interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 23. " RSTDET ,Reset detected interrupt" "No reset,Reset"
|
|
eventfld.long 0x00 21. " INCOMPISOOUT ,Incomplete isochronous OUT transfer" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " IISOIXFR ,Incomplete isochronous IN transfer" "No interrupt,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 19. " OEPINT ,OUT endpoint interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 18. " IEPINT ,IN endpoint interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 15. " EOPF ,End of periodic frame interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " ISOODRP ,Isochronous OUT packet dropped interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 13. " ENUMDNE ,Enumeration done" "Not done,Done"
|
|
eventfld.long 0x00 12. " USBRST ,USB reset" "No reset,Reset"
|
|
eventfld.long 0x00 11. " USBSUSP ,USB suspend" "Not suspended,Suspended"
|
|
eventfld.long 0x00 10. " ESUSP ,Early suspend" "Not suspended,Suspended"
|
|
newline
|
|
rbitfld.long 0x00 7. " GONAKEFF ,Global OUT NAK effective" "Low,High"
|
|
rbitfld.long 0x00 6. " GINAKEFF ,Global IN non-periodic NAK effective" "Low,High"
|
|
rbitfld.long 0x00 4. " RXFLVL ,RxFIFO non-empty" "Empty,Not empty"
|
|
eventfld.long 0x00 3. " SOF ,Start of frame" "Not started,Started"
|
|
newline
|
|
rbitfld.long 0x00 2. " OTGINT ,OTG interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " MMIS ,Mode mismatch interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 0. " CMOD ,Current mode of operation" "Device mode,Host mode"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GINTSTS,OTG_FS Core Interrupt Register"
|
|
eventfld.long 0x00 31. " WKUPINT ,Remote wakeup detected interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " SRQINT ,New session detected interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 28. " CIDSCHG ,Connector ID status change" "Not changed,Changed"
|
|
newline
|
|
eventfld.long 0x00 23. " RSTDET ,Reset detected interrupt" "No reset,Reset"
|
|
eventfld.long 0x00 21. " INCOMPISOOUT ,Incomplete isochronous OUT transfer" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " IISOIXFR ,Incomplete isochronous IN transfer" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 19. " OEPINT ,OUT endpoint interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 18. " IEPINT ,IN endpoint interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 15. " EOPF ,End of periodic frame interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " ISOODRP ,Isochronous OUT packet dropped interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " ENUMDNE ,Enumeration done" "Not done,Done"
|
|
newline
|
|
eventfld.long 0x00 12. " USBRST ,USB reset" "No reset,Reset"
|
|
eventfld.long 0x00 11. " USBSUSP ,USB suspend" "Not suspended,Suspended"
|
|
eventfld.long 0x00 10. " ESUSP ,Early suspend" "Not suspended,Suspended"
|
|
rbitfld.long 0x00 7. " GONAKEFF ,Global OUT NAK effective" "Low,High"
|
|
newline
|
|
rbitfld.long 0x00 6. " GINAKEFF ,Global IN non-periodic NAK effective" "Low,High"
|
|
rbitfld.long 0x00 4. " RXFLVL ,RxFIFO non-empty" "Empty,Not empty"
|
|
eventfld.long 0x00 3. " SOF ,Start of frame" "Not started,Started"
|
|
rbitfld.long 0x00 2. " OTGINT ,OTG interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 1. " MMIS ,Mode mismatch interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 0. " CMOD ,Current mode of operation" "Device mode,Host mode"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "GINTMSK,OTG_FS Interrupt Mask Register"
|
|
bitfld.long 0x00 31. " WUIM ,Remote wakeup detected interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 30. " SRQIM ,New session detected interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 29. " DISCINT ,Disconnect detected interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 28. " CIDSCHGM ,Connector ID status change mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x00 27. " LPMINTM ,LPM interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 23. " RSTDETM ,Reset detected interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 21. " IISOOXFRM ,Incomplete isochronous OUT transfer mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 20. " IISOIXFRM ,Incomplete isochronous IN transfer mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x00 19. " OEPINT ,OUT endpoints interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 18. " IEPINT ,IN endpoints interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 15. " EOPFM ,End of periodic frame interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 14. " ISOODRPM ,Isochronous OUT packet dropped interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x00 13. " ENUMDNEM ,Enumeration done mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 12. " USBRST ,USB reset mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 11. " USBSUSPM ,USB suspend mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 10. " ESUSPM ,Early suspend mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x00 7. " GONAKEFFM ,Global OUT NAK effective mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 6. " GINAKEFFM ,Global non-periodic IN NAK effective mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 4. " RXFLVLM ,Receive FIFO non-empty mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 3. " SOFM ,Start of frame mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x00 2. " OTGINT ,OTG interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 1. " MMISM ,Mode mismatch interrupt mask" "Masked,Unmasked"
|
|
endif
|
|
newline
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "GRXSTSR,OTG_FS Receive Status Debug Read Register"
|
|
in
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "GRXSTSP,OTG Status Read And Pop Register"
|
|
in
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "GRXFSIZ,OTG_FS Receive FIFO Size Register"
|
|
in
|
|
newline
|
|
if (((per.l((ad:0x50000000+0x014)))&0x01)==0x01)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "HNPTXFSIZ,OTG_FS Host Non-periodic Transmit FIFO Size Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " NPTXFD ,Non-periodic TxFIFO depth"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " NPTXFSA ,Non-periodic transmit RAM start address"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "HNPTXSTS,OTG_FS Non-periodic Transmit FIFO/queue Status Register"
|
|
bitfld.long 0x00 27.--30. " NPTXQTOP[30:27] ,Top of the nonperiodic transmit request queue - CH/EP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 25.--26. " NPTXQTOP[26:25] ,Top of the nonperiodic transmit request queue" "IN/OUT Token,Zero-length,,Channel halt"
|
|
bitfld.long 0x00 24. " NPTXQTOP[24] ,Terminate (last entry for selected channel/endpoint)" "Not terminated,Terminated"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " NPTQXSAV ,Non-periodic transmit request queue space available"
|
|
hexmask.long.word 0x00 0.--15. 1. " NPTXFSAV ,Non-periodic TxFIFO space available"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DIEPTXF0,Endpoint 0 Transmit FIFO Size"
|
|
hexmask.long.word 0x00 16.--31. 1. " TX0FD ,Endpoint 0 TxFIFO depth"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " TX0FSA ,Endpoint 0 transmit RAM start address"
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "HNPTXSTS,OTG_FS Non-periodic Transmit FIFO/Queue Status Register"
|
|
endif
|
|
sif (!cpuis("STM32F7*"))
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "GI2CCTL,OTG_FS I2C Access Register"
|
|
bitfld.long 0x00 31. " BSYDNE ,I2C busy/done" "Done,Busy"
|
|
bitfld.long 0x00 30. " RW ,Read/Write indicator" "Write,Read"
|
|
bitfld.long 0x00 28. " I2CDATSE0 ,I2C datse0 USB mode" "VP_VM USB,DAT_SE0 USB"
|
|
bitfld.long 0x00 26.--27. " I2CDEVADR ,I2C device address" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 24. " ACK ,I2C ACK" "NAK,ACK"
|
|
bitfld.long 0x00 23. " I2CEN ,I2C enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " ADDR ,I2C address"
|
|
hexmask.long.byte 0x00 8.--15. 0x01 " REGADDR ,I2C register address"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " RWDATA ,I2C read/write data"
|
|
endif
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "GCCFG,OTG_FS General Core Configuration Register"
|
|
bitfld.long 0x00 21. " VBDEN ,USB VBUS detection enable" "Disabled,Enabled"
|
|
newline
|
|
sif (!cpuis("STM32F74*")&&!cpuis("STM32F75*"))
|
|
bitfld.long 0x00 20. " SDEN ,Secondary detection (SD) mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PDEN ,Primary detection (PD) mode enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 18. " DCDEN ,Data contact detection (DCD) mode enable" "Disabled,Enabled"
|
|
newline
|
|
sif (!cpuis("STM32F74*")&&!cpuis("STM32F75*"))
|
|
bitfld.long 0x00 17. " BCDEN ,Battery charging detector (BCD) enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 16. " PWRDWN ,Power down" "Powered down,Not powered down"
|
|
newline
|
|
sif (!cpuis("STM32F74*")&&!cpuis("STM32F75*"))
|
|
rbitfld.long 0x00 3. " PS2DET ,DM pull-up detection status" "Normal port,PS2 port || proprietary charger"
|
|
rbitfld.long 0x00 2. " SDET ,Secondary detection (SD) status" "CDP detected,DCP detected"
|
|
rbitfld.long 0x00 1. " PDET ,Primary detection (PD) status" "No BCD support,BCD support"
|
|
newline
|
|
endif
|
|
rbitfld.long 0x00 0. " DCDET ,Data contact detection (DCD) status" "Not detected,Detected"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "CID,OTG_FS Core ID Register"
|
|
if (((per.l((ad:0x50000000+0x14)))&0x01)==0x01)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GLPMCFG,OTG Core LPM Configuration Register"
|
|
bitfld.long 0x00 28. " ENBESL ,Enable best effort service latency" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25.--27. " LPMRCNTSTS ,LPM retry count status" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24. " SNDLPM ,Send LPM transaction" "Sent,Cleared"
|
|
bitfld.long 0x00 21.--23. " LPMRCNT ,LPM retry count" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 17.--20. " LPMCHIDX ,LPM channel index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 16. " L1RSMOK ,Sleep state resume OK" "No,Yes"
|
|
rbitfld.long 0x00 15. " SLPSTS ,Port sleep status" "Not in L1,In L1"
|
|
rbitfld.long 0x00 13.--14. " LPMRST ,LPM response" "ERROR,STALL,NYET,ACK"
|
|
newline
|
|
bitfld.long 0x00 12. " L1DSEN ,L1 deep sleep enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " BESLTHRS ,BESL threshold" "75,100,150,250,350,450,950,?..."
|
|
bitfld.long 0x00 7. " L1SSEN ,L1 shallow sleep enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " REMWAKE ,BRemoteWake value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2.--5. " BESL ,Best effort service latency" "125us,150us,200us,300us,400us,500us,1000us,2000us,3000us,4000us,5000us,6000us,7000us,8000us,9000us,10000us"
|
|
bitfld.long 0x00 0. " LPMEN ,LPM support enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GLPMCFG,OTG Core LPM Configuration Register"
|
|
bitfld.long 0x00 28. " ENBESL ,Enable best effort service latency" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16. " L1RSMOK ,Sleep state resume OK" "No,Yes"
|
|
rbitfld.long 0x00 15. " SLPSTS ,Port sleep status" "No sleep,Sleep"
|
|
rbitfld.long 0x00 13.--14. " PMRST ,LPM response" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 12. " L1DSEN ,L1 deep sleep enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " BESLTHRS ,BESL threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. " L1SSEN ,L1 shallow sleep enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " REMWAKE ,BRemoteWake value" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 2.--5. " BESL ,Best effort service latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " LPMACK ,LPM token acknowledge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LPMEN ,LPM support enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "HPTXFSIZ,OTG_FS Host Periodic Transmit FIFO Size Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " PTXFD ,Host periodic TxFIFO depth"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " PTXSA ,Host periodic TxFIFO start address"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "DIEPTXF1,OTG_FS Device IN Endpoint Transmit FIFO Size Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO depth"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " INEPTXSA ,IN endpoint FIFOx transmit RAM start address"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "DIEPTXF2,OTG_FS Device IN Endpoint Transmit FIFO Size Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO depth"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " INEPTXSA ,IN endpoint FIFOx transmit RAM start address"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "DIEPTXF3,OTG_FS Device IN Endpoint Transmit FIFO Size Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO depth"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " INEPTXSA ,IN endpoint FIFOx transmit RAM start address"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DIEPTXF4,OTG_FS Device IN Endpoint Transmit FIFO Size Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO depth"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " INEPTXSA ,IN endpoint FIFOx transmit RAM start address"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "DIEPTXF5,OTG_FS Device IN Endpoint Transmit FIFO Size Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO depth"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " INEPTXSA ,IN endpoint FIFOx transmit RAM start address"
|
|
tree.end
|
|
width 12.
|
|
tree "Host Mode Registers"
|
|
if (((per.l((ad:0x50000000+0x014)))&0x01)==0x01)
|
|
if (((per.l((ad:0x50000000+0x440)))&0x60000)==0x40000)
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "HCFG,OTG_FS Host Configuration Register"
|
|
rbitfld.long 0x00 2. " FSLSS ,FS- and LS-only support" "Not supported,Supported"
|
|
bitfld.long 0x00 0.--1. " FSLSPCS ,FS/LS PHY clock select" ",48 MHz,6 MHz,?..."
|
|
elif (((per.l((ad:0x50000000+0x440)))&0x60000)==0x20000)
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "HCFG,OTG_FS Host Configuration Register"
|
|
rbitfld.long 0x00 2. " FSLSS ,FS- and LS-only support" "Not supported,Supported"
|
|
bitfld.long 0x00 0.--1. " FSLSPCS ,FS/LS PHY clock select" ",48 MHz,?..."
|
|
else
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "HCFG,OTG_FS Host Configuration Register"
|
|
rbitfld.long 0x00 2. " FSLSS ,FS- and LS-only support" "Not supported,Supported"
|
|
endif
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "HFIR,OTG_FS Host Frame Interval Register"
|
|
bitfld.long 0x00 16. " RLDCTRL ,Reload control" "Not automatic,Automatic"
|
|
hexmask.long.word 0x00 0.--15. 1. " FRIVL ,Frame interval"
|
|
rgroup.long 0x408++0x03
|
|
line.long 0x00 "HFNUM,OTG_FS Host Frame Number/Frame Time Remaining Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " FTREM ,Frame time remaining"
|
|
hexmask.long.word 0x00 0.--15. 1. " FRNUM ,Frame number"
|
|
rgroup.long 0x410++0x07
|
|
line.long 0x00 "HPTXSTS,Host Periodic Transmit FIFO/Queue Status Register"
|
|
bitfld.long 0x00 31. " PTXQTOP[31] ,Odd/Even frame" "Even,Odd"
|
|
bitfld.long 0x00 27.--30. " PTXQTOP[27:30] ,Channel/endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 25.--26. " PTXQTOP[25:26] ,Type" "IN/OUT,Zero-length,,Disabled"
|
|
newline
|
|
bitfld.long 0x00 24. " PTXQTOP[24] ,Terminate" "Not terminated,Terminated"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PTXQSAV ,Periodic transmit request queue space available"
|
|
hexmask.long.word 0x00 0.--15. 1. " PTXFSAVL ,Periodic transmit data FIFO space available"
|
|
newline
|
|
line.long 0x04 "HAINT,OTG_FS Host All Channels Interrupt Register"
|
|
sif (!cpuis("STM32F72*")&&!cpuis("STM32F73*")&&!cpuis("STM32F76*")&&!cpuis("STM32F77*"))
|
|
bitfld.long 0x04 15. " HAINT_[15] ,Channel 15 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 14. " [14] ,Channel 14 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 13. " [13] ,Channel 13 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 12. " [12] ,Channel 12 interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 11. " HAINT[11] ,Channel 11 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 10. " [10] ,Channel 10 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 9. " [9] ,Channel 9 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " [8] ,Channel 8 interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Channel 7 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " [6] ,Channel 6 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 5. " [5] ,Channel 5 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " [4] ,Channel 4 interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,Channel 3 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " [2] ,Channel 2 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " [1] ,Channel 1 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " [0] ,Channel 0 interrupt" "No interrupt,Interrupt"
|
|
group.long 0x418++0x03
|
|
line.long 0x00 "HAINTMSK,OTG_FS Host All Channels Interrupt Mask Register"
|
|
sif (!cpuis("STM32F72*")&&!cpuis("STM32F73*")&&!cpuis("STM32F76*")&&!cpuis("STM32F77*"))
|
|
bitfld.long 0x00 15. " HAINTM_[15] ,Channel interrupt mask 15" "Masked,Unmasked"
|
|
bitfld.long 0x00 14. " [14] ,Channel interrupt mask 14" "Masked,Unmasked"
|
|
bitfld.long 0x00 13. " [13] ,Channel interrupt mask 13" "Masked,Unmasked"
|
|
bitfld.long 0x00 12. " [12] ,Channel interrupt mask 12" "Masked,Unmasked"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " HAINTMSK[11] ,Channel interrupt mask 11" "Masked,Unmasked"
|
|
bitfld.long 0x00 10. " [10] ,Channel interrupt mask 10" "Masked,Unmasked"
|
|
bitfld.long 0x00 9. " [9] ,Channel interrupt mask 9" "Masked,Unmasked"
|
|
bitfld.long 0x00 8. " [8] ,Channel interrupt mask 8" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Channel interrupt mask 7" "Masked,Unmasked"
|
|
bitfld.long 0x00 6. " [6] ,Channel interrupt mask 6" "Masked,Unmasked"
|
|
bitfld.long 0x00 5. " [5] ,Channel interrupt mask 5" "Masked,Unmasked"
|
|
bitfld.long 0x00 4. " [4] ,Channel interrupt mask 4" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Channel interrupt mask 3" "Masked,Unmasked"
|
|
bitfld.long 0x00 2. " [2] ,Channel interrupt mask 2" "Masked,Unmasked"
|
|
bitfld.long 0x00 1. " [1] ,Channel interrupt mask 1" "Masked,Unmasked"
|
|
bitfld.long 0x00 0. " [0] ,Channel interrupt mask 0" "Masked,Unmasked"
|
|
newline
|
|
group.long 0x440++0x03
|
|
line.long 0x00 "HPRT,OTG_FS Host Port Control And Status Register"
|
|
rbitfld.long 0x00 17.--18. " PSPD ,Port speed" "High,Full,Low,?..."
|
|
bitfld.long 0x00 13.--16. " PTCTL ,Port test control" "Disabled,J mode,K mode,SE0_NAK mode,Packet mode,Force_Enable,?..."
|
|
bitfld.long 0x00 12. " PPWR ,Port power" "Off,On"
|
|
rbitfld.long 0x00 11. " PLSTS[1] ,Port line status (logic level of FS_DP)" "Low,High"
|
|
newline
|
|
rbitfld.long 0x00 10. " PLSTS[0] ,Port line status (logic level of FS_DM)" "Low,High"
|
|
bitfld.long 0x00 8. " PRST ,Port reset" "No reset,Reset"
|
|
bitfld.long 0x00 7. " PSUSP ,Port suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 6. " PRES ,Port resume" "Not resumed,Resumed"
|
|
newline
|
|
eventfld.long 0x00 5. " POCCHNG ,Port overcurrent change" "Not changed,Changed"
|
|
rbitfld.long 0x00 4. " POCA ,Port overcurrent active" "Not active,Active"
|
|
eventfld.long 0x00 3. " PENCHNG ,Port enable/disable change" "Not changed,Changed"
|
|
eventfld.long 0x00 2. " PENA ,Port enable" "Disabled,Enabled"
|
|
newline
|
|
eventfld.long 0x00 1. " PCDET ,Port connect detected" "Not detected,Detected"
|
|
rbitfld.long 0x00 0. " PCSTS ,Port connect status" "Not connected,Connected"
|
|
group.long 0x500++0x03
|
|
line.long 0x00 "HCCHAR0,OTG_FS Host Channel-0 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed"
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
group.long (0x500+0x08)++0x0F
|
|
line.long 0x00 "HCINT0,OTG_FS Host Channel-0 Interrupt Register"
|
|
eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
newline
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x04 "HCINTMSK0,OTG_FS Host Channel-0 Interrupt Mask Register"
|
|
bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x08 "HCTSIZ0,OTG_FS Host Channel-0 Transfer Size Register"
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/-"
|
|
hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
line.long 0x0C "HCDMA0,OTG_HS Host Channel-0 DMA Address Register"
|
|
group.long 0x520++0x03
|
|
line.long 0x00 "HCCHAR1,OTG_FS Host Channel-1 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed"
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
group.long (0x520+0x08)++0x0F
|
|
line.long 0x00 "HCINT1,OTG_FS Host Channel-1 Interrupt Register"
|
|
eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
newline
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x04 "HCINTMSK1,OTG_FS Host Channel-1 Interrupt Mask Register"
|
|
bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x08 "HCTSIZ1,OTG_FS Host Channel-1 Transfer Size Register"
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/-"
|
|
hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
line.long 0x0C "HCDMA1,OTG_HS Host Channel-1 DMA Address Register"
|
|
group.long 0x540++0x03
|
|
line.long 0x00 "HCCHAR2,OTG_FS Host Channel-2 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed"
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
group.long (0x540+0x08)++0x0F
|
|
line.long 0x00 "HCINT2,OTG_FS Host Channel-2 Interrupt Register"
|
|
eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
newline
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x04 "HCINTMSK2,OTG_FS Host Channel-2 Interrupt Mask Register"
|
|
bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x08 "HCTSIZ2,OTG_FS Host Channel-2 Transfer Size Register"
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/-"
|
|
hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
line.long 0x0C "HCDMA2,OTG_HS Host Channel-2 DMA Address Register"
|
|
group.long 0x560++0x03
|
|
line.long 0x00 "HCCHAR3,OTG_FS Host Channel-3 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed"
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
group.long (0x560+0x08)++0x0F
|
|
line.long 0x00 "HCINT3,OTG_FS Host Channel-3 Interrupt Register"
|
|
eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
newline
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x04 "HCINTMSK3,OTG_FS Host Channel-3 Interrupt Mask Register"
|
|
bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x08 "HCTSIZ3,OTG_FS Host Channel-3 Transfer Size Register"
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/-"
|
|
hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
line.long 0x0C "HCDMA3,OTG_HS Host Channel-3 DMA Address Register"
|
|
group.long 0x580++0x03
|
|
line.long 0x00 "HCCHAR4,OTG_FS Host Channel-4 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed"
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
group.long (0x580+0x08)++0x0F
|
|
line.long 0x00 "HCINT4,OTG_FS Host Channel-4 Interrupt Register"
|
|
eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
newline
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x04 "HCINTMSK4,OTG_FS Host Channel-4 Interrupt Mask Register"
|
|
bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x08 "HCTSIZ4,OTG_FS Host Channel-4 Transfer Size Register"
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/-"
|
|
hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
line.long 0x0C "HCDMA4,OTG_HS Host Channel-4 DMA Address Register"
|
|
group.long 0x5A0++0x03
|
|
line.long 0x00 "HCCHAR5,OTG_FS Host Channel-5 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed"
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
group.long (0x5A0+0x08)++0x0F
|
|
line.long 0x00 "HCINT5,OTG_FS Host Channel-5 Interrupt Register"
|
|
eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
newline
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x04 "HCINTMSK5,OTG_FS Host Channel-5 Interrupt Mask Register"
|
|
bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x08 "HCTSIZ5,OTG_FS Host Channel-5 Transfer Size Register"
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/-"
|
|
hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
line.long 0x0C "HCDMA5,OTG_HS Host Channel-5 DMA Address Register"
|
|
group.long 0x5C0++0x03
|
|
line.long 0x00 "HCCHAR6,OTG_FS Host Channel-6 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed"
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
group.long (0x5C0+0x08)++0x0F
|
|
line.long 0x00 "HCINT6,OTG_FS Host Channel-6 Interrupt Register"
|
|
eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
newline
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x04 "HCINTMSK6,OTG_FS Host Channel-6 Interrupt Mask Register"
|
|
bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x08 "HCTSIZ6,OTG_FS Host Channel-6 Transfer Size Register"
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/-"
|
|
hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
line.long 0x0C "HCDMA6,OTG_HS Host Channel-6 DMA Address Register"
|
|
group.long 0x5E0++0x03
|
|
line.long 0x00 "HCCHAR7,OTG_FS Host Channel-7 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed"
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
group.long (0x5E0+0x08)++0x0F
|
|
line.long 0x00 "HCINT7,OTG_FS Host Channel-7 Interrupt Register"
|
|
eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
newline
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x04 "HCINTMSK7,OTG_FS Host Channel-7 Interrupt Mask Register"
|
|
bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x08 "HCTSIZ7,OTG_FS Host Channel-7 Transfer Size Register"
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/-"
|
|
hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
line.long 0x0C "HCDMA7,OTG_HS Host Channel-7 DMA Address Register"
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "HCCHAR8,OTG_FS Host Channel-8 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed"
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
group.long (0x600+0x08)++0x0F
|
|
line.long 0x00 "HCINT8,OTG_FS Host Channel-8 Interrupt Register"
|
|
eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
newline
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x04 "HCINTMSK8,OTG_FS Host Channel-8 Interrupt Mask Register"
|
|
bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x08 "HCTSIZ8,OTG_FS Host Channel-8 Transfer Size Register"
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/-"
|
|
hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
line.long 0x0C "HCDMA8,OTG_HS Host Channel-8 DMA Address Register"
|
|
group.long 0x620++0x03
|
|
line.long 0x00 "HCCHAR9,OTG_FS Host Channel-9 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed"
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
group.long (0x620+0x08)++0x0F
|
|
line.long 0x00 "HCINT9,OTG_FS Host Channel-9 Interrupt Register"
|
|
eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
newline
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x04 "HCINTMSK9,OTG_FS Host Channel-9 Interrupt Mask Register"
|
|
bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x08 "HCTSIZ9,OTG_FS Host Channel-9 Transfer Size Register"
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/-"
|
|
hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
line.long 0x0C "HCDMA9,OTG_HS Host Channel-9 DMA Address Register"
|
|
group.long 0x640++0x03
|
|
line.long 0x00 "HCCHAR10,OTG_FS Host Channel-10 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed"
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
group.long (0x640+0x08)++0x0F
|
|
line.long 0x00 "HCINT10,OTG_FS Host Channel-10 Interrupt Register"
|
|
eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
newline
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x04 "HCINTMSK10,OTG_FS Host Channel-10 Interrupt Mask Register"
|
|
bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x08 "HCTSIZ10,OTG_FS Host Channel-10 Transfer Size Register"
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/-"
|
|
hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
line.long 0x0C "HCDMA10,OTG_HS Host Channel-10 DMA Address Register"
|
|
group.long 0x660++0x03
|
|
line.long 0x00 "HCCHAR11,OTG_FS Host Channel-11 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed"
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
group.long (0x660+0x08)++0x0F
|
|
line.long 0x00 "HCINT11,OTG_FS Host Channel-11 Interrupt Register"
|
|
eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
newline
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x04 "HCINTMSK11,OTG_FS Host Channel-11 Interrupt Mask Register"
|
|
bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x08 "HCTSIZ11,OTG_FS Host Channel-11 Transfer Size Register"
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/-"
|
|
hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
line.long 0x0C "HCDMA11,OTG_HS Host Channel-11 DMA Address Register"
|
|
else
|
|
hgroup.long 0x400++0x03
|
|
hide.long 0x00 "HCFG,OTG_FS Host Configuration Register"
|
|
hgroup.long 0x404++0x03
|
|
hide.long 0x00 "HFIR,OTG_FS Host Frame Interval Register"
|
|
hgroup.long 0x408++0x03
|
|
hide.long 0x00 "HFNUM,OTG_FS Host Frame Number/Frame Time Remaining Register"
|
|
hgroup.long 0x410++0x03
|
|
hide.long 0x00 "HPTXSTS,Host Periodic Transmit FIFO/Queue Status Register"
|
|
hgroup.long 0x414++0x03
|
|
hide.long 0x00 "HAINT,OTG_FS Host All Channels Interrupt Register"
|
|
hgroup.long 0x418++0x03
|
|
hide.long 0x00 "HAINTMSK,OTG_FS Host All Channels Interrupt Mask Register"
|
|
hgroup.long 0x440++0x03
|
|
hide.long 0x00 "HPRT,OTG_FS Host Port Control And Status Register"
|
|
hgroup.long 0x500++0x03
|
|
hide.long 0x00 "HCCHAR0,OTG_FS Host Channel-0 Characteristics Register"
|
|
hgroup.long (0x500+0x08)++0x03
|
|
hide.long 0x00 "HCINT0,OTG_FS Host Channel-0 Interrupt Register"
|
|
hgroup.long (0x500+0x0C)++0x03
|
|
hide.long 0x00 "HCINTMSK0,OTG_FS Host Channel-0 Interrupt Mask Register"
|
|
hgroup.long (0x500+0x10)++0x03
|
|
hide.long 0x00 "HCTSIZ0,OTG_FS Host Channel-0 Transfer Size Register"
|
|
hgroup.long (0x500+0x14)++0x03
|
|
hide.long 0x00 "HCDMA0,OTG_HS Host Channel-0 DMA Address Register"
|
|
hgroup.long 0x520++0x03
|
|
hide.long 0x00 "HCCHAR1,OTG_FS Host Channel-1 Characteristics Register"
|
|
hgroup.long (0x520+0x08)++0x03
|
|
hide.long 0x00 "HCINT1,OTG_FS Host Channel-1 Interrupt Register"
|
|
hgroup.long (0x520+0x0C)++0x03
|
|
hide.long 0x00 "HCINTMSK1,OTG_FS Host Channel-1 Interrupt Mask Register"
|
|
hgroup.long (0x520+0x10)++0x03
|
|
hide.long 0x00 "HCTSIZ1,OTG_FS Host Channel-1 Transfer Size Register"
|
|
hgroup.long (0x520+0x14)++0x03
|
|
hide.long 0x00 "HCDMA1,OTG_HS Host Channel-1 DMA Address Register"
|
|
hgroup.long 0x540++0x03
|
|
hide.long 0x00 "HCCHAR2,OTG_FS Host Channel-2 Characteristics Register"
|
|
hgroup.long (0x540+0x08)++0x03
|
|
hide.long 0x00 "HCINT2,OTG_FS Host Channel-2 Interrupt Register"
|
|
hgroup.long (0x540+0x0C)++0x03
|
|
hide.long 0x00 "HCINTMSK2,OTG_FS Host Channel-2 Interrupt Mask Register"
|
|
hgroup.long (0x540+0x10)++0x03
|
|
hide.long 0x00 "HCTSIZ2,OTG_FS Host Channel-2 Transfer Size Register"
|
|
hgroup.long (0x540+0x14)++0x03
|
|
hide.long 0x00 "HCDMA2,OTG_HS Host Channel-2 DMA Address Register"
|
|
hgroup.long 0x560++0x03
|
|
hide.long 0x00 "HCCHAR3,OTG_FS Host Channel-3 Characteristics Register"
|
|
hgroup.long (0x560+0x08)++0x03
|
|
hide.long 0x00 "HCINT3,OTG_FS Host Channel-3 Interrupt Register"
|
|
hgroup.long (0x560+0x0C)++0x03
|
|
hide.long 0x00 "HCINTMSK3,OTG_FS Host Channel-3 Interrupt Mask Register"
|
|
hgroup.long (0x560+0x10)++0x03
|
|
hide.long 0x00 "HCTSIZ3,OTG_FS Host Channel-3 Transfer Size Register"
|
|
hgroup.long (0x560+0x14)++0x03
|
|
hide.long 0x00 "HCDMA3,OTG_HS Host Channel-3 DMA Address Register"
|
|
hgroup.long 0x580++0x03
|
|
hide.long 0x00 "HCCHAR4,OTG_FS Host Channel-4 Characteristics Register"
|
|
hgroup.long (0x580+0x08)++0x03
|
|
hide.long 0x00 "HCINT4,OTG_FS Host Channel-4 Interrupt Register"
|
|
hgroup.long (0x580+0x0C)++0x03
|
|
hide.long 0x00 "HCINTMSK4,OTG_FS Host Channel-4 Interrupt Mask Register"
|
|
hgroup.long (0x580+0x10)++0x03
|
|
hide.long 0x00 "HCTSIZ4,OTG_FS Host Channel-4 Transfer Size Register"
|
|
hgroup.long (0x580+0x14)++0x03
|
|
hide.long 0x00 "HCDMA4,OTG_HS Host Channel-4 DMA Address Register"
|
|
hgroup.long 0x5A0++0x03
|
|
hide.long 0x00 "HCCHAR5,OTG_FS Host Channel-5 Characteristics Register"
|
|
hgroup.long (0x5A0+0x08)++0x03
|
|
hide.long 0x00 "HCINT5,OTG_FS Host Channel-5 Interrupt Register"
|
|
hgroup.long (0x5A0+0x0C)++0x03
|
|
hide.long 0x00 "HCINTMSK5,OTG_FS Host Channel-5 Interrupt Mask Register"
|
|
hgroup.long (0x5A0+0x10)++0x03
|
|
hide.long 0x00 "HCTSIZ5,OTG_FS Host Channel-5 Transfer Size Register"
|
|
hgroup.long (0x5A0+0x14)++0x03
|
|
hide.long 0x00 "HCDMA5,OTG_HS Host Channel-5 DMA Address Register"
|
|
hgroup.long 0x5C0++0x03
|
|
hide.long 0x00 "HCCHAR6,OTG_FS Host Channel-6 Characteristics Register"
|
|
hgroup.long (0x5C0+0x08)++0x03
|
|
hide.long 0x00 "HCINT6,OTG_FS Host Channel-6 Interrupt Register"
|
|
hgroup.long (0x5C0+0x0C)++0x03
|
|
hide.long 0x00 "HCINTMSK6,OTG_FS Host Channel-6 Interrupt Mask Register"
|
|
hgroup.long (0x5C0+0x10)++0x03
|
|
hide.long 0x00 "HCTSIZ6,OTG_FS Host Channel-6 Transfer Size Register"
|
|
hgroup.long (0x5C0+0x14)++0x03
|
|
hide.long 0x00 "HCDMA6,OTG_HS Host Channel-6 DMA Address Register"
|
|
hgroup.long 0x5E0++0x03
|
|
hide.long 0x00 "HCCHAR7,OTG_FS Host Channel-7 Characteristics Register"
|
|
hgroup.long (0x5E0+0x08)++0x03
|
|
hide.long 0x00 "HCINT7,OTG_FS Host Channel-7 Interrupt Register"
|
|
hgroup.long (0x5E0+0x0C)++0x03
|
|
hide.long 0x00 "HCINTMSK7,OTG_FS Host Channel-7 Interrupt Mask Register"
|
|
hgroup.long (0x5E0+0x10)++0x03
|
|
hide.long 0x00 "HCTSIZ7,OTG_FS Host Channel-7 Transfer Size Register"
|
|
hgroup.long (0x5E0+0x14)++0x03
|
|
hide.long 0x00 "HCDMA7,OTG_HS Host Channel-7 DMA Address Register"
|
|
hgroup.long 0x600++0x03
|
|
hide.long 0x00 "HCCHAR8,OTG_FS Host Channel-8 Characteristics Register"
|
|
hgroup.long (0x600+0x08)++0x03
|
|
hide.long 0x00 "HCINT8,OTG_FS Host Channel-8 Interrupt Register"
|
|
hgroup.long (0x600+0x0C)++0x03
|
|
hide.long 0x00 "HCINTMSK8,OTG_FS Host Channel-8 Interrupt Mask Register"
|
|
hgroup.long (0x600+0x10)++0x03
|
|
hide.long 0x00 "HCTSIZ8,OTG_FS Host Channel-8 Transfer Size Register"
|
|
hgroup.long (0x600+0x14)++0x03
|
|
hide.long 0x00 "HCDMA8,OTG_HS Host Channel-8 DMA Address Register"
|
|
hgroup.long 0x620++0x03
|
|
hide.long 0x00 "HCCHAR9,OTG_FS Host Channel-9 Characteristics Register"
|
|
hgroup.long (0x620+0x08)++0x03
|
|
hide.long 0x00 "HCINT9,OTG_FS Host Channel-9 Interrupt Register"
|
|
hgroup.long (0x620+0x0C)++0x03
|
|
hide.long 0x00 "HCINTMSK9,OTG_FS Host Channel-9 Interrupt Mask Register"
|
|
hgroup.long (0x620+0x10)++0x03
|
|
hide.long 0x00 "HCTSIZ9,OTG_FS Host Channel-9 Transfer Size Register"
|
|
hgroup.long (0x620+0x14)++0x03
|
|
hide.long 0x00 "HCDMA9,OTG_HS Host Channel-9 DMA Address Register"
|
|
hgroup.long 0x640++0x03
|
|
hide.long 0x00 "HCCHAR10,OTG_FS Host Channel-10 Characteristics Register"
|
|
hgroup.long (0x640+0x08)++0x03
|
|
hide.long 0x00 "HCINT10,OTG_FS Host Channel-10 Interrupt Register"
|
|
hgroup.long (0x640+0x0C)++0x03
|
|
hide.long 0x00 "HCINTMSK10,OTG_FS Host Channel-10 Interrupt Mask Register"
|
|
hgroup.long (0x640+0x10)++0x03
|
|
hide.long 0x00 "HCTSIZ10,OTG_FS Host Channel-10 Transfer Size Register"
|
|
hgroup.long (0x640+0x14)++0x03
|
|
hide.long 0x00 "HCDMA10,OTG_HS Host Channel-10 DMA Address Register"
|
|
hgroup.long 0x660++0x03
|
|
hide.long 0x00 "HCCHAR11,OTG_FS Host Channel-11 Characteristics Register"
|
|
hgroup.long (0x660+0x08)++0x03
|
|
hide.long 0x00 "HCINT11,OTG_FS Host Channel-11 Interrupt Register"
|
|
hgroup.long (0x660+0x0C)++0x03
|
|
hide.long 0x00 "HCINTMSK11,OTG_FS Host Channel-11 Interrupt Mask Register"
|
|
hgroup.long (0x660+0x10)++0x03
|
|
hide.long 0x00 "HCTSIZ11,OTG_FS Host Channel-11 Transfer Size Register"
|
|
hgroup.long (0x660+0x14)++0x03
|
|
hide.long 0x00 "HCDMA11,OTG_HS Host Channel-11 DMA Address Register"
|
|
endif
|
|
tree.end
|
|
tree "Device mode registers"
|
|
if (((per.l((ad:0x50000000+0x14)))&0x01)==0x00)
|
|
group.long 0x800++0x07
|
|
line.long 0x00 "DCFG,OTG_FS Device Configuration Register"
|
|
bitfld.long 0x00 15. " ERRATIM ,Erratic error interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 11.--12. " PFIVL ,Periodic frame interval" "80%,85%,90%,95%"
|
|
hexmask.long.byte 0x00 4.--10. 0x10 " DAD ,Device address"
|
|
newline
|
|
bitfld.long 0x00 2. " NZLSOHSK ,Non-zero-length status OUT handshake" "STALL,NAK and STALL"
|
|
bitfld.long 0x00 0.--1. " DSPD ,Device speed" ",,,Full"
|
|
line.long 0x04 "DCTL,OTG_FS Device Control Register"
|
|
bitfld.long 0x04 18. " DSBESLRJCT ,Deep sleep BESL reject" "Not rejected,Rejected"
|
|
bitfld.long 0x04 11. " POPRGDNE ,Power-on programming done" "Not done,Done"
|
|
bitfld.long 0x04 4.--6. " TCTL ,Test control" "Disabled,J mode,K mode,SE0_NAK mode,Packet mode,Force_Enable,?..."
|
|
newline
|
|
setclrfld.long 0x04 3. 0x04 9. 0x04 10. " GON_SET/CLR ,Global OUT NAK status" "Sent to specific,Sent to all"
|
|
setclrfld.long 0x04 2. 0x04 7. 0x04 8. " GIN_SET/CLR ,Global IN NAK status" "Sent to specific,Sent to all"
|
|
newline
|
|
bitfld.long 0x04 1. " SDIS ,Soft disconnect" "No effect,Disconnect"
|
|
bitfld.long 0x04 0. " RWUSIG ,Remote wakeup signaling" "No effect,Wakeup"
|
|
rgroup.long 0x808++0x03
|
|
line.long 0x00 "DSTS,OTG_FS Device Status Register"
|
|
bitfld.long 0x00 23. " DEVLNSTS_D+ ,Device line status logic level of D+" "Low,High"
|
|
bitfld.long 0x00 22. " DEVLNSTS_D- ,Device line status logic level of D-" "Low,High"
|
|
hexmask.long.word 0x00 8.--21. 1. " FNSOF ,Frame number of the received SOF"
|
|
newline
|
|
bitfld.long 0x00 3. " EERR ,Erratic error" "No error,Error"
|
|
bitfld.long 0x00 1.--2. " ENUMSPD ,Enumerated speed" ",,,Full"
|
|
bitfld.long 0x00 0. " SUSPSTS ,Suspend status" "Not suspended,Suspended"
|
|
group.long 0x810++0x07
|
|
line.long 0x00 "DIEPMSK,OTG_FS Device IN Endpoint Common Interrupt Mask Register"
|
|
bitfld.long 0x00 13. " NAKM ,NAK interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 8. " TXFURM ,FIFO underrun mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 6. " INEPNEM ,IN endpoint NAK effective mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 5. " INEPNMM ,IN token received with EP mismatch mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 4. " ITTXFEMSK ,IN token received when TxFIFO empty mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x00 3. " TOM ,Timeout condition mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 1. " EPDM ,Endpoint disabled interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 0. " XFRCM ,Transfer completed interrupt mask" "Masked,Unmasked"
|
|
line.long 0x04 "DOEPMSK,OTG_FS Device OUT Endpoint Common Interrupt Mask Register"
|
|
bitfld.long 0x04 14. " NYETMSK ,NYET interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 13. " NAKMSK ,NAK interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 12. " BERRM ,Babble error interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 8. " TXFURM ,FIFO underrun mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x04 4. " OTEPDM ,OUT token received when endpoint disabled mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 3. " STUPM ,SETUP phase done mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 1. " EPDM ,Endpoint disabled interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 0. " XFRCM ,Transfer completed interrupt mask" "Masked,Unmasked"
|
|
rgroup.long 0x818++0x03
|
|
line.long 0x00 "DAINT,OTG_FS Device All Endpoints Interrupt Register"
|
|
bitfld.long 0x00 21. " OEPINT_[5] ,OUT endpoint interrupt bit 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " [4] ,OUT endpoint interrupt bit 4" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 19. " [3] ,OUT endpoint interrupt bit 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " [2] ,OUT endpoint interrupt bit 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " [1] ,OUT endpoint interrupt bit 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " [0] ,OUT endpoint interrupt bit 0" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 5. " IEPINT_[5] ,IN endpoint interrupt bit 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " [4] ,IN endpoint interrupt bit 4" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,IN endpoint interrupt bit 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " [2] ,IN endpoint interrupt bit 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " [1] ,IN endpoint interrupt bit 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " [0] ,IN endpoint interrupt bit 0" "No interrupt,Interrupt"
|
|
group.long 0x81C++0x03
|
|
line.long 0x00 "DAINTMSK,OTG_FS All Endpoints Interrupt Mask Register"
|
|
bitfld.long 0x00 21. " OEPM_[5] ,OUT EP interrupt mask bit 5" "Masked,Unmasked"
|
|
bitfld.long 0x00 20. " [4] ,OUT EP interrupt mask bit 4" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x00 19. " [3] ,OUT EP interrupt mask bit 3" "Masked,Unmasked"
|
|
bitfld.long 0x00 18. " [2] ,OUT EP interrupt mask bit 2" "Masked,Unmasked"
|
|
bitfld.long 0x00 17. " [1] ,OUT EP interrupt mask bit 1" "Masked,Unmasked"
|
|
bitfld.long 0x00 16. " [0] ,OUT EP interrupt mask bit 0" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x00 5. " IEPM_[5] ,IN EP interrupt mask bit 5" "Masked,Unmasked"
|
|
bitfld.long 0x00 4. " [4] ,IN EP interrupt mask bit 4" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,IN EP interrupt mask bit 3" "Masked,Unmasked"
|
|
bitfld.long 0x00 2. " [2] ,IN EP interrupt mask bit 2" "Masked,Unmasked"
|
|
bitfld.long 0x00 1. " [1] ,IN EP interrupt mask bit 1" "Masked,Unmasked"
|
|
bitfld.long 0x00 0. " [0] ,IN EP interrupt mask bit 0" "Masked,Unmasked"
|
|
group.long 0x828++0x07
|
|
line.long 0x00 "DVBUSDIS,OTG_FS Device VBUS Discharge Time Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VBUSDT ,Device VBUS discharge time"
|
|
line.long 0x04 "DVBUSPULSE,OTG_FS Device VBUS Pulsing Time Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " DVBUSP ,Device VBUS pulsing time"
|
|
newline
|
|
group.long 0x834++0x03
|
|
line.long 0x00 "DIEPEMPMSK,OTG_FS Device IN Endpoint FIFO Empty Interrupt Mask Register"
|
|
bitfld.long 0x00 5. " INEPTXFEM_[5] ,IN EP Tx FIFO empty interrupt mask bit 5" "Masked,Unmasked"
|
|
bitfld.long 0x00 4. " [4] ,IN EP Tx FIFO empty interrupt mask bit 4" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,IN EP Tx FIFO empty interrupt mask bit 3" "Masked,Unmasked"
|
|
bitfld.long 0x00 2. " [2] ,IN EP Tx FIFO empty interrupt mask bit 2" "Masked,Unmasked"
|
|
bitfld.long 0x00 1. " [1] ,IN EP Tx FIFO empty interrupt mask bit 1" "Masked,Unmasked"
|
|
bitfld.long 0x00 0. " [0] ,IN EP Tx FIFO empty interrupt mask bit 0" "Masked,Unmasked"
|
|
group.long 0x900++0x03
|
|
line.long 0x00 "DIEPCTL0,OTG_FS Device Control IN Endpoint 0 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
rbitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,?..."
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
newline
|
|
rbitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
bitfld.long 0x00 0.--1. " MPSIZ ,Maximum packet size" "64 bytes,32 bytes,16 bytes,8 bytes"
|
|
if (((per.l(ad:0x50000000+0x920))&0xC0000)==0x40000)
|
|
group.long 0x920++0x03
|
|
line.long 0x00 "DIEPCTL1,OTG Device Endpoint-1 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0x920))&0xC0000)==0x80000)
|
|
group.long 0x920++0x03
|
|
line.long 0x00 "DIEPCTL1,OTG Device Endpoint-1 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0x920))&0xC0000)==0xC0000)
|
|
group.long 0x920++0x03
|
|
line.long 0x00 "DIEPCTL1,OTG Device Endpoint-1 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0x920++0x03
|
|
line.long 0x00 "DIEPCTL1,OTG Device Endpoint-1 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
newline
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0x940))&0xC0000)==0x40000)
|
|
group.long 0x940++0x03
|
|
line.long 0x00 "DIEPCTL2,OTG Device Endpoint-2 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0x940))&0xC0000)==0x80000)
|
|
group.long 0x940++0x03
|
|
line.long 0x00 "DIEPCTL2,OTG Device Endpoint-2 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0x940))&0xC0000)==0xC0000)
|
|
group.long 0x940++0x03
|
|
line.long 0x00 "DIEPCTL2,OTG Device Endpoint-2 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0x940++0x03
|
|
line.long 0x00 "DIEPCTL2,OTG Device Endpoint-2 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
newline
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0x960))&0xC0000)==0x40000)
|
|
group.long 0x960++0x03
|
|
line.long 0x00 "DIEPCTL3,OTG Device Endpoint-3 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0x960))&0xC0000)==0x80000)
|
|
group.long 0x960++0x03
|
|
line.long 0x00 "DIEPCTL3,OTG Device Endpoint-3 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0x960))&0xC0000)==0xC0000)
|
|
group.long 0x960++0x03
|
|
line.long 0x00 "DIEPCTL3,OTG Device Endpoint-3 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0x960++0x03
|
|
line.long 0x00 "DIEPCTL3,OTG Device Endpoint-3 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
newline
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0x980))&0xC0000)==0x40000)
|
|
group.long 0x980++0x03
|
|
line.long 0x00 "DIEPCTL4,OTG Device Endpoint-4 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0x980))&0xC0000)==0x80000)
|
|
group.long 0x980++0x03
|
|
line.long 0x00 "DIEPCTL4,OTG Device Endpoint-4 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0x980))&0xC0000)==0xC0000)
|
|
group.long 0x980++0x03
|
|
line.long 0x00 "DIEPCTL4,OTG Device Endpoint-4 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0x980++0x03
|
|
line.long 0x00 "DIEPCTL4,OTG Device Endpoint-4 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
newline
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0x9A0))&0xC0000)==0x40000)
|
|
group.long 0x9A0++0x03
|
|
line.long 0x00 "DIEPCTL5,OTG Device Endpoint-5 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0x9A0))&0xC0000)==0x80000)
|
|
group.long 0x9A0++0x03
|
|
line.long 0x00 "DIEPCTL5,OTG Device Endpoint-5 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0x9A0))&0xC0000)==0xC0000)
|
|
group.long 0x9A0++0x03
|
|
line.long 0x00 "DIEPCTL5,OTG Device Endpoint-5 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0x9A0++0x03
|
|
line.long 0x00 "DIEPCTL5,OTG Device Endpoint-5 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
newline
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
group.long 0xB00++0x03
|
|
line.long 0x00 "DOEPCTL0,OTG_FS Device Control Out Endpoint 0 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
rbitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,?..."
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
newline
|
|
rbitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
rbitfld.long 0x00 0.--1. " MPSIZ ,Maximum packet size" "64 bytes,32 bytes,16 bytes,8 bytes"
|
|
if (((per.l(ad:0x50000000+0xB20))&0xC0000)==0x40000)
|
|
group.long 0xB20++0x03
|
|
line.long 0x00 "DOEPCTL1,OTG_FS Device Endpoint-1 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0xB20))&0xC0000)==0x80000)
|
|
group.long 0xB20++0x03
|
|
line.long 0x00 "DOEPCTL1,OTG_FS Device Endpoint-1 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0xB20))&0xC0000)==0xC0000)
|
|
group.long 0xB20++0x03
|
|
line.long 0x00 "DOEPCTL1,OTG_FS Device Endpoint-1 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0xB20++0x03
|
|
line.long 0x00 "DOEPCTL1,OTG_FS Device Endpoint-1 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0xB40))&0xC0000)==0x40000)
|
|
group.long 0xB40++0x03
|
|
line.long 0x00 "DOEPCTL2,OTG_FS Device Endpoint-2 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0xB40))&0xC0000)==0x80000)
|
|
group.long 0xB40++0x03
|
|
line.long 0x00 "DOEPCTL2,OTG_FS Device Endpoint-2 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0xB40))&0xC0000)==0xC0000)
|
|
group.long 0xB40++0x03
|
|
line.long 0x00 "DOEPCTL2,OTG_FS Device Endpoint-2 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0xB40++0x03
|
|
line.long 0x00 "DOEPCTL2,OTG_FS Device Endpoint-2 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0xB60))&0xC0000)==0x40000)
|
|
group.long 0xB60++0x03
|
|
line.long 0x00 "DOEPCTL3,OTG_FS Device Endpoint-3 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0xB60))&0xC0000)==0x80000)
|
|
group.long 0xB60++0x03
|
|
line.long 0x00 "DOEPCTL3,OTG_FS Device Endpoint-3 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0xB60))&0xC0000)==0xC0000)
|
|
group.long 0xB60++0x03
|
|
line.long 0x00 "DOEPCTL3,OTG_FS Device Endpoint-3 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0xB60++0x03
|
|
line.long 0x00 "DOEPCTL3,OTG_FS Device Endpoint-3 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0xB80))&0xC0000)==0x40000)
|
|
group.long 0xB80++0x03
|
|
line.long 0x00 "DOEPCTL4,OTG_FS Device Endpoint-4 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0xB80))&0xC0000)==0x80000)
|
|
group.long 0xB80++0x03
|
|
line.long 0x00 "DOEPCTL4,OTG_FS Device Endpoint-4 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0xB80))&0xC0000)==0xC0000)
|
|
group.long 0xB80++0x03
|
|
line.long 0x00 "DOEPCTL4,OTG_FS Device Endpoint-4 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0xB80++0x03
|
|
line.long 0x00 "DOEPCTL4,OTG_FS Device Endpoint-4 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0xBA0))&0xC0000)==0x40000)
|
|
group.long 0xBA0++0x03
|
|
line.long 0x00 "DOEPCTL5,OTG_FS Device Endpoint-5 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0xBA0))&0xC0000)==0x80000)
|
|
group.long 0xBA0++0x03
|
|
line.long 0x00 "DOEPCTL5,OTG_FS Device Endpoint-5 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0xBA0))&0xC0000)==0xC0000)
|
|
group.long 0xBA0++0x03
|
|
line.long 0x00 "DOEPCTL5,OTG_FS Device Endpoint-5 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0xBA0++0x03
|
|
line.long 0x00 "DOEPCTL5,OTG_FS Device Endpoint-5 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if ((per.l(ad:0x50000000+0x908)&0xC0000)==0x00)
|
|
group.long 0x908++0x03
|
|
line.long 0x00 "DIEPINT0,OTG_FS Device Endpoint-0 Interrupt Register"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0x908++0x03
|
|
line.long 0x00 "DIEPINT0,OTG_FS Device Endpoint-0 Interrupt Register"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x50000000+0x908)&0xC0000)==0x00)
|
|
group.long 0x928++0x03
|
|
line.long 0x00 "DIEPINT1,OTG_FS Device Endpoint-1 Interrupt Register"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0x928++0x03
|
|
line.long 0x00 "DIEPINT1,OTG_FS Device Endpoint-1 Interrupt Register"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x50000000+0x908)&0xC0000)==0x00)
|
|
group.long 0x948++0x03
|
|
line.long 0x00 "DIEPINT2,OTG_FS Device Endpoint-2 Interrupt Register"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0x948++0x03
|
|
line.long 0x00 "DIEPINT2,OTG_FS Device Endpoint-2 Interrupt Register"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x50000000+0x908)&0xC0000)==0x00)
|
|
group.long 0x968++0x03
|
|
line.long 0x00 "DIEPINT3,OTG_FS Device Endpoint-3 Interrupt Register"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0x968++0x03
|
|
line.long 0x00 "DIEPINT3,OTG_FS Device Endpoint-3 Interrupt Register"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x50000000+0x908)&0xC0000)==0x00)
|
|
group.long 0x988++0x03
|
|
line.long 0x00 "DIEPINT4,OTG_FS Device Endpoint-4 Interrupt Register"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0x988++0x03
|
|
line.long 0x00 "DIEPINT4,OTG_FS Device Endpoint-4 Interrupt Register"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x50000000+0x908)&0xC0000)==0x00)
|
|
group.long 0x9A8++0x03
|
|
line.long 0x00 "DIEPINT5,OTG_FS Device Endpoint-5 Interrupt Register"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0x9A8++0x03
|
|
line.long 0x00 "DIEPINT5,OTG_FS Device Endpoint-5 Interrupt Register"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x50000000+0xB08-0x08)&0xC0000)==0x00)
|
|
group.long 0xB08++0x03
|
|
line.long 0x00 "DOEPINT0,OTG_FS Device Endpoint-0 Interrupt Register"
|
|
eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received"
|
|
newline
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
eventfld.long 0x00 5. " STSPHSRX ,Status phase received for control write" "No interrupt,Interrupt"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "Not received,Received"
|
|
eventfld.long 0x00 3. " STUP ,SETUP phase done" "Not done,Done"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0xB08++0x03
|
|
line.long 0x00 "DOEPINT0,OTG_FS Device Endpoint-0 Interrupt Register"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x50000000+0xB28-0x08)&0xC0000)==0x00)
|
|
group.long 0xB28++0x03
|
|
line.long 0x00 "DOEPINT1,OTG_FS Device Endpoint-1 Interrupt Register"
|
|
eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received"
|
|
newline
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
eventfld.long 0x00 5. " STSPHSRX ,Status phase received for control write" "No interrupt,Interrupt"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "Not received,Received"
|
|
eventfld.long 0x00 3. " STUP ,SETUP phase done" "Not done,Done"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0xB28++0x03
|
|
line.long 0x00 "DOEPINT1,OTG_FS Device Endpoint-1 Interrupt Register"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x50000000+0xB48-0x08)&0xC0000)==0x00)
|
|
group.long 0xB48++0x03
|
|
line.long 0x00 "DOEPINT2,OTG_FS Device Endpoint-2 Interrupt Register"
|
|
eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received"
|
|
newline
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
eventfld.long 0x00 5. " STSPHSRX ,Status phase received for control write" "No interrupt,Interrupt"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "Not received,Received"
|
|
eventfld.long 0x00 3. " STUP ,SETUP phase done" "Not done,Done"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0xB48++0x03
|
|
line.long 0x00 "DOEPINT2,OTG_FS Device Endpoint-2 Interrupt Register"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x50000000+0xB68-0x08)&0xC0000)==0x00)
|
|
group.long 0xB68++0x03
|
|
line.long 0x00 "DOEPINT3,OTG_FS Device Endpoint-3 Interrupt Register"
|
|
eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received"
|
|
newline
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
eventfld.long 0x00 5. " STSPHSRX ,Status phase received for control write" "No interrupt,Interrupt"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "Not received,Received"
|
|
eventfld.long 0x00 3. " STUP ,SETUP phase done" "Not done,Done"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0xB68++0x03
|
|
line.long 0x00 "DOEPINT3,OTG_FS Device Endpoint-3 Interrupt Register"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x50000000+0xB88-0x08)&0xC0000)==0x00)
|
|
group.long 0xB88++0x03
|
|
line.long 0x00 "DOEPINT4,OTG_FS Device Endpoint-4 Interrupt Register"
|
|
eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received"
|
|
newline
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
eventfld.long 0x00 5. " STSPHSRX ,Status phase received for control write" "No interrupt,Interrupt"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "Not received,Received"
|
|
eventfld.long 0x00 3. " STUP ,SETUP phase done" "Not done,Done"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0xB88++0x03
|
|
line.long 0x00 "DOEPINT4,OTG_FS Device Endpoint-4 Interrupt Register"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x50000000+0xBA8-0x08)&0xC0000)==0x00)
|
|
group.long 0xBA8++0x03
|
|
line.long 0x00 "DOEPINT5,OTG_FS Device Endpoint-5 Interrupt Register"
|
|
eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received"
|
|
newline
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
eventfld.long 0x00 5. " STSPHSRX ,Status phase received for control write" "No interrupt,Interrupt"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "Not received,Received"
|
|
eventfld.long 0x00 3. " STUP ,SETUP phase done" "Not done,Done"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0xBA8++0x03
|
|
line.long 0x00 "DOEPINT5,OTG_FS Device Endpoint-5 Interrupt Register"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
group.long 0x910++0x03
|
|
line.long 0x00 "DIEPTSIZ0,OTG_FS Device IN Endpoint 0 Transfer Size Register"
|
|
bitfld.long 0x00 19.--20. " PKTCNT ,Packet count" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--6. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0xB10++0x03
|
|
line.long 0x00 "DOEPTSIZ0,OTG_FS Device OUT Endpoint 0 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3"
|
|
bitfld.long 0x00 19. " PKTCNT ,Packet count" "Low,High"
|
|
hexmask.long.byte 0x00 0.--6. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0x930++0x03
|
|
line.long 0x00 "DIEPTSIZ1,OTG_FS Device Endpoint-1 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " MCNT ,Multi count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0x950++0x03
|
|
line.long 0x00 "DIEPTSIZ2,OTG_FS Device Endpoint-2 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " MCNT ,Multi count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0x970++0x03
|
|
line.long 0x00 "DIEPTSIZ3,OTG_FS Device Endpoint-3 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " MCNT ,Multi count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0x990++0x03
|
|
line.long 0x00 "DIEPTSIZ4,OTG_FS Device Endpoint-4 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " MCNT ,Multi count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0x9B0++0x03
|
|
line.long 0x00 "DIEPTSIZ5,OTG_FS Device Endpoint-5 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " MCNT ,Multi count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
rgroup.long 0x918++0x03
|
|
line.long 0x00 "DTXFSTS0,OTG_FS Device IN Endpoint Transmit FIFO Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint Tx FIFO space available"
|
|
rgroup.long 0x938++0x03
|
|
line.long 0x00 "DTXFSTS1,OTG_FS Device IN Endpoint Transmit FIFO Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint Tx FIFO space available"
|
|
rgroup.long 0x958++0x03
|
|
line.long 0x00 "DTXFSTS2,OTG_FS Device IN Endpoint Transmit FIFO Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint Tx FIFO space available"
|
|
rgroup.long 0x978++0x03
|
|
line.long 0x00 "DTXFSTS3,OTG_FS Device IN Endpoint Transmit FIFO Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint Tx FIFO space available"
|
|
rgroup.long 0x998++0x03
|
|
line.long 0x00 "DTXFSTS4,OTG_FS Device IN Endpoint Transmit FIFO Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint Tx FIFO space available"
|
|
rgroup.long 0x9B8++0x03
|
|
line.long 0x00 "DTXFSTS5,OTG_FS Device IN Endpoint Transmit FIFO Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint Tx FIFO space available"
|
|
if (((per.l(ad:0x50000000+0xB30-0x10))&0xC0000)==0x40000)
|
|
group.long 0xB30++0x03
|
|
line.long 0x00 "DOEPTSIZ1,OTG_FS Device Endpoint-X Transfer Size Register"
|
|
rbitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
elif (((per.l(ad:0x50000000+0xB30-0x10))&0xC0000)==0x00)
|
|
group.long 0xB30++0x03
|
|
line.long 0x00 "DOEPTSIZ1,OTG_FS Device Endpoint-X Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
else
|
|
group.long 0xB30++0x03
|
|
line.long 0x00 "DOEPTSIZ1,OTG_FS Device Endpoint-X Transfer Size Register"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0xB50-0x10))&0xC0000)==0x40000)
|
|
group.long 0xB50++0x03
|
|
line.long 0x00 "DOEPTSIZ2,OTG_FS Device Endpoint-X Transfer Size Register"
|
|
rbitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
elif (((per.l(ad:0x50000000+0xB50-0x10))&0xC0000)==0x00)
|
|
group.long 0xB50++0x03
|
|
line.long 0x00 "DOEPTSIZ2,OTG_FS Device Endpoint-X Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
else
|
|
group.long 0xB50++0x03
|
|
line.long 0x00 "DOEPTSIZ2,OTG_FS Device Endpoint-X Transfer Size Register"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0xB70-0x10))&0xC0000)==0x40000)
|
|
group.long 0xB70++0x03
|
|
line.long 0x00 "DOEPTSIZ3,OTG_FS Device Endpoint-X Transfer Size Register"
|
|
rbitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
elif (((per.l(ad:0x50000000+0xB70-0x10))&0xC0000)==0x00)
|
|
group.long 0xB70++0x03
|
|
line.long 0x00 "DOEPTSIZ3,OTG_FS Device Endpoint-X Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
else
|
|
group.long 0xB70++0x03
|
|
line.long 0x00 "DOEPTSIZ3,OTG_FS Device Endpoint-X Transfer Size Register"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0xB90-0x10))&0xC0000)==0x40000)
|
|
group.long 0xB90++0x03
|
|
line.long 0x00 "DOEPTSIZ4,OTG_FS Device Endpoint-X Transfer Size Register"
|
|
rbitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
elif (((per.l(ad:0x50000000+0xB90-0x10))&0xC0000)==0x00)
|
|
group.long 0xB90++0x03
|
|
line.long 0x00 "DOEPTSIZ4,OTG_FS Device Endpoint-X Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
else
|
|
group.long 0xB90++0x03
|
|
line.long 0x00 "DOEPTSIZ4,OTG_FS Device Endpoint-X Transfer Size Register"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0xBB0-0x10))&0xC0000)==0x40000)
|
|
group.long 0xBB0++0x03
|
|
line.long 0x00 "DOEPTSIZ5,OTG_FS Device Endpoint-X Transfer Size Register"
|
|
rbitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
elif (((per.l(ad:0x50000000+0xBB0-0x10))&0xC0000)==0x00)
|
|
group.long 0xBB0++0x03
|
|
line.long 0x00 "DOEPTSIZ5,OTG_FS Device Endpoint-X Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
else
|
|
group.long 0xBB0++0x03
|
|
line.long 0x00 "DOEPTSIZ5,OTG_FS Device Endpoint-X Transfer Size Register"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
endif
|
|
else
|
|
hgroup.long 0x800++0x03
|
|
hide.long 0x00 "DCFG,OTG_FS Device Configuration Register"
|
|
hgroup.long 0x804++0x03
|
|
hide.long 0x00 "DCTL,OTG_FS Device Control Register"
|
|
hgroup.long 0x808++0x03
|
|
hide.long 0x00 "DSTS,OTG_FS Device Status Register"
|
|
hgroup.long 0x810++0x03
|
|
hide.long 0x00 "DIEPMSK,OTG_FS Device In Endpoint Common Interrupt Mask Register"
|
|
hgroup.long 0x814++0x03
|
|
hide.long 0x00 "DOEPMSK,OTG_FS Device Out Endpoint Common Interrupt Mask Register"
|
|
hgroup.long 0x818++0x03
|
|
hide.long 0x00 "DAINT,OTG_FS Device All Endpoints Interrupt Register"
|
|
hgroup.long 0x81C++0x03
|
|
hide.long 0x00 "DAINTMSK,OTG_FS All Endpoints Interrupt Mask Register"
|
|
hgroup.long 0x828++0x03
|
|
hide.long 0x00 "DVBUSDIS,OTG_FS Device VBUS Discharge Time Register"
|
|
hgroup.long 0x82C++0x03
|
|
hide.long 0x00 "DVBUSPULSE,OTG_FS Device VBUS Pulsing Time Register"
|
|
hgroup.long 0x834++0x03
|
|
hide.long 0x00 "DIEPEMPMSK,OTG_FS Device IN Endpoint FIFO Empty Interrupt Mask Register"
|
|
hgroup.long 0x900++0x03
|
|
hide.long 0x00 "DIEPCTL0,OTG_FS Device Control IN Endpoint 0 Control Register"
|
|
hgroup.long 0x920++0x03
|
|
hide.long 0x00 "DIEPCTL1,OTG Device Endpoint-1 Control Register"
|
|
hgroup.long 0x940++0x03
|
|
hide.long 0x00 "DIEPCTL2,OTG Device Endpoint-2 Control Register"
|
|
hgroup.long 0x960++0x03
|
|
hide.long 0x00 "DIEPCTL3,OTG Device Endpoint-3 Control Register"
|
|
hgroup.long 0x980++0x03
|
|
hide.long 0x00 "DIEPCTL4,OTG Device Endpoint-4 Control Register"
|
|
hgroup.long 0x9A0++0x03
|
|
hide.long 0x00 "DIEPCTL5,OTG Device Endpoint-5 Control Register"
|
|
hgroup.long 0xB00++0x03
|
|
hide.long 0x00 "DOEPCTL0,OTG_FS Device Control OUT Endpoint 0 Control Register"
|
|
hgroup.long 0xB20++0x03
|
|
hide.long 0x00 "DOEPCTL1,OTG_FS Device Endpoint-1 Control Register"
|
|
hgroup.long 0xB40++0x03
|
|
hide.long 0x00 "DOEPCTL2,OTG_FS Device Endpoint-2 Control Register"
|
|
hgroup.long 0xB60++0x03
|
|
hide.long 0x00 "DOEPCTL3,OTG_FS Device Endpoint-3 Control Register"
|
|
hgroup.long 0xB80++0x03
|
|
hide.long 0x00 "DOEPCTL4,OTG_FS Device Endpoint-4 Control Register"
|
|
hgroup.long 0xBA0++0x03
|
|
hide.long 0x00 "DOEPCTL5,OTG_FS Device Endpoint-5 Control Register"
|
|
hgroup.long 0x908++0x03
|
|
hide.long 0x00 "DIEPINT0,OTG_FS Device Endpoint-0 Interrupt Register"
|
|
hgroup.long 0x928++0x03
|
|
hide.long 0x00 "DIEPINT1,OTG_FS Device Endpoint-1 Interrupt Register"
|
|
hgroup.long 0x948++0x03
|
|
hide.long 0x00 "DIEPINT2,OTG_FS Device Endpoint-2 Interrupt Register"
|
|
hgroup.long 0x968++0x03
|
|
hide.long 0x00 "DIEPINT3,OTG_FS Device Endpoint-3 Interrupt Register"
|
|
hgroup.long 0x988++0x03
|
|
hide.long 0x00 "DIEPINT4,OTG_FS Device Endpoint-4 Interrupt Register"
|
|
hgroup.long 0x9A8++0x03
|
|
hide.long 0x00 "DIEPINT5,OTG_FS Device Endpoint-5 Interrupt Register"
|
|
hgroup.long 0xB08++0x03
|
|
hide.long 0x00 "DOEPINT0,OTG_FS Device Endpoint-0 Interrupt Register"
|
|
hgroup.long 0xB28++0x03
|
|
hide.long 0x00 "DOEPINT1,OTG_FS Device Endpoint-1 Interrupt Register"
|
|
hgroup.long 0xB48++0x03
|
|
hide.long 0x00 "DOEPINT2,OTG_FS Device Endpoint-2 Interrupt Register"
|
|
hgroup.long 0xB68++0x03
|
|
hide.long 0x00 "DOEPINT3,OTG_FS Device Endpoint-3 Interrupt Register"
|
|
hgroup.long 0xB88++0x03
|
|
hide.long 0x00 "DOEPINT4,OTG_FS Device Endpoint-4 Interrupt Register"
|
|
hgroup.long 0xBA8++0x03
|
|
hide.long 0x00 "DOEPINT5,OTG_FS Device Endpoint-5 Interrupt Register"
|
|
hgroup.long 0x910++0x03
|
|
hide.long 0x00 "DIEPTSIZ0,OTG_FS Device IN Endpoint 0 Transfer Size Register"
|
|
hgroup.long 0xB10++0x03
|
|
hide.long 0x00 "DOEPTSIZ0,OTG_FS Device OUT Endpoint 0 Transfer Size Register"
|
|
hgroup.long 0x930++0x03
|
|
hide.long 0x00 "DIEPTSIZ1,OTG_FS Device Endpoint-1 Transfer Size Register"
|
|
hgroup.long 0x950++0x03
|
|
hide.long 0x00 "DIEPTSIZ2,OTG_FS Device Endpoint-2 Transfer Size Register"
|
|
hgroup.long 0x970++0x03
|
|
hide.long 0x00 "DIEPTSIZ3,OTG_FS Device Endpoint-3 Transfer Size Register"
|
|
hgroup.long 0x990++0x03
|
|
hide.long 0x00 "DIEPTSIZ4,OTG_FS Device Endpoint-4 Transfer Size Register"
|
|
hgroup.long 0x9B0++0x03
|
|
hide.long 0x00 "DIEPTSIZ5,OTG_FS Device Endpoint-5 Transfer Size Register"
|
|
hgroup.long 0x918++0x03
|
|
hide.long 0x00 "DTXFSTS0,OTG_FS Device IN Endpoint Transmit FIFO Status Register"
|
|
hgroup.long 0x938++0x03
|
|
hide.long 0x00 "DTXFSTS1,OTG_FS Device IN Endpoint Transmit FIFO Status Register"
|
|
hgroup.long 0x958++0x03
|
|
hide.long 0x00 "DTXFSTS2,OTG_FS Device IN Endpoint Transmit FIFO Status Register"
|
|
hgroup.long 0x978++0x03
|
|
hide.long 0x00 "DTXFSTS3,OTG_FS Device IN Endpoint Transmit FIFO Status Register"
|
|
hgroup.long 0x998++0x03
|
|
hide.long 0x00 "DTXFSTS4,OTG_FS Device IN Endpoint Transmit FIFO Status Register"
|
|
hgroup.long 0x9B8++0x03
|
|
hide.long 0x00 "DTXFSTS5,OTG_FS Device IN Endpoint Transmit FIFO Status Register"
|
|
hgroup.long 0xB30++0x03
|
|
hide.long 0x00 "DOEPTSIZ1,OTG_FS Device Endpoint-X Transfer Size Register"
|
|
hgroup.long 0xB50++0x03
|
|
hide.long 0x00 "DOEPTSIZ2,OTG_FS Device Endpoint-X Transfer Size Register"
|
|
hgroup.long 0xB70++0x03
|
|
hide.long 0x00 "DOEPTSIZ3,OTG_FS Device Endpoint-X Transfer Size Register"
|
|
hgroup.long 0xB90++0x03
|
|
hide.long 0x00 "DOEPTSIZ4,OTG_FS Device Endpoint-X Transfer Size Register"
|
|
hgroup.long 0xBB0++0x03
|
|
hide.long 0x00 "DOEPTSIZ5,OTG_FS Device Endpoint-X Transfer Size Register"
|
|
endif
|
|
tree.end
|
|
tree "Power and clock gating control and status registers"
|
|
group.long 0xE00++0x03
|
|
line.long 0x00 "PCGCCTL,OTG_FS Power And Clock Gating Control Register"
|
|
rbitfld.long 0x00 7. " SUSP ,Deep sleep" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " PHYSLEEP ,PHY in sleep" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ENL1GTG ,Enable sleep clock gating" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 4. " PHYSUSP ,PHY suspended" "Not suspended,Suspended"
|
|
bitfld.long 0x00 1. " GATEHCLK ,Gate HCLK" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " STPPCLK ,Stop PHY clock" "Not stopped,Stopped"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "USB_OTG_HS (USB on-the-go high-speed)"
|
|
base ad:0x40040000
|
|
width 11.
|
|
tree "OTG_HS Global Registers"
|
|
if (((per.l((ad:0x40040000+0x014)))&0x01)==0x01)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GOTGCTL,Control And Status Register"
|
|
rbitfld.long 0x00 21. " CURMOD ,Current mode of operation" "Device mode,Host mode"
|
|
bitfld.long 0x00 20. " OTGVER ,OTG version" "1.3,2.0"
|
|
rbitfld.long 0x00 18. " ASVLD ,A-session valid" "Not valid,Valid"
|
|
newline
|
|
rbitfld.long 0x00 17. " DBCT ,Long/short debounce time" "Long,Short"
|
|
rbitfld.long 0x00 16. " CIDSTS ,Connector ID status" "A-Device,B-Device"
|
|
bitfld.long 0x00 12. " EHEN ,Embedded host enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " HSHNPEN ,Host set HNP enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " AVALOVAL ,A-peripheral session valid override value" "0,1"
|
|
bitfld.long 0x00 4. " AVALOEN ,A-peripheral session valid override enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " VBVALOVAL ,VBUS valid override value" "0,1"
|
|
bitfld.long 0x00 2. " VBVALOEN ,VBUS valid override enable" "Disabled,Enabled"
|
|
if (((per.l((ad:0x40040000+0x0C)))&0x300)!=0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "GOTGINT,Interrupt Register"
|
|
eventfld.long 0x00 20. " IDCHNG ,Change in the value of the ID input pin" "Not changed,Changed"
|
|
eventfld.long 0x00 19. " DBCDNE ,Debounce done" "Not done,Done"
|
|
eventfld.long 0x00 18. " ADTOCHG ,A-device timeout change" "Not changed,Changed"
|
|
newline
|
|
eventfld.long 0x00 17. " HNGDET ,Host negotiation detected" "Not detected,Detected"
|
|
eventfld.long 0x00 9. " HNSSCHG ,Host negotiation success status change" "Not changed,Changed"
|
|
eventfld.long 0x00 8. " SRSSCHG ,Session request success status change" "Not changed,Changed"
|
|
newline
|
|
eventfld.long 0x00 2. " SEDET ,Session end detected" "Not detected,Detected"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "GOTGINT,Interrupt Register"
|
|
eventfld.long 0x00 20. " IDCHNG ,Change in the value of the ID input pin" "Not changed,Changed"
|
|
eventfld.long 0x00 18. " ADTOCHG ,A-device timeout change" "Not changed,Changed"
|
|
eventfld.long 0x00 17. " HNGDET ,Host negotiation detected" "Not detected,Detected"
|
|
newline
|
|
eventfld.long 0x00 9. " HNSSCHG ,Host negotiation success status change" "Not changed,Changed"
|
|
eventfld.long 0x00 8. " SRSSCHG ,Session request success status change" "Not changed,Changed"
|
|
eventfld.long 0x00 2. " SEDET ,Session end detected" "Not detected,Detected"
|
|
endif
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "GAHBCFG,AHB Configuration Register"
|
|
bitfld.long 0x00 8. " PTXFELVL ,Periodic TxFIFO empty level" "Half empty,Empty"
|
|
bitfld.long 0x00 7. " TXFELVL ,IN endpoint TxFIFO empty level" "Half empty,Empty"
|
|
bitfld.long 0x00 5. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1.--4. " HBSTLEN ,Burst length/type" "Single,INCR,,INCR4,,INCR8,,INCR16,?..."
|
|
bitfld.long 0x00 0. " GINT ,Global interrupt mask" "Masked,Unmasked"
|
|
line.long 0x04 "GUSBCFG,USB Configuration Register"
|
|
bitfld.long 0x04 30. " FDMOD ,Force device mode" "Normal,Forced"
|
|
bitfld.long 0x04 29. " FHMOD ,Force host mode" "Normal,Forced"
|
|
bitfld.long 0x04 25. " ULPIIPD ,ULPI interface protect disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 24. " PTCI ,Indicator pass through" "Compared,Not compared"
|
|
bitfld.long 0x04 23. " PCCI ,Indicator complement" "Not inverted,Inverted"
|
|
bitfld.long 0x04 22. " TSDPS ,TermSel DLine pulsing selection" "Utmi_txvalid,Utmi_termsel"
|
|
newline
|
|
bitfld.long 0x04 21. " ULPIEVBUSI ,ULPI external VBUS indicator" "Internal,External"
|
|
bitfld.long 0x04 20. " ULPIEVBUSD ,ULPI external VBUS drive" "Internal,External"
|
|
bitfld.long 0x04 19. " ULPICSM ,ULPI clock SuspendM" "Power down,Power up"
|
|
newline
|
|
bitfld.long 0x04 18. " ULPIAR ,ULPI auto-resume enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " ULPIFSLS ,ULPI FS/LS select" "ULPI,ULPI FS/LS"
|
|
bitfld.long 0x04 15. " PHYLPCS ,PHY low-power clock select" "480 MHz,48 MHz"
|
|
newline
|
|
bitfld.long 0x04 9. " HNPCAP ,HNP-capable" "Not capable,Capable"
|
|
bitfld.long 0x04 8. " SRPCAP ,SRP-capable" "Not capable,Capable"
|
|
bitfld.long 0x04 6. " PHYSEL ,Full speed serial transceiver select" "High speed,Full speed"
|
|
newline
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*"))
|
|
bitfld.long 0x04 4. " ULPI_SEL ,Select which high speed interface is to be used" "UTMI,ULPI"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 0.--2. " TOCAL ,FS timeout calibration" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "GRSTCTL,Reset Register"
|
|
rbitfld.long 0x08 31. " AHBIDL ,AHB master idle" "Busy,Idle"
|
|
rbitfld.long 0x08 30. " DMAREQ ,DMA request signal" "Not requested,Requested"
|
|
bitfld.long 0x08 6.--10. " TXFNUM ,TxFIFO number" "Non-periodic TxFIFO,Periodic TxFIFO,,,,,,,,,,,,,,,All TxFIFOs,?..."
|
|
newline
|
|
bitfld.long 0x08 5. " TXFFLSH ,TxFIFO flush" "No effect,Flush"
|
|
bitfld.long 0x08 4. " RXFFLSH ,RxFIFO flush" "No effect,Flush"
|
|
newline
|
|
sif (!cpuis("STM32F7*"))
|
|
bitfld.long 0x08 2. " FCRST ,Host frame counter reset" "No reset,Reset"
|
|
newline
|
|
endif
|
|
bitfld.long 0x08 1. " PSRST ,Partial soft reset" "No reset,Reset"
|
|
bitfld.long 0x08 0. " CSRST ,Core soft reset" "No reset,Reset"
|
|
if (((per.l(ad:0x40040000+0x08)&0x20)==0x20))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GINTSTS,Core Interrupt Register"
|
|
eventfld.long 0x00 31. " WKUPINT ,Resume/remote wakeup detected interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " SRQINT ,Session request/new session detected interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 29. " DISCINT ,Disconnect detected interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 28. " CIDSCHG ,Connector ID status change" "Not changed,Changed"
|
|
rbitfld.long 0x00 26. " PTXFE ,Periodic TxFIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 25. " HCINT ,Host channels interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 24. " HPRTINT ,Host port interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " DATAFSUSP ,Data fetch suspended" "Not suspended,Suspended"
|
|
eventfld.long 0x00 21. " IPXFR ,Incomplete periodic transfer" "No interrupt,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 5. " NPTXFE ,Non-periodic TxFIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 4. " RXFLVL ,RxFIFO non-empty" "Empty,Not empty"
|
|
eventfld.long 0x00 3. " SOF ,Start of frame" "Not started,Started"
|
|
newline
|
|
rbitfld.long 0x00 2. " OTGINT ,OTG interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " MMIS ,Mode mismatch interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 0. " CMOD ,Current mode of operation" "Device mode,Host mode"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GINTSTS,Core Interrupt Register"
|
|
eventfld.long 0x00 31. " WKUPINT ,Remote wakeup detected interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " SRQINT ,Session request/new session detected interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 29. " DISCINT ,Disconnect detected interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 28. " CIDSCHG ,Connector ID status change" "Not changed,Changed"
|
|
rbitfld.long 0x00 26. " PTXFE ,Periodic TxFIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 25. " HCINT ,Host channels interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 24. " HPRTINT ,Host port interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 21. " IPXFR ,Incomplete periodic transfer" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 5. " NPTXFE ,Non-periodic TxFIFO empty" "Not empty,Empty"
|
|
newline
|
|
rbitfld.long 0x00 4. " RXFLVL ,RxFIFO non-empty" "Empty,Not empty"
|
|
eventfld.long 0x00 3. " SOF ,Start of frame" "Not started,Started"
|
|
rbitfld.long 0x00 2. " OTGINT ,OTG interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 1. " MMIS ,Mode mismatch interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 0. " CMOD ,Current mode of operation" "Device mode,Host mode"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "GINTMSK,Interrupt Mask Register"
|
|
bitfld.long 0x00 31. " WUIM ,Remote wakeup detected interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 30. " SRQIM ,Session request/new session detected interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 28. " CIDSCHGM ,Connector ID status change mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x00 27. " LPMINTM ,LPM interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 26. " PTXFEM ,Periodic TxFIFO empty mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 25. " HCIM ,Host channels interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
rbitfld.long 0x00 24. " PRTIM ,Host port interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 22. " FSUSPM ,Data fetch suspended mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 21. " IPXFRM ,Incomplete periodic transfer mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x00 5. " NPTXFEM ,Non-periodic TxFIFO empty mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 4. " RXFLVLM ,Receive FIFO non-empty mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 3. " SOFM ,Start of frame mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x00 2. " OTGINT ,OTG interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 1. " MMISM ,Mode mismatch interrupt mask" "Masked,Unmasked"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "GOTGCTL,Control And Status Register"
|
|
rbitfld.long 0x00 21. " CURMOD ,Current mode of operation" "Device mode,Host mode"
|
|
bitfld.long 0x00 20. " OTGVER ,OTG version" "1.3,2.0"
|
|
rbitfld.long 0x00 19. " BSVLD ,B-session valid" "Not valid,Valid"
|
|
newline
|
|
rbitfld.long 0x00 16. " CIDSTS ,Connector ID status" "A-Device,B-Device"
|
|
bitfld.long 0x00 12. " EHEN ,Embedded host enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " DHNPEN ,Device HNP enabled" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " HNPRQ ,HNP request" "Not requested,Requested"
|
|
rbitfld.long 0x00 8. " HNGSCS ,Host negotiation success" "Failed,Successful"
|
|
bitfld.long 0x00 7. " BVALOVAL ,B-peripheral session valid override value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. " BVALOEN ,B-peripheral session valid override enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SRQ ,Session request" "Not requested,Requested"
|
|
rbitfld.long 0x00 0. " SRQSCS ,Session request success" "Failed,Successful"
|
|
line.long 0x04 "GOTGINT,Interrupt Register"
|
|
eventfld.long 0x04 20. " IDCHNG ,Change in the value of the ID input pin" "Not changed,Changed"
|
|
eventfld.long 0x04 18. " ADTOCHG ,A-device timeout change" "Not changed,Changed"
|
|
eventfld.long 0x04 17. " HNGDET ,Host negotiation detected" "Not detected,Detected"
|
|
newline
|
|
eventfld.long 0x04 9. " HNSSCHG ,Host negotiation success status change" "Not changed,Changed"
|
|
eventfld.long 0x04 8. " SRSSCHG ,Session request success status change" "Not changed,Changed"
|
|
eventfld.long 0x04 2. " SEDET ,Session end detected" "Not detected,Detected"
|
|
line.long 0x08 "GAHBCFG,AHB Configuration Register"
|
|
bitfld.long 0x08 7. " TXFELVL ,IN endpoint TxFIFO empty level" "Half empty,Empty"
|
|
bitfld.long 0x08 5. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1.--4. " HBSTLEN ,Burst length/type" "Single,INCR,,INCR4,,INCR8,,INCR16,?..."
|
|
newline
|
|
bitfld.long 0x08 0. " GINT ,Global interrupt mask" "Masked,Unmasked"
|
|
line.long 0x0C "GUSBCFG,USB Configuration Register"
|
|
bitfld.long 0x0C 30. " FDMOD ,Force device mode" "Normal,Forced"
|
|
bitfld.long 0x0C 29. " FHMOD ,Force host mode" "Normal,Forced"
|
|
bitfld.long 0x0C 25. " ULPIIPD ,ULPI interface protect disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x0C 24. " PTCI ,Indicator pass through" "Compared,Not compared"
|
|
bitfld.long 0x0C 23. " PCCI ,Indicator complement" "Not inverted,Inverted"
|
|
bitfld.long 0x0C 22. " TSDPS ,TermSel DLine pulsing selection" "Utmi_txvalid,Utmi_termsel"
|
|
newline
|
|
bitfld.long 0x0C 21. " ULPIEVBUSI ,ULPI external VBUS indicator" "Internal,External"
|
|
bitfld.long 0x0C 20. " ULPIEVBUSD ,ULPI external VBUS drive" "Internal,External"
|
|
bitfld.long 0x0C 19. " ULPICSM ,ULPI clock SuspendM" "Power down,Power up"
|
|
newline
|
|
bitfld.long 0x0C 18. " ULPIAR ,ULPI auto-resume enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " ULPIFSLS ,ULPI FS/LS select" "ULPI,ULPI FS/LS"
|
|
bitfld.long 0x0C 15. " PHYLPCS ,PHY low-power clock select" "480 MHz,48 MHz"
|
|
newline
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
bitfld.long 0x0C 10.--13. " TRDT ,USB turnaround time" ",,,,,,32MHz,27.5MHz - 32MHz,24MHz - 27.5MHz,21.8MHz - 24MHz || 30MHz,20MHz - 21.8MHz,18.5MHz - 20MHz,17.2MHz - 18.5MHz,16MHz - 17.2MHz,15MHz - 16MHz,14.2MHz - 15MHz"
|
|
newline
|
|
elif (cpuis("STM32F7*"))
|
|
bitfld.long 0x0C 10.--13. " TRDT ,USB turnaround time" ",,,,,,,,,30MHz-,?..."
|
|
newline
|
|
else
|
|
bitfld.long 0x0C 10.--13. " TRDT ,USB turnaround time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0C 9. " HNPCAP ,HNP-capable" "Not capable,Capable"
|
|
bitfld.long 0x0C 8. " SRPCAP ,SRP-capable" "Not capable,Capable"
|
|
bitfld.long 0x0C 6. " PHYSEL ,Full speed serial transceiver select" "High speed,Full speed"
|
|
newline
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*"))
|
|
bitfld.long 0x0C 4. " ULPI_SEL ,Select which high speed interface is to be used" "UTMI,ULPI"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0C 0.--2. " TOCAL ,FS timeout calibration" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "GRSTCTL,Reset Register"
|
|
rbitfld.long 0x10 31. " AHBIDL ,AHB master idle" "Low,High"
|
|
rbitfld.long 0x10 30. " DMAREQ ,DMA request signal" "Not requested,Requested"
|
|
bitfld.long 0x10 6.--10. " TXFNUM ,TxFIFO number" "TxFIFO 0,TxFIFO 1,TxFIFO 2,TxFIFO 3,TxFIFO 4,TxFIFO 5,TxFIFO 6,TxFIFO 7,TxFIFO 8,TxFIFO 9,TxFIFO 10,TxFIFO 11,TxFIFO 12,TxFIFO 13,TxFIFO 14,TxFIFO 15,All TxFIFOs,?..."
|
|
newline
|
|
bitfld.long 0x10 5. " TXFFLSH ,TxFIFO flush" "No effect,Flush"
|
|
bitfld.long 0x10 4. " RXFFLSH ,RxFIFO flush" "No effect,Flush"
|
|
bitfld.long 0x10 1. " PSRST ,Partial soft reset" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x10 0. " CSRST ,Core soft reset" "No reset,Reset"
|
|
if (((per.l(ad:0x40040000+0x08)&0x20)==0x20))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GINTSTS,Core Interrupt Register"
|
|
eventfld.long 0x00 31. " WKUPINT ,Resume wakeup detected interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " SRQINT ,Session request/new session detected interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 28. " CIDSCHG ,Connector ID status change" "Not changed,Changed"
|
|
newline
|
|
eventfld.long 0x00 22. " DATAFSUSP ,Data fetch suspended" "Not suspended,Suspended"
|
|
eventfld.long 0x00 21. " IPXFR ,Incomplete periodic transfer" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " IISOIXFR ,Incomplete isochronous IN transfer" "No interrupt,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 19. " OEPINT ,OUT endpoint interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 18. " IEPINT ,IN endpoint interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 15. " EOPF ,End of periodic frame interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 14. " ISOODRP ,Isochronous OUT packet dropped interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " ENUMDNE ,Enumeration done" "Not done,Done"
|
|
eventfld.long 0x00 12. " USBRST ,USB reset" "No reset,Reset"
|
|
newline
|
|
eventfld.long 0x00 11. " USBSUSP ,USB suspend" "Not suspended,Suspended"
|
|
eventfld.long 0x00 10. " ESUSP ,Early suspend" "Not suspended,Suspended"
|
|
rbitfld.long 0x00 7. " GONAKEFF ,Global OUT NAK effective" "Low,High"
|
|
newline
|
|
rbitfld.long 0x00 6. " GINAKEFF ,Global IN non-periodic NAK effective" "Low,High"
|
|
rbitfld.long 0x00 4. " RXFLVL ,RxFIFO non-empty" "Empty,Not empty"
|
|
eventfld.long 0x00 3. " SOF ,Start of frame" "Not started,Started"
|
|
newline
|
|
rbitfld.long 0x00 2. " OTGINT ,OTG interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " MMIS ,Mode mismatch interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 0. " CMOD ,Current mode of operation" "Device mode,Host mode"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GINTSTS,Core Interrupt Register"
|
|
eventfld.long 0x00 31. " WKUPINT ,Resume wakeup detected interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " SRQINT ,Session request/new session detected interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 28. " CIDSCHG ,Connector ID status change" "Not changed,Changed"
|
|
newline
|
|
eventfld.long 0x00 22. " DATAFSUSP ,Data fetch suspended" "Not suspended,Suspended"
|
|
eventfld.long 0x00 21. " IPXFR ,Incomplete periodic transfer" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " IISOIXFR ,Incomplete isochronous IN transfer" "No interrupt,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 19. " OEPINT ,OUT endpoint interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 18. " IEPINT ,IN endpoint interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 15. " EOPF ,End of periodic frame interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 14. " ISOODRP ,Isochronous OUT packet dropped interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " ENUMDNE ,Enumeration done" "Not done,Done"
|
|
eventfld.long 0x00 12. " USBRST ,USB reset" "No reset,Reset"
|
|
newline
|
|
eventfld.long 0x00 11. " USBSUSP ,USB suspend" "Not suspended,Suspended"
|
|
eventfld.long 0x00 10. " ESUSP ,Early suspend" "Not suspended,Suspended"
|
|
rbitfld.long 0x00 7. " GONAKEFF ,Global OUT NAK effective" "Low,High"
|
|
newline
|
|
rbitfld.long 0x00 6. " GINAKEFF ,Global IN non-periodic NAK effective" "Low,High"
|
|
rbitfld.long 0x00 4. " RXFLVL ,RxFIFO non-empty" "Empty,Not empty"
|
|
eventfld.long 0x00 3. " SOF ,Start of frame" "Not started,Started"
|
|
newline
|
|
rbitfld.long 0x00 2. " OTGINT ,OTG interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " MMIS ,Mode mismatch interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 0. " CMOD ,Current mode of operation" "Device mode,Host mode"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "GINTMSK,Interrupt Mask Register"
|
|
bitfld.long 0x00 31. " WUIM ,Resume wakeup detected interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 30. " SRQIM ,Session request/new session detected interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 29. " DISCINT ,Disconnect detected interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x00 28. " CIDSCHGM ,Connector ID status change mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 27. " LPMINTM ,LPM interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 23. " RSTDETM ,Reset detected interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x00 22. " FSUSPM ,Data fetch suspended mask" "Masked,Unmasked"
|
|
newline
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
bitfld.long 0x00 21. " IPXFRM ,Incomplete periodic transfer mask" "Masked,Unmasked"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 21. " IISOOXFRM ,Incomplete isochronous OUT transfer mask" "Masked,Unmasked"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 20. " IISOIXFRM ,Incomplete isochronous IN transfer mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 19. " OEPINT ,OUT endpoints interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 18. " IEPINT ,IN endpoints interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x00 15. " EOPFM ,End of periodic frame interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 14. " ISOODRPM ,Isochronous OUT packet dropped interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 13. " ENUMDNEM ,Enumeration done mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x00 12. " USBRST ,USB reset mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 11. " USBSUSPM ,USB suspend mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 10. " ESUSPM ,Early suspend mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x00 7. " GONAKEFFM ,Global OUT NAK effective mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 6. " GINAKEFFM ,Global non-periodic IN NAK effective mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 4. " RXFLVLM ,Receive FIFO non-empty mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x00 3. " SOFM ,Start of frame mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 2. " OTGINT ,OTG interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 1. " MMISM ,Mode mismatch interrupt mask" "Masked,Unmasked"
|
|
endif
|
|
newline
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "GRXSTSR,Receive Status Debug Read Register"
|
|
in
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "GRXSTSP,OTG Status Read And Pop Register"
|
|
in
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "GRXFSIZ,Receive FIFO Size Register"
|
|
in
|
|
newline
|
|
if (((per.l((ad:0x40040000+0x014)))&0x01)==0x01)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "HNPTXFSIZ,Non-Periodic Transmit FIFO Size Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " NPTXFD ,Non-periodic TxFIFO depth"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " NPTXFSA ,Non-periodic transmit RAM start address"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "HNPTXSTS,Non-Periodic Transmit FIFO/queue Status Register"
|
|
bitfld.long 0x00 27.--30. " NPTXQTOP[30:27] ,Top of the nonperiodic transmit request queue [CH/EP number]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 25.--26. " NPTXQTOP[26:25] ,Top of the nonperiodic transmit request queue" "IN/OUT Token,Zero-length,,Channel halt"
|
|
bitfld.long 0x00 24. " NPTXQTOP[24] ,Top of the nonperiodic transmit request queue" "Not terminated,Terminated"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " NPTQXSAV ,Non-periodic transmit request queue space available"
|
|
hexmask.long.word 0x00 0.--15. 1. " NPTXFSAV ,Non-periodic TxFIFO space available"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DIEPTXF,Endpoint 0 Transmit FIFO Size Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " T0XFD ,Endpoint 0 TxFIFO depth"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " TX0FSA ,Endpoint 0 transmit RAM start address"
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "HNPTXSTS,Non-Periodic Transmit FIFO/Queue Status Register"
|
|
endif
|
|
sif (!cpuis("STM32F7*"))
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "GI2CCTL,I2C Access Register"
|
|
bitfld.long 0x00 31. " BSYDNE ,I2C busy/done" "Done,Busy"
|
|
bitfld.long 0x00 30. " RW ,Read/Write indicator" "Write,Read"
|
|
bitfld.long 0x00 28. " I2CDATSE0 ,I2C datse0 USB mode" "VP_VM USB,DAT_SE0 USB"
|
|
newline
|
|
bitfld.long 0x00 26.--27. " I2CDEVADR ,I2C device address" "0,1,2,3"
|
|
bitfld.long 0x00 24. " ACK ,I2C ACK" "NAK,ACK"
|
|
bitfld.long 0x00 23. " I2CEN ,I2C enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " ADDR ,I2C address"
|
|
hexmask.long.byte 0x00 8.--15. 0x01 " REGADDR ,I2C register address"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RWDATA ,I2C read/write data"
|
|
endif
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "GCCFG,General Core Configuration Register"
|
|
bitfld.long 0x00 21. " VBDEN ,USB VBUS detection enable" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.long 0x00 20. " SDEN ,Secondary detection (SD) mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PDEN ,Primary detection (PD) mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DCDEN ,Data contact detection (DCD) mode enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " BCDEN ,Battery charging detector (BCD) enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " PWRDWN ,Power down" "Powered down,Not powered down"
|
|
bitfld.long 0x00 3. " PS2DET ,DM pull-up detection status" "Normal port,PS2 port || proprietary charger"
|
|
newline
|
|
bitfld.long 0x00 2. " SDET ,Secondary detection (SD) status" "CDP detected,DCP detected"
|
|
bitfld.long 0x00 1. " PDET ,Primary detection (PD) status" "No BCD support,BCD support"
|
|
bitfld.long 0x00 0. " DCDET ,Data contact detection (DCD) status" "Not detected,Detected"
|
|
else
|
|
sif (!cpuis("STM32F74")&&!cpuis("STM32F75"))
|
|
bitfld.long 0x00 20. " SDEN ,Secondary detection (SD) mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PDEN ,Primary detection (PD) mode enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 18. " DCDEN ,Data contact detection (DCD) mode enable" "Disabled,Enabled"
|
|
newline
|
|
sif (!cpuis("STM32F74")&&!cpuis("STM32F75"))
|
|
bitfld.long 0x00 17. " BCDEN ,Battery charging detector (BCD) enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 16. " PWRDWN ,Power down" "Powered down,Not powered down"
|
|
newline
|
|
sif (!cpuis("STM32F74")&&!cpuis("STM32F75"))
|
|
rbitfld.long 0x00 3. " PS2DET ,DM pull-up detection status" "Normal port,PS2 port || proprietary charger"
|
|
rbitfld.long 0x00 2. " SDET ,Secondary detection (SD) status" "CDP detected,DCP detected"
|
|
rbitfld.long 0x00 1. " PDET ,Primary detection (PD) status" "No BCD support,BCD support"
|
|
newline
|
|
endif
|
|
rbitfld.long 0x00 0. " DCDET ,Data contact detection (DCD) status" "Not detected,Detected"
|
|
endif
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "CID,Core ID Register"
|
|
if (((per.l((ad:0x40040000+0x14)))&0x01)==0x01)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GLPMCFG,OTG Core LPM Configuration Register"
|
|
bitfld.long 0x00 28. " ENBESL ,Enable best effort service latency" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25.--27. " LPMRCNTSTS ,LPM retry count status" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24. " SNDLPM ,Send LPM transaction" "Sending,Cleared"
|
|
newline
|
|
bitfld.long 0x00 21.--23. " LPMRCNT ,LPM retry count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 17.--20. " LPMCHIDX ,LPM channel index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 16. " L1RSMOK ,Sleep state resume OK" "No,Yes"
|
|
newline
|
|
rbitfld.long 0x00 15. " SLPSTS ,Port sleep status" "Not in L1,In L1"
|
|
rbitfld.long 0x00 13.--14. " LPMRST ,LPM response" "ERROR,STALL,NYET,ACK"
|
|
bitfld.long 0x00 12. " L1DSEN ,L1 deep sleep enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " BESLTHRS ,BESL threshold" "75,100,150,250,350,450,950,?..."
|
|
bitfld.long 0x00 7. " L1SSEN ,L1 shallow sleep enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " REMWAKE ,BRemoteWake value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2.--5. " BESL ,Best effort service latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " LPMEN ,LPM support enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GLPMCFG,OTG Core LPM Configuration Register"
|
|
bitfld.long 0x00 28. " ENBESL ,Enable best effort service latency" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16. " L1RSMOK ,Sleep state resume OK" "No,Yes"
|
|
rbitfld.long 0x00 15. " SLPSTS ,Port sleep status" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 13.--14. " LPMRST ,LPM response" "0,1,2,3"
|
|
bitfld.long 0x00 12. " L1DSEN ,L1 deep sleep enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " BESLTHRS ,BESL threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7. " L1SSEN ,L1 shallow sleep enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " REMWAKE ,BRemoteWake value" "0,1"
|
|
rbitfld.long 0x00 2.--5. " BESL ,Best effort service latency" "125 us,150 us,200 us,300 us,400 us,500 us,1000 us,2000 us,3000 us,4000 us,5000 us,6000 us,7000 us,8000 us,9000 us,10000 us"
|
|
newline
|
|
bitfld.long 0x00 1. " LPMACK ,LPM token acknowledge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LPMEN ,LPM support enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "HPTXFSIZ,Host Periodic Transmit FIFO Size Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " PTXFD ,Host periodic TxFIFO depth"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " PTXSA ,Host periodic TxFIFO start address"
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "DIEPTXF1,Device IN Endpoint Transmit FIFO Size Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO depth"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " INEPTXSA ,IN endpoint FIFOx transmit RAM start address"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "DIEPTXF2,Device IN Endpoint Transmit FIFO Size Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO depth"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " INEPTXSA ,IN endpoint FIFOx transmit RAM start address"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "DIEPTXF3,Device IN Endpoint Transmit FIFO Size Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO depth"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " INEPTXSA ,IN endpoint FIFOx transmit RAM start address"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DIEPTXF4,Device IN Endpoint Transmit FIFO Size Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO depth"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " INEPTXSA ,IN endpoint FIFOx transmit RAM start address"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "DIEPTXF5,Device IN Endpoint Transmit FIFO Size Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO depth"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " INEPTXSA ,IN endpoint FIFOx transmit RAM start address"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "DIEPTXF6,Device IN Endpoint Transmit FIFO Size Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO depth"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " INEPTXSA ,IN endpoint FIFOx transmit RAM start address"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "DIEPTXF7,Device IN Endpoint Transmit FIFO Size Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO depth"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " INEPTXSA ,IN endpoint FIFOx transmit RAM start address"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "DIEPTXF8,Device IN Endpoint Transmit FIFO Size Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO depth"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " INEPTXSA ,IN endpoint FIFOx transmit RAM start address"
|
|
else
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "DIEPTXF1,Device IN Endpoint Transmit FIFO Size Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO 1 depth"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " INEPTXSA ,IN endpoint TxFIFO 1 transmit RAM start address"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "DIEPTXF2,Device IN Endpoint Transmit FIFO Size Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO 2 depth"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " INEPTXSA ,IN endpoint TxFIFO 2 transmit RAM start address"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "DIEPTXF3,Device IN Endpoint Transmit FIFO Size Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO 3 depth"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " INEPTXSA ,IN endpoint TxFIFO 3 transmit RAM start address"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DIEPTXF4,Device IN Endpoint Transmit FIFO Size Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO 4 depth"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " INEPTXSA ,IN endpoint TxFIFO 4 transmit RAM start address"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "DIEPTXF5,Device IN Endpoint Transmit FIFO Size Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO 5 depth"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " INEPTXSA ,IN endpoint TxFIFO 5 transmit RAM start address"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "DIEPTXF6,Device IN Endpoint Transmit FIFO Size Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO 6 depth"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " INEPTXSA ,IN endpoint TxFIFO 6 transmit RAM start address"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "DIEPTXF7,Device IN Endpoint Transmit FIFO Size Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO 7 depth"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " INEPTXSA ,IN endpoint TxFIFO 7 transmit RAM start address"
|
|
endif
|
|
tree.end
|
|
width 14.
|
|
tree "Host Mode Registers"
|
|
if (((per.l((ad:0x40040000+0x014)))&0x01)==0x01)
|
|
sif (cpuis("STM32F7*"))
|
|
if (((per.l((ad:0x40040000+0x440)))&0x60000)==0x40000)
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "HCFG,OTG_FS Host Configuration Register"
|
|
rbitfld.long 0x00 2. " FSLSS ,FS- and LS-only support" "Not supported,Supported"
|
|
bitfld.long 0x00 0.--1. " FSLSPCS ,FS/LS PHY clock select" ",48 MHz,6 MHz,?..."
|
|
elif (((per.l((ad:0x40040000+0x440)))&0x60000)==0x20000)
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "HCFG,OTG_FS Host Configuration Register"
|
|
rbitfld.long 0x00 2. " FSLSS ,FS- and LS-only support" "Not supported,Supported"
|
|
bitfld.long 0x00 0.--1. " FSLSPCS ,FS/LS PHY clock select" ",48 MHz,?..."
|
|
else
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "HCFG,OTG_FS Host Configuration Register"
|
|
rbitfld.long 0x00 2. " FSLSS ,FS- and LS-only support" "Not supported,Supported"
|
|
endif
|
|
else
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "HCFG,Host Configuration Register"
|
|
rbitfld.long 0x00 2. " FSLSS ,FS- and LS-only support" "Not supported,Supported"
|
|
bitfld.long 0x00 0.--1. " FSLSPCS ,FS/LS PHY clock select" ",48 MHz,6 MHz,?..."
|
|
endif
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "HFIR,Host Frame Interval Register"
|
|
bitfld.long 0x00 16. " RLDCTRL ,Reload control" "Not automatic,Automatic"
|
|
hexmask.long.word 0x00 0.--15. 1. " FRIVL ,Frame interval"
|
|
rgroup.long 0x408++0x03
|
|
line.long 0x00 "HFNUM,Host Frame Number/Frame Time Remaining Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " FTREM ,Frame time remaining"
|
|
hexmask.long.word 0x00 0.--15. 1. " FRNUM ,Frame number"
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
rgroup.long 0x410++0x03
|
|
line.long 0x00 "HPTXSTS,Host Periodic Transmit FIFO/Queue Status Register"
|
|
bitfld.long 0x00 31. " PTXQTOP[31] ,Odd/Even frame" "Even,Odd"
|
|
bitfld.long 0x00 27.--30. " PTXQTOP[27:30] ,Channel/endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 25.--26. " PTXQTOP[25:26] ,Type" "IN/OUT,Zero-length,,Disabled"
|
|
newline
|
|
bitfld.long 0x00 24. " PTXQTOP[24] ,Terminate" "Not terminated,Terminated"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PTXQSAV ,Periodic transmit request queue space available"
|
|
hexmask.long.word 0x00 0.--15. 1. " PTXFSAVL ,Periodic transmit data FIFO space available"
|
|
newline
|
|
else
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "HPTXSTS,Host Periodic Transmit FIFO/Queue Status Register"
|
|
bitfld.long 0x00 31. " PTXQTOP[31] ,Odd/Even frame" "Even,Odd"
|
|
bitfld.long 0x00 27.--30. " PTXQTOP[27:30] ,Channel/endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 25.--26. " PTXQTOP[25:26] ,Type" "IN/OUT,Zero-length,,Disabled"
|
|
newline
|
|
bitfld.long 0x00 24. " PTXQTOP[24] ,Terminate" "Not terminated,Terminated"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PTXQSAV ,Periodic transmit request queue space available"
|
|
hexmask.long.word 0x00 0.--15. 1. " PTXFSAVL ,Periodic transmit data FIFO space available"
|
|
newline
|
|
endif
|
|
rgroup.long 0x414++0x03
|
|
line.long 0x00 "HAINT,Host All Channels Interrupt Register"
|
|
bitfld.long 0x00 15. " HAINT_[15] ,Channel 15 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " [14] ,Channel 14 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " [13] ,Channel 13 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " [12] ,Channel 12 interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Channel 11 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " [10] ,Channel 10 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " [9] ,Channel 9 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " [8] ,Channel 8 interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Channel 7 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " [6] ,Channel 6 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " [5] ,Channel 5 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " [4] ,Channel 4 interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Channel 3 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " [2] ,Channel 2 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " [1] ,Channel 1 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " [0] ,Channel 0 interrupt" "No interrupt,Interrupt"
|
|
group.long 0x418++0x03
|
|
line.long 0x00 "HAINTMSK,Host All Channels Interrupt Mask Register"
|
|
bitfld.long 0x00 15. " HAINTM_[15] ,Channel interrupt mask 15" "Masked,Unmasked"
|
|
bitfld.long 0x00 14. " [14] ,Channel interrupt mask 14" "Masked,Unmasked"
|
|
bitfld.long 0x00 13. " [13] ,Channel interrupt mask 13" "Masked,Unmasked"
|
|
bitfld.long 0x00 12. " [12] ,Channel interrupt mask 12" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Channel interrupt mask 11" "Masked,Unmasked"
|
|
bitfld.long 0x00 10. " [10] ,Channel interrupt mask 10" "Masked,Unmasked"
|
|
bitfld.long 0x00 9. " [9] ,Channel interrupt mask 9" "Masked,Unmasked"
|
|
bitfld.long 0x00 8. " [8] ,Channel interrupt mask 8" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Channel interrupt mask 7" "Masked,Unmasked"
|
|
bitfld.long 0x00 6. " [6] ,Channel interrupt mask 6" "Masked,Unmasked"
|
|
bitfld.long 0x00 5. " [5] ,Channel interrupt mask 5" "Masked,Unmasked"
|
|
bitfld.long 0x00 4. " [4] ,Channel interrupt mask 4" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Channel interrupt mask 3" "Masked,Unmasked"
|
|
bitfld.long 0x00 2. " [2] ,Channel interrupt mask 2" "Masked,Unmasked"
|
|
bitfld.long 0x00 1. " [1] ,Channel interrupt mask 1" "Masked,Unmasked"
|
|
bitfld.long 0x00 0. " [0] ,Channel interrupt mask 0" "Masked,Unmasked"
|
|
newline
|
|
group.long 0x440++0x03
|
|
line.long 0x00 "HPRT,Host Port Control And Status Register"
|
|
rbitfld.long 0x00 17.--18. " PSPD ,Port speed" "High,Full,Low,?..."
|
|
bitfld.long 0x00 13.--16. " PTCTL ,Port test control" "Disabled,J mode,K mode,SE0_NAK mode,Packet mode,Force_Enable,?..."
|
|
bitfld.long 0x00 12. " PPWR ,Port power" "Off,On"
|
|
rbitfld.long 0x00 11. " PLSTS[1] ,Port line status (Logic level of HS_DP)" "Low,High"
|
|
newline
|
|
rbitfld.long 0x00 10. " PLSTS[0] ,Port line status (Logic level of HS_DM)" "Low,High"
|
|
bitfld.long 0x00 8. " PRST ,Port reset" "No reset,Reset"
|
|
bitfld.long 0x00 7. " PSUSP ,Port suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 6. " PRES ,Port resume" "Not resumed,Resumed"
|
|
newline
|
|
eventfld.long 0x00 5. " POCCHNG ,Port overcurrent change" "Not changed,Changed"
|
|
rbitfld.long 0x00 4. " POCA ,Port overcurrent active" "Not active,Active"
|
|
eventfld.long 0x00 3. " PENCHNG ,Port enable/disable change" "Not changed,Changed"
|
|
newline
|
|
sif (cpuis("STM32F7*"))
|
|
eventfld.long 0x00 2. " PENA ,Port enable" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 2. " PENA ,Port enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 1. " PCDET ,Port connect detected" "Not detected,Detected"
|
|
rbitfld.long 0x00 0. " PCSTS ,Port connect status" "Not connected,Connected"
|
|
group.long 0x500++0x17
|
|
line.long 0x00 "HCCHAR0,Host Channel-0 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes"
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
line.long 0x04 "HCSPLT0,Host Channel-0 Split Control Register"
|
|
bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested"
|
|
bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All"
|
|
newline
|
|
hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address"
|
|
hexmask.long.byte 0x04 0.--6. 0x01 " PRTADDR ,Port address"
|
|
line.long 0x08 "HCINT0,OTG_FH Host Channel-0 Interrupt Register"
|
|
eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 6. " NYET ,Not yet ready response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error"
|
|
eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x0C "HCINTMSK0,Host Channel-0 Interrupt Mask Register"
|
|
bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked"
|
|
bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x10 "HCTSIZ0,Host Channel-0 Transfer Size Register"
|
|
bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/MDATA"
|
|
hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
line.long 0x14 "HCDMA0,Host Channel-0 DMA Address Register"
|
|
group.long 0x520++0x17
|
|
line.long 0x00 "HCCHAR1,Host Channel-1 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes"
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
line.long 0x04 "HCSPLT1,Host Channel-1 Split Control Register"
|
|
bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested"
|
|
bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All"
|
|
newline
|
|
hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address"
|
|
hexmask.long.byte 0x04 0.--6. 0x01 " PRTADDR ,Port address"
|
|
line.long 0x08 "HCINT1,OTG_FH Host Channel-1 Interrupt Register"
|
|
eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 6. " NYET ,Not yet ready response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error"
|
|
eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x0C "HCINTMSK1,Host Channel-1 Interrupt Mask Register"
|
|
bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked"
|
|
bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x10 "HCTSIZ1,Host Channel-1 Transfer Size Register"
|
|
bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/MDATA"
|
|
hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
line.long 0x14 "HCDMA1,Host Channel-1 DMA Address Register"
|
|
group.long 0x540++0x17
|
|
line.long 0x00 "HCCHAR2,Host Channel-2 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes"
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
line.long 0x04 "HCSPLT2,Host Channel-2 Split Control Register"
|
|
bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested"
|
|
bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All"
|
|
newline
|
|
hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address"
|
|
hexmask.long.byte 0x04 0.--6. 0x01 " PRTADDR ,Port address"
|
|
line.long 0x08 "HCINT2,OTG_FH Host Channel-2 Interrupt Register"
|
|
eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 6. " NYET ,Not yet ready response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error"
|
|
eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x0C "HCINTMSK2,Host Channel-2 Interrupt Mask Register"
|
|
bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked"
|
|
bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x10 "HCTSIZ2,Host Channel-2 Transfer Size Register"
|
|
bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/MDATA"
|
|
hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
line.long 0x14 "HCDMA2,Host Channel-2 DMA Address Register"
|
|
group.long 0x560++0x17
|
|
line.long 0x00 "HCCHAR3,Host Channel-3 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes"
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
line.long 0x04 "HCSPLT3,Host Channel-3 Split Control Register"
|
|
bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested"
|
|
bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All"
|
|
newline
|
|
hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address"
|
|
hexmask.long.byte 0x04 0.--6. 0x01 " PRTADDR ,Port address"
|
|
line.long 0x08 "HCINT3,OTG_FH Host Channel-3 Interrupt Register"
|
|
eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 6. " NYET ,Not yet ready response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error"
|
|
eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x0C "HCINTMSK3,Host Channel-3 Interrupt Mask Register"
|
|
bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked"
|
|
bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x10 "HCTSIZ3,Host Channel-3 Transfer Size Register"
|
|
bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/MDATA"
|
|
hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
line.long 0x14 "HCDMA3,Host Channel-3 DMA Address Register"
|
|
group.long 0x580++0x17
|
|
line.long 0x00 "HCCHAR4,Host Channel-4 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes"
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
line.long 0x04 "HCSPLT4,Host Channel-4 Split Control Register"
|
|
bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested"
|
|
bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All"
|
|
newline
|
|
hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address"
|
|
hexmask.long.byte 0x04 0.--6. 0x01 " PRTADDR ,Port address"
|
|
line.long 0x08 "HCINT4,OTG_FH Host Channel-4 Interrupt Register"
|
|
eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 6. " NYET ,Not yet ready response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error"
|
|
eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x0C "HCINTMSK4,Host Channel-4 Interrupt Mask Register"
|
|
bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked"
|
|
bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x10 "HCTSIZ4,Host Channel-4 Transfer Size Register"
|
|
bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/MDATA"
|
|
hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
line.long 0x14 "HCDMA4,Host Channel-4 DMA Address Register"
|
|
group.long 0x5A0++0x17
|
|
line.long 0x00 "HCCHAR5,Host Channel-5 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes"
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
line.long 0x04 "HCSPLT5,Host Channel-5 Split Control Register"
|
|
bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested"
|
|
bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All"
|
|
newline
|
|
hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address"
|
|
hexmask.long.byte 0x04 0.--6. 0x01 " PRTADDR ,Port address"
|
|
line.long 0x08 "HCINT5,OTG_FH Host Channel-5 Interrupt Register"
|
|
eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 6. " NYET ,Not yet ready response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error"
|
|
eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x0C "HCINTMSK5,Host Channel-5 Interrupt Mask Register"
|
|
bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked"
|
|
bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x10 "HCTSIZ5,Host Channel-5 Transfer Size Register"
|
|
bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/MDATA"
|
|
hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
line.long 0x14 "HCDMA5,Host Channel-5 DMA Address Register"
|
|
group.long 0x5C0++0x17
|
|
line.long 0x00 "HCCHAR6,Host Channel-6 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes"
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
line.long 0x04 "HCSPLT6,Host Channel-6 Split Control Register"
|
|
bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested"
|
|
bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All"
|
|
newline
|
|
hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address"
|
|
hexmask.long.byte 0x04 0.--6. 0x01 " PRTADDR ,Port address"
|
|
line.long 0x08 "HCINT6,OTG_FH Host Channel-6 Interrupt Register"
|
|
eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 6. " NYET ,Not yet ready response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error"
|
|
eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x0C "HCINTMSK6,Host Channel-6 Interrupt Mask Register"
|
|
bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked"
|
|
bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x10 "HCTSIZ6,Host Channel-6 Transfer Size Register"
|
|
bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/MDATA"
|
|
hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
line.long 0x14 "HCDMA6,Host Channel-6 DMA Address Register"
|
|
group.long 0x5E0++0x17
|
|
line.long 0x00 "HCCHAR7,Host Channel-7 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes"
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
line.long 0x04 "HCSPLT7,Host Channel-7 Split Control Register"
|
|
bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested"
|
|
bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All"
|
|
newline
|
|
hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address"
|
|
hexmask.long.byte 0x04 0.--6. 0x01 " PRTADDR ,Port address"
|
|
line.long 0x08 "HCINT7,OTG_FH Host Channel-7 Interrupt Register"
|
|
eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 6. " NYET ,Not yet ready response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error"
|
|
eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x0C "HCINTMSK7,Host Channel-7 Interrupt Mask Register"
|
|
bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked"
|
|
bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x10 "HCTSIZ7,Host Channel-7 Transfer Size Register"
|
|
bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/MDATA"
|
|
hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
line.long 0x14 "HCDMA7,Host Channel-7 DMA Address Register"
|
|
group.long 0x600++0x17
|
|
line.long 0x00 "HCCHAR8,Host Channel-8 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes"
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
line.long 0x04 "HCSPLT8,Host Channel-8 Split Control Register"
|
|
bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested"
|
|
bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All"
|
|
newline
|
|
hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address"
|
|
hexmask.long.byte 0x04 0.--6. 0x01 " PRTADDR ,Port address"
|
|
line.long 0x08 "HCINT8,OTG_FH Host Channel-8 Interrupt Register"
|
|
eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 6. " NYET ,Not yet ready response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error"
|
|
eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x0C "HCINTMSK8,Host Channel-8 Interrupt Mask Register"
|
|
bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked"
|
|
bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x10 "HCTSIZ8,Host Channel-8 Transfer Size Register"
|
|
bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/MDATA"
|
|
hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
line.long 0x14 "HCDMA8,Host Channel-8 DMA Address Register"
|
|
group.long 0x620++0x17
|
|
line.long 0x00 "HCCHAR9,Host Channel-9 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes"
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
line.long 0x04 "HCSPLT9,Host Channel-9 Split Control Register"
|
|
bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested"
|
|
bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All"
|
|
newline
|
|
hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address"
|
|
hexmask.long.byte 0x04 0.--6. 0x01 " PRTADDR ,Port address"
|
|
line.long 0x08 "HCINT9,OTG_FH Host Channel-9 Interrupt Register"
|
|
eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 6. " NYET ,Not yet ready response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error"
|
|
eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x0C "HCINTMSK9,Host Channel-9 Interrupt Mask Register"
|
|
bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked"
|
|
bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x10 "HCTSIZ9,Host Channel-9 Transfer Size Register"
|
|
bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/MDATA"
|
|
hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
line.long 0x14 "HCDMA9,Host Channel-9 DMA Address Register"
|
|
group.long 0x640++0x17
|
|
line.long 0x00 "HCCHAR10,Host Channel-10 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes"
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
line.long 0x04 "HCSPLT10,Host Channel-10 Split Control Register"
|
|
bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested"
|
|
bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All"
|
|
newline
|
|
hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address"
|
|
hexmask.long.byte 0x04 0.--6. 0x01 " PRTADDR ,Port address"
|
|
line.long 0x08 "HCINT10,OTG_FH Host Channel-10 Interrupt Register"
|
|
eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 6. " NYET ,Not yet ready response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error"
|
|
eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x0C "HCINTMSK10,Host Channel-10 Interrupt Mask Register"
|
|
bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked"
|
|
bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x10 "HCTSIZ10,Host Channel-10 Transfer Size Register"
|
|
bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/MDATA"
|
|
hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
line.long 0x14 "HCDMA10,Host Channel-10 DMA Address Register"
|
|
group.long 0x660++0x17
|
|
line.long 0x00 "HCCHAR11,Host Channel-11 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes"
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
line.long 0x04 "HCSPLT11,Host Channel-11 Split Control Register"
|
|
bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested"
|
|
bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All"
|
|
newline
|
|
hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address"
|
|
hexmask.long.byte 0x04 0.--6. 0x01 " PRTADDR ,Port address"
|
|
line.long 0x08 "HCINT11,OTG_FH Host Channel-11 Interrupt Register"
|
|
eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 6. " NYET ,Not yet ready response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error"
|
|
eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x0C "HCINTMSK11,Host Channel-11 Interrupt Mask Register"
|
|
bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked"
|
|
bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x10 "HCTSIZ11,Host Channel-11 Transfer Size Register"
|
|
bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/MDATA"
|
|
hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
line.long 0x14 "HCDMA11,Host Channel-11 DMA Address Register"
|
|
group.long 0x680++0x17
|
|
line.long 0x00 "HCCHAR12,Host Channel-12 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes"
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
line.long 0x04 "HCSPLT12,Host Channel-12 Split Control Register"
|
|
bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested"
|
|
bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All"
|
|
newline
|
|
hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address"
|
|
hexmask.long.byte 0x04 0.--6. 0x01 " PRTADDR ,Port address"
|
|
line.long 0x08 "HCINT12,OTG_FH Host Channel-12 Interrupt Register"
|
|
eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 6. " NYET ,Not yet ready response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error"
|
|
eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x0C "HCINTMSK12,Host Channel-12 Interrupt Mask Register"
|
|
bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked"
|
|
bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x10 "HCTSIZ12,Host Channel-12 Transfer Size Register"
|
|
bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/MDATA"
|
|
hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
line.long 0x14 "HCDMA12,Host Channel-12 DMA Address Register"
|
|
group.long 0x6A0++0x17
|
|
line.long 0x00 "HCCHAR13,Host Channel-13 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes"
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
line.long 0x04 "HCSPLT13,Host Channel-13 Split Control Register"
|
|
bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested"
|
|
bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All"
|
|
newline
|
|
hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address"
|
|
hexmask.long.byte 0x04 0.--6. 0x01 " PRTADDR ,Port address"
|
|
line.long 0x08 "HCINT13,OTG_FH Host Channel-13 Interrupt Register"
|
|
eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 6. " NYET ,Not yet ready response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error"
|
|
eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x0C "HCINTMSK13,Host Channel-13 Interrupt Mask Register"
|
|
bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked"
|
|
bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x10 "HCTSIZ13,Host Channel-13 Transfer Size Register"
|
|
bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/MDATA"
|
|
hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
line.long 0x14 "HCDMA13,Host Channel-13 DMA Address Register"
|
|
group.long 0x6C0++0x17
|
|
line.long 0x00 "HCCHAR14,Host Channel-14 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes"
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
line.long 0x04 "HCSPLT14,Host Channel-14 Split Control Register"
|
|
bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested"
|
|
bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All"
|
|
newline
|
|
hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address"
|
|
hexmask.long.byte 0x04 0.--6. 0x01 " PRTADDR ,Port address"
|
|
line.long 0x08 "HCINT14,OTG_FH Host Channel-14 Interrupt Register"
|
|
eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 6. " NYET ,Not yet ready response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error"
|
|
eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x0C "HCINTMSK14,Host Channel-14 Interrupt Mask Register"
|
|
bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked"
|
|
bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x10 "HCTSIZ14,Host Channel-14 Transfer Size Register"
|
|
bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/MDATA"
|
|
hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
line.long 0x14 "HCDMA14,Host Channel-14 DMA Address Register"
|
|
group.long 0x6E0++0x17
|
|
line.long 0x00 "HCCHAR15,Host Channel-15 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes"
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
line.long 0x04 "HCSPLT15,Host Channel-15 Split Control Register"
|
|
bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested"
|
|
bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All"
|
|
newline
|
|
hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address"
|
|
hexmask.long.byte 0x04 0.--6. 0x01 " PRTADDR ,Port address"
|
|
line.long 0x08 "HCINT15,OTG_FH Host Channel-15 Interrupt Register"
|
|
eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 6. " NYET ,Not yet ready response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error"
|
|
eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x0C "HCINTMSK15,Host Channel-15 Interrupt Mask Register"
|
|
bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked"
|
|
bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x10 "HCTSIZ15,Host Channel-15 Transfer Size Register"
|
|
bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/MDATA"
|
|
hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
line.long 0x14 "HCDMA15,Host Channel-15 DMA Address Register"
|
|
else
|
|
hgroup.long 0x400++0x03
|
|
hide.long 0x00 "HCFG,Host Configuration Register"
|
|
hgroup.long 0x404++0x03
|
|
hide.long 0x00 "HFIR,Host Frame Interval Register"
|
|
hgroup.long 0x408++0x03
|
|
hide.long 0x00 "HFNUM,Host Frame Number/Frame Time Remaining Register"
|
|
hgroup.long 0x410++0x03
|
|
hide.long 0x00 "HPTXSTS,Host Periodic Transmit FIFO/Queue Status Register"
|
|
hgroup.long 0x414++0x03
|
|
hide.long 0x00 "HAINT,Host All Channels Interrupt Register"
|
|
hgroup.long 0x418++0x03
|
|
hide.long 0x00 "HAINTMSK,Host All Channels Interrupt Mask Register"
|
|
hgroup.long 0x440++0x03
|
|
hide.long 0x00 "HPRT,Host Port Control And Status Register"
|
|
hgroup.long 0x500++0x03
|
|
hide.long 0x00 "HCCHAR0,Host Channel-0 Characteristics Register"
|
|
hgroup.long (0x500+0x04)++0x03
|
|
hide.long 0x00 "HCSPLT0,Host Channel-0 Split Control Register"
|
|
hgroup.long (0x500+0x08)++0x03
|
|
hide.long 0x00 "HCINT0,Host Channel-0 Interrupt Register"
|
|
hgroup.long (0x500+0x0C)++0x03
|
|
hide.long 0x00 "HCINTMSK0,Host Channel-0 Interrupt Mask Register"
|
|
hgroup.long (0x500+0x10)++0x03
|
|
hide.long 0x00 "HCTSIZ0,Host Channel-0 Transfer Size Register"
|
|
hgroup.long (0x500+0x14)++0x03
|
|
hide.long 0x00 "HCDMA0,Host Channel-0 DMA Address Register"
|
|
hgroup.long 0x520++0x03
|
|
hide.long 0x00 "HCCHAR1,Host Channel-1 Characteristics Register"
|
|
hgroup.long (0x520+0x04)++0x03
|
|
hide.long 0x00 "HCSPLT1,Host Channel-1 Split Control Register"
|
|
hgroup.long (0x520+0x08)++0x03
|
|
hide.long 0x00 "HCINT1,Host Channel-1 Interrupt Register"
|
|
hgroup.long (0x520+0x0C)++0x03
|
|
hide.long 0x00 "HCINTMSK1,Host Channel-1 Interrupt Mask Register"
|
|
hgroup.long (0x520+0x10)++0x03
|
|
hide.long 0x00 "HCTSIZ1,Host Channel-1 Transfer Size Register"
|
|
hgroup.long (0x520+0x14)++0x03
|
|
hide.long 0x00 "HCDMA1,Host Channel-1 DMA Address Register"
|
|
hgroup.long 0x540++0x03
|
|
hide.long 0x00 "HCCHAR2,Host Channel-2 Characteristics Register"
|
|
hgroup.long (0x540+0x04)++0x03
|
|
hide.long 0x00 "HCSPLT2,Host Channel-2 Split Control Register"
|
|
hgroup.long (0x540+0x08)++0x03
|
|
hide.long 0x00 "HCINT2,Host Channel-2 Interrupt Register"
|
|
hgroup.long (0x540+0x0C)++0x03
|
|
hide.long 0x00 "HCINTMSK2,Host Channel-2 Interrupt Mask Register"
|
|
hgroup.long (0x540+0x10)++0x03
|
|
hide.long 0x00 "HCTSIZ2,Host Channel-2 Transfer Size Register"
|
|
hgroup.long (0x540+0x14)++0x03
|
|
hide.long 0x00 "HCDMA2,Host Channel-2 DMA Address Register"
|
|
hgroup.long 0x560++0x03
|
|
hide.long 0x00 "HCCHAR3,Host Channel-3 Characteristics Register"
|
|
hgroup.long (0x560+0x04)++0x03
|
|
hide.long 0x00 "HCSPLT3,Host Channel-3 Split Control Register"
|
|
hgroup.long (0x560+0x08)++0x03
|
|
hide.long 0x00 "HCINT3,Host Channel-3 Interrupt Register"
|
|
hgroup.long (0x560+0x0C)++0x03
|
|
hide.long 0x00 "HCINTMSK3,Host Channel-3 Interrupt Mask Register"
|
|
hgroup.long (0x560+0x10)++0x03
|
|
hide.long 0x00 "HCTSIZ3,Host Channel-3 Transfer Size Register"
|
|
hgroup.long (0x560+0x14)++0x03
|
|
hide.long 0x00 "HCDMA3,Host Channel-3 DMA Address Register"
|
|
hgroup.long 0x580++0x03
|
|
hide.long 0x00 "HCCHAR4,Host Channel-4 Characteristics Register"
|
|
hgroup.long (0x580+0x04)++0x03
|
|
hide.long 0x00 "HCSPLT4,Host Channel-4 Split Control Register"
|
|
hgroup.long (0x580+0x08)++0x03
|
|
hide.long 0x00 "HCINT4,Host Channel-4 Interrupt Register"
|
|
hgroup.long (0x580+0x0C)++0x03
|
|
hide.long 0x00 "HCINTMSK4,Host Channel-4 Interrupt Mask Register"
|
|
hgroup.long (0x580+0x10)++0x03
|
|
hide.long 0x00 "HCTSIZ4,Host Channel-4 Transfer Size Register"
|
|
hgroup.long (0x580+0x14)++0x03
|
|
hide.long 0x00 "HCDMA4,Host Channel-4 DMA Address Register"
|
|
hgroup.long 0x5A0++0x03
|
|
hide.long 0x00 "HCCHAR5,Host Channel-5 Characteristics Register"
|
|
hgroup.long (0x5A0+0x04)++0x03
|
|
hide.long 0x00 "HCSPLT5,Host Channel-5 Split Control Register"
|
|
hgroup.long (0x5A0+0x08)++0x03
|
|
hide.long 0x00 "HCINT5,Host Channel-5 Interrupt Register"
|
|
hgroup.long (0x5A0+0x0C)++0x03
|
|
hide.long 0x00 "HCINTMSK5,Host Channel-5 Interrupt Mask Register"
|
|
hgroup.long (0x5A0+0x10)++0x03
|
|
hide.long 0x00 "HCTSIZ5,Host Channel-5 Transfer Size Register"
|
|
hgroup.long (0x5A0+0x14)++0x03
|
|
hide.long 0x00 "HCDMA5,Host Channel-5 DMA Address Register"
|
|
hgroup.long 0x5C0++0x03
|
|
hide.long 0x00 "HCCHAR6,Host Channel-6 Characteristics Register"
|
|
hgroup.long (0x5C0+0x04)++0x03
|
|
hide.long 0x00 "HCSPLT6,Host Channel-6 Split Control Register"
|
|
hgroup.long (0x5C0+0x08)++0x03
|
|
hide.long 0x00 "HCINT6,Host Channel-6 Interrupt Register"
|
|
hgroup.long (0x5C0+0x0C)++0x03
|
|
hide.long 0x00 "HCINTMSK6,Host Channel-6 Interrupt Mask Register"
|
|
hgroup.long (0x5C0+0x10)++0x03
|
|
hide.long 0x00 "HCTSIZ6,Host Channel-6 Transfer Size Register"
|
|
hgroup.long (0x5C0+0x14)++0x03
|
|
hide.long 0x00 "HCDMA6,Host Channel-6 DMA Address Register"
|
|
hgroup.long 0x5E0++0x03
|
|
hide.long 0x00 "HCCHAR7,Host Channel-7 Characteristics Register"
|
|
hgroup.long (0x5E0+0x04)++0x03
|
|
hide.long 0x00 "HCSPLT7,Host Channel-7 Split Control Register"
|
|
hgroup.long (0x5E0+0x08)++0x03
|
|
hide.long 0x00 "HCINT7,Host Channel-7 Interrupt Register"
|
|
hgroup.long (0x5E0+0x0C)++0x03
|
|
hide.long 0x00 "HCINTMSK7,Host Channel-7 Interrupt Mask Register"
|
|
hgroup.long (0x5E0+0x10)++0x03
|
|
hide.long 0x00 "HCTSIZ7,Host Channel-7 Transfer Size Register"
|
|
hgroup.long (0x5E0+0x14)++0x03
|
|
hide.long 0x00 "HCDMA7,Host Channel-7 DMA Address Register"
|
|
hgroup.long 0x600++0x03
|
|
hide.long 0x00 "HCCHAR8,Host Channel-8 Characteristics Register"
|
|
hgroup.long (0x600+0x04)++0x03
|
|
hide.long 0x00 "HCSPLT8,Host Channel-8 Split Control Register"
|
|
hgroup.long (0x600+0x08)++0x03
|
|
hide.long 0x00 "HCINT8,Host Channel-8 Interrupt Register"
|
|
hgroup.long (0x600+0x0C)++0x03
|
|
hide.long 0x00 "HCINTMSK8,Host Channel-8 Interrupt Mask Register"
|
|
hgroup.long (0x600+0x10)++0x03
|
|
hide.long 0x00 "HCTSIZ8,Host Channel-8 Transfer Size Register"
|
|
hgroup.long (0x600+0x14)++0x03
|
|
hide.long 0x00 "HCDMA8,Host Channel-8 DMA Address Register"
|
|
hgroup.long 0x620++0x03
|
|
hide.long 0x00 "HCCHAR9,Host Channel-9 Characteristics Register"
|
|
hgroup.long (0x620+0x04)++0x03
|
|
hide.long 0x00 "HCSPLT9,Host Channel-9 Split Control Register"
|
|
hgroup.long (0x620+0x08)++0x03
|
|
hide.long 0x00 "HCINT9,Host Channel-9 Interrupt Register"
|
|
hgroup.long (0x620+0x0C)++0x03
|
|
hide.long 0x00 "HCINTMSK9,Host Channel-9 Interrupt Mask Register"
|
|
hgroup.long (0x620+0x10)++0x03
|
|
hide.long 0x00 "HCTSIZ9,Host Channel-9 Transfer Size Register"
|
|
hgroup.long (0x620+0x14)++0x03
|
|
hide.long 0x00 "HCDMA9,Host Channel-9 DMA Address Register"
|
|
hgroup.long 0x640++0x03
|
|
hide.long 0x00 "HCCHAR10,Host Channel-10 Characteristics Register"
|
|
hgroup.long (0x640+0x04)++0x03
|
|
hide.long 0x00 "HCSPLT10,Host Channel-10 Split Control Register"
|
|
hgroup.long (0x640+0x08)++0x03
|
|
hide.long 0x00 "HCINT10,Host Channel-10 Interrupt Register"
|
|
hgroup.long (0x640+0x0C)++0x03
|
|
hide.long 0x00 "HCINTMSK10,Host Channel-10 Interrupt Mask Register"
|
|
hgroup.long (0x640+0x10)++0x03
|
|
hide.long 0x00 "HCTSIZ10,Host Channel-10 Transfer Size Register"
|
|
hgroup.long (0x640+0x14)++0x03
|
|
hide.long 0x00 "HCDMA10,Host Channel-10 DMA Address Register"
|
|
hgroup.long 0x660++0x03
|
|
hide.long 0x00 "HCCHAR11,Host Channel-11 Characteristics Register"
|
|
hgroup.long (0x660+0x04)++0x03
|
|
hide.long 0x00 "HCSPLT11,Host Channel-11 Split Control Register"
|
|
hgroup.long (0x660+0x08)++0x03
|
|
hide.long 0x00 "HCINT11,Host Channel-11 Interrupt Register"
|
|
hgroup.long (0x660+0x0C)++0x03
|
|
hide.long 0x00 "HCINTMSK11,Host Channel-11 Interrupt Mask Register"
|
|
hgroup.long (0x660+0x10)++0x03
|
|
hide.long 0x00 "HCTSIZ11,Host Channel-11 Transfer Size Register"
|
|
hgroup.long (0x660+0x14)++0x03
|
|
hide.long 0x00 "HCDMA11,Host Channel-11 DMA Address Register"
|
|
hgroup.long 0x680++0x03
|
|
hide.long 0x00 "HCCHAR12,Host Channel-12 Characteristics Register"
|
|
hgroup.long (0x680+0x04)++0x03
|
|
hide.long 0x00 "HCSPLT12,Host Channel-12 Split Control Register"
|
|
hgroup.long (0x680+0x08)++0x03
|
|
hide.long 0x00 "HCINT12,Host Channel-12 Interrupt Register"
|
|
hgroup.long (0x680+0x0C)++0x03
|
|
hide.long 0x00 "HCINTMSK12,Host Channel-12 Interrupt Mask Register"
|
|
hgroup.long (0x680+0x10)++0x03
|
|
hide.long 0x00 "HCTSIZ12,Host Channel-12 Transfer Size Register"
|
|
hgroup.long (0x680+0x14)++0x03
|
|
hide.long 0x00 "HCDMA12,Host Channel-12 DMA Address Register"
|
|
hgroup.long 0x6A0++0x03
|
|
hide.long 0x00 "HCCHAR13,Host Channel-13 Characteristics Register"
|
|
hgroup.long (0x6A0+0x04)++0x03
|
|
hide.long 0x00 "HCSPLT13,Host Channel-13 Split Control Register"
|
|
hgroup.long (0x6A0+0x08)++0x03
|
|
hide.long 0x00 "HCINT13,Host Channel-13 Interrupt Register"
|
|
hgroup.long (0x6A0+0x0C)++0x03
|
|
hide.long 0x00 "HCINTMSK13,Host Channel-13 Interrupt Mask Register"
|
|
hgroup.long (0x6A0+0x10)++0x03
|
|
hide.long 0x00 "HCTSIZ13,Host Channel-13 Transfer Size Register"
|
|
hgroup.long (0x6A0+0x14)++0x03
|
|
hide.long 0x00 "HCDMA13,Host Channel-13 DMA Address Register"
|
|
hgroup.long 0x6C0++0x03
|
|
hide.long 0x00 "HCCHAR14,Host Channel-14 Characteristics Register"
|
|
hgroup.long (0x6C0+0x04)++0x03
|
|
hide.long 0x00 "HCSPLT14,Host Channel-14 Split Control Register"
|
|
hgroup.long (0x6C0+0x08)++0x03
|
|
hide.long 0x00 "HCINT14,Host Channel-14 Interrupt Register"
|
|
hgroup.long (0x6C0+0x0C)++0x03
|
|
hide.long 0x00 "HCINTMSK14,Host Channel-14 Interrupt Mask Register"
|
|
hgroup.long (0x6C0+0x10)++0x03
|
|
hide.long 0x00 "HCTSIZ14,Host Channel-14 Transfer Size Register"
|
|
hgroup.long (0x6C0+0x14)++0x03
|
|
hide.long 0x00 "HCDMA14,Host Channel-14 DMA Address Register"
|
|
hgroup.long 0x6E0++0x03
|
|
hide.long 0x00 "HCCHAR15,Host Channel-15 Characteristics Register"
|
|
hgroup.long (0x6E0+0x04)++0x03
|
|
hide.long 0x00 "HCSPLT15,Host Channel-15 Split Control Register"
|
|
hgroup.long (0x6E0+0x08)++0x03
|
|
hide.long 0x00 "HCINT15,Host Channel-15 Interrupt Register"
|
|
hgroup.long (0x6E0+0x0C)++0x03
|
|
hide.long 0x00 "HCINTMSK15,Host Channel-15 Interrupt Mask Register"
|
|
hgroup.long (0x6E0+0x10)++0x03
|
|
hide.long 0x00 "HCTSIZ15,Host Channel-15 Transfer Size Register"
|
|
hgroup.long (0x6E0+0x14)++0x03
|
|
hide.long 0x00 "HCDMA15,Host Channel-15 DMA Address Register"
|
|
endif
|
|
tree.end
|
|
tree "Device mode registers"
|
|
if (((per.l((ad:0x40040000+0x014)))&0x01)==0x00)
|
|
group.long 0x800++0x07
|
|
line.long 0x00 "DCFG,Device Configuration Register"
|
|
bitfld.long 0x00 24.--25. " PERSCHIVL ,Periodic scheduling interval" "25%,50%,75%,?..."
|
|
bitfld.long 0x00 15. " ERRATIM ,Erratic error interrupt mask" "Generated,Mask"
|
|
newline
|
|
sif (cpuis("STM32F7*"))
|
|
bitfld.long 0x00 14. " XCVRDLY ,Transceiver delay" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11.--12. " PFIVL ,Periodic frame interval" "80%,85%,90%,95%"
|
|
hexmask.long.byte 0x00 4.--10. 0x10 " DAD ,Device address"
|
|
newline
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
bitfld.long 0x00 2. " NZLSOHSK ,Non-zero-length status OUT handshake" "NAK and STALL,STALL"
|
|
bitfld.long 0x00 0.--1. " DSPD ,Device speed" "High speed,Full speed HS,,Full speed FS PHY"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 2. " NZLSOHSK ,Non-zero-length status OUT handshake" "STALL,NAK and STALL"
|
|
bitfld.long 0x00 0.--1. " DSPD ,Device speed" "High,Full external,,Full internal"
|
|
newline
|
|
endif
|
|
line.long 0x04 "DCTL,Device Control Register"
|
|
bitfld.long 0x04 18. " DSBESLRJCT ,Deep sleep BESL reject" "Not rejected,Rejected"
|
|
bitfld.long 0x04 11. " POPRGDNE ,Power-on programming done" "Not done,Done"
|
|
bitfld.long 0x04 4.--6. " TCTL ,Test control" "Disabled,J mode,K mode,SE0_NAK mode,Packet mode,Force_Enable,?..."
|
|
newline
|
|
setclrfld.long 0x04 3. 0x04 9. 0x04 10. " GON_SET/CLR ,Global OUT NAK status" "Sent to specific,Sent to all"
|
|
setclrfld.long 0x04 2. 0x04 7. 0x04 8. " GIN_SET/CLR ,Global IN NAK status" "Sent to specific,Sent to all"
|
|
newline
|
|
bitfld.long 0x04 1. " SDIS ,Soft disconnect" "No effect,Disconnect"
|
|
bitfld.long 0x04 0. " RWUSIG ,Remote wakeup signaling" "No effect,Wakeup"
|
|
newline
|
|
rgroup.long 0x808++0x03
|
|
line.long 0x00 "DSTS,Device Status Register"
|
|
bitfld.long 0x00 23. " DEVLNSTS_D+ ,Device line status logic level of D+" "Low,High"
|
|
bitfld.long 0x00 22. " DEVLNSTS_D- ,Device line status logic level of D-" "Low,High"
|
|
hexmask.long.word 0x00 8.--21. 1. " FNSOF ,Frame number of the received SOF"
|
|
bitfld.long 0x00 3. " EERR ,Erratic error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ENUMSPD ,Enumerated speed" ",,,Full"
|
|
bitfld.long 0x00 0. " SUSPSTS ,Suspend status" "Not suspended,Suspended"
|
|
group.long 0x810++0x07
|
|
line.long 0x00 "DIEPMSK,Device IN Endpoint Common Interrupt Mask Register"
|
|
bitfld.long 0x00 13. " NAKM ,NAK interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
sif (!cpuis("STM32F7*"))
|
|
bitfld.long 0x00 9. " BIM ,BNA interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 8. " TXFURM ,FIFO underrun mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 6. " INEPNEM ,IN endpoint NAK effective mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x00 5. " INEPNMM ,IN token received with EP mismatch mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 4. " ITTXFEMSK ,IN token received when TxFIFO empty mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 3. " TOM ,Timeout condition mask" "Masked,Unmasked"
|
|
newline
|
|
sif (cpuis("STM32F7*"))
|
|
bitfld.long 0x00 2. " AHBERRM ,AHB error mask for USB OTG HS" "Masked,Unmasked"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " EPDM ,Endpoint disabled interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 0. " XFRCM ,Transfer completed interrupt mask" "Masked,Unmasked"
|
|
line.long 0x04 "DOEPMSK,Device OUT Endpoint Common Interrupt Mask Register"
|
|
bitfld.long 0x04 14. " NYETMSK ,NYET interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
sif (cpuis("STM32F7*"))
|
|
bitfld.long 0x04 13. " NAKMSK ,NAK interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 12. " BERRM ,Babble error interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
endif
|
|
sif !cpuis("STM32F7*")
|
|
bitfld.long 0x04 9. " BOIM ,BNA interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 8. " TXFURM ,FIFO underrun mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 6. " B2BSTUP ,Back-to-back SETUP packets received mask" "Masked,Unmasked"
|
|
newline
|
|
sif (cpuis("STM32F7*"))
|
|
bitfld.long 0x04 5. " STSPHSRXM ,Status phase received for control write mask" "Masked,Unmasked"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 4. " OTEPDM ,OUT token received when endpoint disabled mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 3. " STUPM ,SETUP phase done mask" "Masked,Unmasked"
|
|
newline
|
|
sif (cpuis("STM32F7*"))
|
|
bitfld.long 0x04 2. " AHBERRM ,AHB error mask for USB OTG HS" "Masked,Unmasked"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 1. " EPDM ,Endpoint disabled interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 0. " XFRCM ,Transfer completed interrupt mask" "Masked,Unmasked"
|
|
rgroup.long 0x818++0x03
|
|
line.long 0x00 "DAINT,Device All Endpoints Interrupt Register"
|
|
sif !cpuis("STM32F7*")
|
|
bitfld.long 0x00 31. " OEPINT_[15] ,OUT endpoint interrupt bit 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " [14] ,OUT endpoint interrupt bit 14" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " [13] ,OUT endpoint interrupt bit 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " [12] ,OUT endpoint interrupt bit 12" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 27. " [11] ,OUT endpoint interrupt bit 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " [10] ,OUT endpoint interrupt bit 10" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " [9] ,OUT endpoint interrupt bit 9" "No interrupt,Interrupt"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 24. " OEPINT_[8] ,OUT endpoint interrupt bit 8" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 23. " [7] ,OUT endpoint interrupt bit 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " [6] ,OUT endpoint interrupt bit 6" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " [5] ,OUT endpoint interrupt bit 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " [4] ,OUT endpoint interrupt bit 4" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 19. " [3] ,OUT endpoint interrupt bit 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " [2] ,OUT endpoint interrupt bit 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " [1] ,OUT endpoint interrupt bit 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " [0] ,OUT endpoint interrupt bit 0" "No interrupt,Interrupt"
|
|
newline
|
|
sif (!cpuis("STM32F7*"))
|
|
bitfld.long 0x00 15. " IEPINT_[15] ,IN endpoint interrupt bit 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " [14] ,IN endpoint interrupt bit 14" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " [13] ,IN endpoint interrupt bit 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " [12] ,IN endpoint interrupt bit 12" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,IN endpoint interrupt bit 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " [10] ,IN endpoint interrupt bit 10" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " [9] ,IN endpoint interrupt bit 9" "No interrupt,Interrupt"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 8. " IEPINT_[8] ,IN endpoint interrupt bit 8" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,IN endpoint interrupt bit 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " [6] ,IN endpoint interrupt bit 6" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " [5] ,IN endpoint interrupt bit 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " [4] ,IN endpoint interrupt bit 4" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,IN endpoint interrupt bit 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " [2] ,IN endpoint interrupt bit 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " [1] ,IN endpoint interrupt bit 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " [0] ,IN endpoint interrupt bit 0" "No interrupt,Interrupt"
|
|
newline
|
|
group.long 0x81C++0x03
|
|
line.long 0x00 "DAINTMSK,All Endpoints Interrupt Mask Register"
|
|
sif !cpuis("STM32F7*")
|
|
bitfld.long 0x00 31. " OEPM_[15] ,OUT EP interrupt mask bit 15" "Masked,Unmasked"
|
|
bitfld.long 0x00 30. " [14] ,OUT EP interrupt mask bit 14" "Masked,Unmasked"
|
|
bitfld.long 0x00 29. " [13] ,OUT EP interrupt mask bit 13" "Masked,Unmasked"
|
|
bitfld.long 0x00 28. " [12] ,OUT EP interrupt mask bit 12" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x00 27. " [11] ,OUT EP interrupt mask bit 11" "Masked,Unmasked"
|
|
bitfld.long 0x00 26. " [10] ,OUT EP interrupt mask bit 10" "Masked,Unmasked"
|
|
bitfld.long 0x00 25. " [9] ,OUT EP interrupt mask bit 9" "Masked,Unmasked"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 24. " OEPM_[8] ,OUT EP interrupt mask bit 8" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x00 23. " [7] ,OUT EP interrupt mask bit 7" "Masked,Unmasked"
|
|
bitfld.long 0x00 22. " [6] ,OUT EP interrupt mask bit 6" "Masked,Unmasked"
|
|
bitfld.long 0x00 21. " [5] ,OUT EP interrupt mask bit 5" "Masked,Unmasked"
|
|
bitfld.long 0x00 20. " [4] ,OUT EP interrupt mask bit 4" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x00 19. " [3] ,OUT EP interrupt mask bit 3" "Masked,Unmasked"
|
|
bitfld.long 0x00 18. " [2] ,OUT EP interrupt mask bit 2" "Masked,Unmasked"
|
|
bitfld.long 0x00 17. " [1] ,OUT EP interrupt mask bit 1" "Masked,Unmasked"
|
|
bitfld.long 0x00 16. " [0] ,OUT EP interrupt mask bit 0" "Masked,Unmasked"
|
|
newline
|
|
sif !cpuis("STM32F7*")
|
|
bitfld.long 0x00 15. " IEPM_[15] ,IN EP interrupt mask bit 15" "Masked,Unmasked"
|
|
bitfld.long 0x00 14. " [14] ,IN EP interrupt mask bit 14" "Masked,Unmasked"
|
|
bitfld.long 0x00 13. " [13] ,IN EP interrupt mask bit 13" "Masked,Unmasked"
|
|
bitfld.long 0x00 12. " [12] ,IN EP interrupt mask bit 12" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,IN EP interrupt mask bit 11" "Masked,Unmasked"
|
|
bitfld.long 0x00 10. " [10] ,IN EP interrupt mask bit 10" "Masked,Unmasked"
|
|
bitfld.long 0x00 9. " [9] ,IN EP interrupt mask bit 9" "Masked,Unmasked"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 8. " IEPM_[8] ,IN EP interrupt mask bit 8" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,IN EP interrupt mask bit 7" "Masked,Unmasked"
|
|
bitfld.long 0x00 6. " [6] ,IN EP interrupt mask bit 6" "Masked,Unmasked"
|
|
bitfld.long 0x00 5. " [5] ,IN EP interrupt mask bit 5" "Masked,Unmasked"
|
|
bitfld.long 0x00 4. " [4] ,IN EP interrupt mask bit 4" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,IN EP interrupt mask bit 3" "Masked,Unmasked"
|
|
bitfld.long 0x00 2. " [2] ,IN EP interrupt mask bit 2" "Masked,Unmasked"
|
|
bitfld.long 0x00 1. " [1] ,IN EP interrupt mask bit 1" "Masked,Unmasked"
|
|
bitfld.long 0x00 0. " [0] ,IN EP interrupt mask bit 0" "Masked,Unmasked"
|
|
group.long 0x828++0x0F
|
|
line.long 0x00 "DVBUSDIS,Device VBUS Discharge Time Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VBUSDT ,Device VBUS discharge time"
|
|
line.long 0x04 "DVBUSPULSE,Device VBUS Pulsing Time Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " DVBUSP ,Device VBUS pulsing time"
|
|
line.long 0x08 "DTHRCTL,Device Threshold Control Register"
|
|
bitfld.long 0x08 27. " ARPEN ,Arbiter parking enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x08 17.--25. 1. " RXTHRLEN ,Receive threshold length"
|
|
bitfld.long 0x08 16. " RXTHREN ,Receive threshold enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x08 2.--10. 1. " TXTHRLEN ,Transmit threshold length"
|
|
newline
|
|
bitfld.long 0x08 1. " ISOTHREN ,Isochronous IN endpoint threshold enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " NONISOTHREN ,Nonisochronous IN endpoints threshold enable" "Disabled,Enabled"
|
|
line.long 0x0C "DIEPEMPMSK,Device IN Endpoint FIFO Empty Interrupt Mask Register"
|
|
sif !cpuis("STM32F7*")
|
|
bitfld.long 0x0C 15. " INEPTXFEM_[15] ,IN EP Tx FIFO empty interrupt mask bit 15" "Masked,Unmasked"
|
|
bitfld.long 0x0C 14. " [14] ,IN EP Tx FIFO empty interrupt mask bit 14" "Masked,Unmasked"
|
|
bitfld.long 0x0C 13. " [13] ,IN EP Tx FIFO empty interrupt mask bit 13" "Masked,Unmasked"
|
|
bitfld.long 0x0C 12. " [12] ,IN EP Tx FIFO empty interrupt mask bit 12" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x0C 11. " [11] ,IN EP Tx FIFO empty interrupt mask bit 11" "Masked,Unmasked"
|
|
bitfld.long 0x0C 10. " [10] ,IN EP Tx FIFO empty interrupt mask bit 10" "Masked,Unmasked"
|
|
bitfld.long 0x0C 9. " [9] ,IN EP Tx FIFO empty interrupt mask bit 9" "Masked,Unmasked"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0C 8. " INEPTXFEM_[8] ,IN EP Tx FIFO empty interrupt mask bit 8" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x0C 7. " [7] ,IN EP Tx FIFO empty interrupt mask bit 7" "Masked,Unmasked"
|
|
bitfld.long 0x0C 6. " [6] ,IN EP Tx FIFO empty interrupt mask bit 6" "Masked,Unmasked"
|
|
bitfld.long 0x0C 5. " [5] ,IN EP Tx FIFO empty interrupt mask bit 5" "Masked,Unmasked"
|
|
bitfld.long 0x0C 4. " [4] ,IN EP Tx FIFO empty interrupt mask bit 4" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x0C 3. " [3] ,IN EP Tx FIFO empty interrupt mask bit 3" "Masked,Unmasked"
|
|
bitfld.long 0x0C 2. " [2] ,IN EP Tx FIFO empty interrupt mask bit 2" "Masked,Unmasked"
|
|
bitfld.long 0x0C 1. " [1] ,IN EP Tx FIFO empty interrupt mask bit 1" "Masked,Unmasked"
|
|
bitfld.long 0x0C 0. " [0] ,IN EP Tx FIFO empty interrupt mask bit 0" "Masked,Unmasked"
|
|
rgroup.long 0x838++0x03
|
|
line.long 0x00 "DEACHINT,Device Each Endpoint Interrupt Register"
|
|
bitfld.long 0x00 17. " OEP1INT ,OUT endpoint 1 interrupt bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " IEP1INT ,IN endpoint 1 interrupt bit" "No interrupt,Interrupt"
|
|
group.long 0x83C++0x03
|
|
line.long 0x00 "DEACHINTMSK,OTG Device Each Endpoint Interrupt Register Mask"
|
|
bitfld.long 0x00 17. " OEP1INTM ,OUT endpoint 1 interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 1. " IEP1INTM ,IN endpoint 1 interrupt mask" "Masked,Unmasked"
|
|
group.long 0x844++0x03
|
|
line.long 0x00 "DIEPEACHMSK1,OTG Device Each In Endpoint-1 Interrupt Mask Register"
|
|
bitfld.long 0x00 13. " NAKM ,NAK interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 8. " TXFURM ,FIFO underrun mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 6. " INEPNEM ,IN endpoint NAK effective mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 4. " ITTXFEMSK ,IN token received when Tx FIFO empty mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x00 3. " TOM ,Timeout condition mask (Non-isochronous endpoints)" "Masked,Unmasked"
|
|
bitfld.long 0x00 2. " AHBERRM ,AHB error mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 1. " EPDM ,Endpoint disabled interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 0. " XFRCM ,Transfer completed interrupt mask" "Masked,Unmasked"
|
|
group.long 0x884++0x03
|
|
line.long 0x00 "DOEPEACHMSK1,Otg Device Each Out Endpoint-1 Interrupt Mask Register"
|
|
bitfld.long 0x00 14. " NYETMSK ,NYET interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 13. " NAKMSK ,NAK interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 12. " BERRM ,Babble error interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 8. " OUTPKTERRM ,Out packet error mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x00 6. " B2BSTUPM ,Back-to-back SETUP packets received mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 4. " OTEPDM ,OUT token received when endpoint disabled mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 3. " STUPM ,STUPM: SETUP phase done mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 2. " AHBERRM ,AHB error mask" "Masked,Unmasked"
|
|
newline
|
|
bitfld.long 0x00 1. " EPDM ,Endpoint disabled interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 0. " XFRCM ,Transfer completed interrupt mask" "Masked,Unmasked"
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40040000+0x920))&0xC0000)==0x40000)
|
|
group.long 0x920++0x03
|
|
line.long 0x00 "DIEPCTL1,OTG Device Endpoint-1 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0x920))&0xC0000)==0x80000)
|
|
group.long 0x920++0x03
|
|
line.long 0x00 "DIEPCTL1,OTG Device Endpoint-1 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
newline
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0x920))&0xC0000)==0xC0000)
|
|
group.long 0x920++0x03
|
|
line.long 0x00 "DIEPCTL1,OTG Device Endpoint-1 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
newline
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0x920++0x03
|
|
line.long 0x00 "DIEPCTL1,OTG Device Endpoint-1 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x40040000+0x940))&0xC0000)==0x40000)
|
|
group.long 0x940++0x03
|
|
line.long 0x00 "DIEPCTL2,OTG Device Endpoint-2 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0x940))&0xC0000)==0x80000)
|
|
group.long 0x940++0x03
|
|
line.long 0x00 "DIEPCTL2,OTG Device Endpoint-2 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
newline
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0x940))&0xC0000)==0xC0000)
|
|
group.long 0x940++0x03
|
|
line.long 0x00 "DIEPCTL2,OTG Device Endpoint-2 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
newline
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0x940++0x03
|
|
line.long 0x00 "DIEPCTL2,OTG Device Endpoint-2 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x40040000+0x960))&0xC0000)==0x40000)
|
|
group.long 0x960++0x03
|
|
line.long 0x00 "DIEPCTL3,OTG Device Endpoint-3 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0x960))&0xC0000)==0x80000)
|
|
group.long 0x960++0x03
|
|
line.long 0x00 "DIEPCTL3,OTG Device Endpoint-3 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
newline
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0x960))&0xC0000)==0xC0000)
|
|
group.long 0x960++0x03
|
|
line.long 0x00 "DIEPCTL3,OTG Device Endpoint-3 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
newline
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0x960++0x03
|
|
line.long 0x00 "DIEPCTL3,OTG Device Endpoint-3 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x40040000+0x980))&0xC0000)==0x40000)
|
|
group.long 0x980++0x03
|
|
line.long 0x00 "DIEPCTL4,OTG Device Endpoint-4 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0x980))&0xC0000)==0x80000)
|
|
group.long 0x980++0x03
|
|
line.long 0x00 "DIEPCTL4,OTG Device Endpoint-4 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
newline
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0x980))&0xC0000)==0xC0000)
|
|
group.long 0x980++0x03
|
|
line.long 0x00 "DIEPCTL4,OTG Device Endpoint-4 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
newline
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0x980++0x03
|
|
line.long 0x00 "DIEPCTL4,OTG Device Endpoint-4 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x40040000+0x9A0))&0xC0000)==0x40000)
|
|
group.long 0x9A0++0x03
|
|
line.long 0x00 "DIEPCTL5,OTG Device Endpoint-5 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0x9A0))&0xC0000)==0x80000)
|
|
group.long 0x9A0++0x03
|
|
line.long 0x00 "DIEPCTL5,OTG Device Endpoint-5 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
newline
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0x9A0))&0xC0000)==0xC0000)
|
|
group.long 0x9A0++0x03
|
|
line.long 0x00 "DIEPCTL5,OTG Device Endpoint-5 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
newline
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0x9A0++0x03
|
|
line.long 0x00 "DIEPCTL5,OTG Device Endpoint-5 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x40040000+0x9C0))&0xC0000)==0x40000)
|
|
group.long 0x9C0++0x03
|
|
line.long 0x00 "DIEPCTL6,OTG Device Endpoint-6 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0x9C0))&0xC0000)==0x80000)
|
|
group.long 0x9C0++0x03
|
|
line.long 0x00 "DIEPCTL6,OTG Device Endpoint-6 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
newline
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0x9C0))&0xC0000)==0xC0000)
|
|
group.long 0x9C0++0x03
|
|
line.long 0x00 "DIEPCTL6,OTG Device Endpoint-6 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
newline
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0x9C0++0x03
|
|
line.long 0x00 "DIEPCTL6,OTG Device Endpoint-6 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x40040000+0x9E0))&0xC0000)==0x40000)
|
|
group.long 0x9E0++0x03
|
|
line.long 0x00 "DIEPCTL7,OTG Device Endpoint-7 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0x9E0))&0xC0000)==0x80000)
|
|
group.long 0x9E0++0x03
|
|
line.long 0x00 "DIEPCTL7,OTG Device Endpoint-7 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
newline
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0x9E0))&0xC0000)==0xC0000)
|
|
group.long 0x9E0++0x03
|
|
line.long 0x00 "DIEPCTL7,OTG Device Endpoint-7 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
newline
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0x9E0++0x03
|
|
line.long 0x00 "DIEPCTL7,OTG Device Endpoint-7 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x40040000+0xA00))&0xC0000)==0x40000)
|
|
group.long 0xA00++0x03
|
|
line.long 0x00 "DIEPCTL8,OTG Device Endpoint-8 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0xA00))&0xC0000)==0x80000)
|
|
group.long 0xA00++0x03
|
|
line.long 0x00 "DIEPCTL8,OTG Device Endpoint-8 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
newline
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0xA00))&0xC0000)==0xC0000)
|
|
group.long 0xA00++0x03
|
|
line.long 0x00 "DIEPCTL8,OTG Device Endpoint-8 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
newline
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0xA00++0x03
|
|
line.long 0x00 "DIEPCTL8,OTG Device Endpoint-8 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40040000+0x900))&0xC0000)==0x40000)
|
|
group.long 0x900++0x03
|
|
line.long 0x00 "DIEPCTL0,OTG Device Endpoint-0 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0x900))&0xC0000)==0x80000)
|
|
group.long 0x900++0x03
|
|
line.long 0x00 "DIEPCTL0,OTG Device Endpoint-0 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0x900))&0xC0000)==0xC0000)
|
|
group.long 0x900++0x03
|
|
line.long 0x00 "DIEPCTL0,OTG Device Endpoint-0 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0x900++0x03
|
|
line.long 0x00 "DIEPCTL0,OTG Device Endpoint-0 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x40040000+0x920))&0xC0000)==0x40000)
|
|
group.long 0x920++0x03
|
|
line.long 0x00 "DIEPCTL1,OTG Device Endpoint-1 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0x920))&0xC0000)==0x80000)
|
|
group.long 0x920++0x03
|
|
line.long 0x00 "DIEPCTL1,OTG Device Endpoint-1 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0x920))&0xC0000)==0xC0000)
|
|
group.long 0x920++0x03
|
|
line.long 0x00 "DIEPCTL1,OTG Device Endpoint-1 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0x920++0x03
|
|
line.long 0x00 "DIEPCTL1,OTG Device Endpoint-1 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x40040000+0x940))&0xC0000)==0x40000)
|
|
group.long 0x940++0x03
|
|
line.long 0x00 "DIEPCTL2,OTG Device Endpoint-2 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0x940))&0xC0000)==0x80000)
|
|
group.long 0x940++0x03
|
|
line.long 0x00 "DIEPCTL2,OTG Device Endpoint-2 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0x940))&0xC0000)==0xC0000)
|
|
group.long 0x940++0x03
|
|
line.long 0x00 "DIEPCTL2,OTG Device Endpoint-2 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0x940++0x03
|
|
line.long 0x00 "DIEPCTL2,OTG Device Endpoint-2 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x40040000+0x960))&0xC0000)==0x40000)
|
|
group.long 0x960++0x03
|
|
line.long 0x00 "DIEPCTL3,OTG Device Endpoint-3 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0x960))&0xC0000)==0x80000)
|
|
group.long 0x960++0x03
|
|
line.long 0x00 "DIEPCTL3,OTG Device Endpoint-3 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0x960))&0xC0000)==0xC0000)
|
|
group.long 0x960++0x03
|
|
line.long 0x00 "DIEPCTL3,OTG Device Endpoint-3 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0x960++0x03
|
|
line.long 0x00 "DIEPCTL3,OTG Device Endpoint-3 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x40040000+0x980))&0xC0000)==0x40000)
|
|
group.long 0x980++0x03
|
|
line.long 0x00 "DIEPCTL4,OTG Device Endpoint-4 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0x980))&0xC0000)==0x80000)
|
|
group.long 0x980++0x03
|
|
line.long 0x00 "DIEPCTL4,OTG Device Endpoint-4 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0x980))&0xC0000)==0xC0000)
|
|
group.long 0x980++0x03
|
|
line.long 0x00 "DIEPCTL4,OTG Device Endpoint-4 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0x980++0x03
|
|
line.long 0x00 "DIEPCTL4,OTG Device Endpoint-4 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x40040000+0x9A0))&0xC0000)==0x40000)
|
|
group.long 0x9A0++0x03
|
|
line.long 0x00 "DIEPCTL5,OTG Device Endpoint-5 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0x9A0))&0xC0000)==0x80000)
|
|
group.long 0x9A0++0x03
|
|
line.long 0x00 "DIEPCTL5,OTG Device Endpoint-5 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0x9A0))&0xC0000)==0xC0000)
|
|
group.long 0x9A0++0x03
|
|
line.long 0x00 "DIEPCTL5,OTG Device Endpoint-5 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0x9A0++0x03
|
|
line.long 0x00 "DIEPCTL5,OTG Device Endpoint-5 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x40040000+0x9C0))&0xC0000)==0x40000)
|
|
group.long 0x9C0++0x03
|
|
line.long 0x00 "DIEPCTL6,OTG Device Endpoint-6 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0x9C0))&0xC0000)==0x80000)
|
|
group.long 0x9C0++0x03
|
|
line.long 0x00 "DIEPCTL6,OTG Device Endpoint-6 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0x9C0))&0xC0000)==0xC0000)
|
|
group.long 0x9C0++0x03
|
|
line.long 0x00 "DIEPCTL6,OTG Device Endpoint-6 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0x9C0++0x03
|
|
line.long 0x00 "DIEPCTL6,OTG Device Endpoint-6 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x40040000+0x9E0))&0xC0000)==0x40000)
|
|
group.long 0x9E0++0x03
|
|
line.long 0x00 "DIEPCTL7,OTG Device Endpoint-7 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0x9E0))&0xC0000)==0x80000)
|
|
group.long 0x9E0++0x03
|
|
line.long 0x00 "DIEPCTL7,OTG Device Endpoint-7 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0x9E0))&0xC0000)==0xC0000)
|
|
group.long 0x9E0++0x03
|
|
line.long 0x00 "DIEPCTL7,OTG Device Endpoint-7 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0x9E0++0x03
|
|
line.long 0x00 "DIEPCTL7,OTG Device Endpoint-7 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x40040000+0xA00))&0xC0000)==0x40000)
|
|
group.long 0xA00++0x03
|
|
line.long 0x00 "DIEPCTL8,OTG Device Endpoint-8 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0xA00))&0xC0000)==0x80000)
|
|
group.long 0xA00++0x03
|
|
line.long 0x00 "DIEPCTL8,OTG Device Endpoint-8 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0xA00))&0xC0000)==0xC0000)
|
|
group.long 0xA00++0x03
|
|
line.long 0x00 "DIEPCTL8,OTG Device Endpoint-8 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0xA00++0x03
|
|
line.long 0x00 "DIEPCTL8,OTG Device Endpoint-8 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
endif
|
|
newline
|
|
group.long 0xB00++0x03
|
|
line.long 0x00 "DOEPCTL0,Device Control OUT Endpoint 0 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,?..."
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
newline
|
|
rbitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
rbitfld.long 0x00 0.--1. " MPSIZ ,Maximum packet size" "64 bytes,32 bytes,16 bytes,8 bytes"
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40040000+0xB20))&0xC0000)==0x40000)
|
|
group.long 0xB20++0x03
|
|
line.long 0x00 "DOEPCTL1,Device Endpoint-1 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0xB20))&0xC0000)==0x80000)
|
|
group.long 0xB20++0x03
|
|
line.long 0x00 "DOEPCTL1,Device Endpoint-1 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0xB20))&0xC0000)==0xC0000)
|
|
group.long 0xB20++0x03
|
|
line.long 0x00 "DOEPCTL1,Device Endpoint-1 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0xB20++0x03
|
|
line.long 0x00 "DOEPCTL1,Device Endpoint-1 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x40040000+0xB40))&0xC0000)==0x40000)
|
|
group.long 0xB40++0x03
|
|
line.long 0x00 "DOEPCTL2,Device Endpoint-2 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0xB40))&0xC0000)==0x80000)
|
|
group.long 0xB40++0x03
|
|
line.long 0x00 "DOEPCTL2,Device Endpoint-2 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0xB40))&0xC0000)==0xC0000)
|
|
group.long 0xB40++0x03
|
|
line.long 0x00 "DOEPCTL2,Device Endpoint-2 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0xB40++0x03
|
|
line.long 0x00 "DOEPCTL2,Device Endpoint-2 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x40040000+0xB60))&0xC0000)==0x40000)
|
|
group.long 0xB60++0x03
|
|
line.long 0x00 "DOEPCTL3,Device Endpoint-3 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0xB60))&0xC0000)==0x80000)
|
|
group.long 0xB60++0x03
|
|
line.long 0x00 "DOEPCTL3,Device Endpoint-3 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0xB60))&0xC0000)==0xC0000)
|
|
group.long 0xB60++0x03
|
|
line.long 0x00 "DOEPCTL3,Device Endpoint-3 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0xB60++0x03
|
|
line.long 0x00 "DOEPCTL3,Device Endpoint-3 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x40040000+0xB80))&0xC0000)==0x40000)
|
|
group.long 0xB80++0x03
|
|
line.long 0x00 "DOEPCTL4,Device Endpoint-4 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0xB80))&0xC0000)==0x80000)
|
|
group.long 0xB80++0x03
|
|
line.long 0x00 "DOEPCTL4,Device Endpoint-4 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0xB80))&0xC0000)==0xC0000)
|
|
group.long 0xB80++0x03
|
|
line.long 0x00 "DOEPCTL4,Device Endpoint-4 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0xB80++0x03
|
|
line.long 0x00 "DOEPCTL4,Device Endpoint-4 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x40040000+0xBA0))&0xC0000)==0x40000)
|
|
group.long 0xBA0++0x03
|
|
line.long 0x00 "DOEPCTL5,Device Endpoint-5 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0xBA0))&0xC0000)==0x80000)
|
|
group.long 0xBA0++0x03
|
|
line.long 0x00 "DOEPCTL5,Device Endpoint-5 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0xBA0))&0xC0000)==0xC0000)
|
|
group.long 0xBA0++0x03
|
|
line.long 0x00 "DOEPCTL5,Device Endpoint-5 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0xBA0++0x03
|
|
line.long 0x00 "DOEPCTL5,Device Endpoint-5 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x40040000+0xBC0))&0xC0000)==0x40000)
|
|
group.long 0xBC0++0x03
|
|
line.long 0x00 "DOEPCTL6,Device Endpoint-6 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0xBC0))&0xC0000)==0x80000)
|
|
group.long 0xBC0++0x03
|
|
line.long 0x00 "DOEPCTL6,Device Endpoint-6 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0xBC0))&0xC0000)==0xC0000)
|
|
group.long 0xBC0++0x03
|
|
line.long 0x00 "DOEPCTL6,Device Endpoint-6 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0xBC0++0x03
|
|
line.long 0x00 "DOEPCTL6,Device Endpoint-6 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x40040000+0xBE0))&0xC0000)==0x40000)
|
|
group.long 0xBE0++0x03
|
|
line.long 0x00 "DOEPCTL7,Device Endpoint-7 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0xBE0))&0xC0000)==0x80000)
|
|
group.long 0xBE0++0x03
|
|
line.long 0x00 "DOEPCTL7,Device Endpoint-7 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0xBE0))&0xC0000)==0xC0000)
|
|
group.long 0xBE0++0x03
|
|
line.long 0x00 "DOEPCTL7,Device Endpoint-7 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0xBE0++0x03
|
|
line.long 0x00 "DOEPCTL7,Device Endpoint-7 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x40040000+0xC00))&0xC0000)==0x40000)
|
|
group.long 0xC00++0x03
|
|
line.long 0x00 "DOEPCTL8,Device Endpoint-8 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0xC00))&0xC0000)==0x80000)
|
|
group.long 0xC00++0x03
|
|
line.long 0x00 "DOEPCTL8,Device Endpoint-8 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0xC00))&0xC0000)==0xC0000)
|
|
group.long 0xC00++0x03
|
|
line.long 0x00 "DOEPCTL8,Device Endpoint-8 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0xC00++0x03
|
|
line.long 0x00 "DOEPCTL8,Device Endpoint-8 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enable"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40040000+0xB20))&0xC0000)==0x40000)
|
|
group.long 0xB20++0x03
|
|
line.long 0x00 "DOEPCTL1,Device Endpoint-1 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0xB20))&0xC0000)==0x80000)
|
|
group.long 0xB20++0x03
|
|
line.long 0x00 "DOEPCTL1,Device Endpoint-1 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0xB20))&0xC0000)==0xC0000)
|
|
group.long 0xB20++0x03
|
|
line.long 0x00 "DOEPCTL1,Device Endpoint-1 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0xB20++0x03
|
|
line.long 0x00 "DOEPCTL1,Device Endpoint-1 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
newline
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x40040000+0xB40))&0xC0000)==0x40000)
|
|
group.long 0xB40++0x03
|
|
line.long 0x00 "DOEPCTL2,Device Endpoint-2 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0xB40))&0xC0000)==0x80000)
|
|
group.long 0xB40++0x03
|
|
line.long 0x00 "DOEPCTL2,Device Endpoint-2 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0xB40))&0xC0000)==0xC0000)
|
|
group.long 0xB40++0x03
|
|
line.long 0x00 "DOEPCTL2,Device Endpoint-2 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0xB40++0x03
|
|
line.long 0x00 "DOEPCTL2,Device Endpoint-2 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
newline
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x40040000+0xB60))&0xC0000)==0x40000)
|
|
group.long 0xB60++0x03
|
|
line.long 0x00 "DOEPCTL3,Device Endpoint-3 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0xB60))&0xC0000)==0x80000)
|
|
group.long 0xB60++0x03
|
|
line.long 0x00 "DOEPCTL3,Device Endpoint-3 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0xB60))&0xC0000)==0xC0000)
|
|
group.long 0xB60++0x03
|
|
line.long 0x00 "DOEPCTL3,Device Endpoint-3 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0xB60++0x03
|
|
line.long 0x00 "DOEPCTL3,Device Endpoint-3 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
newline
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x40040000+0xB80))&0xC0000)==0x40000)
|
|
group.long 0xB80++0x03
|
|
line.long 0x00 "DOEPCTL4,Device Endpoint-4 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0xB80))&0xC0000)==0x80000)
|
|
group.long 0xB80++0x03
|
|
line.long 0x00 "DOEPCTL4,Device Endpoint-4 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0xB80))&0xC0000)==0xC0000)
|
|
group.long 0xB80++0x03
|
|
line.long 0x00 "DOEPCTL4,Device Endpoint-4 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0xB80++0x03
|
|
line.long 0x00 "DOEPCTL4,Device Endpoint-4 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
newline
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x40040000+0xBA0))&0xC0000)==0x40000)
|
|
group.long 0xBA0++0x03
|
|
line.long 0x00 "DOEPCTL5,Device Endpoint-5 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0xBA0))&0xC0000)==0x80000)
|
|
group.long 0xBA0++0x03
|
|
line.long 0x00 "DOEPCTL5,Device Endpoint-5 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0xBA0))&0xC0000)==0xC0000)
|
|
group.long 0xBA0++0x03
|
|
line.long 0x00 "DOEPCTL5,Device Endpoint-5 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0xBA0++0x03
|
|
line.long 0x00 "DOEPCTL5,Device Endpoint-5 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
newline
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x40040000+0xBC0))&0xC0000)==0x40000)
|
|
group.long 0xBC0++0x03
|
|
line.long 0x00 "DOEPCTL6,Device Endpoint-6 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0xBC0))&0xC0000)==0x80000)
|
|
group.long 0xBC0++0x03
|
|
line.long 0x00 "DOEPCTL6,Device Endpoint-6 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0xBC0))&0xC0000)==0xC0000)
|
|
group.long 0xBC0++0x03
|
|
line.long 0x00 "DOEPCTL6,Device Endpoint-6 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0xBC0++0x03
|
|
line.long 0x00 "DOEPCTL6,Device Endpoint-6 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
newline
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x40040000+0xBE0))&0xC0000)==0x40000)
|
|
group.long 0xBE0++0x03
|
|
line.long 0x00 "DOEPCTL7,Device Endpoint-7 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0xBE0))&0xC0000)==0x80000)
|
|
group.long 0xBE0++0x03
|
|
line.long 0x00 "DOEPCTL7,Device Endpoint-7 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0xBE0))&0xC0000)==0xC0000)
|
|
group.long 0xBE0++0x03
|
|
line.long 0x00 "DOEPCTL7,Device Endpoint-7 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0xBE0++0x03
|
|
line.long 0x00 "DOEPCTL7,Device Endpoint-7 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
newline
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x40040000+0xC00))&0xC0000)==0x40000)
|
|
group.long 0xC00++0x03
|
|
line.long 0x00 "DOEPCTL8,Device Endpoint-8 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0xC00))&0xC0000)==0x80000)
|
|
group.long 0xC00++0x03
|
|
line.long 0x00 "DOEPCTL8,Device Endpoint-8 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x40040000+0xC00))&0xC0000)==0xC0000)
|
|
group.long 0xC00++0x03
|
|
line.long 0x00 "DOEPCTL8,Device Endpoint-8 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0xC00++0x03
|
|
line.long 0x00 "DOEPCTL8,Device Endpoint-8 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 26. 0x00 27. " NAK_SET/CLR ,NAK status" "Non-NAK,NAK"
|
|
newline
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
endif
|
|
newline
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
if ((per.l(ad:0x40040000+0x908)&0xC0000)==0x00)
|
|
group.long 0x908++0x03
|
|
line.long 0x00 "DIEPINT0,Device Endpoint-0 Interrupt Register"
|
|
eventfld.long 0x00 13. " NAK ,NAK input for USB OTG HS" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped"
|
|
eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit fifo underrun (TxfifoUndrn)" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0x908++0x03
|
|
line.long 0x00 "DIEPINT0,Device Endpoint-0 Interrupt Register"
|
|
eventfld.long 0x00 13. " NAK ,NAK input for USB OTG HS" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped"
|
|
eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit fifo underrun (TxfifoUndrn)" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x40040000+0x908)&0xC0000)==0x00)
|
|
group.long 0x928++0x03
|
|
line.long 0x00 "DIEPINT1,Device Endpoint-1 Interrupt Register"
|
|
eventfld.long 0x00 13. " NAK ,NAK input for USB OTG HS" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped"
|
|
eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit fifo underrun (TxfifoUndrn)" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0x928++0x03
|
|
line.long 0x00 "DIEPINT1,Device Endpoint-1 Interrupt Register"
|
|
eventfld.long 0x00 13. " NAK ,NAK input for USB OTG HS" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped"
|
|
eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit fifo underrun (TxfifoUndrn)" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x40040000+0x908)&0xC0000)==0x00)
|
|
group.long 0x948++0x03
|
|
line.long 0x00 "DIEPINT2,Device Endpoint-2 Interrupt Register"
|
|
eventfld.long 0x00 13. " NAK ,NAK input for USB OTG HS" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped"
|
|
eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit fifo underrun (TxfifoUndrn)" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0x948++0x03
|
|
line.long 0x00 "DIEPINT2,Device Endpoint-2 Interrupt Register"
|
|
eventfld.long 0x00 13. " NAK ,NAK input for USB OTG HS" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped"
|
|
eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit fifo underrun (TxfifoUndrn)" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x40040000+0x908)&0xC0000)==0x00)
|
|
group.long 0x968++0x03
|
|
line.long 0x00 "DIEPINT3,Device Endpoint-3 Interrupt Register"
|
|
eventfld.long 0x00 13. " NAK ,NAK input for USB OTG HS" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped"
|
|
eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit fifo underrun (TxfifoUndrn)" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0x968++0x03
|
|
line.long 0x00 "DIEPINT3,Device Endpoint-3 Interrupt Register"
|
|
eventfld.long 0x00 13. " NAK ,NAK input for USB OTG HS" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped"
|
|
eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit fifo underrun (TxfifoUndrn)" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x40040000+0x908)&0xC0000)==0x00)
|
|
group.long 0x988++0x03
|
|
line.long 0x00 "DIEPINT4,Device Endpoint-4 Interrupt Register"
|
|
eventfld.long 0x00 13. " NAK ,NAK input for USB OTG HS" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped"
|
|
eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit fifo underrun (TxfifoUndrn)" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0x988++0x03
|
|
line.long 0x00 "DIEPINT4,Device Endpoint-4 Interrupt Register"
|
|
eventfld.long 0x00 13. " NAK ,NAK input for USB OTG HS" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped"
|
|
eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit fifo underrun (TxfifoUndrn)" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x40040000+0x908)&0xC0000)==0x00)
|
|
group.long 0x9A8++0x03
|
|
line.long 0x00 "DIEPINT5,Device Endpoint-5 Interrupt Register"
|
|
eventfld.long 0x00 13. " NAK ,NAK input for USB OTG HS" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped"
|
|
eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit fifo underrun (TxfifoUndrn)" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0x9A8++0x03
|
|
line.long 0x00 "DIEPINT5,Device Endpoint-5 Interrupt Register"
|
|
eventfld.long 0x00 13. " NAK ,NAK input for USB OTG HS" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped"
|
|
eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit fifo underrun (TxfifoUndrn)" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x40040000+0x908)&0xC0000)==0x00)
|
|
group.long 0x9C8++0x03
|
|
line.long 0x00 "DIEPINT6,Device Endpoint-6 Interrupt Register"
|
|
eventfld.long 0x00 13. " NAK ,NAK input for USB OTG HS" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped"
|
|
eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit fifo underrun (TxfifoUndrn)" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0x9C8++0x03
|
|
line.long 0x00 "DIEPINT6,Device Endpoint-6 Interrupt Register"
|
|
eventfld.long 0x00 13. " NAK ,NAK input for USB OTG HS" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped"
|
|
eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit fifo underrun (TxfifoUndrn)" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x40040000+0x908)&0xC0000)==0x00)
|
|
group.long 0x9E8++0x03
|
|
line.long 0x00 "DIEPINT7,Device Endpoint-7 Interrupt Register"
|
|
eventfld.long 0x00 13. " NAK ,NAK input for USB OTG HS" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped"
|
|
eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit fifo underrun (TxfifoUndrn)" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0x9E8++0x03
|
|
line.long 0x00 "DIEPINT7,Device Endpoint-7 Interrupt Register"
|
|
eventfld.long 0x00 13. " NAK ,NAK input for USB OTG HS" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped"
|
|
eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit fifo underrun (TxfifoUndrn)" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x40040000+0x908)&0xC0000)==0x00)
|
|
group.long 0xA08++0x03
|
|
line.long 0x00 "DIEPINT8,Device Endpoint-8 Interrupt Register"
|
|
eventfld.long 0x00 13. " NAK ,NAK input for USB OTG HS" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped"
|
|
eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit fifo underrun (TxfifoUndrn)" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0xA08++0x03
|
|
line.long 0x00 "DIEPINT8,Device Endpoint-8 Interrupt Register"
|
|
eventfld.long 0x00 13. " NAK ,NAK input for USB OTG HS" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped"
|
|
eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit fifo underrun (TxfifoUndrn)" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x40040000+0xB08-0x08)&0xC0000)==0x00)
|
|
group.long 0xB08++0x03
|
|
line.long 0x00 "DOEPINT0,Device Endpoint-0 Interrupt Register"
|
|
eventfld.long 0x00 15. " STPKTRX ,Setup packet received" "Not received,Received"
|
|
eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received"
|
|
eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "Not received,Received"
|
|
eventfld.long 0x00 3. " STUP ,SETUP phase done" "Not done,Done"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0xB08++0x03
|
|
line.long 0x00 "DOEPINT0,Device Endpoint-0 Interrupt Register"
|
|
eventfld.long 0x00 15. " STPKTRX ,Setup packet received" "Not received,Received"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x40040000+0xB28-0x08)&0xC0000)==0x00)
|
|
group.long 0xB28++0x03
|
|
line.long 0x00 "DOEPINT1,Device Endpoint-1 Interrupt Register"
|
|
eventfld.long 0x00 15. " STPKTRX ,Setup packet received" "Not received,Received"
|
|
eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received"
|
|
eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "Not received,Received"
|
|
eventfld.long 0x00 3. " STUP ,SETUP phase done" "Not done,Done"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0xB28++0x03
|
|
line.long 0x00 "DOEPINT1,Device Endpoint-1 Interrupt Register"
|
|
eventfld.long 0x00 15. " STPKTRX ,Setup packet received" "Not received,Received"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x40040000+0xB48-0x08)&0xC0000)==0x00)
|
|
group.long 0xB48++0x03
|
|
line.long 0x00 "DOEPINT2,Device Endpoint-2 Interrupt Register"
|
|
eventfld.long 0x00 15. " STPKTRX ,Setup packet received" "Not received,Received"
|
|
eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received"
|
|
eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "Not received,Received"
|
|
eventfld.long 0x00 3. " STUP ,SETUP phase done" "Not done,Done"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0xB48++0x03
|
|
line.long 0x00 "DOEPINT2,Device Endpoint-2 Interrupt Register"
|
|
eventfld.long 0x00 15. " STPKTRX ,Setup packet received" "Not received,Received"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x40040000+0xB68-0x08)&0xC0000)==0x00)
|
|
group.long 0xB68++0x03
|
|
line.long 0x00 "DOEPINT3,Device Endpoint-3 Interrupt Register"
|
|
eventfld.long 0x00 15. " STPKTRX ,Setup packet received" "Not received,Received"
|
|
eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received"
|
|
eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "Not received,Received"
|
|
eventfld.long 0x00 3. " STUP ,SETUP phase done" "Not done,Done"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0xB68++0x03
|
|
line.long 0x00 "DOEPINT3,Device Endpoint-3 Interrupt Register"
|
|
eventfld.long 0x00 15. " STPKTRX ,Setup packet received" "Not received,Received"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x40040000+0xB88-0x08)&0xC0000)==0x00)
|
|
group.long 0xB88++0x03
|
|
line.long 0x00 "DOEPINT4,Device Endpoint-4 Interrupt Register"
|
|
eventfld.long 0x00 15. " STPKTRX ,Setup packet received" "Not received,Received"
|
|
eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received"
|
|
eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "Not received,Received"
|
|
eventfld.long 0x00 3. " STUP ,SETUP phase done" "Not done,Done"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0xB88++0x03
|
|
line.long 0x00 "DOEPINT4,Device Endpoint-4 Interrupt Register"
|
|
eventfld.long 0x00 15. " STPKTRX ,Setup packet received" "Not received,Received"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x40040000+0xBA8-0x08)&0xC0000)==0x00)
|
|
group.long 0xBA8++0x03
|
|
line.long 0x00 "DOEPINT5,Device Endpoint-5 Interrupt Register"
|
|
eventfld.long 0x00 15. " STPKTRX ,Setup packet received" "Not received,Received"
|
|
eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received"
|
|
eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "Not received,Received"
|
|
eventfld.long 0x00 3. " STUP ,SETUP phase done" "Not done,Done"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0xBA8++0x03
|
|
line.long 0x00 "DOEPINT5,Device Endpoint-5 Interrupt Register"
|
|
eventfld.long 0x00 15. " STPKTRX ,Setup packet received" "Not received,Received"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x40040000+0xBC8-0x08)&0xC0000)==0x00)
|
|
group.long 0xBC8++0x03
|
|
line.long 0x00 "DOEPINT6,Device Endpoint-6 Interrupt Register"
|
|
eventfld.long 0x00 15. " STPKTRX ,Setup packet received" "Not received,Received"
|
|
eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received"
|
|
eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "Not received,Received"
|
|
eventfld.long 0x00 3. " STUP ,SETUP phase done" "Not done,Done"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0xBC8++0x03
|
|
line.long 0x00 "DOEPINT6,Device Endpoint-6 Interrupt Register"
|
|
eventfld.long 0x00 15. " STPKTRX ,Setup packet received" "Not received,Received"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x40040000+0xBE8-0x08)&0xC0000)==0x00)
|
|
group.long 0xBE8++0x03
|
|
line.long 0x00 "DOEPINT7,Device Endpoint-7 Interrupt Register"
|
|
eventfld.long 0x00 15. " STPKTRX ,Setup packet received" "Not received,Received"
|
|
eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received"
|
|
eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "Not received,Received"
|
|
eventfld.long 0x00 3. " STUP ,SETUP phase done" "Not done,Done"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0xBE8++0x03
|
|
line.long 0x00 "DOEPINT7,Device Endpoint-7 Interrupt Register"
|
|
eventfld.long 0x00 15. " STPKTRX ,Setup packet received" "Not received,Received"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x40040000+0xC08-0x08)&0xC0000)==0x00)
|
|
group.long 0xC08++0x03
|
|
line.long 0x00 "DOEPINT8,Device Endpoint-8 Interrupt Register"
|
|
eventfld.long 0x00 15. " STPKTRX ,Setup packet received" "Not received,Received"
|
|
eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received"
|
|
eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "Not received,Received"
|
|
eventfld.long 0x00 3. " STUP ,SETUP phase done" "Not done,Done"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0xC08++0x03
|
|
line.long 0x00 "DOEPINT8,Device Endpoint-8 Interrupt Register"
|
|
eventfld.long 0x00 15. " STPKTRX ,Setup packet received" "Not received,Received"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40040000+0x908+0x1F8)&0xC0000)==0x00)
|
|
group.long 0x908++0x03
|
|
line.long 0x00 "DIEPINT0,Device Endpoint-0 Interrupt Register"
|
|
eventfld.long 0x00 13. " NAK ,NAK interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped"
|
|
eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit FIFO Underrun interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0x908++0x03
|
|
line.long 0x00 "DIEPINT0,Device Endpoint-0 Interrupt Register"
|
|
eventfld.long 0x00 13. " NAK ,NAK interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped"
|
|
eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit FIFO Underrun interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x40040000+0x928+0x1F8)&0xC0000)==0x00)
|
|
group.long 0x928++0x03
|
|
line.long 0x00 "DIEPINT1,Device Endpoint-1 Interrupt Register"
|
|
eventfld.long 0x00 13. " NAK ,NAK interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped"
|
|
eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit FIFO Underrun interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0x928++0x03
|
|
line.long 0x00 "DIEPINT1,Device Endpoint-1 Interrupt Register"
|
|
eventfld.long 0x00 13. " NAK ,NAK interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped"
|
|
eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit FIFO Underrun interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x40040000+0x948+0x1F8)&0xC0000)==0x00)
|
|
group.long 0x948++0x03
|
|
line.long 0x00 "DIEPINT2,Device Endpoint-2 Interrupt Register"
|
|
eventfld.long 0x00 13. " NAK ,NAK interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped"
|
|
eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit FIFO Underrun interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0x948++0x03
|
|
line.long 0x00 "DIEPINT2,Device Endpoint-2 Interrupt Register"
|
|
eventfld.long 0x00 13. " NAK ,NAK interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped"
|
|
eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit FIFO Underrun interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x40040000+0x968+0x1F8)&0xC0000)==0x00)
|
|
group.long 0x968++0x03
|
|
line.long 0x00 "DIEPINT3,Device Endpoint-3 Interrupt Register"
|
|
eventfld.long 0x00 13. " NAK ,NAK interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped"
|
|
eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit FIFO Underrun interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0x968++0x03
|
|
line.long 0x00 "DIEPINT3,Device Endpoint-3 Interrupt Register"
|
|
eventfld.long 0x00 13. " NAK ,NAK interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped"
|
|
eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit FIFO Underrun interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x40040000+0x988+0x1F8)&0xC0000)==0x00)
|
|
group.long 0x988++0x03
|
|
line.long 0x00 "DIEPINT4,Device Endpoint-4 Interrupt Register"
|
|
eventfld.long 0x00 13. " NAK ,NAK interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped"
|
|
eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit FIFO Underrun interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0x988++0x03
|
|
line.long 0x00 "DIEPINT4,Device Endpoint-4 Interrupt Register"
|
|
eventfld.long 0x00 13. " NAK ,NAK interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped"
|
|
eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit FIFO Underrun interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x40040000+0x9A8+0x1F8)&0xC0000)==0x00)
|
|
group.long 0x9A8++0x03
|
|
line.long 0x00 "DIEPINT5,Device Endpoint-5 Interrupt Register"
|
|
eventfld.long 0x00 13. " NAK ,NAK interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped"
|
|
eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit FIFO Underrun interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0x9A8++0x03
|
|
line.long 0x00 "DIEPINT5,Device Endpoint-5 Interrupt Register"
|
|
eventfld.long 0x00 13. " NAK ,NAK interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped"
|
|
eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit FIFO Underrun interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x40040000+0x9C8+0x1F8)&0xC0000)==0x00)
|
|
group.long 0x9C8++0x03
|
|
line.long 0x00 "DIEPINT6,Device Endpoint-6 Interrupt Register"
|
|
eventfld.long 0x00 13. " NAK ,NAK interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped"
|
|
eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit FIFO Underrun interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0x9C8++0x03
|
|
line.long 0x00 "DIEPINT6,Device Endpoint-6 Interrupt Register"
|
|
eventfld.long 0x00 13. " NAK ,NAK interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped"
|
|
eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit FIFO Underrun interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x40040000+0x9E8+0x1F8)&0xC0000)==0x00)
|
|
group.long 0x9E8++0x03
|
|
line.long 0x00 "DIEPINT7,Device Endpoint-7 Interrupt Register"
|
|
eventfld.long 0x00 13. " NAK ,NAK interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped"
|
|
eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit FIFO Underrun interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0x9E8++0x03
|
|
line.long 0x00 "DIEPINT7,Device Endpoint-7 Interrupt Register"
|
|
eventfld.long 0x00 13. " NAK ,NAK interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped"
|
|
eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit FIFO Underrun interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x40040000+0xA08+0x1F8)&0xC0000)==0x00)
|
|
group.long 0xA08++0x03
|
|
line.long 0x00 "DIEPINT8,Device Endpoint-8 Interrupt Register"
|
|
eventfld.long 0x00 13. " NAK ,NAK interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped"
|
|
eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit FIFO Underrun interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0xA08++0x03
|
|
line.long 0x00 "DIEPINT8,Device Endpoint-8 Interrupt Register"
|
|
eventfld.long 0x00 13. " NAK ,NAK interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped"
|
|
eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit FIFO Underrun interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x40040000+0xB08-0x08)&0xC0000)==0x00)
|
|
group.long 0xB08++0x03
|
|
line.long 0x00 "DOEPINT0,Device Endpoint-0 Interrupt Register"
|
|
eventfld.long 0x00 15. " STPKTRX ,Setup packet received" "Not received,Received"
|
|
eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received"
|
|
newline
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
eventfld.long 0x00 5. " STSPHSRX ,Status phase received for control write" "No interrupt,Interrupt"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "Not received,Received"
|
|
eventfld.long 0x00 3. " STUP ,SETUP phase done" "Not done,Done"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0xB08++0x03
|
|
line.long 0x00 "DOEPINT0,Device Endpoint-0 Interrupt Register"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x40040000+0xB28-0x08)&0xC0000)==0x00)
|
|
group.long 0xB28++0x03
|
|
line.long 0x00 "DOEPINT1,Device Endpoint-1 Interrupt Register"
|
|
eventfld.long 0x00 15. " STPKTRX ,Setup packet received" "Not received,Received"
|
|
eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received"
|
|
newline
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
eventfld.long 0x00 5. " STSPHSRX ,Status phase received for control write" "No interrupt,Interrupt"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "Not received,Received"
|
|
eventfld.long 0x00 3. " STUP ,SETUP phase done" "Not done,Done"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0xB28++0x03
|
|
line.long 0x00 "DOEPINT1,Device Endpoint-1 Interrupt Register"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x40040000+0xB48-0x08)&0xC0000)==0x00)
|
|
group.long 0xB48++0x03
|
|
line.long 0x00 "DOEPINT2,Device Endpoint-2 Interrupt Register"
|
|
eventfld.long 0x00 15. " STPKTRX ,Setup packet received" "Not received,Received"
|
|
eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received"
|
|
newline
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
eventfld.long 0x00 5. " STSPHSRX ,Status phase received for control write" "No interrupt,Interrupt"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "Not received,Received"
|
|
eventfld.long 0x00 3. " STUP ,SETUP phase done" "Not done,Done"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0xB48++0x03
|
|
line.long 0x00 "DOEPINT2,Device Endpoint-2 Interrupt Register"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x40040000+0xB68-0x08)&0xC0000)==0x00)
|
|
group.long 0xB68++0x03
|
|
line.long 0x00 "DOEPINT3,Device Endpoint-3 Interrupt Register"
|
|
eventfld.long 0x00 15. " STPKTRX ,Setup packet received" "Not received,Received"
|
|
eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received"
|
|
newline
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
eventfld.long 0x00 5. " STSPHSRX ,Status phase received for control write" "No interrupt,Interrupt"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "Not received,Received"
|
|
eventfld.long 0x00 3. " STUP ,SETUP phase done" "Not done,Done"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0xB68++0x03
|
|
line.long 0x00 "DOEPINT3,Device Endpoint-3 Interrupt Register"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x40040000+0xB88-0x08)&0xC0000)==0x00)
|
|
group.long 0xB88++0x03
|
|
line.long 0x00 "DOEPINT4,Device Endpoint-4 Interrupt Register"
|
|
eventfld.long 0x00 15. " STPKTRX ,Setup packet received" "Not received,Received"
|
|
eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received"
|
|
newline
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
eventfld.long 0x00 5. " STSPHSRX ,Status phase received for control write" "No interrupt,Interrupt"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "Not received,Received"
|
|
eventfld.long 0x00 3. " STUP ,SETUP phase done" "Not done,Done"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0xB88++0x03
|
|
line.long 0x00 "DOEPINT4,Device Endpoint-4 Interrupt Register"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x40040000+0xBA8-0x08)&0xC0000)==0x00)
|
|
group.long 0xBA8++0x03
|
|
line.long 0x00 "DOEPINT5,Device Endpoint-5 Interrupt Register"
|
|
eventfld.long 0x00 15. " STPKTRX ,Setup packet received" "Not received,Received"
|
|
eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received"
|
|
newline
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
eventfld.long 0x00 5. " STSPHSRX ,Status phase received for control write" "No interrupt,Interrupt"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "Not received,Received"
|
|
eventfld.long 0x00 3. " STUP ,SETUP phase done" "Not done,Done"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0xBA8++0x03
|
|
line.long 0x00 "DOEPINT5,Device Endpoint-5 Interrupt Register"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x40040000+0xBC8-0x08)&0xC0000)==0x00)
|
|
group.long 0xBC8++0x03
|
|
line.long 0x00 "DOEPINT6,Device Endpoint-6 Interrupt Register"
|
|
eventfld.long 0x00 15. " STPKTRX ,Setup packet received" "Not received,Received"
|
|
eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received"
|
|
newline
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
eventfld.long 0x00 5. " STSPHSRX ,Status phase received for control write" "No interrupt,Interrupt"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "Not received,Received"
|
|
eventfld.long 0x00 3. " STUP ,SETUP phase done" "Not done,Done"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0xBC8++0x03
|
|
line.long 0x00 "DOEPINT6,Device Endpoint-6 Interrupt Register"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x40040000+0xBE8-0x08)&0xC0000)==0x00)
|
|
group.long 0xBE8++0x03
|
|
line.long 0x00 "DOEPINT7,Device Endpoint-7 Interrupt Register"
|
|
eventfld.long 0x00 15. " STPKTRX ,Setup packet received" "Not received,Received"
|
|
eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received"
|
|
newline
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
eventfld.long 0x00 5. " STSPHSRX ,Status phase received for control write" "No interrupt,Interrupt"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "Not received,Received"
|
|
eventfld.long 0x00 3. " STUP ,SETUP phase done" "Not done,Done"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0xBE8++0x03
|
|
line.long 0x00 "DOEPINT7,Device Endpoint-7 Interrupt Register"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x40040000+0xC08-0x08)&0xC0000)==0x00)
|
|
group.long 0xC08++0x03
|
|
line.long 0x00 "DOEPINT8,Device Endpoint-8 Interrupt Register"
|
|
eventfld.long 0x00 15. " STPKTRX ,Setup packet received" "Not received,Received"
|
|
eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received"
|
|
newline
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
eventfld.long 0x00 5. " STSPHSRX ,Status phase received for control write" "No interrupt,Interrupt"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "Not received,Received"
|
|
eventfld.long 0x00 3. " STUP ,SETUP phase done" "Not done,Done"
|
|
newline
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0xC08++0x03
|
|
line.long 0x00 "DOEPINT8,Device Endpoint-8 Interrupt Register"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
endif
|
|
group.long 0x910++0x03
|
|
line.long 0x00 "DIEPTSIZ0,Device IN Endpoint 0 Transfer Size Register"
|
|
bitfld.long 0x00 19.--20. " PKTCNT ,Packet count" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--6. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0x914++0x03
|
|
line.long 0x00 "DIEPDMA0,OTG Device Channel-0 DMA Address Register"
|
|
group.long 0x934++0x03
|
|
line.long 0x00 "DIEPDMA1,OTG Device Channel-1 DMA Address Register"
|
|
group.long 0x954++0x03
|
|
line.long 0x00 "DIEPDMA2,OTG Device Channel-2 DMA Address Register"
|
|
group.long 0x974++0x03
|
|
line.long 0x00 "DIEPDMA3,OTG Device Channel-3 DMA Address Register"
|
|
group.long 0x994++0x03
|
|
line.long 0x00 "DIEPDMA4,OTG Device Channel-4 DMA Address Register"
|
|
group.long 0x9B4++0x03
|
|
line.long 0x00 "DIEPDMA5,OTG Device Channel-5 DMA Address Register"
|
|
group.long 0x9D4++0x03
|
|
line.long 0x00 "DIEPDMA6,OTG Device Channel-6 DMA Address Register"
|
|
group.long 0x9F4++0x03
|
|
line.long 0x00 "DIEPDMA7,OTG Device Channel-7 DMA Address Register"
|
|
group.long 0xA14++0x03
|
|
line.long 0x00 "DIEPDMA8,OTG Device Channel-8 DMA Address Register"
|
|
group.long 0xA34++0x03
|
|
line.long 0x00 "DIEPDMA9,OTG Device Channel-9 DMA Address Register"
|
|
group.long 0xA54++0x03
|
|
line.long 0x00 "DIEPDMA10,OTG Device Channel-10 DMA Address Register"
|
|
group.long 0xA74++0x03
|
|
line.long 0x00 "DIEPDMA11,OTG Device Channel-11 DMA Address Register"
|
|
group.long 0xA94++0x03
|
|
line.long 0x00 "DIEPDMA12,OTG Device Channel-12 DMA Address Register"
|
|
group.long 0xAB4++0x03
|
|
line.long 0x00 "DIEPDMA13,OTG Device Channel-13 DMA Address Register"
|
|
group.long 0xAD4++0x03
|
|
line.long 0x00 "DIEPDMA14,OTG Device Channel-14 DMA Address Register"
|
|
group.long 0xAF4++0x03
|
|
line.long 0x00 "DIEPDMA15,OTG Device Channel-15 DMA Address Register"
|
|
group.long 0xB14++0x03
|
|
line.long 0x00 "DOEPDMA0,OTG Device Channel-0 DMA Address Register"
|
|
group.long 0xB34++0x03
|
|
line.long 0x00 "DOEPDMA1,OTG Device Channel-1 DMA Address Register"
|
|
group.long 0xB54++0x03
|
|
line.long 0x00 "DOEPDMA2,OTG Device Channel-2 DMA Address Register"
|
|
group.long 0xB74++0x03
|
|
line.long 0x00 "DOEPDMA3,OTG Device Channel-3 DMA Address Register"
|
|
group.long 0xB94++0x03
|
|
line.long 0x00 "DOEPDMA4,OTG Device Channel-4 DMA Address Register"
|
|
group.long 0xBB4++0x03
|
|
line.long 0x00 "DOEPDMA5,OTG Device Channel-5 DMA Address Register"
|
|
group.long 0xBD4++0x03
|
|
line.long 0x00 "DOEPDMA6,OTG Device Channel-6 DMA Address Register"
|
|
group.long 0xBF4++0x03
|
|
line.long 0x00 "DOEPDMA7,OTG Device Channel-7 DMA Address Register"
|
|
group.long 0xC14++0x03
|
|
line.long 0x00 "DOEPDMA8,OTG Device Channel-8 DMA Address Register"
|
|
group.long 0xC34++0x03
|
|
line.long 0x00 "DOEPDMA9,OTG Device Channel-9 DMA Address Register"
|
|
group.long 0xC54++0x03
|
|
line.long 0x00 "DOEPDMA10,OTG Device Channel-10 DMA Address Register"
|
|
group.long 0xC74++0x03
|
|
line.long 0x00 "DOEPDMA11,OTG Device Channel-11 DMA Address Register"
|
|
group.long 0xC94++0x03
|
|
line.long 0x00 "DOEPDMA12,OTG Device Channel-12 DMA Address Register"
|
|
group.long 0xCB4++0x03
|
|
line.long 0x00 "DOEPDMA13,OTG Device Channel-13 DMA Address Register"
|
|
group.long 0xCD4++0x03
|
|
line.long 0x00 "DOEPDMA14,OTG Device Channel-14 DMA Address Register"
|
|
group.long 0xCF4++0x03
|
|
line.long 0x00 "DOEPDMA15,OTG Device Channel-15 DMA Address Register"
|
|
group.long 0xB10++0x03
|
|
line.long 0x00 "DOEPTSIZ0,Device OUT Endpoint 0 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3"
|
|
bitfld.long 0x00 19. " PKTCNT ,Packet count" "Low,High"
|
|
hexmask.long.byte 0x00 0.--6. 1. " XFRSIZ ,Transfer size"
|
|
sif (cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
group.long 0x910++0x03
|
|
line.long 0x00 "DIEPTSIZ0,OTG Device IN Endpoint-0 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " MCNT ,Multi count" ",1 packet,2 packet,3 packet"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.byte 0x00 0.--6. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0x930++0x03
|
|
line.long 0x00 "DIEPTSIZ1,OTG Device IN Endpoint-1 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " MCNT ,Multi count" ",1 packet,2 packet,3 packet"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.byte 0x00 0.--6. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0x950++0x03
|
|
line.long 0x00 "DIEPTSIZ2,OTG Device IN Endpoint-2 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " MCNT ,Multi count" ",1 packet,2 packet,3 packet"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.byte 0x00 0.--6. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0x970++0x03
|
|
line.long 0x00 "DIEPTSIZ3,OTG Device IN Endpoint-3 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " MCNT ,Multi count" ",1 packet,2 packet,3 packet"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.byte 0x00 0.--6. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0x990++0x03
|
|
line.long 0x00 "DIEPTSIZ4,OTG Device IN Endpoint-4 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " MCNT ,Multi count" ",1 packet,2 packet,3 packet"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.byte 0x00 0.--6. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0x9B0++0x03
|
|
line.long 0x00 "DIEPTSIZ5,OTG Device IN Endpoint-5 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " MCNT ,Multi count" ",1 packet,2 packet,3 packet"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.byte 0x00 0.--6. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0x9D0++0x03
|
|
line.long 0x00 "DIEPTSIZ6,OTG Device IN Endpoint-6 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " MCNT ,Multi count" ",1 packet,2 packet,3 packet"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.byte 0x00 0.--6. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0x9F0++0x03
|
|
line.long 0x00 "DIEPTSIZ7,OTG Device IN Endpoint-7 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " MCNT ,Multi count" ",1 packet,2 packet,3 packet"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.byte 0x00 0.--6. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0xA10++0x03
|
|
line.long 0x00 "DIEPTSIZ8,OTG Device IN Endpoint-8 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " MCNT ,Multi count" ",1 packet,2 packet,3 packet"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.byte 0x00 0.--6. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0xA30++0x03
|
|
line.long 0x00 "DIEPTSIZ9,OTG Device IN Endpoint-9 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " MCNT ,Multi count" ",1 packet,2 packet,3 packet"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.byte 0x00 0.--6. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0xA50++0x03
|
|
line.long 0x00 "DIEPTSIZ10,OTG Device IN Endpoint-10 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " MCNT ,Multi count" ",1 packet,2 packet,3 packet"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.byte 0x00 0.--6. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0xA70++0x03
|
|
line.long 0x00 "DIEPTSIZ11,OTG Device IN Endpoint-11 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " MCNT ,Multi count" ",1 packet,2 packet,3 packet"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.byte 0x00 0.--6. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0xA90++0x03
|
|
line.long 0x00 "DIEPTSIZ12,OTG Device IN Endpoint-12 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " MCNT ,Multi count" ",1 packet,2 packet,3 packet"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.byte 0x00 0.--6. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0xAB0++0x03
|
|
line.long 0x00 "DIEPTSIZ13,OTG Device IN Endpoint-13 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " MCNT ,Multi count" ",1 packet,2 packet,3 packet"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.byte 0x00 0.--6. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0xAD0++0x03
|
|
line.long 0x00 "DIEPTSIZ14,OTG Device IN Endpoint-14 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " MCNT ,Multi count" ",1 packet,2 packet,3 packet"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.byte 0x00 0.--6. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0xAF0++0x03
|
|
line.long 0x00 "DIEPTSIZ15,OTG Device IN Endpoint-15 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " MCNT ,Multi count" ",1 packet,2 packet,3 packet"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.byte 0x00 0.--6. 1. " XFRSIZ ,Transfer size"
|
|
rgroup.long 0x918++0x03
|
|
line.long 0x00 "DTXFSTS0,Device IN Endpoint Transmit FIFO Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint Tx FIFO space available"
|
|
rgroup.long 0x938++0x03
|
|
line.long 0x00 "DTXFSTS1,Device IN Endpoint Transmit FIFO Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint Tx FIFO space available"
|
|
rgroup.long 0x958++0x03
|
|
line.long 0x00 "DTXFSTS2,Device IN Endpoint Transmit FIFO Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint Tx FIFO space available"
|
|
rgroup.long 0x978++0x03
|
|
line.long 0x00 "DTXFSTS3,Device IN Endpoint Transmit FIFO Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint Tx FIFO space available"
|
|
rgroup.long 0x998++0x03
|
|
line.long 0x00 "DTXFSTS4,Device IN Endpoint Transmit FIFO Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint Tx FIFO space available"
|
|
rgroup.long 0x9B8++0x03
|
|
line.long 0x00 "DTXFSTS5,Device IN Endpoint Transmit FIFO Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint Tx FIFO space available"
|
|
rgroup.long 0x9D8++0x03
|
|
line.long 0x00 "DTXFSTS6,Device IN Endpoint Transmit FIFO Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint Tx FIFO space available"
|
|
rgroup.long 0x9F8++0x03
|
|
line.long 0x00 "DTXFSTS7,Device IN Endpoint Transmit FIFO Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint Tx FIFO space available"
|
|
rgroup.long 0xA18++0x03
|
|
line.long 0x00 "DTXFSTS8,Device IN Endpoint Transmit FIFO Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint Tx FIFO space available"
|
|
else
|
|
group.long 0x930++0x03
|
|
line.long 0x00 "DIEPTSIZ1,Device Endpoint-1 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " MCNT ,Multi count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0x950++0x03
|
|
line.long 0x00 "DIEPTSIZ2,Device Endpoint-2 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " MCNT ,Multi count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0x970++0x03
|
|
line.long 0x00 "DIEPTSIZ3,Device Endpoint-3 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " MCNT ,Multi count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0x990++0x03
|
|
line.long 0x00 "DIEPTSIZ4,Device Endpoint-4 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " MCNT ,Multi count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0x9B0++0x03
|
|
line.long 0x00 "DIEPTSIZ5,Device Endpoint-5 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " MCNT ,Multi count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0x9D0++0x03
|
|
line.long 0x00 "DIEPTSIZ6,Device Endpoint-6 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " MCNT ,Multi count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0x9F0++0x03
|
|
line.long 0x00 "DIEPTSIZ7,Device Endpoint-7 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " MCNT ,Multi count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0xA10++0x03
|
|
line.long 0x00 "DIEPTSIZ8,Device Endpoint-8 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " MCNT ,Multi count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
rgroup.long 0x918++0x03
|
|
line.long 0x00 "DTXFSTS0,Device IN Endpoint Transmit FIFO Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint Tx FIFO space available"
|
|
rgroup.long 0x938++0x03
|
|
line.long 0x00 "DTXFSTS1,Device IN Endpoint Transmit FIFO Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint Tx FIFO space available"
|
|
rgroup.long 0x958++0x03
|
|
line.long 0x00 "DTXFSTS2,Device IN Endpoint Transmit FIFO Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint Tx FIFO space available"
|
|
rgroup.long 0x978++0x03
|
|
line.long 0x00 "DTXFSTS3,Device IN Endpoint Transmit FIFO Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint Tx FIFO space available"
|
|
rgroup.long 0x998++0x03
|
|
line.long 0x00 "DTXFSTS4,Device IN Endpoint Transmit FIFO Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint Tx FIFO space available"
|
|
rgroup.long 0x9B8++0x03
|
|
line.long 0x00 "DTXFSTS5,Device IN Endpoint Transmit FIFO Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint Tx FIFO space available"
|
|
rgroup.long 0x9D8++0x03
|
|
line.long 0x00 "DTXFSTS6,Device IN Endpoint Transmit FIFO Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint Tx FIFO space available"
|
|
rgroup.long 0x9F8++0x03
|
|
line.long 0x00 "DTXFSTS7,Device IN Endpoint Transmit FIFO Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint Tx FIFO space available"
|
|
rgroup.long 0xA18++0x03
|
|
line.long 0x00 "DTXFSTS8,Device IN Endpoint Transmit FIFO Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint Tx FIFO space available"
|
|
endif
|
|
if (((per.l(ad:0x40040000+0xB30-0x10))&0xC0000)==0x40000)
|
|
group.long 0xB30++0x03
|
|
line.long 0x00 "DOEPTSIZ1,Device Endpoint-1 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
elif (((per.l(ad:0x40040000+0xB30-0x10))&0xC0000)==0x00)
|
|
group.long 0xB30++0x03
|
|
line.long 0x00 "DOEPTSIZ1,Device Endpoint-1 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
else
|
|
group.long 0xB30++0x03
|
|
line.long 0x00 "DOEPTSIZ1,Device Endpoint-1 Transfer Size Register"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
endif
|
|
if (((per.l(ad:0x40040000+0xB50-0x10))&0xC0000)==0x40000)
|
|
group.long 0xB50++0x03
|
|
line.long 0x00 "DOEPTSIZ2,Device Endpoint-2 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
elif (((per.l(ad:0x40040000+0xB50-0x10))&0xC0000)==0x00)
|
|
group.long 0xB50++0x03
|
|
line.long 0x00 "DOEPTSIZ2,Device Endpoint-2 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
else
|
|
group.long 0xB50++0x03
|
|
line.long 0x00 "DOEPTSIZ2,Device Endpoint-2 Transfer Size Register"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
endif
|
|
if (((per.l(ad:0x40040000+0xB70-0x10))&0xC0000)==0x40000)
|
|
group.long 0xB70++0x03
|
|
line.long 0x00 "DOEPTSIZ3,Device Endpoint-3 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
elif (((per.l(ad:0x40040000+0xB70-0x10))&0xC0000)==0x00)
|
|
group.long 0xB70++0x03
|
|
line.long 0x00 "DOEPTSIZ3,Device Endpoint-3 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
else
|
|
group.long 0xB70++0x03
|
|
line.long 0x00 "DOEPTSIZ3,Device Endpoint-3 Transfer Size Register"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
endif
|
|
if (((per.l(ad:0x40040000+0xB90-0x10))&0xC0000)==0x40000)
|
|
group.long 0xB90++0x03
|
|
line.long 0x00 "DOEPTSIZ4,Device Endpoint-4 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
elif (((per.l(ad:0x40040000+0xB90-0x10))&0xC0000)==0x00)
|
|
group.long 0xB90++0x03
|
|
line.long 0x00 "DOEPTSIZ4,Device Endpoint-4 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
else
|
|
group.long 0xB90++0x03
|
|
line.long 0x00 "DOEPTSIZ4,Device Endpoint-4 Transfer Size Register"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
endif
|
|
if (((per.l(ad:0x40040000+0xBB0-0x10))&0xC0000)==0x40000)
|
|
group.long 0xBB0++0x03
|
|
line.long 0x00 "DOEPTSIZ5,Device Endpoint-5 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
elif (((per.l(ad:0x40040000+0xBB0-0x10))&0xC0000)==0x00)
|
|
group.long 0xBB0++0x03
|
|
line.long 0x00 "DOEPTSIZ5,Device Endpoint-5 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
else
|
|
group.long 0xBB0++0x03
|
|
line.long 0x00 "DOEPTSIZ5,Device Endpoint-5 Transfer Size Register"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
endif
|
|
if (((per.l(ad:0x40040000+0xBD0-0x10))&0xC0000)==0x40000)
|
|
group.long 0xBD0++0x03
|
|
line.long 0x00 "DOEPTSIZ6,Device Endpoint-6 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
elif (((per.l(ad:0x40040000+0xBD0-0x10))&0xC0000)==0x00)
|
|
group.long 0xBD0++0x03
|
|
line.long 0x00 "DOEPTSIZ6,Device Endpoint-6 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
else
|
|
group.long 0xBD0++0x03
|
|
line.long 0x00 "DOEPTSIZ6,Device Endpoint-6 Transfer Size Register"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
endif
|
|
if (((per.l(ad:0x40040000+0xBF0-0x10))&0xC0000)==0x40000)
|
|
group.long 0xBF0++0x03
|
|
line.long 0x00 "DOEPTSIZ7,Device Endpoint-7 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
elif (((per.l(ad:0x40040000+0xBF0-0x10))&0xC0000)==0x00)
|
|
group.long 0xBF0++0x03
|
|
line.long 0x00 "DOEPTSIZ7,Device Endpoint-7 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
else
|
|
group.long 0xBF0++0x03
|
|
line.long 0x00 "DOEPTSIZ7,Device Endpoint-7 Transfer Size Register"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
endif
|
|
if (((per.l(ad:0x40040000+0xC10-0x10))&0xC0000)==0x40000)
|
|
group.long 0xC10++0x03
|
|
line.long 0x00 "DOEPTSIZ8,Device Endpoint-8 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
elif (((per.l(ad:0x40040000+0xC10-0x10))&0xC0000)==0x00)
|
|
group.long 0xC10++0x03
|
|
line.long 0x00 "DOEPTSIZ8,Device Endpoint-8 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
else
|
|
group.long 0xC10++0x03
|
|
line.long 0x00 "DOEPTSIZ8,Device Endpoint-8 Transfer Size Register"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
endif
|
|
else
|
|
hgroup.long 0x800++0x03
|
|
hide.long 0x00 "DCFG,Device Configuration Register"
|
|
hgroup.long 0x804++0x03
|
|
hide.long 0x00 "DCTL,Device Control Register"
|
|
hgroup.long 0x808++0x03
|
|
hide.long 0x00 "DSTS,Device Status Register"
|
|
hgroup.long 0x810++0x03
|
|
hide.long 0x00 "DIEPMSK,Device IN Endpoint Common Interrupt Mask Register"
|
|
hgroup.long 0x814++0x03
|
|
hide.long 0x00 "DOEPMSK,Device OUT Endpoint Common Interrupt Mask Register"
|
|
hgroup.long 0x818++0x03
|
|
hide.long 0x00 "DAINT,Device All Endpoints Interrupt Register"
|
|
hgroup.long 0x81C++0x03
|
|
hide.long 0x00 "DAINTMSK,All Endpoints Interrupt Mask Register"
|
|
hgroup.long 0x828++0x03
|
|
hide.long 0x00 "DVBUSDIS,Device VBUS Discharge Time Register"
|
|
hgroup.long 0x82C++0x03
|
|
hide.long 0x00 "DVBUSPULSE,Device VBUS Pulsing Time Register"
|
|
hgroup.long 0x830++0x03
|
|
hide.long 0x00 "DTHRCTL,Device Threshold Control Register"
|
|
hgroup.long 0x838++0x03
|
|
hide.long 0x00 "DEACHINT,Device Each Endpoint Interrupt Register"
|
|
hgroup.long 0x834++0x03
|
|
hide.long 0x00 "DIEPEMPMSK,Device IN Endpoint FIFO Empty Interrupt Mask Register"
|
|
hgroup.long 0x83C++0x03
|
|
hide.long 0x00 "DEACHINTMSK,OTG Device Each Endpoint Interrupt Register Mask"
|
|
hgroup.long 0x900++0x03
|
|
hide.long 0x00 "DIEPCTL1,OTG Device Endpoint-1 Control Register"
|
|
hgroup.long 0x920++0x03
|
|
hide.long 0x00 "DIEPCTL2,OTG Device Endpoint-2 Control Register"
|
|
hgroup.long 0x940++0x03
|
|
hide.long 0x00 "DIEPCTL3,OTG Device Endpoint-3 Control Register"
|
|
hgroup.long 0x960++0x03
|
|
hide.long 0x00 "DIEPCTL4,OTG Device Endpoint-4 Control Register"
|
|
hgroup.long 0x980++0x03
|
|
hide.long 0x00 "DIEPCTL5,OTG Device Endpoint-5 Control Register"
|
|
hgroup.long 0x9A0++0x03
|
|
hide.long 0x00 "DIEPCTL6,OTG Device Endpoint-6 Control Register"
|
|
hgroup.long 0x9C0++0x03
|
|
hide.long 0x00 "DIEPCTL7,OTG Device Endpoint-7 Control Register"
|
|
hgroup.long 0x9E0++0x03
|
|
hide.long 0x00 "DIEPCTL8,OTG Device Endpoint-8 Control Register"
|
|
hgroup.long 0xA00++0x03
|
|
hide.long 0x00 "DIEPCTL9,OTG Device Endpoint-9 Control Register"
|
|
hgroup.long 0xB00++0x03
|
|
hide.long 0x00 "DOEPCTL0,Device Control OUT Endpoint 0 Control Register"
|
|
hgroup.long 0xB20++0x03
|
|
hide.long 0x00 "DOEPCTL1,Device Endpoint-1 Control Register"
|
|
hgroup.long 0xB40++0x03
|
|
hide.long 0x00 "DOEPCTL2,Device Endpoint-2 Control Register"
|
|
hgroup.long 0xB60++0x03
|
|
hide.long 0x00 "DOEPCTL3,Device Endpoint-3 Control Register"
|
|
hgroup.long 0xB80++0x03
|
|
hide.long 0x00 "DOEPCTL4,Device Endpoint-4 Control Register"
|
|
hgroup.long 0xBA0++0x03
|
|
hide.long 0x00 "DOEPCTL5,Device Endpoint-5 Control Register"
|
|
hgroup.long 0xBC0++0x03
|
|
hide.long 0x00 "DOEPCTL6,Device Endpoint-6 Control Register"
|
|
hgroup.long 0xBE0++0x03
|
|
hide.long 0x00 "DOEPCTL7,Device Endpoint-7 Control Register"
|
|
hgroup.long 0xC00++0x03
|
|
hide.long 0x00 "DOEPCTL8,Device Endpoint-8 Control Register"
|
|
hgroup.long 0x908++0x03
|
|
hide.long 0x00 "DIEPINT0,Device Endpoint-0 Interrupt Register"
|
|
hgroup.long 0x928++0x03
|
|
hide.long 0x00 "DIEPINT1,Device Endpoint-1 Interrupt Register"
|
|
hgroup.long 0x948++0x03
|
|
hide.long 0x00 "DIEPINT2,Device Endpoint-2 Interrupt Register"
|
|
hgroup.long 0x968++0x03
|
|
hide.long 0x00 "DIEPINT3,Device Endpoint-3 Interrupt Register"
|
|
hgroup.long 0x988++0x03
|
|
hide.long 0x00 "DIEPINT4,Device Endpoint-4 Interrupt Register"
|
|
hgroup.long 0x9A8++0x03
|
|
hide.long 0x00 "DIEPINT5,Device Endpoint-5 Interrupt Register"
|
|
hgroup.long 0x9C8++0x03
|
|
hide.long 0x00 "DIEPINT6,Device Endpoint-6 Interrupt Register"
|
|
hgroup.long 0x9E8++0x03
|
|
hide.long 0x00 "DIEPINT7,Device Endpoint-7 Interrupt Register"
|
|
hgroup.long 0xA08++0x03
|
|
hide.long 0x00 "DIEPINT8,Device Endpoint-8 Interrupt Register"
|
|
hgroup.long 0xB08++0x03
|
|
hide.long 0x00 "DOEPINT0,Device Endpoint-0 Interrupt Register"
|
|
hgroup.long 0xB28++0x03
|
|
hide.long 0x00 "DOEPINT1,Device Endpoint-1 Interrupt Register"
|
|
hgroup.long 0xB48++0x03
|
|
hide.long 0x00 "DOEPINT2,Device Endpoint-2 Interrupt Register"
|
|
hgroup.long 0xB68++0x03
|
|
hide.long 0x00 "DOEPINT3,Device Endpoint-3 Interrupt Register"
|
|
hgroup.long 0xB88++0x03
|
|
hide.long 0x00 "DOEPINT4,Device Endpoint-4 Interrupt Register"
|
|
hgroup.long 0xBA8++0x03
|
|
hide.long 0x00 "DOEPINT5,Device Endpoint-5 Interrupt Register"
|
|
hgroup.long 0xBC8++0x03
|
|
hide.long 0x00 "DOEPINT6,Device Endpoint-6 Interrupt Register"
|
|
hgroup.long 0xBE8++0x03
|
|
hide.long 0x00 "DOEPINT7,Device Endpoint-7 Interrupt Register"
|
|
hgroup.long 0xC08++0x03
|
|
hide.long 0x00 "DOEPINT8,Device Endpoint-8 Interrupt Register"
|
|
hgroup.long 0x910++0x03
|
|
hide.long 0x00 "DIEPTSIZ0,Device IN Endpoint 0 Transfer Size Register"
|
|
hgroup.long 0x914++0x03
|
|
hide.long 0x00 "DIEPDMA0,OTG Device Channel-0 DMA Address Register"
|
|
hgroup.long 0x934++0x03
|
|
hide.long 0x00 "DIEPDMA1,OTG Device Channel-1 DMA Address Register"
|
|
hgroup.long 0x954++0x03
|
|
hide.long 0x00 "DIEPDMA2,OTG Device Channel-2 DMA Address Register"
|
|
hgroup.long 0x974++0x03
|
|
hide.long 0x00 "DIEPDMA3,OTG Device Channel-3 DMA Address Register"
|
|
hgroup.long 0x994++0x03
|
|
hide.long 0x00 "DIEPDMA4,OTG Device Channel-4 DMA Address Register"
|
|
hgroup.long 0x9B4++0x03
|
|
hide.long 0x00 "DIEPDMA5,OTG Device Channel-5 DMA Address Register"
|
|
hgroup.long 0x9D4++0x03
|
|
hide.long 0x00 "DIEPDMA6,OTG Device Channel-6 DMA Address Register"
|
|
hgroup.long 0x9F4++0x03
|
|
hide.long 0x00 "DIEPDMA7,OTG Device Channel-7 DMA Address Register"
|
|
hgroup.long 0xA14++0x03
|
|
hide.long 0x00 "DIEPDMA8,OTG Device Channel-8 DMA Address Register"
|
|
hgroup.long 0xA34++0x03
|
|
hide.long 0x00 "DIEPDMA9,OTG Device Channel-9 DMA Address Register"
|
|
hgroup.long 0xA54++0x03
|
|
hide.long 0x00 "DIEPDMA10,OTG Device Channel-10 DMA Address Register"
|
|
hgroup.long 0xA74++0x03
|
|
hide.long 0x00 "DIEPDMA11,OTG Device Channel-11 DMA Address Register"
|
|
hgroup.long 0xA94++0x03
|
|
hide.long 0x00 "DIEPDMA12,OTG Device Channel-12 DMA Address Register"
|
|
hgroup.long 0xAB4++0x03
|
|
hide.long 0x00 "DIEPDMA13,OTG Device Channel-13 DMA Address Register"
|
|
hgroup.long 0xAD4++0x03
|
|
hide.long 0x00 "DIEPDMA14,OTG Device Channel-14 DMA Address Register"
|
|
hgroup.long 0xAF4++0x03
|
|
hide.long 0x00 "DIEPDMA15,OTG Device Channel-15 DMA Address Register"
|
|
hgroup.long 0xB14++0x03
|
|
hide.long 0x00 "DOEPDMA0,OTG Device Channel-0 DMA Address Register"
|
|
hgroup.long 0xB34++0x03
|
|
hide.long 0x00 "DOEPDMA1,OTG Device Channel-1 DMA Address Register"
|
|
hgroup.long 0xB54++0x03
|
|
hide.long 0x00 "DOEPDMA2,OTG Device Channel-2 DMA Address Register"
|
|
hgroup.long 0xB74++0x03
|
|
hide.long 0x00 "DOEPDMA3,OTG Device Channel-3 DMA Address Register"
|
|
hgroup.long 0xB94++0x03
|
|
hide.long 0x00 "DOEPDMA4,OTG Device Channel-4 DMA Address Register"
|
|
hgroup.long 0xBB4++0x03
|
|
hide.long 0x00 "DOEPDMA5,OTG Device Channel-5 DMA Address Register"
|
|
hgroup.long 0xBD4++0x03
|
|
hide.long 0x00 "DOEPDMA6,OTG Device Channel-6 DMA Address Register"
|
|
hgroup.long 0xBF4++0x03
|
|
hide.long 0x00 "DOEPDMA7,OTG Device Channel-7 DMA Address Register"
|
|
hgroup.long 0xC14++0x03
|
|
hide.long 0x00 "DOEPDMA8,OTG Device Channel-8 DMA Address Register"
|
|
hgroup.long 0xC34++0x03
|
|
hide.long 0x00 "DOEPDMA9,OTG Device Channel-9 DMA Address Register"
|
|
hgroup.long 0xC54++0x03
|
|
hide.long 0x00 "DOEPDMA10,OTG Device Channel-10 DMA Address Register"
|
|
hgroup.long 0xC74++0x03
|
|
hide.long 0x00 "DOEPDMA11,OTG Device Channel-11 DMA Address Register"
|
|
hgroup.long 0xC94++0x03
|
|
hide.long 0x00 "DOEPDMA12,OTG Device Channel-12 DMA Address Register"
|
|
hgroup.long 0xCB4++0x03
|
|
hide.long 0x00 "DOEPDMA13,OTG Device Channel-13 DMA Address Register"
|
|
hgroup.long 0xCD4++0x03
|
|
hide.long 0x00 "DOEPDMA14,OTG Device Channel-14 DMA Address Register"
|
|
hgroup.long 0xCF4++0x03
|
|
hide.long 0x00 "DOEPDMA15,OTG Device Channel-15 DMA Address Register"
|
|
hgroup.long 0x930++0x03
|
|
hide.long 0x00 "DIEPTSIZ1,Device Endpoint-1 Transfer Size Register"
|
|
hgroup.long 0x950++0x03
|
|
hide.long 0x00 "DIEPTSIZ2,Device Endpoint-2 Transfer Size Register"
|
|
hgroup.long 0x970++0x03
|
|
hide.long 0x00 "DIEPTSIZ3,Device Endpoint-3 Transfer Size Register"
|
|
hgroup.long 0x990++0x03
|
|
hide.long 0x00 "DIEPTSIZ4,Device Endpoint-4 Transfer Size Register"
|
|
hgroup.long 0x9B0++0x03
|
|
hide.long 0x00 "DIEPTSIZ5,Device Endpoint-5 Transfer Size Register"
|
|
hgroup.long 0x9D0++0x03
|
|
hide.long 0x00 "DIEPTSIZ6,Device Endpoint-6 Transfer Size Register"
|
|
hgroup.long 0x9F0++0x03
|
|
hide.long 0x00 "DIEPTSIZ7,Device Endpoint-7 Transfer Size Register"
|
|
hgroup.long 0xA10++0x03
|
|
hide.long 0x00 "DIEPTSIZ8,Device Endpoint-8 Transfer Size Register"
|
|
hgroup.long 0x918++0x03
|
|
hide.long 0x00 "DTXFSTS0,Device IN Endpoint Transmit FIFO Status Register"
|
|
hgroup.long 0x938++0x03
|
|
hide.long 0x00 "DTXFSTS1,Device IN Endpoint Transmit FIFO Status Register"
|
|
hgroup.long 0x958++0x03
|
|
hide.long 0x00 "DTXFSTS2,Device IN Endpoint Transmit FIFO Status Register"
|
|
hgroup.long 0x978++0x03
|
|
hide.long 0x00 "DTXFSTS3,Device IN Endpoint Transmit FIFO Status Register"
|
|
hgroup.long 0x998++0x03
|
|
hide.long 0x00 "DTXFSTS4,Device IN Endpoint Transmit FIFO Status Register"
|
|
hgroup.long 0x9B8++0x03
|
|
hide.long 0x00 "DTXFSTS5,Device IN Endpoint Transmit FIFO Status Register"
|
|
hgroup.long 0x9D8++0x03
|
|
hide.long 0x00 "DTXFSTS6,Device IN Endpoint Transmit FIFO Status Register"
|
|
hgroup.long 0x9F8++0x03
|
|
hide.long 0x00 "DTXFSTS7,Device IN Endpoint Transmit FIFO Status Register"
|
|
hgroup.long 0xA18++0x03
|
|
hide.long 0x00 "DTXFSTS8,Device IN Endpoint Transmit FIFO Status Register"
|
|
hgroup.long 0xB10++0x03
|
|
hide.long 0x00 "DOEPTSIZ0,Device Endpoint-0 Transfer Size Register"
|
|
hgroup.long 0xB30++0x03
|
|
hide.long 0x00 "DOEPTSIZ1,Device Endpoint-1 Transfer Size Register"
|
|
hgroup.long 0xB50++0x03
|
|
hide.long 0x00 "DOEPTSIZ2,Device Endpoint-2 Transfer Size Register"
|
|
hgroup.long 0xB70++0x03
|
|
hide.long 0x00 "DOEPTSIZ3,Device Endpoint-3 Transfer Size Register"
|
|
hgroup.long 0xB90++0x03
|
|
hide.long 0x00 "DOEPTSIZ4,Device Endpoint-4 Transfer Size Register"
|
|
hgroup.long 0xBB0++0x03
|
|
hide.long 0x00 "DOEPTSIZ5,Device Endpoint-5 Transfer Size Register"
|
|
hgroup.long 0xBD0++0x03
|
|
hide.long 0x00 "DOEPTSIZ6,Device Endpoint-6 Transfer Size Register"
|
|
hgroup.long 0xBF0++0x03
|
|
hide.long 0x00 "DOEPTSIZ7,Device Endpoint-7 Transfer Size Register"
|
|
hgroup.long 0xC10++0x03
|
|
hide.long 0x00 "DOEPTSIZ8,Device Endpoint-8 Transfer Size Register"
|
|
endif
|
|
tree.end
|
|
width 9.
|
|
tree "Power and clock gating control and status registers"
|
|
group.long 0xE00++0x03
|
|
line.long 0x00 "PCGCCTL,Power And Clock Gating Control Register"
|
|
rbitfld.long 0x00 7. " SUSP ,Deep sleep" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " PHYSLEEP ,PHY in sleep" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ENL1GTG ,Enable sleep clock gating" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " PHYSUSP ,PHY suspended" "Not suspended,Suspended"
|
|
newline
|
|
bitfld.long 0x00 1. " GATEHCLK ,Gate HCLK" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " STPPCLK ,Stop PHY clock" "Not stopped,Stopped"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
sif (!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
tree "ETH (Ethernet)"
|
|
base ad:0x40028000
|
|
width 11.
|
|
tree "MAC Registers"
|
|
if (((per.l((ad:0x40028000+0x00)))&0x800)==0x800)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MACCR,Ethernet MAC Configuration Register"
|
|
bitfld.long 0x00 25. " CSTF ,CRC stripping for type frames" "Not stripped,Stripped"
|
|
bitfld.long 0x00 23. " WD ,Watchdog disable" "No,Yes"
|
|
bitfld.long 0x00 22. " JD ,Jabber disable" "No,Yes"
|
|
bitfld.long 0x00 17.--19. " IFG ,Interframe gap" "96 bit,88 bit,80 bit,72 bit,64 bit,56 bit,48 bit,40 bit"
|
|
newline
|
|
bitfld.long 0x00 16. " CSD ,Carrier sense disable" "No,Yes"
|
|
bitfld.long 0x00 14. " FES ,Fast ethernet speed" "10 Mbit/s,100 Mbit/s"
|
|
textfld " "
|
|
bitfld.long 0x00 12. " LM ,Loopback mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " DM ,Duplex mode" "Half-Duplex,Full-Duplex"
|
|
bitfld.long 0x00 10. " IPCO ,IPv4 checksum offload" "Disabled,Enabled"
|
|
textfld " "
|
|
bitfld.long 0x00 7. " APCS ,Automatic pad/CRC stripping" "No stripping,< 1501 bytes"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MACCR,Ethernet MAC Configuration Register"
|
|
bitfld.long 0x00 25. " CSTF ,CRC stripping for type frames" "Not stripped,Stripped"
|
|
bitfld.long 0x00 23. " WD ,Watchdog disable" "No,Yes"
|
|
bitfld.long 0x00 22. " JD ,Jabber disable" "No,Yes"
|
|
bitfld.long 0x00 17.--19. " IFG ,Interframe gap" "96 bit,88 bit,80 bit,72 bit,64 bit,?..."
|
|
newline
|
|
bitfld.long 0x00 16. " CSD ,Carrier sense disable" "No,Yes"
|
|
bitfld.long 0x00 14. " FES ,Fast ethernet speed" "10 Mbit/s,100 Mbit/s"
|
|
bitfld.long 0x00 13. " ROD ,Receive own disable" "No,Yes"
|
|
bitfld.long 0x00 12. " LM ,Loopback mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " DM ,Duplex mode" "Half-Duplex,Full-Duplex"
|
|
bitfld.long 0x00 10. " IPCO ,IPv4 checksum offload" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RD ,Retry disable" "No,Yes"
|
|
bitfld.long 0x00 7. " APCS ,Automatic pad/CRC stripping" "No stripping,< 1501 bytes"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " BL ,Back-off limit" "K = min (n.10),K = min (n.8),K = min (n.4),K = min (n.1)"
|
|
bitfld.long 0x00 4. " DC ,Deferral check" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40028000+0x18))&0x04)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MACFFR,Ethernet MAC Frame Filter Register"
|
|
bitfld.long 0x00 31. " RA ,Receive all" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " HPF ,Hash or perfect filter" "Hash,Hash/Perfect"
|
|
bitfld.long 0x00 9. " SAF ,Source address filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SAIF ,Source address inverse filtering" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " PCF ,Pass control frames" "Filters all,Filters pause frames,Forwards all,Forwards frames that pass"
|
|
bitfld.long 0x00 5. " BFD ,Broadcast frames disable" "No,Yes"
|
|
bitfld.long 0x00 4. " PAM ,Pass all multicast" "Filtered,Passed"
|
|
bitfld.long 0x00 3. " DAIF ,Destination address inverse filtering" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 2. " HM ,Hash multicast" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HU ,Hash unicast" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PM ,Promiscuous mode" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MACFFR,Ethernet MAC Frame Filter Register"
|
|
bitfld.long 0x00 31. " RA ,Receive all" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " HPF ,Hash or perfect filter" "Hash,Hash/Perfect"
|
|
bitfld.long 0x00 9. " SAF ,Source address filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SAIF ,Source address inverse filtering" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " PCF ,Pass control frames" "Filters all,Filters all,Forwards all,Forwards frames that pass"
|
|
bitfld.long 0x00 5. " BFD ,Broadcast frames disable" "No,Yes"
|
|
bitfld.long 0x00 4. " PAM ,Pass all multicast" "Filtered,Passed"
|
|
bitfld.long 0x00 3. " DAIF ,Destination address inverse filtering" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 2. " HM ,Hash multicast" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HU ,Hash unicast" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PM ,Promiscuous mode" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x08++0x0F
|
|
line.long 0x00 "MACHTHR,Ethernet MAC Hash Table High Register"
|
|
line.long 0x04 "MACHTLR,Ethernet MAC Hash Table Low Register"
|
|
line.long 0x08 "MACMIIAR,Ethernet MAC MII Address Register"
|
|
bitfld.long 0x08 11.--15. " PA ,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 6.--10. " MR ,MII register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 2.--4. " CR ,Clock range (HCLK/MDC clock)" "60-100 MHz/HCLK/42,100-150 MHz/HCLK/62,20-35 MHz/HCLK/16,35-60 MHz/HCLK/26,150-216/HCLK/102,?..."
|
|
bitfld.long 0x08 1. " MW ,MII write" "Read,Write"
|
|
newline
|
|
eventfld.long 0x08 0. " MB ,MII busy" "Not busy,Busy"
|
|
line.long 0x0C "MACMIIDR,Ethernet MAC MII Data Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " MD ,MII data"
|
|
if (((per.l((ad:0x40028000+0x00)))&0x800)==0x800)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "MACFCR,Ethernet MAC Flow Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " PT ,Pause time"
|
|
bitfld.long 0x00 7. " ZQPD ,Zero-quanta pause disable" "No,Yes"
|
|
bitfld.long 0x00 4.--5. " PLT ,Pause low threshold" "4 slot,28 slot,144 slot,256 slot"
|
|
bitfld.long 0x00 3. " UPFD ,Unicast pause frame detect" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 2. " RFCE ,Receive flow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TFCE ,Transmit flow control enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " FCB ,Flow control busy" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "MACFCR,Ethernet MAC Flow Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " PT ,Pause time"
|
|
bitfld.long 0x00 7. " ZQPD ,Zero-quanta pause disable" "No,Yes"
|
|
bitfld.long 0x00 4.--5. " PLT ,Pause low threshold" "4 slot,28 slot,144 slot,256 slot"
|
|
bitfld.long 0x00 3. " UPFD ,Unicast pause frame detect" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 2. " RFCE ,Receive flow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TFCE ,Transmit flow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BPA ,Back pressure activate" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "MACVLANTR,Ethernet MAC VLAN Tag Register"
|
|
bitfld.long 0x00 16. " VLANTC ,12-bit VLAN tag comparison" "16-bits,12-bits"
|
|
hexmask.long.word 0x00 0.--15. 1. " VLANTI ,VLAN tag identifier (for receive frames)"
|
|
newline
|
|
hgroup.long 0x28++0x03
|
|
hide.long 0x00 "MACRWUFFR,Ethernet MAC Remote Wakeup Frame Filter Register"
|
|
in
|
|
newline
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "MACPMTCSR,Ethernet MAC PMT Control And Status Register"
|
|
in
|
|
newline
|
|
if (((per.l((ad:0x40028000+0x00)))&0x800)==0x800)
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "MACDBGR,Ethernet MAC Debug Register"
|
|
bitfld.long 0x00 25. " TFF ,TX FIFO full" "Not full,Full"
|
|
bitfld.long 0x00 24. " TFNE ,TX FIFO not empty" "Empty,Not empty"
|
|
bitfld.long 0x00 22. " TFWA ,TX FIFO write active" "Not activated,Activated"
|
|
bitfld.long 0x00 20.--21. " TFRS ,TX FIFO read status" "Idle,Read,Waiting,Writing"
|
|
newline
|
|
bitfld.long 0x00 19. " MTP ,MAC transmitter in pause" "Not paused,Paused"
|
|
bitfld.long 0x00 17.--18. " MTFCS ,MAC transmit frame controller status" "Idle,Waiting,Generating,Transferring"
|
|
bitfld.long 0x00 16. " MMTEA ,MAC MII transmit engine active" "Not activated,Activated"
|
|
bitfld.long 0x00 8.--9. " RFFL ,RX FIFO fill level" "Empty,Below flow-control,Above flow-control,Full"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " RFRCS ,RX FIFO read controller status" "Idle,Reading data,Reading status,Flushing"
|
|
bitfld.long 0x00 4. " RFWRA ,RX FIFO write controller active" "Not activated,Activated"
|
|
bitfld.long 0x00 1.--2. " MSFRWCS ,MAC small FIFO read/write controllers status" "0,1,2,3"
|
|
bitfld.long 0x00 0. " MMRPEA ,MAC MII receive protocol engine active" "Not activated,Activated"
|
|
else
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "MACDBGR,Ethernet MAC Debug Register"
|
|
bitfld.long 0x00 25. " TFF ,TX FIFO full" "Not full,Full"
|
|
bitfld.long 0x00 24. " TFNE ,TX FIFO not empty" "Empty,Not empty"
|
|
bitfld.long 0x00 22. " TFWA ,TX FIFO write active" "Not activated,Activated"
|
|
bitfld.long 0x00 20.--21. " TFRS ,TX FIFO read status" "Idle,Read,Waiting,Writing"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 17.--18. " MTFCS ,MAC transmit frame controller status" "Idle,Waiting,,Transferring"
|
|
bitfld.long 0x00 16. " MMTEA ,MAC MII transmit engine active" "Not activated,Activated"
|
|
bitfld.long 0x00 8.--9. " RFFL ,RX FIFO fill level" "Empty,Below flow-control,Above flow-control,Full"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " RFRCS ,RX FIFO read controller status" "Idle,Reading data,Reading status,Flushing"
|
|
bitfld.long 0x00 4. " RFWRA ,RX FIFO write controller active" "Not activated,Activated"
|
|
bitfld.long 0x00 1.--2. " MSFRWCS ,MAC small FIFO read/write controllers status" "0,1,2,3"
|
|
bitfld.long 0x00 0. " MMRPEA ,MAC MII receive protocol engine active" "Not activated,Activated"
|
|
newline
|
|
endif
|
|
hgroup.word 0x38++0x01
|
|
hide.word 0x00 "MACSR,Ethernet MAC Interrupt Status Register"
|
|
in
|
|
newline
|
|
width 9.
|
|
group.word 0x3C++0x01
|
|
line.word 0x00 "MACIMR,Ethernet MAC Interrupt Mask Register"
|
|
bitfld.word 0x00 9. " TSTIM ,Time stamp trigger interrupt mask" "Not masked,Masked"
|
|
bitfld.word 0x00 3. " PMTIM ,PMT interrupt mask" "Not masked,Masked"
|
|
group.long 0x40++0x1F
|
|
line.long 0x00 "MACA0HR,Ethernet MAC Address 0 High Register"
|
|
bitfld.long 0x00 31. " MO ,MO" "Low,High"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " MACA0H ,MAC address0 high [32:47]"
|
|
line.long 0x04 "MACA0LR,Ethernet MAC Address 0 Low Register"
|
|
line.long 0x08 "MACA1HR,Ethernet MAC Address 1 High Register"
|
|
bitfld.long 0x08 31. " AE ,Address enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " SA ,Source address" "DA,SA"
|
|
bitfld.long 0x08 29. " MBC[5] ,Mask MAC address1 HR[8:15]" "Not masked,Masked"
|
|
bitfld.long 0x08 28. " [4] ,Mask MAC address1 HR[0:7]" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 27. " [3] ,Mask MAC address1 LR[24:31]" "Not masked,Masked"
|
|
bitfld.long 0x08 26. " [2] ,Mask MAC address1 LR[16:23]" "Not masked,Masked"
|
|
bitfld.long 0x08 25. " [1] ,Mask mask MAC address1 LR[8:15]" "Not masked,Masked"
|
|
bitfld.long 0x08 24. " [0] ,Mask MAC address1 LR[0:7]" "Not masked,Masked"
|
|
newline
|
|
hexmask.long.word 0x08 0.--15. 0x01 " MACA1H ,MAC address1 high [32:47]"
|
|
line.long 0x0C "MACA1LR,Ethernet MAC Address 1 Low Register"
|
|
line.long 0x10 "MACA2HR,Ethernet MAC Address 2 High Register"
|
|
bitfld.long 0x10 31. " AE ,Address enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " SA ,Source address" "DA,SA"
|
|
bitfld.long 0x10 29. " MBC[5] ,Mask MAC address2 HR[8:15]" "Not masked,Masked"
|
|
bitfld.long 0x10 28. " [4] ,Mask MAC address2 HR[0:7]" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x10 27. " [3] ,Mask MAC address2 LR[24:31]" "Not masked,Masked"
|
|
bitfld.long 0x10 26. " [2] ,Mask MAC address2 LR[16:23]" "Not masked,Masked"
|
|
bitfld.long 0x10 25. " [1] ,Mask MAC address2 LR[8:15]" "Not masked,Masked"
|
|
bitfld.long 0x10 24. " [0] ,Mask MAC address2 LR[0:7]" "Not masked,Masked"
|
|
newline
|
|
hexmask.long.word 0x10 0.--15. 0x01 " MACA2H ,MAC address2 high [47:32]"
|
|
line.long 0x14 "MACA2LR,Ethernet MAC Address 2 Low Register"
|
|
line.long 0x18 "MACA3HR,Ethernet MAC Address 3 High Register"
|
|
bitfld.long 0x18 31. " AE ,Address enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 30. " SA ,Source address" "DA,SA"
|
|
bitfld.long 0x18 29. " MBC[5] ,Mask MAC address3 HR[8:15]" "Not masked,Masked"
|
|
bitfld.long 0x18 28. " [4] ,Mask MAC address3 HR[0:7]" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x18 27. " [3] ,Mask MAC address3 LR[24:31]" "Not masked,Masked"
|
|
bitfld.long 0x18 26. " [2] ,Mask MAC address3 LR[16:23]" "Not masked,Masked"
|
|
bitfld.long 0x18 25. " [1] ,Mask mask MAC address3 LR[8:15]" "Not masked,Masked"
|
|
bitfld.long 0x18 24. " [0] ,Mask MAC address3 LR[0:7]" "Not masked,Masked"
|
|
newline
|
|
hexmask.long.word 0x18 0.--15. 0x01 " MACA3H ,MAC address3 high [32:47]"
|
|
line.long 0x1C "MACA3LR,Ethernet MAC Address 3 Low Register"
|
|
tree.end
|
|
width 13.
|
|
tree "MMC Registers"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "MMCCR,Ethernet MMC Control Register"
|
|
bitfld.long 0x00 5. " MCFHP ,MMC counter full-half preset" "Not preset,Preset"
|
|
bitfld.long 0x00 4. " MCP ,MMC counter preset" "Not preset,Preset"
|
|
bitfld.long 0x00 3. " MCF ,MMC counter freeze" "Normal,Frozen"
|
|
newline
|
|
bitfld.long 0x00 2. " ROR ,Reset on read" "No reset,Reset"
|
|
bitfld.long 0x00 1. " CSR ,Counter stop rollover" "Not stopped,Stopped"
|
|
bitfld.long 0x00 0. " CR ,Counter reset" "No reset,Reset"
|
|
newline
|
|
hgroup.long 0x104++0x03
|
|
hide.long 0x00 "MMCRIR,Ethernet MMC Receive Interrupt Register"
|
|
in
|
|
newline
|
|
hgroup.long 0x108++0x03
|
|
hide.long 0x00 "MMCTIR,Ethernet MMC Transmit Interrupt Register"
|
|
in
|
|
newline
|
|
group.long 0x10C++0x07
|
|
line.long 0x00 "MMCRIMR,Ethernet MMC Receive Interrupt Mask Register"
|
|
bitfld.long 0x00 17. " RGUFM ,Received good unicast frames mask" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " RFAEM ,Received frames alignment error mask" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " RFCEM ,Received frame CRC error mask" "Not masked,Masked"
|
|
line.long 0x04 "MMCTIMR,Ethernet MMC Transmit Interrupt Mask Register"
|
|
bitfld.long 0x04 21. " TGFM ,Transmitted good frames mask" "Not masked,Masked"
|
|
bitfld.long 0x04 15. " TGFMSCM ,Transmitted good frames more single collision mask" "Not masked,Masked"
|
|
bitfld.long 0x04 14. " TGFSCM ,Transmitted good frames single collision mask" "Not masked,Masked"
|
|
rgroup.long 0x14C++0x07
|
|
line.long 0x00 "MMCTGFSCCR,Ethernet MMC Transmitted Good Frames After A Single Collision Counter Register"
|
|
line.long 0x04 "MMCTGFMSCCR,Ethernet MMC Transmitted Good Frames After More Than A Single Collision Counter Register"
|
|
rgroup.long 0x168++0x03
|
|
line.long 0x00 "MMCTGFCR,Ethernet MMC Transmitted Good Frames Counter Register"
|
|
rgroup.long 0x194++0x07
|
|
line.long 0x00 "MMCRFCECR,Ethernet MMC Received Frames With CRC Error Counter Register"
|
|
line.long 0x04 "MMCRFAECR,Ethernet MMC Received Frames With Alignment Error Counter Register"
|
|
rgroup.long 0x1C4++0x03
|
|
line.long 0x00 "MMCRGUFCR,MMC Received Good Unicast Frames Counter Register"
|
|
tree.end
|
|
width 10.
|
|
tree "IEEE 1588 Time Stamp Registers"
|
|
if (((per.l(ad:0x40028000+0x700))&0x30000)<=0x10000)
|
|
group.long 0x700++0x03
|
|
line.long 0x00 "PTPTSCR,Ethernet PTP Time Stamp Control Register"
|
|
bitfld.long 0x00 18. " TSPFFMAE ,Time stamp PTP frame filtering MAC address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " TSCNT ,Time stamp clock node type" "Ordinary,Boundary,End-to-end,Peer-to-peer"
|
|
bitfld.long 0x00 15. " TSSMRME ,Time stamp snapshot for message relevant to master enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TSSEME ,Time stamp snapshot for event message enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " TSSIPV4FE ,Time stamp snapshot for IPv4 frames enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " TSSIPV6FE ,Time stamp snapshot for IPv6 frames enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TSSPTPOEFE ,Time stamp snapshot for PTP over ethernet frames enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TSPTPPSV2E ,Time stamp PTP packet snooping for version2 format enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " TSSSR ,Time stamp subsecond rollover enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TSSARFE ,Time stamp snapshot for all received frames enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TSARU ,Time stamp addend register update" "Not updated,Updated"
|
|
bitfld.long 0x00 4. " TSITE ,Time stamp interrupt trigger enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " TSSTU ,Time stamp system time update" "Not updated,Updated"
|
|
bitfld.long 0x00 2. " TSSTI ,Time stamp system time initialize" "Not initialized,Initialized"
|
|
bitfld.long 0x00 1. " TSFCU ,Time stamp fine or coarse update" "Not updated,Updated"
|
|
bitfld.long 0x00 0. " TSE ,Time stamp enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x700++0x03
|
|
line.long 0x00 "PTPTSCR,Ethernet PTP Time Stamp Control Register"
|
|
bitfld.long 0x00 18. " TSPFFMAE ,Time stamp PTP frame filtering MAC address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " TSCNT ,Time stamp clock node type" "Ordinary,Boundary,End-to-end,Peer-to-peer"
|
|
textfld " "
|
|
bitfld.long 0x00 14. " TSSEME ,Time stamp snapshot for event message enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " TSSIPV4FE ,Time stamp snapshot for IPv4 frames enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " TSSIPV6FE ,Time stamp snapshot for IPv6 frames enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TSSPTPOEFE ,Time stamp snapshot for PTP over ethernet frames enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TSPTPPSV2E ,Time stamp PTP packet snooping for version2 format enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " TSSSR ,Time stamp subsecond rollover enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TSSARFE ,Time stamp snapshot for all received frames enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TSARU ,Time stamp addend register update" "Not updated,Updated"
|
|
bitfld.long 0x00 4. " TSITE ,Time stamp interrupt trigger enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " TSSTU ,Time stamp system time update" "Not updated,Updated"
|
|
bitfld.long 0x00 2. " TSSTI ,Time stamp system time initialize" "Not initialized,Initialized"
|
|
bitfld.long 0x00 1. " TSFCU ,Time stamp fine or coarse update" "Not updated,Updated"
|
|
bitfld.long 0x00 0. " TSE ,Time stamp enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x704++0x03
|
|
line.long 0x00 "PTPSSIR,Ethernet PTP Subsecond Increment Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " STSSI ,System time subsecond increment"
|
|
rgroup.long 0x708++0x07
|
|
line.long 0x00 "PTPTSHR,Ethernet PTP Time Stamp High Register"
|
|
line.long 0x04 "PTPTSLR,Ethernet PTP Time Stamp Low Register"
|
|
bitfld.long 0x04 31. " STPNS ,System time positive or negative sign" "Positive,Negative"
|
|
hexmask.long 0x04 0.--30. 1. " STSS ,System time subseconds"
|
|
group.long 0x710++0x13
|
|
line.long 0x00 "PTPTSHUR,Ethernet PTP Time Stamp High Update Register"
|
|
line.long 0x04 "PTPTSLUR,Ethernet PTP Time Stamp Low Update Register"
|
|
bitfld.long 0x04 31. " TSUPNS ,Time stamp update positive or negative sign" "Positive,Negative"
|
|
hexmask.long 0x04 0.--30. 1. " TSUSS ,Time stamp update subseconds"
|
|
line.long 0x08 "PTPTSAR,Ethernet PTP Time Stamp Addend Register"
|
|
line.long 0x0C "PTPTTHR,Ethernet PTP Target Time High Register"
|
|
line.long 0x10 "PTPTTLR,Ethernet PTP Target Time Low Register"
|
|
newline
|
|
hgroup.long 0x728++0x03
|
|
hide.long 0x00 "PTPTSSR,Ethernet PTP Time Stamp Status Register"
|
|
in
|
|
newline
|
|
group.long 0x72C++0x03
|
|
line.long 0x00 "PTPPPSCR,Ethernet PTP PPS Control Register"
|
|
bitfld.long 0x00 0.--3. " PPSFREQ ,PPS frequency selection" "1Hz,2Hz,4Hz,8Hz,16Hz,32Hz,64Hz,128Hz,256Hz,512Hz,1024Hz,2048Hz,4096Hz,8192Hz,16384Hz,32768Hz"
|
|
tree.end
|
|
width 11.
|
|
tree "DMA Registers"
|
|
if (((per.l(ad:0x40028000+0x1000))&0x800002)==0x800000)
|
|
group.long 0x1000++0x03
|
|
line.long 0x00 "DMABMR,Ethernet DMA Bus Mode Register"
|
|
bitfld.long 0x00 26. " MB ,Mixed burst" "Fixed bursts,Mixed bursts"
|
|
bitfld.long 0x00 25. " AAB ,Address-aligned beats" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " FPM ,4xPBL mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " USP ,Use separate PBL" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17.--22. " RDP ,Rx DMA programmable burst length" "1,2,4,8,16,32,?..."
|
|
bitfld.long 0x00 16. " FB ,Fixed burst" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PM ,RX TX priority ratio" "1:1,2:1,3:1,4:1"
|
|
bitfld.long 0x00 8.--13. " PBL ,TX DMA programmable burst length" "1,2,4,8,16,32,?..."
|
|
newline
|
|
bitfld.long 0x00 7. " EDFE ,Enhanced descriptor format enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--6. " DSL ,Descriptor skip length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 1. " DA ,DMA arbitration" "Round-robin,Rx first"
|
|
bitfld.long 0x00 0. " SR ,Software reset" "No reset,Reset"
|
|
elif (((per.l(ad:0x40028000+0x1000))&0x800002)==0x800002)
|
|
group.long 0x1000++0x03
|
|
line.long 0x00 "DMABMR,Ethernet DMA Bus Mode Register"
|
|
bitfld.long 0x00 26. " MB ,Mixed burst" "Fixed bursts,Mixed bursts"
|
|
bitfld.long 0x00 25. " AAB ,Address-aligned beats" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " FPM ,4xPBL mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " USP ,Use separate PBL" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17.--22. " RDP ,Rx DMA programmable burst length" "1,2,4,8,16,32,?..."
|
|
bitfld.long 0x00 16. " FB ,Fixed burst" "Disabled,Enabled"
|
|
textfld " "
|
|
bitfld.long 0x00 8.--13. " PBL ,TX DMA programmable burst length" "1,2,4,8,16,32,?..."
|
|
newline
|
|
bitfld.long 0x00 7. " EDFE ,Enhanced descriptor format enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--6. " DSL ,Descriptor skip length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 1. " DA ,DMA arbitration" "Round-robin,Rx first"
|
|
bitfld.long 0x00 0. " SR ,Software reset" "No reset,Reset"
|
|
elif (((per.l(ad:0x40028000+0x1000))&0x800002)==0x00)
|
|
group.long 0x1000++0x03
|
|
line.long 0x00 "DMABMR,Ethernet DMA Bus Mode Register"
|
|
bitfld.long 0x00 26. " MB ,Mixed burst" "Fixed bursts,Mixed bursts"
|
|
bitfld.long 0x00 25. " AAB ,Address-aligned beats" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " FPM ,4xPBL mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " USP ,Use separate PBL" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 16. " FB ,Fixed burst" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PM ,RX TX priority ratio" "1:1,2:1,3:1,4:1"
|
|
bitfld.long 0x00 8.--13. " PBL ,TX DMA programmable burst length" "1,2,4,8,16,32,?..."
|
|
newline
|
|
bitfld.long 0x00 7. " EDFE ,Enhanced descriptor format enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--6. " DSL ,Descriptor skip length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 1. " DA ,DMA arbitration" "Round-robin,Rx first"
|
|
bitfld.long 0x00 0. " SR ,Software reset" "No reset,Reset"
|
|
else
|
|
group.long 0x1000++0x03
|
|
line.long 0x00 "DMABMR,Ethernet DMA Bus Mode Register"
|
|
bitfld.long 0x00 26. " MB ,Mixed burst" "Fixed bursts,Mixed bursts"
|
|
bitfld.long 0x00 25. " AAB ,Address-aligned beats" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " FPM ,4xPBL mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " USP ,Use separate PBL" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 16. " FB ,Fixed burst" "Disabled,Enabled"
|
|
textfld " "
|
|
bitfld.long 0x00 8.--13. " PBL ,TX DMA programmable burst length" "1,2,4,8,16,32,?..."
|
|
newline
|
|
bitfld.long 0x00 7. " EDFE ,Enhanced descriptor format enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--6. " DSL ,Descriptor skip length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 1. " DA ,DMA arbitration" "Round-robin,Rx first"
|
|
bitfld.long 0x00 0. " SR ,Software reset" "No reset,Reset"
|
|
endif
|
|
group.long 0x1004++0x13
|
|
line.long 0x00 "DMATPDR,Ethernet DMA Transmit Poll Demand Register"
|
|
line.long 0x04 "DMARPDR,Ethernet DMA Receive Poll Demand Register"
|
|
line.long 0x08 "DMARDLAR,Ethernet DMA Receive Descriptor List Address Register"
|
|
line.long 0x0C "DMATDLAR,Ethernet DMA Transmit Descriptor List Address Register"
|
|
line.long 0x10 "DMASR,Ethernet DMA Status Register"
|
|
rbitfld.long 0x10 29. " TSTS ,Time stamp trigger status" "No interrupt,Interrupt"
|
|
rbitfld.long 0x10 28. " PMTS ,PMT status" "No interrupt,Interrupt"
|
|
rbitfld.long 0x10 27. " MMCS ,MMC status" "No interrupt,Interrupt"
|
|
rbitfld.long 0x10 25. " EBS[2] ,Error during data buffer/descriptor access" "Data buffer,Descriptor"
|
|
newline
|
|
rbitfld.long 0x10 24. " [1] ,Error during write/read transfer" "Write,Read"
|
|
rbitfld.long 0x10 23. " [0] ,Error during data transfer by RxDMA/TxDMA" "RxDMA,TxDMA"
|
|
rbitfld.long 0x10 20.--22. " TPS ,Transmit process state" "Stopped,Running/Fetching,Running/Waiting,Running/Reading,,,Suspended,Running/Closing"
|
|
rbitfld.long 0x10 17.--19. " RPS ,Receive process state" "Stopped,Running/Fetching,,Running/Waiting,Suspended,Running/Closing,,Running/Transferring"
|
|
newline
|
|
eventfld.long 0x10 16. " NIS ,Normal interrupt summary" "Not occurred,Occurred"
|
|
eventfld.long 0x10 15. " AIS ,Abnormal interrupt summary" "Not occurred,Occurred"
|
|
eventfld.long 0x10 14. " ERS ,Early receive status" "No interrupt,Interrupt"
|
|
eventfld.long 0x10 13. " FBES ,Fatal bus error status" "No error,Error"
|
|
newline
|
|
eventfld.long 0x10 10. " ETS ,Early transmit status" "Not transfered,Transfered"
|
|
eventfld.long 0x10 9. " RWTS ,Receive watchdog timeout status" "No timeout,Timeout"
|
|
eventfld.long 0x10 8. " RPSS ,Receive process stopped status" "Not stopped,Stopped"
|
|
eventfld.long 0x10 7. " RBUS ,Receive buffer unavailable status" "Available,Not available"
|
|
newline
|
|
eventfld.long 0x10 6. " RS ,Receive status" "Not completed,Completed"
|
|
eventfld.long 0x10 5. " TUS ,Transmit underflow status" "No underflow,Underflow"
|
|
eventfld.long 0x10 4. " ROS ,Receive overflow status" "No overflow,Overflow"
|
|
eventfld.long 0x10 3. " TJTS ,Transmit jabber timeout status" "No timeout,Timeout"
|
|
newline
|
|
eventfld.long 0x10 2. " TBUS ,Transmit buffer unavailable status" "Available,Not available"
|
|
eventfld.long 0x10 1. " TPSS ,Transmit process stopped status" "Not stopped,Stopped"
|
|
eventfld.long 0x10 0. " TS ,Transmit status" "Not finished,Finished"
|
|
if (((per.l(ad:0x40028000+0x1018))&0x2200000)==0x00)
|
|
group.long 0x1018++0x03
|
|
line.long 0x00 "DMAOMR,Ethernet DMA Operation Mode Register"
|
|
bitfld.long 0x00 26. " DTCEFD ,Dropping of TCP/IP checksum error frames disable" "No,Yes"
|
|
bitfld.long 0x00 25. " RSF ,Receive store and forward" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DFRF ,Disable flushing of received frames" "No,Yes"
|
|
bitfld.long 0x00 21. " TSF ,Transmit store and forward" "Not full,Full"
|
|
newline
|
|
bitfld.long 0x00 20. " FTF ,Flush transmit FIFO" "No reset,Reset"
|
|
bitfld.long 0x00 14.--16. " TTC ,Transmit threshold control" "64,128,192,256,40,32,24,16"
|
|
bitfld.long 0x00 13. " ST ,Start/stop transmission" "Stopped,Started"
|
|
bitfld.long 0x00 7. " FEF ,Forward error frames" "Not forwarded,Forwarded"
|
|
newline
|
|
bitfld.long 0x00 6. " FUGF ,Forward undersized good frames" "Not forwarded,Forwarded"
|
|
bitfld.long 0x00 3.--4. " RTC ,Receive threshold control" "64,32,96,128"
|
|
bitfld.long 0x00 2. " OSF ,Operate on second frame" "Normal,On second"
|
|
bitfld.long 0x00 1. " SR ,Start/stop receive" "Stopped,Started"
|
|
elif (((per.l(ad:0x40028000+0x1018))&0x2200000)==0x200000)
|
|
group.long 0x1018++0x03
|
|
line.long 0x00 "DMAOMR,Ethernet DMA Operation Mode Register"
|
|
bitfld.long 0x00 26. " DTCEFD ,Dropping of TCP/IP checksum error frames disable" "No,Yes"
|
|
bitfld.long 0x00 25. " RSF ,Receive store and forward" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DFRF ,Disable flushing of received frames" "No,Yes"
|
|
bitfld.long 0x00 21. " TSF ,Transmit store and forward" "Not full,Full"
|
|
newline
|
|
bitfld.long 0x00 20. " FTF ,Flush transmit FIFO" "No reset,Reset"
|
|
textfld " "
|
|
bitfld.long 0x00 13. " ST ,Start/stop transmission" "Stopped,Started"
|
|
bitfld.long 0x00 7. " FEF ,Forward error frames" "Not forwarded,Forwarded"
|
|
newline
|
|
bitfld.long 0x00 6. " FUGF ,Forward undersized good frames" "Not forwarded,Forwarded"
|
|
bitfld.long 0x00 3.--4. " RTC ,Receive threshold control" "64,32,96,128"
|
|
bitfld.long 0x00 2. " OSF ,Operate on second frame" "Normal,On second"
|
|
bitfld.long 0x00 1. " SR ,Start/stop receive" "Stopped,Started"
|
|
elif (((per.l(ad:0x40028000+0x1018))&0x2200000)==0x2000000)
|
|
group.long 0x1018++0x03
|
|
line.long 0x00 "DMAOMR,Ethernet DMA Operation Mode Register"
|
|
bitfld.long 0x00 26. " DTCEFD ,Dropping of TCP/IP checksum error frames disable" "No,Yes"
|
|
bitfld.long 0x00 25. " RSF ,Receive store and forward" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DFRF ,Disable flushing of received frames" "No,Yes"
|
|
bitfld.long 0x00 21. " TSF ,Transmit store and forward" "Not full,Full"
|
|
newline
|
|
bitfld.long 0x00 20. " FTF ,Flush transmit FIFO" "No reset,Reset"
|
|
bitfld.long 0x00 14.--16. " TTC ,Transmit threshold control" "64,128,192,256,40,32,24,16"
|
|
bitfld.long 0x00 13. " ST ,Start/stop transmission" "Stopped,Started"
|
|
bitfld.long 0x00 7. " FEF ,Forward error frames" "Not forwarded,Forwarded"
|
|
newline
|
|
bitfld.long 0x00 6. " FUGF ,Forward undersized good frames" "Not forwarded,Forwarded"
|
|
textfld " "
|
|
bitfld.long 0x00 2. " OSF ,Operate on second frame" "Normal,On second"
|
|
bitfld.long 0x00 1. " SR ,Start/stop receive" "Stopped,Started"
|
|
else
|
|
group.long 0x1018++0x03
|
|
line.long 0x00 "DMAOMR,Ethernet DMA Operation Mode Register"
|
|
bitfld.long 0x00 26. " DTCEFD ,Dropping of TCP/IP checksum error frames disable" "No,Yes"
|
|
bitfld.long 0x00 25. " RSF ,Receive store and forward" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DFRF ,Disable flushing of received frames" "No,Yes"
|
|
bitfld.long 0x00 21. " TSF ,Transmit store and forward" "Not full,Full"
|
|
newline
|
|
bitfld.long 0x00 20. " FTF ,Flush transmit FIFO" "No reset,Reset"
|
|
textfld " "
|
|
bitfld.long 0x00 13. " ST ,Start/stop transmission" "Stopped,Started"
|
|
bitfld.long 0x00 7. " FEF ,Forward error frames" "Not forwarded,Forwarded"
|
|
newline
|
|
bitfld.long 0x00 6. " FUGF ,Forward undersized good frames" "Not forwarded,Forwarded"
|
|
textfld " "
|
|
bitfld.long 0x00 2. " OSF ,Operate on second frame" "Normal,On second"
|
|
bitfld.long 0x00 1. " SR ,Start/stop receive" "Stopped,Started"
|
|
endif
|
|
group.long 0x101C++0x03
|
|
line.long 0x00 "DMAIER,Ethernet DMA Interrupt Enable Register"
|
|
bitfld.long 0x00 16. " NISE ,Normal interrupt summary enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " AISE ,Abnormal interrupt summary enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ERIE ,Early receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " FBEIE ,Fatal bus error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " ETIE ,Early transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RWTIE ,Receive watchdog timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RPSIE ,Receive process stopped interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " RBUIE ,Receive buffer unavailable interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " RIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TUIE ,Underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ROIE ,Overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TJTIE ,Transmit jabber timeout interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " TBUIE ,Transmit buffer unavailable interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TPSIE ,Transmit process stopped interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0x1020++0x03
|
|
hide.long 0x00 "DMAMFBOCR,Ethernet DMA Missed Frame And Buffer Overflow Counter Register"
|
|
in
|
|
newline
|
|
group.long 0x1024++0x03
|
|
line.long 0x00 "DMARSWTR,Ethernet DMA Receive Status Watchdog Timer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RSWTC ,Receive status (RS) watchdog timer count"
|
|
rgroup.long 0x1048++0x0F
|
|
line.long 0x00 "DMACHTDR,Ethernet DMA Current Host Transmit Descriptor Register"
|
|
line.long 0x04 "DMACHRDR,Ethernet DMA Current Host Receive Descriptor Register"
|
|
line.long 0x08 "DMACHTBAR,Ethernet DMA Current Host Transmit Buffer Address Register"
|
|
line.long 0x0C "DMACHRBAR,Ethernet DMA Current Host Receive Buffer Address Register"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "HDMI-CEC (HDMI-CEC controller)"
|
|
base ad:0x40006C00
|
|
width 6.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,CEC Control Register"
|
|
bitfld.long 0x00 2. " TXEOM ,TX end of message" "TXDR with EOM=0,TXDR with EOM=1"
|
|
bitfld.long 0x00 1. " TXSOM ,TX start of message" "No CEC transmission,CEC transmission"
|
|
bitfld.long 0x00 0. " CECEN ,CEC enable" "Off,On"
|
|
if (((per.l((ad:0x40006C00+0x00)))&0x01)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CFGR,CEC Configuration Register"
|
|
bitfld.long 0x00 31. " LSTN ,Listen mode" "OAR,OAR/positive acknowledge"
|
|
hexmask.long.word 0x00 16.--30. 0x01 " OAR ,Own address configuration"
|
|
bitfld.long 0x00 8. " SFTOP ,SFT option bit" "On TXSOM set,Automatically"
|
|
bitfld.long 0x00 7. " BRDNOGEN ,Avoid error-bit generation in broadcast" "BRESTP=1&&BREGEN=0||LBPEGEN=0,Not generated"
|
|
newline
|
|
bitfld.long 0x00 6. " LBPEGEN ,Generate error-bit on long bit period error" "Not generated,Generated"
|
|
bitfld.long 0x00 5. " BREGEN ,Generate error-bit on bit rising error" "Not generated,Generated"
|
|
bitfld.long 0x00 4. " BRESTP ,RX-stop on bit rising error" "Not stopped,Stopped"
|
|
bitfld.long 0x00 3. " RXTOL ,RX-tolerance" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " SFT ,Signal free time" "2.5 periods/4 periods/6 periods,0.5 periods,1.5 periods,2.5 periods,3.5 periods,4.5 periods,5.5 periods,6.5 periods"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "CFGR,CEC Configuration Register"
|
|
bitfld.long 0x00 31. " LSTN ,Listen mode" "OAR,OAR/positive acknowledge"
|
|
hexmask.long.word 0x00 16.--30. 1. " OAR ,Own address configuration"
|
|
bitfld.long 0x00 8. " SFTOP ,SFT option bit" "On TXSOM set,Automatically"
|
|
bitfld.long 0x00 7. " BRDNOGEN ,Avoid error-bit generation in broadcast" "BRESTP=1&&BREGEN=0||LBPEGEN=0,Not generated"
|
|
newline
|
|
bitfld.long 0x00 6. " LBPEGEN ,Generate error-bit on long bit period error" "Not generated,Generated"
|
|
bitfld.long 0x00 5. " BREGEN ,Generate error-bit on bit rising error" "Not generated,Generated"
|
|
bitfld.long 0x00 4. " BRESTP ,RX-stop on bit rising error" "Not stopped,Stopped"
|
|
bitfld.long 0x00 3. " RXTOL ,RX-tolerance" "Standard,Extended"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " SFT ,Signal free time" "2.5 periods/4 periods/6 periods,0.5 periods,1.5 periods,2.5 periods,3.5 periods,4.5 periods,5.5 periods,6.5 periods"
|
|
endif
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "TXDR,CEC TX Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXD ,TX data register value"
|
|
newline
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "RXDR,CEC RX Data Register"
|
|
in
|
|
newline
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ISR,CEC Interrupt And Status Register"
|
|
eventfld.long 0x00 12. " TXACKE ,TX-missing acknowledge error" "No error,Error"
|
|
eventfld.long 0x00 11. " TXERR ,TX-error" "No error,Error"
|
|
eventfld.long 0x00 10. " TXUDR ,TX-buffer underrun" "Not occurred,Occurred"
|
|
eventfld.long 0x00 9. " TXEND ,End of transmission" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 8. " TXBR ,TX-byte request" "Not occurred,Occurred"
|
|
eventfld.long 0x00 7. " ARBLST ,Arbitration lost" "Not occurred,Occurred"
|
|
eventfld.long 0x00 6. " RXACKE ,RX-missing acknowledge" "No error,Error"
|
|
eventfld.long 0x00 5. " LBPE ,RX-long bit period error" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 4. " SBPE ,RX-short bit period error" "No error,Error"
|
|
eventfld.long 0x00 3. " BRE ,RX-bit rising error" "No error,Error"
|
|
eventfld.long 0x00 2. " RXOVR ,RX-overrun" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " RXEND ,End of reception" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 0. " RXBR ,RX-byte received" "Not received,Received"
|
|
if (((per.l((ad:0x40006C00+0x00)))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "IER,CEC Interrupt Enable Register"
|
|
bitfld.long 0x00 12. " TXACKEIE ,TX-missing acknowledge error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TXERRIE ,TX-error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TXUDRIE ,TX-buffer underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TXENDIE ,End of transmission interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " TXBRIE ,TX-byte request interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " ARBLSTIE ,Arbitration lost interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RXACKEIE ,RX-missing acknowledge error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBPEIE ,Long bit period error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " SBPEIE ,Short bit period error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " BREIE ,Bit rising error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXOVRIE ,RX-buffer overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RXENDIE ,End of reception interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " RXBRIE ,RX-byte received interrupt enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "IER,CEC Interrupt Enable Register"
|
|
bitfld.long 0x00 12. " TXACKEIE ,TX-missing acknowledge error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TXERRIE ,TX-error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TXUDRIE ,TX-buffer underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TXENDIE ,End of transmission interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " TXBRIE ,TX-byte request interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " ARBLSTIE ,Arbitration lost interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RXACKEIE ,RX-missing acknowledge error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBPEIE ,Long bit period error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " SBPEIE ,Short bit period error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " BREIE ,Bit rising error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXOVRIE ,RX-buffer overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RXENDIE ,End of reception interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " RXBRIE ,RX-byte received interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (!cpuis("STM32F72*")&&!cpuis("STM32F73*"))
|
|
tree "DES (Device Electronic Signature)"
|
|
base ad:0x1FF0F420
|
|
width 12.
|
|
rgroup.long 0x00++0x0B
|
|
line.long 0x00 "U_ID0,Unique ID Bits Register 0"
|
|
line.long 0x04 "U_ID1,Unique ID Bits Register 1"
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F75*"))
|
|
hexmask.long.tbyte 0x04 8.--31. 1. " LOT_NUM ,Lot number"
|
|
hexmask.long.byte 0x04 0.--7. 1. " WAF_NUM ,Wafer number"
|
|
endif
|
|
line.long 0x08 "U_ID2,Unique ID Bits Register 2"
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*"))
|
|
rgroup.word 0x12++0x01
|
|
line.word 0x00 "FLASH_SIZE,Flash Size Data Register"
|
|
else
|
|
rgroup.word 0x22++0x01
|
|
line.word 0x00 "FLASH_SIZE,Flash Size Data Register"
|
|
endif
|
|
base ad:0x1FFF7BF0
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PKG,Package Data Register"
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.word 0x00 8.--10. " PGK ,Package type" ",LQFP100,LQFP144,WLCSP180,LQFP176,LQFP176,LQFP208/TFBGA216,LQFP208/TFBGA216"
|
|
elif (cpuis("STM32F72*")||cpuis("STM32F75*"))
|
|
bitfld.word 0x00 8.--10. " PGK ,Package type" ",LQFP100,WLCSP143/LQFP144,LQFP176/UFBGA176,LQFP208/TFBGA216,LQFP208/TFBGA216,LQFP208/TFBGA216,LQFP208/TFBGA216"
|
|
elif (cpuis("STM32F73*"))
|
|
bitfld.word 0x00 8.--10. " PGK ,Package type" "LQFP64,LQFP100,LQFP144,LQFP176/UFBGA176,WLCSP100,LQFP144/UFBGA144,LQFP176/UFBGA176,?..."
|
|
else
|
|
bitfld.word 0x00 8.--10. " PGK ,Package type" ",LQFP100,LQFP144,UFBGA176,TFBGA216,TFBGA216,TFBGA216,TFBGA216"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
tree "DES (Device Electronic Signature)"
|
|
base ad:0x1FF07A10
|
|
width 12.
|
|
rgroup.long 0x00++0x0B
|
|
line.long 0x00 "U_ID0,Unique ID Bits Register 0"
|
|
line.long 0x04 "U_ID1,Unique ID Bits Register 1"
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F75*"))
|
|
hexmask.long.tbyte 0x04 8.--31. 1. " LOT_NUM ,Lot number"
|
|
hexmask.long.byte 0x04 0.--7. 1. " WAF_NUM ,Wafer number"
|
|
endif
|
|
line.long 0x08 "U_ID2,Unique ID Bits Register 2"
|
|
sif (cpuis("STM32F72*")||cpuis("STM32F73*"))
|
|
rgroup.word 0x12++0x01
|
|
line.word 0x00 "FLASH_SIZE,Flash Size Data Register"
|
|
else
|
|
rgroup.word 0x22++0x01
|
|
line.word 0x00 "FLASH_SIZE,Flash Size Data Register"
|
|
endif
|
|
base ad:0x1FFF7BF0
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PKG,Package Data Register"
|
|
sif (cpuis("STM32F76*")||cpuis("STM32F77*"))
|
|
bitfld.word 0x00 8.--10. " PGK ,Package type" ",LQFP100,LQFP144,WLCSP180,LQFP176,LQFP176,LQFP208/TFBGA216,LQFP208/TFBGA216"
|
|
elif (cpuis("STM32F72*")||cpuis("STM32F75*"))
|
|
bitfld.word 0x00 8.--10. " PGK ,Package type" ",LQFP100,WLCSP143/LQFP144,LQFP176/UFBGA176,LQFP208/TFBGA216,LQFP208/TFBGA216,LQFP208/TFBGA216,LQFP208/TFBGA216"
|
|
elif (cpuis("STM32F73*"))
|
|
bitfld.word 0x00 8.--10. " PGK ,Package type" "LQFP64,LQFP100,LQFP144,LQFP176/UFBGA176,WLCSP100,LQFP144/UFBGA144,LQFP176/UFBGA176,?..."
|
|
else
|
|
bitfld.word 0x00 8.--10. " PGK ,Package type" ",LQFP100,LQFP144,UFBGA176,TFBGA216,TFBGA216,TFBGA216,TFBGA216"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F7?3*")||cpuis("STM32F73*"))
|
|
sif (!cpuis("STM32F72?R*")&&!cpuis("STM32F73?R*")&&!cpuis("STM32F730V*")&&!cpuis("STM32F76*")&&!cpuis("STM32F77*"))
|
|
tree "USBPHYC (USB PHY Controller)"
|
|
base ad:0x40017C00
|
|
width 6.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "PLL1,USBPHYC PLL1 Control Register"
|
|
bitfld.byte 0x00 1.--3. " PLL1SEL ,Controls the PHY PLL1 input clock frequency selection" "12MHz,12.5MHz,12.5MHz,16MHz,24MHz,25MHz,25MHz,?..."
|
|
bitfld.byte 0x00 0. " PLL1EN ,Enable the PLL1 inside PHY" "Disabled,Enabled"
|
|
sif (cpuis("STM32F7?3*"))
|
|
if ((per.l((ad:0x40017C00)+0x0C)&0x40)==0x40)
|
|
if ((per.l((ad:0x40017C00)+0x0C)&0x01)==0x01)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TUNE,USBPHYC Tuning Control Register"
|
|
bitfld.long 0x00 23. " SQLBYP ,This pin is used to bypass the squelch inter-locking circuitry" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 22. " SHTCCTCTLPROT ,Enables the short circuit protection circuitry in LS/FS driver" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " HSRXOFF ,HS receiver offset adjustment" "Off,+5mV,+10mV,-5mV"
|
|
bitfld.long 0x00 19. " HSFALLPREEM ,HS fall time control of single ended signals during pre-emphasis" "On,Off"
|
|
newline
|
|
bitfld.long 0x00 18. " STAGSEL ,HS TX staggering enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " HDRXGNEQEN ,Enables the HS RX gain equalizer" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--16. " SQLCHCTL ,Adjust the squelch DC threshold value" "No shift,-5mV,+7mV,+14mV"
|
|
bitfld.long 0x00 13.--14. " HSDRVCHKZTRM ,Controls the PHY bus HS driver impedance tuning for choke compensation" "No impedance,2 ohms,4 ohms,6 ohms"
|
|
newline
|
|
bitfld.long 0x00 9.--12. " HSDRVCHKITRM ,HS driver current trimming pins for choke compensation" "18.87 mA,19.165 mA,19.46 mA,19.755 mA,20.05 mA,20.345 mA,20.64 mA,20.935 mA,21.23 mA,21.525 mA,21.82 mA,22.115 mA,22.458 mA,22.755 mA,23.052 mA,23.348 mA"
|
|
bitfld.long 0x00 8. " HSDRVRFRED ,High speed rise-fall reduction enable" "Default,Increased"
|
|
bitfld.long 0x00 7. " FSDRVRFADJ ,Tuning pin to adjust the full speed rise/fall time" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HSDRVCURINCR ,Enable the HS driver current increase feature" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " HSDRVDCLEV ,Increases the HS driver DC level" "5-7 mV,10-14 mV"
|
|
bitfld.long 0x00 4. " HSDRVDCCUR ,Decreases the HS driver DC level" "Default,Decreased"
|
|
bitfld.long 0x00 3. " HSDRVSLEW ,Controls the HS driver slew rate" "Default,Slowed"
|
|
bitfld.long 0x00 2. " LFSCAPEN ,Enables the low full speed feedback capacitor" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " INCURRINT ,Controls PHY current boosting" "1 mA,2 mA"
|
|
bitfld.long 0x00 0. " NCURREN ,Controls the current boosting function" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TUNE,USBPHYC Tuning Control Register"
|
|
bitfld.long 0x00 23. " SQLBYP ,This pin is used to bypass the squelch inter-locking circuitry" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 22. " SHTCCTCTLPROT ,Enables the short circuit protection circuitry in LS/FS driver" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " HSRXOFF ,HS receiver offset adjustment" "Off,+5mV,+10mV,-5mV"
|
|
bitfld.long 0x00 19. " HSFALLPREEM ,HS fall time control of single ended signals during pre-emphasis" "On,Off"
|
|
newline
|
|
bitfld.long 0x00 18. " STAGSEL ,HS TX staggering enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " HDRXGNEQEN ,Enables the HS RX gain equalizer" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--16. " SQLCHCTL ,Adjust the squelch DC threshold value" "No shift,-5mV,+7mV,+14mV"
|
|
bitfld.long 0x00 13.--14. " HSDRVCHKZTRM ,Controls the PHY bus HS driver impedance tuning for choke compensation" "No impedance,2 ohms,4 ohms,6 ohms"
|
|
newline
|
|
bitfld.long 0x00 9.--12. " HSDRVCHKITRM ,HS driver current trimming pins for choke compensation" "18.87 mA,19.165 mA,19.46 mA,19.755 mA,20.05 mA,20.345 mA,20.64 mA,20.935 mA,21.23 mA,21.525 mA,21.82 mA,22.115 mA,22.458 mA,22.755 mA,23.052 mA,23.348 mA"
|
|
bitfld.long 0x00 8. " HSDRVRFRED ,High speed rise-fall reduction enable" "Default,Increased"
|
|
bitfld.long 0x00 7. " FSDRVRFADJ ,Tuning pin to adjust the full speed rise/fall time" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HSDRVCURINCR ,Enable the HS driver current increase feature" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " HSDRVDCLEV ,Increases the HS driver DC level" "5-7 mV,10-14 mV"
|
|
bitfld.long 0x00 4. " HSDRVDCCUR ,Decreases the HS driver DC level" "Default,Decreased"
|
|
bitfld.long 0x00 3. " HSDRVSLEW ,Controls the HS driver slew rate" "Default,Slowed"
|
|
bitfld.long 0x00 2. " LFSCAPEN ,Enables the low full speed feedback capacitor" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 0. " NCURREN ,Controls the current boosting function" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if ((per.l((ad:0x40017C00)+0x0C)&0x01)==0x01)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TUNE,USBPHYC Tuning Control Register"
|
|
bitfld.long 0x00 23. " SQLBYP ,This pin is used to bypass the squelch inter-locking circuitry" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 22. " SHTCCTCTLPROT ,Enables the short circuit protection circuitry in LS/FS driver" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " HSRXOFF ,HS receiver offset adjustment" "Off,+5mV,+10mV,-5mV"
|
|
bitfld.long 0x00 19. " HSFALLPREEM ,HS fall time control of single ended signals during pre-emphasis" "On,Off"
|
|
newline
|
|
bitfld.long 0x00 18. " STAGSEL ,HS TX staggering enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " HDRXGNEQEN ,Enables the HS RX gain equalizer" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--16. " SQLCHCTL ,Adjust the squelch DC threshold value" "No shift,-5mV,+7mV,+14mV"
|
|
bitfld.long 0x00 13.--14. " HSDRVCHKZTRM ,Controls the PHY bus HS driver impedance tuning for choke compensation" "No impedance,2 ohms,4 ohms,6 ohms"
|
|
newline
|
|
bitfld.long 0x00 9.--12. " HSDRVCHKITRM ,HS driver current trimming pins for choke compensation" "18.87 mA,19.165 mA,19.46 mA,19.755 mA,20.05 mA,20.345 mA,20.64 mA,20.935 mA,21.23 mA,21.525 mA,21.82 mA,22.115 mA,22.458 mA,22.755 mA,23.052 mA,23.348 mA"
|
|
bitfld.long 0x00 8. " HSDRVRFRED ,High speed rise-fall reduction enable" "Default,Increased"
|
|
bitfld.long 0x00 7. " FSDRVRFADJ ,Tuning pin to adjust the full speed rise/fall time" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HSDRVCURINCR ,Enable the HS driver current increase feature" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " HSDRVDCCUR ,Decreases the HS driver DC level" "Default,Decreased"
|
|
bitfld.long 0x00 3. " HSDRVSLEW ,Controls the HS driver slew rate" "Default,Slowed"
|
|
bitfld.long 0x00 2. " LFSCAPEN ,Enables the low full speed feedback capacitor" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " INCURRINT ,Controls PHY current boosting" "1 mA,2 mA"
|
|
bitfld.long 0x00 0. " NCURREN ,Controls the current boosting function" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TUNE,USBPHYC Tuning Control Register"
|
|
bitfld.long 0x00 23. " SQLBYP ,This pin is used to bypass the squelch inter-locking circuitry" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 22. " SHTCCTCTLPROT ,Enables the short circuit protection circuitry in LS/FS driver" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " HSRXOFF ,HS receiver offset adjustment" "Off,+5mV,+10mV,-5mV"
|
|
bitfld.long 0x00 19. " HSFALLPREEM ,HS fall time control of single ended signals during pre-emphasis" "On,Off"
|
|
newline
|
|
bitfld.long 0x00 18. " STAGSEL ,HS TX staggering enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " HDRXGNEQEN ,Enables the HS RX gain equalizer" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--16. " SQLCHCTL ,Adjust the squelch DC threshold value" "No shift,-5mV,+7mV,+14mV"
|
|
bitfld.long 0x00 13.--14. " HSDRVCHKZTRM ,Controls the PHY bus HS driver impedance tuning for choke compensation" "No impedance,2 ohms,4 ohms,6 ohms"
|
|
newline
|
|
bitfld.long 0x00 9.--12. " HSDRVCHKITRM ,HS driver current trimming pins for choke compensation" "18.87 mA,19.165 mA,19.46 mA,19.755 mA,20.05 mA,20.345 mA,20.64 mA,20.935 mA,21.23 mA,21.525 mA,21.82 mA,22.115 mA,22.458 mA,22.755 mA,23.052 mA,23.348 mA"
|
|
bitfld.long 0x00 8. " HSDRVRFRED ,High speed rise-fall reduction enable" "Default,Increased"
|
|
bitfld.long 0x00 7. " FSDRVRFADJ ,Tuning pin to adjust the full speed rise/fall time" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HSDRVCURINCR ,Enable the HS driver current increase feature" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " HSDRVDCCUR ,Decreases the HS driver DC level" "Default,Decreased"
|
|
bitfld.long 0x00 3. " HSDRVSLEW ,Controls the HS driver slew rate" "Default,Slowed"
|
|
bitfld.long 0x00 2. " LFSCAPEN ,Enables the low full speed feedback capacitor" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 0. " NCURREN ,Controls the current boosting function" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TUNE,USBPHYC Tuning Control Register"
|
|
bitfld.long 0x00 23. " SQLBYP ,This pin is used to bypass the squelch inter-locking circuitry" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 22. " SHTCCTCTLPROT ,Enables the short circuit protection circuitry in LS/FS driver" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " HSRXOFF ,HS receiver offset adjustment" "Off,+5mV,+10mV,-5mV"
|
|
bitfld.long 0x00 19. " HSFALLPREEM ,HS fall time control of single ended signals during pre-emphasis" "On,Off"
|
|
newline
|
|
bitfld.long 0x00 18. " STAGSEL ,HS TX staggering enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " HDRXGNEQEN ,Enables the HS RX gain equalizer" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--16. " SQLCHCTL ,Adjust the squelch DC threshold value" "No shift,-5mV,+7mV,+14mV"
|
|
bitfld.long 0x00 13.--14. " HSDRVCHKZTRM ,Controls the PHY bus HS driver impedance tuning for choke compensation" "No impedance,2 ohms,4 ohms,6 ohms"
|
|
newline
|
|
bitfld.long 0x00 9.--12. " HSDRVCHKITRM ,HS driver current trimming pins for choke compensation" "18.87 mA,19.165 mA,19.46 mA,19.755 mA,20.05 mA,20.345 mA,20.64 mA,20.935 mA,21.23 mA,21.525 mA,21.82 mA,22.115 mA,22.458 mA,22.755 mA,23.052 mA,23.348 mA"
|
|
bitfld.long 0x00 8. " HSDRVRFRED ,High speed rise-fall reduction enable" "Default,Increased"
|
|
bitfld.long 0x00 7. " FSDRVRFADJ ,Tuning pin to adjust the full speed rise/fall time" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HSDRVCURINCR ,Enable the HS driver current increase feature" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " HSDRVDCCUR ,Decreases the HS driver DC level" "Default,Decreased"
|
|
bitfld.long 0x00 3. " HSDRVSLEW ,Controls the HS driver slew rate" "Default,Slowed"
|
|
bitfld.long 0x00 2. " LFSCAPEN ,Enables the low full speed feedback capacitor" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " INCURRINT ,Controls PHY current boosting" "1 mA,2 mA"
|
|
bitfld.long 0x00 0. " INCURREN ,Controls the current boosting function" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "LDO,USBPHYC LDO Control And Status Register"
|
|
bitfld.byte 0x00 2. " LDO_DISABLE ,Controls disable of the high speed PHY's LDO" "No,Yes"
|
|
rbitfld.byte 0x00 1. " LDO_STATUS ,Monitors the status of the PHY's LDO" "Not ready,Ready"
|
|
rbitfld.byte 0x00 0. " LDO_USED ,Indicates the presence of the LDO in the chip" "Not used,Used"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
endif
|
|
newline
|