5274 lines
370 KiB
Plaintext
5274 lines
370 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: RA0E1 On-Chip Peripherals
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; @Props: Released
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; @Author: NEJ
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; @Changelog: 2024-04-18 NEJ
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; @Manufacturer: RENESAS - Renesas Technology, Corp.
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; @Doc: Generated (TRACE32, build: 168535.), based on: R7FA0E107.svd (Ver. 0.6)
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; @Core: Cortex-M23
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; @Chip: R7FA0E1073CFJ, R7FA0E1073CNH, R7FA0E1073CNK, R7FA0E1073CSC,
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; R7FA0E1073CNL, R7FA0E1053CFJ, R7FA0E1053CNH, R7FA0E1053CNK,
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; R7FA0E1053CSC, R7FA0E1053CNL
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; @Copyright: (C) 1989-2024 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; This software is supplied by Renesas Electronics Corporation and is only intended for \n
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; use with Renesas products. No other uses are authorized. This software is owned by \n
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; Renesas Electronics Corporation and is protected under all applicable laws, including \n
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; copyright laws. \n
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; \n
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; THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING \n
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; THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO \n
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; WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. \n
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||
; ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM EXTENT PERMITTED NOT \n
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; PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED \n
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; COMPANIES SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL \n
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; DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE \n
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; BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. \n
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; \n
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; Renesas reserves the right, without notice, to make changes to this software and to \n
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; discontinue the availability of this software. By using this software, you agree to \n
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; the additional terms and conditions found by accessing the following link: \n
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; http://www.renesas.com/disclaimer \n
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; \n
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; --------------------------------------------------------------------------------
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; $Id: perra0e1.per 17789 2024-04-19 10:28:07Z kwisniewski $
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AUTOINDENT.ON CENTER TREE
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ENUMDELIMITER ","
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base ad:0x0
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tree.close "Core Registers (Cortex-M23)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 29. " EXTEXCLALL ,LDREX and STREX instructions use the Global Exclusive Monitor" "Only on Shared regions,Always"
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newline
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group.long 0x10++0x03
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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newline
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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group.long 0x14++0x07
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line.long 0x00 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x00 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x04 "SYST_CVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " CURRENT ,Current counter value"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPUID Base Register"
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abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
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bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8-M w/o Main Extension,Reserved,Reserved,Reserved"
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newline
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abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xD20=Cortex-M23"
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bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
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group.long 0xD04++0x13
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line.long 0x00 "ICSR,Interrupt Control and State Register"
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setclrfld.long 0x00 31. 0x00 31. 0x00 30. " PENDNMISET ,On writes allows the NMI exception to be set as pending. On reads indicates whether the NMI exception is pending" "Not pending,Pending"
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setclrfld.long 0x00 28. 0x00 28. 0x00 27. " PENDSVSET ,On writes allows the PendSV exception for the selected Security state to be set as pending. On reads indicates whether the PendSV for the selected Security state exception is pending" "Not pending,Pending"
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setclrfld.long 0x00 26. 0x00 26. 0x00 25. " PENDSTSET ,On writes, sets the SysTick exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending"
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newline
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bitfld.long 0x00 24. " STTNS ,Controls whether in a single SysTick implementation the SysTick is Secure or Non-secure" "Secure,Non-secure"
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rbitfld.long 0x00 23. " ISRPREEMPT ,Indicates whether a pending exception will be serviced on exit from debug halt state" "Disabled,Enabled"
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rbitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt, generated by the NVIC, is pending" "Not pending,Pending"
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newline
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,The exception number of the highest priority pending and enabled interrupt"
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rbitfld.long 0x00 11. " RETTOBASE ,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "Present,Absent"
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Bits[31:7] of the vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEYSTAT ,Vector Key"
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rbitfld.long 0x08 15. " ENDIANNESS ,Indicates the memory system endianness" "Little endian,Big endian"
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bitfld.long 0x08 14. " PRIS ,Prioritize Secure exceptions" "Disabled,Enabled"
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newline
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bitfld.long 0x08 13. " BFHFNMINS ,BusFault BusFault HardFault and NMI Non-secure enable" "Disabled,Enabled"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Priority grouping. Group priority field bits/Subpriority field bits" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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bitfld.long 0x08 3. " SYSRESETREQS ,System reset request Secure only" "Both states,Secure only"
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newline
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bitfld.long 0x08 2. " SYSRESETREQ ,System reset request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "No effect,Clear"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 3. " SLEEPDEEPS ,Controls whether the SLEEPDEEP bit is only accessible from the secure state" "Both states,Secure only"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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newline
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration and Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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newline
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||
bitfld.long 0x10 10. " STKOFHFNMIGN ,Controls the effect of a stack limit violation while executing at a requested priority less than 0" "Not ignored,Ignored"
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bitfld.long 0x10 8. " BFHFNMIGN ,Determines the effect of precise busfaults on handlers running at a requested priority less than 0" "Not ignored,Ignored"
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bitfld.long 0x10 4. " DIV_0_TRP ,Controls the trap on divide by 0" "Disabled,Enabled"
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newline
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||
bitfld.long 0x10 3. " UNALIGN_TRP ,Controls the trapping of unaligned word or halfword accesses" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Disabled,Enabled"
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group.long 0xD1C++0x0B
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line.long 0x00 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x00 24.--31. 1. " PRI_11 ,Priority of system handler 11, SVCall"
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line.long 0x04 "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x04 24.--31. 1. " PRI_15 ,Priority of system handler 15, SysTick"
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hexmask.long.byte 0x04 16.--23. 1. " PRI_14 ,Priority of system handler 14, PendSV"
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hexmask.long.byte 0x04 0.--7. 1. " PRI_12 ,Priority of system handler 12, DebugMonitor"
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line.long 0x08 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x08 21. " HARDFAULTPENDED ,HardFault exception status" "Not pending,Pending"
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bitfld.long 0x08 20. " SECUREFAULTPENDED ,SecureFault exception status" "Not pending,Pending"
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bitfld.long 0x08 19. " SECUREFAULTENA ,SecureFault exception enable" "Disabled,Enabled"
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newline
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||
bitfld.long 0x08 18. " USGFAULTENA ,UsageFault exception enable" "Disabled,Enabled"
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bitfld.long 0x08 17. " BUSFAULTENA ,BusFault exception enable" "Disabled,Enabled"
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bitfld.long 0x08 16. " MEMFAULTENA ,MemManage exception enable" "Disabled,Enabled"
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newline
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||
bitfld.long 0x08 15. " SVCALLPENDED ,SVCall exception status" "Not pending,Pending"
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bitfld.long 0x08 14. " BUSFAULTPENDED ,BusFault exception status" "Not pending,Pending"
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bitfld.long 0x08 13. " MEMFAULTPENDED ,MemManage exception status" "Not pending,Pending"
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||
newline
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||
bitfld.long 0x08 12. " USGFAULTPENDED ,UsageFault exception status" "Not pending,Pending"
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bitfld.long 0x08 11. " SYSTICKACT ,SysTick exception status" "Not active,Active"
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bitfld.long 0x08 10. " PENDSVACT ,PendSV exception status" "Not active,Active"
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||
newline
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||
bitfld.long 0x08 8. " MONITORACT ,Monitor exception status" "Not active,Active"
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bitfld.long 0x08 7. " SVCALLACT ,SVCall exception status" "Not active,Active"
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||
bitfld.long 0x08 5. " NMIACT ,NMI exception status" "Not active,Active"
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||
newline
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||
bitfld.long 0x08 4. " SECUREFAULTACT ,SecureFault exception status" "Not active,Active"
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||
bitfld.long 0x08 3. " USGFAULTACT ,UsageFault exception status" "Not active,Active"
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||
bitfld.long 0x08 2. " HARDFAULTACT ,HardFault exception status for the selected Security state" "Not active,Active"
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||
newline
|
||
bitfld.long 0x08 1. " BUSFAULTACT ,BusFault exception status" "Not active,Active"
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||
bitfld.long 0x08 0. " MEMFAULTACT ,MemManage exception status" "Not active,Active"
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||
tree "Memory System"
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||
width 10.
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rgroup.long 0xD78++0x0B
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line.long 0x00 "CLIDR,Cache Level ID Register"
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bitfld.long 0x00 30.--31. " ICB ,Inner cache boundary" "Not disclosed,L1 cache highest,L2 cache highest,L3 cache highest"
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||
bitfld.long 0x00 27.--29. " LOU ,LOUU" "Level 1,Level 2,?..."
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||
bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,?..."
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||
textline " "
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||
bitfld.long 0x00 18.--20. " CL7 ,Cache type field level 7" "No cache,Instr. only,Data only,Data and Instr.,Unified cache,?..."
|
||
line.long 0x04 "CTR,Cache Type Register"
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||
bitfld.long 0x04 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,?..."
|
||
bitfld.long 0x04 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,?..."
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||
textline " "
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||
bitfld.long 0x04 16.--19. " DMINLINE ,Log 2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 0.--3. " IMINLINE ,Log 2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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||
line.long 0x08 "CCSIDR,Cache Size ID Register"
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bitfld.long 0x08 31. " WT ,Indicates support available for Write-Through" "Not supported,Supported"
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||
bitfld.long 0x08 30. " WB ,Indicates support available for Write-Back" "Not supported,Supported"
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||
bitfld.long 0x08 29. " RA ,Indicates support available for read allocation" "Not supported,Supported"
|
||
textline " "
|
||
bitfld.long 0x08 28. " WA ,Indicates support available for write allocation" "Not supported,Supported"
|
||
hexmask.long.word 0x08 13.--27. 1. " NUMSETS ,Indicates the number of sets as (number of sets) - 1"
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||
hexmask.long.word 0x08 3.--12. 1. " ASSOCIATIVITY ,Indicates the number of ways as (number of ways) - 1"
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||
textline " "
|
||
bitfld.long 0x08 0.--2. " LINESIZE ,Indicates the number of words in each cache line" "4,8,16,32,64,128,256,512"
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group.long 0xD84++0x03
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line.long 0x00 "CSSELR,Cache Size Selection Register"
|
||
bitfld.long 0x00 1.--3. " LEVEL ,Identifies which cache level to select" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,?..."
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||
bitfld.long 0x00 0. " IND ,Identifies instruction or data cache to use" "Data/Unified,Instruction"
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wgroup.long 0xF50++0x03
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line.long 0x00 "ICIALLU,I-Cache Invalidate All to PoU"
|
||
wgroup.long 0xF58++0x23
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||
line.long 0x00 "ICIMVAU,I-Cache Invalidate by MVA to PoU"
|
||
line.long 0x04 "DCIMVAC,D-Cache Invalidate by MVA to PoC"
|
||
line.long 0x08 "DCISW,D-Cache Invalidate by Set-Way"
|
||
hexmask.long 0x08 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
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||
bitfld.long 0x08 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
|
||
line.long 0x0C "DCCMVAU,D-Cache Clean by MVA to PoU"
|
||
line.long 0x10 "DCCMVAC,D-Cache Clean by MVA to PoC"
|
||
line.long 0x14 "DCCSW,D-Cache Clean by Set-Way"
|
||
hexmask.long 0x14 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
|
||
bitfld.long 0x14 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
|
||
line.long 0x18 "DCCIMVAC,D-Cache Clean and Invalidate by MVA to PoC"
|
||
line.long 0x1C "DCCISW,D-Cache Clean and Invalidate by Set-Way"
|
||
hexmask.long 0x1C 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
|
||
bitfld.long 0x1C 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
|
||
line.long 0x20 "BPIALL,Branch Predictor Invalidate All"
|
||
tree.end
|
||
width 11.
|
||
tree "CoreSight Identification Registers"
|
||
rgroup.long 0xFE0++0x0F
|
||
line.long 0x00 "DPIDR0,Peripheral ID0"
|
||
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
||
line.long 0x04 "DPIDR1,Peripheral ID1"
|
||
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
||
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
||
line.long 0x08 "DPIDR2,Peripheral ID2"
|
||
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
||
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
||
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
||
line.long 0x0c "DPIDR3,Peripheral ID3"
|
||
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
||
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
||
rgroup.long 0xFD0++0x03
|
||
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
||
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
||
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
||
rgroup.long 0xFF0++0x0F
|
||
line.long 0x00 "DCIDR0,Component ID0 (Preamble)"
|
||
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
|
||
line.long 0x04 "DCIDR1,Component ID1"
|
||
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
||
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
|
||
line.long 0x08 "DCIDR2,Component ID2"
|
||
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
|
||
line.long 0x0C "DCIDR3,Component ID3"
|
||
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
|
||
tree.end
|
||
width 0x0B
|
||
else
|
||
newline
|
||
textline "COREDEBUG component base address not specified"
|
||
newline
|
||
endif
|
||
tree.end
|
||
tree "Memory Protection Unit (MPU)"
|
||
sif COMPonent.AVAILABLE("COREDEBUG")
|
||
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
||
width 15.
|
||
rgroup.long 0xD90++0x03
|
||
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
||
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,,,,4,,,,8,,,,,,,,16,?..."
|
||
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,?..."
|
||
group.long 0xD94++0x03
|
||
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
||
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
||
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
||
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
||
group.long 0xD98++0x03
|
||
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
||
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
||
tree.close "MPU regions"
|
||
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
||
group.long 0xD9C++0x03 "Region 0"
|
||
saveout 0xD98 %l 0x0
|
||
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
||
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
||
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
||
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
||
newline
|
||
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
||
group.long 0xDA0++0x03
|
||
saveout 0xD98 %l 0x0
|
||
line.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
|
||
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
||
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
||
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
||
else
|
||
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
||
saveout 0xD98 %l 0x0
|
||
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
||
newline
|
||
hgroup.long 0xDA0++0x03
|
||
saveout 0xD98 %l 0x0
|
||
hide.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
|
||
endif
|
||
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
||
group.long 0xD9C++0x03 "Region 1"
|
||
saveout 0xD98 %l 0x1
|
||
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
||
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
||
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
||
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
||
newline
|
||
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
||
group.long 0xDA0++0x03
|
||
saveout 0xD98 %l 0x1
|
||
line.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
|
||
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
||
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
||
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
||
else
|
||
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
||
saveout 0xD98 %l 0x1
|
||
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
||
newline
|
||
hgroup.long 0xDA0++0x03
|
||
saveout 0xD98 %l 0x1
|
||
hide.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
|
||
endif
|
||
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
||
group.long 0xD9C++0x03 "Region 2"
|
||
saveout 0xD98 %l 0x2
|
||
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
||
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
||
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
||
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
||
newline
|
||
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
||
group.long 0xDA0++0x03
|
||
saveout 0xD98 %l 0x2
|
||
line.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
|
||
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
||
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
||
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
||
else
|
||
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
||
saveout 0xD98 %l 0x2
|
||
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
||
newline
|
||
hgroup.long 0xDA0++0x03
|
||
saveout 0xD98 %l 0x2
|
||
hide.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
|
||
endif
|
||
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
||
group.long 0xD9C++0x03 "Region 3"
|
||
saveout 0xD98 %l 0x3
|
||
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
||
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
||
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
||
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
||
newline
|
||
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
||
group.long 0xDA0++0x03
|
||
saveout 0xD98 %l 0x3
|
||
line.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
|
||
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
||
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
||
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
||
else
|
||
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
||
saveout 0xD98 %l 0x3
|
||
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
||
newline
|
||
hgroup.long 0xDA0++0x03
|
||
saveout 0xD98 %l 0x3
|
||
hide.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
|
||
endif
|
||
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
||
group.long 0xD9C++0x03 "Region 4"
|
||
saveout 0xD98 %l 0x4
|
||
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
||
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
||
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
||
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
||
newline
|
||
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
||
group.long 0xDA0++0x03
|
||
saveout 0xD98 %l 0x4
|
||
line.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
|
||
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
||
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
||
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
||
else
|
||
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
||
saveout 0xD98 %l 0x4
|
||
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
||
newline
|
||
hgroup.long 0xDA0++0x03
|
||
saveout 0xD98 %l 0x4
|
||
hide.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
|
||
endif
|
||
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
||
group.long 0xD9C++0x03 "Region 5"
|
||
saveout 0xD98 %l 0x5
|
||
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
||
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
||
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
||
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
||
newline
|
||
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
||
group.long 0xDA0++0x03
|
||
saveout 0xD98 %l 0x5
|
||
line.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
|
||
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
||
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
||
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
||
else
|
||
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
||
saveout 0xD98 %l 0x5
|
||
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
||
newline
|
||
hgroup.long 0xDA0++0x03
|
||
saveout 0xD98 %l 0x5
|
||
hide.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
|
||
endif
|
||
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
||
group.long 0xD9C++0x03 "Region 6"
|
||
saveout 0xD98 %l 0x6
|
||
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
||
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
||
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
||
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
||
newline
|
||
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
||
group.long 0xDA0++0x03
|
||
saveout 0xD98 %l 0x6
|
||
line.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
|
||
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
||
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
||
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
||
else
|
||
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
||
saveout 0xD98 %l 0x6
|
||
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
||
newline
|
||
hgroup.long 0xDA0++0x03
|
||
saveout 0xD98 %l 0x6
|
||
hide.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
|
||
endif
|
||
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
||
group.long 0xD9C++0x03 "Region 7"
|
||
saveout 0xD98 %l 0x7
|
||
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
||
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
||
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
||
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
||
newline
|
||
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
||
group.long 0xDA0++0x03
|
||
saveout 0xD98 %l 0x7
|
||
line.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
|
||
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
||
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
||
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
||
else
|
||
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
||
saveout 0xD98 %l 0x7
|
||
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
||
newline
|
||
hgroup.long 0xDA0++0x03
|
||
saveout 0xD98 %l 0x7
|
||
hide.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
|
||
endif
|
||
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
||
group.long 0xD9C++0x03 "Region 8"
|
||
saveout 0xD98 %l 0x8
|
||
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
||
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
||
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
||
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
||
newline
|
||
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
||
group.long 0xDA0++0x03
|
||
saveout 0xD98 %l 0x8
|
||
line.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
|
||
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
||
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
||
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
||
else
|
||
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
||
saveout 0xD98 %l 0x8
|
||
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
||
newline
|
||
hgroup.long 0xDA0++0x03
|
||
saveout 0xD98 %l 0x8
|
||
hide.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
|
||
endif
|
||
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
||
group.long 0xD9C++0x03 "Region 9"
|
||
saveout 0xD98 %l 0x9
|
||
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
||
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
||
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
||
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
||
newline
|
||
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
||
group.long 0xDA0++0x03
|
||
saveout 0xD98 %l 0x9
|
||
line.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
|
||
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
||
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
||
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
||
else
|
||
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
||
saveout 0xD98 %l 0x9
|
||
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
||
newline
|
||
hgroup.long 0xDA0++0x03
|
||
saveout 0xD98 %l 0x9
|
||
hide.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
|
||
endif
|
||
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
||
group.long 0xD9C++0x03 "Region 10"
|
||
saveout 0xD98 %l 0xA
|
||
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
||
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
||
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
||
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
||
newline
|
||
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
||
group.long 0xDA0++0x03
|
||
saveout 0xD98 %l 0xA
|
||
line.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
|
||
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
||
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
||
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
||
else
|
||
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
||
saveout 0xD98 %l 0xA
|
||
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
||
newline
|
||
hgroup.long 0xDA0++0x03
|
||
saveout 0xD98 %l 0xA
|
||
hide.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
|
||
endif
|
||
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
||
group.long 0xD9C++0x03 "Region 11"
|
||
saveout 0xD98 %l 0xB
|
||
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
||
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
||
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
||
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
||
newline
|
||
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
||
group.long 0xDA0++0x03
|
||
saveout 0xD98 %l 0xB
|
||
line.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
|
||
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
||
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
||
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
||
else
|
||
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
||
saveout 0xD98 %l 0xB
|
||
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
||
newline
|
||
hgroup.long 0xDA0++0x03
|
||
saveout 0xD98 %l 0xB
|
||
hide.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
|
||
endif
|
||
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
||
group.long 0xD9C++0x03 "Region 12"
|
||
saveout 0xD98 %l 0xC
|
||
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
||
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
||
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
||
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
||
newline
|
||
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
||
group.long 0xDA0++0x03
|
||
saveout 0xD98 %l 0xC
|
||
line.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
|
||
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
||
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
||
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
||
else
|
||
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
||
saveout 0xD98 %l 0xC
|
||
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
||
newline
|
||
hgroup.long 0xDA0++0x03
|
||
saveout 0xD98 %l 0xC
|
||
hide.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
|
||
endif
|
||
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
||
group.long 0xD9C++0x03 "Region 13"
|
||
saveout 0xD98 %l 0xD
|
||
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
||
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
||
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
||
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
||
newline
|
||
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
||
group.long 0xDA0++0x03
|
||
saveout 0xD98 %l 0xD
|
||
line.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
|
||
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
||
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
||
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
||
else
|
||
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
||
saveout 0xD98 %l 0xD
|
||
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
||
newline
|
||
hgroup.long 0xDA0++0x03
|
||
saveout 0xD98 %l 0xD
|
||
hide.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
|
||
endif
|
||
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
||
group.long 0xD9C++0x03 "Region 14"
|
||
saveout 0xD98 %l 0xE
|
||
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
||
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
||
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
||
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
||
newline
|
||
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
||
group.long 0xDA0++0x03
|
||
saveout 0xD98 %l 0xE
|
||
line.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
|
||
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
||
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
||
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
||
else
|
||
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
||
saveout 0xD98 %l 0xE
|
||
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
||
newline
|
||
hgroup.long 0xDA0++0x03
|
||
saveout 0xD98 %l 0xE
|
||
hide.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
|
||
endif
|
||
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
||
group.long 0xD9C++0x03 "Region 15"
|
||
saveout 0xD98 %l 0xF
|
||
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
||
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
||
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
||
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
||
newline
|
||
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
||
group.long 0xDA0++0x03
|
||
saveout 0xD98 %l 0xF
|
||
line.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
|
||
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
||
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
||
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
||
else
|
||
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
||
saveout 0xD98 %l 0xF
|
||
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
||
newline
|
||
hgroup.long 0xDA0++0x03
|
||
saveout 0xD98 %l 0xF
|
||
hide.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
|
||
endif
|
||
tree.end
|
||
newline
|
||
group.long 0xDC0++0x07
|
||
line.long 0x00 "MPU_MAIR0,MPU Memory Attribute Indirection Register 0"
|
||
hexmask.long.byte 0x00 24.--31. 1. " ATTR3 ,Memory attribute encoding for MPU regions with an AttrIndex of 3"
|
||
hexmask.long.byte 0x00 16.--23. 1. " ATTR2 ,Memory attribute encoding for MPU regions with an AttrIndex of 2"
|
||
hexmask.long.byte 0x00 8.--15. 1. " ATTR1 ,Memory attribute encoding for MPU regions with an AttrIndex of 1"
|
||
hexmask.long.byte 0x00 0.--7. 1. " ATTR0 ,Memory attribute encoding for MPU regions with an AttrIndex of 0"
|
||
line.long 0x04 "MPU_MAIR1,MPU Memory Attribute Indirection Register 1"
|
||
hexmask.long.byte 0x04 24.--31. 1. " ATTR7 ,Memory attribute encoding for MPU regions with an AttrIndex of 7"
|
||
hexmask.long.byte 0x04 16.--23. 1. " ATTR6 ,Memory attribute encoding for MPU regions with an AttrIndex of 6"
|
||
hexmask.long.byte 0x04 8.--15. 1. " ATTR5 ,Memory attribute encoding for MPU regions with an AttrIndex of 5"
|
||
hexmask.long.byte 0x04 0.--7. 1. " ATTR4 ,Memory attribute encoding for MPU regions with an AttrIndex of 4"
|
||
width 0x0b
|
||
else
|
||
newline
|
||
textline "COREDEBUG component base address not specified"
|
||
newline
|
||
endif
|
||
tree.end
|
||
tree "Security Attribution Unit (SAU)"
|
||
sif COMPonent.AVAILABLE("COREDEBUG")
|
||
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
||
width 15.
|
||
group.long 0xDD0++0x03
|
||
line.long 0x00 "SAU_CTRL,SAU Control Register"
|
||
bitfld.long 0x00 1. " ALLNS ,When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure" "Secure,Non-Secure"
|
||
bitfld.long 0x00 0. " ENABLE ,Enables the SAU" "Disabled,Enabled"
|
||
rgroup.long 0xDD4++0x03
|
||
line.long 0x00 "SAU_TYPE,SAU Type Register"
|
||
bitfld.long 0x00 0.--7. " SREGION ,The number of implemented SAU regions" "0,,,,4,,,,8,?..."
|
||
group.long 0xDD8++0x03
|
||
line.long 0x00 "SAU_RNR,SAU Region Number Register"
|
||
hexmask.long.byte 0x00 0.--7. 1. " SAU_RNR ,Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR"
|
||
tree.close "SAU regions"
|
||
if ADDRESS.isSECUREEX(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD0)
|
||
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x0
|
||
group.long 0xDDC++0x03 "Region 0"
|
||
saveout 0xDD8 %l 0x0
|
||
line.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
|
||
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
||
group.long 0xDE0++0x03
|
||
saveout 0xDD8 %l 0x0
|
||
line.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
|
||
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
||
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
||
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
||
else
|
||
hgroup.long 0xDDC++0x03 "Region 0 (not implemented)"
|
||
saveout 0xDD8 %l 0x0
|
||
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
|
||
hgroup.long 0xDE0++0x03
|
||
saveout 0xDD8 %l 0x0
|
||
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
|
||
endif
|
||
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x1
|
||
group.long 0xDDC++0x03 "Region 1"
|
||
saveout 0xDD8 %l 0x1
|
||
line.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
|
||
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
||
group.long 0xDE0++0x03
|
||
saveout 0xDD8 %l 0x1
|
||
line.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
|
||
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
||
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
||
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
||
else
|
||
hgroup.long 0xDDC++0x03 "Region 1 (not implemented)"
|
||
saveout 0xDD8 %l 0x1
|
||
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
|
||
hgroup.long 0xDE0++0x03
|
||
saveout 0xDD8 %l 0x1
|
||
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
|
||
endif
|
||
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x2
|
||
group.long 0xDDC++0x03 "Region 2"
|
||
saveout 0xDD8 %l 0x2
|
||
line.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
|
||
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
||
group.long 0xDE0++0x03
|
||
saveout 0xDD8 %l 0x2
|
||
line.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
|
||
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
||
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
||
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
||
else
|
||
hgroup.long 0xDDC++0x03 "Region 2 (not implemented)"
|
||
saveout 0xDD8 %l 0x2
|
||
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
|
||
hgroup.long 0xDE0++0x03
|
||
saveout 0xDD8 %l 0x2
|
||
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
|
||
endif
|
||
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x3
|
||
group.long 0xDDC++0x03 "Region 3"
|
||
saveout 0xDD8 %l 0x3
|
||
line.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
|
||
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
||
group.long 0xDE0++0x03
|
||
saveout 0xDD8 %l 0x3
|
||
line.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
|
||
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
||
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
||
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
||
else
|
||
hgroup.long 0xDDC++0x03 "Region 3 (not implemented)"
|
||
saveout 0xDD8 %l 0x3
|
||
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
|
||
hgroup.long 0xDE0++0x03
|
||
saveout 0xDD8 %l 0x3
|
||
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
|
||
endif
|
||
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x4
|
||
group.long 0xDDC++0x03 "Region 4"
|
||
saveout 0xDD8 %l 0x4
|
||
line.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
|
||
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
||
group.long 0xDE0++0x03
|
||
saveout 0xDD8 %l 0x4
|
||
line.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
|
||
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
||
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
||
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
||
else
|
||
hgroup.long 0xDDC++0x03 "Region 4 (not implemented)"
|
||
saveout 0xDD8 %l 0x4
|
||
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
|
||
hgroup.long 0xDE0++0x03
|
||
saveout 0xDD8 %l 0x4
|
||
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
|
||
endif
|
||
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x5
|
||
group.long 0xDDC++0x03 "Region 5"
|
||
saveout 0xDD8 %l 0x5
|
||
line.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
|
||
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
||
group.long 0xDE0++0x03
|
||
saveout 0xDD8 %l 0x5
|
||
line.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
|
||
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
||
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
||
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
||
else
|
||
hgroup.long 0xDDC++0x03 "Region 5 (not implemented)"
|
||
saveout 0xDD8 %l 0x5
|
||
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
|
||
hgroup.long 0xDE0++0x03
|
||
saveout 0xDD8 %l 0x5
|
||
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
|
||
endif
|
||
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x6
|
||
group.long 0xDDC++0x03 "Region 6"
|
||
saveout 0xDD8 %l 0x6
|
||
line.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
|
||
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
||
group.long 0xDE0++0x03
|
||
saveout 0xDD8 %l 0x6
|
||
line.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
|
||
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
||
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
||
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
||
else
|
||
hgroup.long 0xDDC++0x03 "Region 6 (not implemented)"
|
||
saveout 0xDD8 %l 0x6
|
||
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
|
||
hgroup.long 0xDE0++0x03
|
||
saveout 0xDD8 %l 0x6
|
||
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
|
||
endif
|
||
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x7
|
||
group.long 0xDDC++0x03 "Region 7"
|
||
saveout 0xDD8 %l 0x7
|
||
line.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
|
||
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
||
group.long 0xDE0++0x03
|
||
saveout 0xDD8 %l 0x7
|
||
line.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
|
||
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
||
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
||
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
||
else
|
||
hgroup.long 0xDDC++0x03 "Region 7 (not implemented)"
|
||
saveout 0xDD8 %l 0x7
|
||
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
|
||
hgroup.long 0xDE0++0x03
|
||
saveout 0xDD8 %l 0x7
|
||
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
|
||
endif
|
||
else
|
||
hgroup.long 0xDDC++0x03 "Region 0 (not accessible)"
|
||
saveout 0xDD8 %l 0x0
|
||
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
|
||
hgroup.long 0xDE0++0x03
|
||
saveout 0xDD8 %l 0x0
|
||
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
|
||
hgroup.long 0xDDC++0x03 "Region 1 (not accessible)"
|
||
saveout 0xDD8 %l 0x1
|
||
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
|
||
hgroup.long 0xDE0++0x03
|
||
saveout 0xDD8 %l 0x1
|
||
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
|
||
hgroup.long 0xDDC++0x03 "Region 2 (not accessible)"
|
||
saveout 0xDD8 %l 0x2
|
||
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
|
||
hgroup.long 0xDE0++0x03
|
||
saveout 0xDD8 %l 0x2
|
||
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
|
||
hgroup.long 0xDDC++0x03 "Region 3 (not accessible)"
|
||
saveout 0xDD8 %l 0x3
|
||
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
|
||
hgroup.long 0xDE0++0x03
|
||
saveout 0xDD8 %l 0x3
|
||
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
|
||
hgroup.long 0xDDC++0x03 "Region 4 (not accessible)"
|
||
saveout 0xDD8 %l 0x4
|
||
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
|
||
hgroup.long 0xDE0++0x03
|
||
saveout 0xDD8 %l 0x4
|
||
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
|
||
hgroup.long 0xDDC++0x03 "Region 5 (not accessible)"
|
||
saveout 0xDD8 %l 0x5
|
||
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
|
||
hgroup.long 0xDE0++0x03
|
||
saveout 0xDD8 %l 0x5
|
||
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
|
||
hgroup.long 0xDDC++0x03 "Region 6 (not accessible)"
|
||
saveout 0xDD8 %l 0x6
|
||
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
|
||
hgroup.long 0xDE0++0x03
|
||
saveout 0xDD8 %l 0x6
|
||
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
|
||
hgroup.long 0xDDC++0x03 "Region 7 (not accessible)"
|
||
saveout 0xDD8 %l 0x7
|
||
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
|
||
hgroup.long 0xDE0++0x03
|
||
saveout 0xDD8 %l 0x7
|
||
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
|
||
hgroup.long 0xDDC++0x03 "Region 8 (not accessible)"
|
||
saveout 0xDD8 %l 0x8
|
||
hide.long 0x00 "SAU_RBAR8,SAU Region Base Address Register 8"
|
||
hgroup.long 0xDE0++0x03
|
||
saveout 0xDD8 %l 0x8
|
||
hide.long 0x00 "SAU_RLAR8,SAU Region Limit Address Register 8"
|
||
hgroup.long 0xDDC++0x03 "Region 9 (not accessible)"
|
||
saveout 0xDD8 %l 0x9
|
||
hide.long 0x00 "SAU_RBAR9,SAU Region Base Address Register 9"
|
||
hgroup.long 0xDE0++0x03
|
||
saveout 0xDD8 %l 0x9
|
||
hide.long 0x00 "SAU_RLAR9,SAU Region Limit Address Register 9"
|
||
hgroup.long 0xDDC++0x03 "Region 10 (not accessible)"
|
||
saveout 0xDD8 %l 0xA
|
||
hide.long 0x00 "SAU_RBAR10,SAU Region Base Address Register 10"
|
||
hgroup.long 0xDE0++0x03
|
||
saveout 0xDD8 %l 0xA
|
||
hide.long 0x00 "SAU_RLAR10,SAU Region Limit Address Register 10"
|
||
hgroup.long 0xDDC++0x03 "Region 11 (not accessible)"
|
||
saveout 0xDD8 %l 0xB
|
||
hide.long 0x00 "SAU_RBAR11,SAU Region Base Address Register 11"
|
||
hgroup.long 0xDE0++0x03
|
||
saveout 0xDD8 %l 0xB
|
||
hide.long 0x00 "SAU_RLAR11,SAU Region Limit Address Register 11"
|
||
hgroup.long 0xDDC++0x03 "Region 12 (not accessible)"
|
||
saveout 0xDD8 %l 0xC
|
||
hide.long 0x00 "SAU_RBAR12,SAU Region Base Address Register 12"
|
||
hgroup.long 0xDE0++0x03
|
||
saveout 0xDD8 %l 0xC
|
||
hide.long 0x00 "SAU_RLAR12,SAU Region Limit Address Register 12"
|
||
hgroup.long 0xDDC++0x03 "Region 13 (not accessible)"
|
||
saveout 0xDD8 %l 0xD
|
||
hide.long 0x00 "SAU_RBAR13,SAU Region Base Address Register 13"
|
||
hgroup.long 0xDE0++0x03
|
||
saveout 0xDD8 %l 0xD
|
||
hide.long 0x00 "SAU_RLAR13,SAU Region Limit Address Register 13"
|
||
hgroup.long 0xDDC++0x03 "Region 14 (not accessible)"
|
||
saveout 0xDD8 %l 0xE
|
||
hide.long 0x00 "SAU_RBAR14,SAU Region Base Address Register 14"
|
||
hgroup.long 0xDE0++0x03
|
||
saveout 0xDD8 %l 0xE
|
||
hide.long 0x00 "SAU_RLAR14,SAU Region Limit Address Register 14"
|
||
hgroup.long 0xDDC++0x03 "Region 15 (not accessible)"
|
||
saveout 0xDD8 %l 0xF
|
||
hide.long 0x00 "SAU_RBAR15,SAU Region Base Address Register 15"
|
||
hgroup.long 0xDE0++0x03
|
||
saveout 0xDD8 %l 0xF
|
||
hide.long 0x00 "SAU_RLAR15,SAU Region Limit Address Register 15"
|
||
endif
|
||
tree.end
|
||
width 0x0B
|
||
else
|
||
newline
|
||
textline "COREDEBUG component base address not specified"
|
||
newline
|
||
endif
|
||
tree.end
|
||
tree "Nested Vectored Interrupt Controller (NVIC)"
|
||
sif COMPonent.AVAILABLE("COREDEBUG")
|
||
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
||
width 6.
|
||
group.long 0x04++0x03
|
||
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
||
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,0-64,0-96,0-128,0-160,0-192,0-224,0-239,?..."
|
||
tree "Interrupt Enable Registers"
|
||
width 24.
|
||
group.long 0x100++0x03
|
||
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
||
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
textline " "
|
||
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
textline " "
|
||
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
textline " "
|
||
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
textline " "
|
||
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
textline " "
|
||
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
||
group.long 0x104++0x03
|
||
line.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
||
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
textline " "
|
||
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
textline " "
|
||
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
textline " "
|
||
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
textline " "
|
||
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
textline " "
|
||
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
else
|
||
hgroup.long 0x104++0x03
|
||
hide.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
||
endif
|
||
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
||
group.long 0x108++0x03
|
||
line.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
||
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
textline " "
|
||
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
textline " "
|
||
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
textline " "
|
||
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
textline " "
|
||
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
textline " "
|
||
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
else
|
||
hgroup.long 0x108++0x03
|
||
hide.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
||
endif
|
||
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
||
group.long 0x10C++0x03
|
||
line.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
||
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
textline " "
|
||
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
textline " "
|
||
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
textline " "
|
||
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
textline " "
|
||
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
textline " "
|
||
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
else
|
||
hgroup.long 0x10C++0x03
|
||
hide.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
||
endif
|
||
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
||
group.long 0x110++0x03
|
||
line.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
||
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
textline " "
|
||
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
textline " "
|
||
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
textline " "
|
||
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
textline " "
|
||
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
textline " "
|
||
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
else
|
||
hgroup.long 0x110++0x03
|
||
hide.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
||
endif
|
||
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
||
group.long 0x114++0x03
|
||
line.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
||
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
textline " "
|
||
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
textline " "
|
||
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
textline " "
|
||
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
textline " "
|
||
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
textline " "
|
||
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
else
|
||
hgroup.long 0x114++0x03
|
||
hide.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
||
endif
|
||
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
||
group.long 0x118++0x03
|
||
line.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
||
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
textline " "
|
||
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
textline " "
|
||
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
textline " "
|
||
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
textline " "
|
||
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
textline " "
|
||
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
else
|
||
hgroup.long 0x118++0x03
|
||
hide.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
||
endif
|
||
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
||
group.long 0x11C++0x03
|
||
line.long 0x00 "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
||
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
textline " "
|
||
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
textline " "
|
||
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
||
else
|
||
hgroup.long 0x11C++0x03
|
||
hide.long 0x00 "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
||
endif
|
||
tree.end
|
||
tree "Interrupt Pending Registers"
|
||
width 24.
|
||
group.long 0x200++0x03
|
||
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
||
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
textline " "
|
||
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
textline " "
|
||
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
textline " "
|
||
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
textline " "
|
||
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
textline " "
|
||
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
||
group.long 0x204++0x03
|
||
line.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
||
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
textline " "
|
||
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
textline " "
|
||
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
textline " "
|
||
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
textline " "
|
||
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
textline " "
|
||
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
else
|
||
hgroup.long 0x204++0x03
|
||
hide.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
||
endif
|
||
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
||
group.long 0x208++0x03
|
||
line.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
||
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
textline " "
|
||
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
textline " "
|
||
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
textline " "
|
||
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
textline " "
|
||
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
textline " "
|
||
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
else
|
||
hgroup.long 0x208++0x03
|
||
hide.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
||
endif
|
||
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
||
group.long 0x20C++0x03
|
||
line.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
||
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
textline " "
|
||
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
textline " "
|
||
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
textline " "
|
||
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
textline " "
|
||
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
textline " "
|
||
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
else
|
||
hgroup.long 0x20C++0x03
|
||
hide.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
||
endif
|
||
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
||
group.long 0x210++0x03
|
||
line.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
||
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
textline " "
|
||
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
textline " "
|
||
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
textline " "
|
||
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
textline " "
|
||
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
textline " "
|
||
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
else
|
||
hgroup.long 0x210++0x03
|
||
hide.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
||
endif
|
||
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
||
group.long 0x214++0x03
|
||
line.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
||
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
textline " "
|
||
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
textline " "
|
||
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
textline " "
|
||
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
textline " "
|
||
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
textline " "
|
||
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
else
|
||
hgroup.long 0x214++0x03
|
||
hide.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
||
endif
|
||
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
||
group.long 0x218++0x03
|
||
line.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
||
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
textline " "
|
||
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
textline " "
|
||
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
textline " "
|
||
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
textline " "
|
||
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
textline " "
|
||
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
else
|
||
hgroup.long 0x218++0x03
|
||
hide.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
||
endif
|
||
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
||
group.long 0x21C++0x03
|
||
line.long 0x00 "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
||
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
textline " "
|
||
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
textline " "
|
||
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
||
else
|
||
hgroup.long 0x21C++0x03
|
||
hide.long 0x00 "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
||
endif
|
||
tree.end
|
||
tree "Interrupt Active Bit Registers"
|
||
width 11.
|
||
rgroup.long 0x300++0x03
|
||
line.long 0x00 "ACTIVE0,Active Bit Register 0"
|
||
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
||
textline " "
|
||
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
||
textline " "
|
||
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
||
textline " "
|
||
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
||
textline " "
|
||
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
||
textline " "
|
||
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
||
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
||
rgroup.long 0x304++0x03
|
||
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
||
bitfld.long 0x00 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
||
textline " "
|
||
bitfld.long 0x00 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
||
textline " "
|
||
bitfld.long 0x00 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
||
textline " "
|
||
bitfld.long 0x00 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
||
textline " "
|
||
bitfld.long 0x00 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
||
textline " "
|
||
bitfld.long 0x00 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
||
else
|
||
hgroup.long 0x304++0x03
|
||
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
||
endif
|
||
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
||
rgroup.long 0x308++0x03
|
||
line.long 0x00 "ACTIVE2,Active Bit Register 2"
|
||
bitfld.long 0x00 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
||
textline " "
|
||
bitfld.long 0x00 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
||
textline " "
|
||
bitfld.long 0x00 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
||
textline " "
|
||
bitfld.long 0x00 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
||
textline " "
|
||
bitfld.long 0x00 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
||
textline " "
|
||
bitfld.long 0x00 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
||
else
|
||
hgroup.long 0x308++0x03
|
||
hide.long 0x00 "ACTIVE2,Active Bit Register 2"
|
||
endif
|
||
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
||
rgroup.long 0x30C++0x03
|
||
line.long 0x00 "ACTIVE3,Active Bit Register 3"
|
||
bitfld.long 0x00 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
||
textline " "
|
||
bitfld.long 0x00 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
||
textline " "
|
||
bitfld.long 0x00 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
||
textline " "
|
||
bitfld.long 0x00 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
||
textline " "
|
||
bitfld.long 0x00 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
||
textline " "
|
||
bitfld.long 0x00 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
||
else
|
||
hgroup.long 0x30C++0x03
|
||
hide.long 0x00 "ACTIVE3,Active Bit Register 3"
|
||
endif
|
||
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
||
rgroup.long 0x310++0x03
|
||
line.long 0x00 "ACTIVE4,Active Bit Register 4"
|
||
bitfld.long 0x00 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
||
textline " "
|
||
bitfld.long 0x00 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
||
textline " "
|
||
bitfld.long 0x00 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
||
textline " "
|
||
bitfld.long 0x00 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
||
textline " "
|
||
bitfld.long 0x00 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
||
textline " "
|
||
bitfld.long 0x00 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
||
else
|
||
hgroup.long 0x310++0x03
|
||
hide.long 0x00 "ACTIVE4,Active Bit Register 4"
|
||
endif
|
||
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
||
rgroup.long 0x314++0x03
|
||
line.long 0x00 "ACTIVE5,Active Bit Register 5"
|
||
bitfld.long 0x00 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
||
textline " "
|
||
bitfld.long 0x00 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
||
textline " "
|
||
bitfld.long 0x00 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
||
textline " "
|
||
bitfld.long 0x00 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
||
textline " "
|
||
bitfld.long 0x00 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
||
textline " "
|
||
bitfld.long 0x00 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
||
else
|
||
hgroup.long 0x314++0x03
|
||
hide.long 0x00 "ACTIVE5,Active Bit Register 5"
|
||
endif
|
||
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
||
rgroup.long 0x318++0x03
|
||
line.long 0x00 "ACTIVE6,Active Bit Register 6"
|
||
bitfld.long 0x00 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
||
textline " "
|
||
bitfld.long 0x00 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
||
textline " "
|
||
bitfld.long 0x00 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
||
textline " "
|
||
bitfld.long 0x00 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
||
textline " "
|
||
bitfld.long 0x00 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
||
textline " "
|
||
bitfld.long 0x00 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
||
else
|
||
hgroup.long 0x318++0x03
|
||
hide.long 0x00 "ACTIVE6,Active Bit Register 6"
|
||
endif
|
||
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
||
rgroup.long 0x31C++0x03
|
||
line.long 0x00 "ACTIVE7,Active Bit Register 7"
|
||
bitfld.long 0x00 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
||
textline " "
|
||
bitfld.long 0x00 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
||
textline " "
|
||
bitfld.long 0x00 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
||
bitfld.long 0x00 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
||
else
|
||
hgroup.long 0x31C++0x03
|
||
hide.long 0x00 "ACTIVE7,Active Bit Register 7"
|
||
endif
|
||
tree.end
|
||
tree "Interrupt Target Non-Secure Registers"
|
||
width 13.
|
||
group.long 0x380++0x03
|
||
line.long 0x00 "NVIC_ITNS0,Interrupt Target Non-Secure Register 0"
|
||
bitfld.long 0x00 31. " ITNS31 ,Interrupt Targets Non-secure 31" "Secure,Non-secure"
|
||
bitfld.long 0x00 30. " ITNS30 ,Interrupt Targets Non-secure 30" "Secure,Non-secure"
|
||
bitfld.long 0x00 29. " ITNS29 ,Interrupt Targets Non-secure 29" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 28. " ITNS28 ,Interrupt Targets Non-secure 28" "Secure,Non-secure"
|
||
bitfld.long 0x00 27. " ITNS27 ,Interrupt Targets Non-secure 27" "Secure,Non-secure"
|
||
bitfld.long 0x00 26. " ITNS26 ,Interrupt Targets Non-secure 26" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 25. " ITNS25 ,Interrupt Targets Non-secure 25" "Secure,Non-secure"
|
||
bitfld.long 0x00 24. " ITNS24 ,Interrupt Targets Non-secure 24" "Secure,Non-secure"
|
||
bitfld.long 0x00 23. " ITNS23 ,Interrupt Targets Non-secure 23" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 22. " ITNS22 ,Interrupt Targets Non-secure 22" "Secure,Non-secure"
|
||
bitfld.long 0x00 21. " ITNS21 ,Interrupt Targets Non-secure 21" "Secure,Non-secure"
|
||
bitfld.long 0x00 20. " ITNS20 ,Interrupt Targets Non-secure 20" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 19. " ITNS19 ,Interrupt Targets Non-secure 19" "Secure,Non-secure"
|
||
bitfld.long 0x00 18. " ITNS18 ,Interrupt Targets Non-secure 18" "Secure,Non-secure"
|
||
bitfld.long 0x00 17. " ITNS17 ,Interrupt Targets Non-secure 17" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 16. " ITNS16 ,Interrupt Targets Non-secure 16" "Secure,Non-secure"
|
||
bitfld.long 0x00 15. " ITNS15 ,Interrupt Targets Non-secure 15" "Secure,Non-secure"
|
||
bitfld.long 0x00 14. " ITNS14 ,Interrupt Targets Non-secure 14" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 13. " ITNS13 ,Interrupt Targets Non-secure 13" "Secure,Non-secure"
|
||
bitfld.long 0x00 12. " ITNS12 ,Interrupt Targets Non-secure 12" "Secure,Non-secure"
|
||
bitfld.long 0x00 11. " ITNS11 ,Interrupt Targets Non-secure 11" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 10. " ITNS10 ,Interrupt Targets Non-secure 10" "Secure,Non-secure"
|
||
bitfld.long 0x00 9. " ITNS9 ,Interrupt Targets Non-secure 9" "Secure,Non-secure"
|
||
bitfld.long 0x00 8. " ITNS8 ,Interrupt Targets Non-secure 8" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 7. " ITNS7 ,Interrupt Targets Non-secure 7" "Secure,Non-secure"
|
||
bitfld.long 0x00 6. " ITNS6 ,Interrupt Targets Non-secure 6" "Secure,Non-secure"
|
||
bitfld.long 0x00 5. " ITNS5 ,Interrupt Targets Non-secure 5" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 4. " ITNS4 ,Interrupt Targets Non-secure 4" "Secure,Non-secure"
|
||
bitfld.long 0x00 3. " ITNS3 ,Interrupt Targets Non-secure 3" "Secure,Non-secure"
|
||
bitfld.long 0x00 2. " ITNS2 ,Interrupt Targets Non-secure 2" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 1. " ITNS1 ,Interrupt Targets Non-secure 1" "Secure,Non-secure"
|
||
bitfld.long 0x00 0. " ITNS0 ,Interrupt Targets Non-secure 0" "Secure,Non-secure"
|
||
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
||
group.long 0x384++0x03
|
||
line.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
|
||
bitfld.long 0x00 31. " ITNS63 ,Interrupt Targets Non-secure 63" "Secure,Non-secure"
|
||
bitfld.long 0x00 30. " ITNS62 ,Interrupt Targets Non-secure 62" "Secure,Non-secure"
|
||
bitfld.long 0x00 29. " ITNS61 ,Interrupt Targets Non-secure 61" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 28. " ITNS60 ,Interrupt Targets Non-secure 60" "Secure,Non-secure"
|
||
bitfld.long 0x00 27. " ITNS59 ,Interrupt Targets Non-secure 59" "Secure,Non-secure"
|
||
bitfld.long 0x00 26. " ITNS58 ,Interrupt Targets Non-secure 58" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 25. " ITNS57 ,Interrupt Targets Non-secure 57" "Secure,Non-secure"
|
||
bitfld.long 0x00 24. " ITNS56 ,Interrupt Targets Non-secure 56" "Secure,Non-secure"
|
||
bitfld.long 0x00 23. " ITNS55 ,Interrupt Targets Non-secure 55" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 22. " ITNS54 ,Interrupt Targets Non-secure 54" "Secure,Non-secure"
|
||
bitfld.long 0x00 21. " ITNS53 ,Interrupt Targets Non-secure 53" "Secure,Non-secure"
|
||
bitfld.long 0x00 20. " ITNS52 ,Interrupt Targets Non-secure 52" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 19. " ITNS51 ,Interrupt Targets Non-secure 51" "Secure,Non-secure"
|
||
bitfld.long 0x00 18. " ITNS50 ,Interrupt Targets Non-secure 50" "Secure,Non-secure"
|
||
bitfld.long 0x00 17. " ITNS49 ,Interrupt Targets Non-secure 49" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 16. " ITNS48 ,Interrupt Targets Non-secure 48" "Secure,Non-secure"
|
||
bitfld.long 0x00 15. " ITNS47 ,Interrupt Targets Non-secure 47" "Secure,Non-secure"
|
||
bitfld.long 0x00 14. " ITNS46 ,Interrupt Targets Non-secure 46" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 13. " ITNS45 ,Interrupt Targets Non-secure 45" "Secure,Non-secure"
|
||
bitfld.long 0x00 12. " ITNS44 ,Interrupt Targets Non-secure 44" "Secure,Non-secure"
|
||
bitfld.long 0x00 11. " ITNS43 ,Interrupt Targets Non-secure 43" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 10. " ITNS42 ,Interrupt Targets Non-secure 42" "Secure,Non-secure"
|
||
bitfld.long 0x00 9. " ITNS41 ,Interrupt Targets Non-secure 41" "Secure,Non-secure"
|
||
bitfld.long 0x00 8. " ITNS40 ,Interrupt Targets Non-secure 40" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 7. " ITNS39 ,Interrupt Targets Non-secure 39" "Secure,Non-secure"
|
||
bitfld.long 0x00 6. " ITNS38 ,Interrupt Targets Non-secure 38" "Secure,Non-secure"
|
||
bitfld.long 0x00 5. " ITNS37 ,Interrupt Targets Non-secure 37" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 4. " ITNS36 ,Interrupt Targets Non-secure 36" "Secure,Non-secure"
|
||
bitfld.long 0x00 3. " ITNS35 ,Interrupt Targets Non-secure 35" "Secure,Non-secure"
|
||
bitfld.long 0x00 2. " ITNS34 ,Interrupt Targets Non-secure 34" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 1. " ITNS33 ,Interrupt Targets Non-secure 33" "Secure,Non-secure"
|
||
bitfld.long 0x00 0. " ITNS32 ,Interrupt Targets Non-secure 32" "Secure,Non-secure"
|
||
else
|
||
hgroup.long 0x384++0x03
|
||
hide.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
|
||
endif
|
||
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
||
group.long 0x388++0x03
|
||
line.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
|
||
bitfld.long 0x00 31. " ITNS95 ,Interrupt Targets Non-secure 95" "Secure,Non-secure"
|
||
bitfld.long 0x00 30. " ITNS94 ,Interrupt Targets Non-secure 94" "Secure,Non-secure"
|
||
bitfld.long 0x00 29. " ITNS93 ,Interrupt Targets Non-secure 93" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 28. " ITNS92 ,Interrupt Targets Non-secure 92" "Secure,Non-secure"
|
||
bitfld.long 0x00 27. " ITNS91 ,Interrupt Targets Non-secure 91" "Secure,Non-secure"
|
||
bitfld.long 0x00 26. " ITNS90 ,Interrupt Targets Non-secure 90" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 25. " ITNS89 ,Interrupt Targets Non-secure 89" "Secure,Non-secure"
|
||
bitfld.long 0x00 24. " ITNS88 ,Interrupt Targets Non-secure 88" "Secure,Non-secure"
|
||
bitfld.long 0x00 23. " ITNS87 ,Interrupt Targets Non-secure 87" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 22. " ITNS86 ,Interrupt Targets Non-secure 86" "Secure,Non-secure"
|
||
bitfld.long 0x00 21. " ITNS85 ,Interrupt Targets Non-secure 85" "Secure,Non-secure"
|
||
bitfld.long 0x00 20. " ITNS84 ,Interrupt Targets Non-secure 84" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 19. " ITNS83 ,Interrupt Targets Non-secure 83" "Secure,Non-secure"
|
||
bitfld.long 0x00 18. " ITNS82 ,Interrupt Targets Non-secure 82" "Secure,Non-secure"
|
||
bitfld.long 0x00 17. " ITNS81 ,Interrupt Targets Non-secure 81" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 16. " ITNS80 ,Interrupt Targets Non-secure 80" "Secure,Non-secure"
|
||
bitfld.long 0x00 15. " ITNS79 ,Interrupt Targets Non-secure 79" "Secure,Non-secure"
|
||
bitfld.long 0x00 14. " ITNS78 ,Interrupt Targets Non-secure 78" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 13. " ITNS77 ,Interrupt Targets Non-secure 77" "Secure,Non-secure"
|
||
bitfld.long 0x00 12. " ITNS76 ,Interrupt Targets Non-secure 76" "Secure,Non-secure"
|
||
bitfld.long 0x00 11. " ITNS75 ,Interrupt Targets Non-secure 75" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 10. " ITNS74 ,Interrupt Targets Non-secure 74" "Secure,Non-secure"
|
||
bitfld.long 0x00 9. " ITNS73 ,Interrupt Targets Non-secure 73" "Secure,Non-secure"
|
||
bitfld.long 0x00 8. " ITNS72 ,Interrupt Targets Non-secure 72" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 7. " ITNS71 ,Interrupt Targets Non-secure 71" "Secure,Non-secure"
|
||
bitfld.long 0x00 6. " ITNS70 ,Interrupt Targets Non-secure 70" "Secure,Non-secure"
|
||
bitfld.long 0x00 5. " ITNS69 ,Interrupt Targets Non-secure 69" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 4. " ITNS68 ,Interrupt Targets Non-secure 68" "Secure,Non-secure"
|
||
bitfld.long 0x00 3. " ITNS67 ,Interrupt Targets Non-secure 67" "Secure,Non-secure"
|
||
bitfld.long 0x00 2. " ITNS66 ,Interrupt Targets Non-secure 66" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 1. " ITNS65 ,Interrupt Targets Non-secure 65" "Secure,Non-secure"
|
||
bitfld.long 0x00 0. " ITNS64 ,Interrupt Targets Non-secure 64" "Secure,Non-secure"
|
||
else
|
||
hgroup.long 0x388++0x03
|
||
hide.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
|
||
endif
|
||
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
||
group.long 0x38C++0x03
|
||
line.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
|
||
bitfld.long 0x00 31. " ITNS127 ,Interrupt Targets Non-secure 127" "Secure,Non-secure"
|
||
bitfld.long 0x00 30. " ITNS126 ,Interrupt Targets Non-secure 126" "Secure,Non-secure"
|
||
bitfld.long 0x00 29. " ITNS125 ,Interrupt Targets Non-secure 125" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 28. " ITNS124 ,Interrupt Targets Non-secure 124" "Secure,Non-secure"
|
||
bitfld.long 0x00 27. " ITNS123 ,Interrupt Targets Non-secure 123" "Secure,Non-secure"
|
||
bitfld.long 0x00 26. " ITNS122 ,Interrupt Targets Non-secure 122" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 25. " ITNS121 ,Interrupt Targets Non-secure 121" "Secure,Non-secure"
|
||
bitfld.long 0x00 24. " ITNS120 ,Interrupt Targets Non-secure 120" "Secure,Non-secure"
|
||
bitfld.long 0x00 23. " ITNS119 ,Interrupt Targets Non-secure 119" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 22. " ITNS118 ,Interrupt Targets Non-secure 118" "Secure,Non-secure"
|
||
bitfld.long 0x00 21. " ITNS117 ,Interrupt Targets Non-secure 117" "Secure,Non-secure"
|
||
bitfld.long 0x00 20. " ITNS116 ,Interrupt Targets Non-secure 116" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 19. " ITNS115 ,Interrupt Targets Non-secure 115" "Secure,Non-secure"
|
||
bitfld.long 0x00 18. " ITNS114 ,Interrupt Targets Non-secure 114" "Secure,Non-secure"
|
||
bitfld.long 0x00 17. " ITNS113 ,Interrupt Targets Non-secure 113" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 16. " ITNS112 ,Interrupt Targets Non-secure 112" "Secure,Non-secure"
|
||
bitfld.long 0x00 15. " ITNS111 ,Interrupt Targets Non-secure 111" "Secure,Non-secure"
|
||
bitfld.long 0x00 14. " ITNS110 ,Interrupt Targets Non-secure 110" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 13. " ITNS109 ,Interrupt Targets Non-secure 109" "Secure,Non-secure"
|
||
bitfld.long 0x00 12. " ITNS108 ,Interrupt Targets Non-secure 108" "Secure,Non-secure"
|
||
bitfld.long 0x00 11. " ITNS107 ,Interrupt Targets Non-secure 107" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 10. " ITNS106 ,Interrupt Targets Non-secure 106" "Secure,Non-secure"
|
||
bitfld.long 0x00 9. " ITNS105 ,Interrupt Targets Non-secure 105" "Secure,Non-secure"
|
||
bitfld.long 0x00 8. " ITNS104 ,Interrupt Targets Non-secure 104" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 7. " ITNS103 ,Interrupt Targets Non-secure 103" "Secure,Non-secure"
|
||
bitfld.long 0x00 6. " ITNS102 ,Interrupt Targets Non-secure 102" "Secure,Non-secure"
|
||
bitfld.long 0x00 5. " ITNS101 ,Interrupt Targets Non-secure 101" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 4. " ITNS100 ,Interrupt Targets Non-secure 100" "Secure,Non-secure"
|
||
bitfld.long 0x00 3. " ITNS99 ,Interrupt Targets Non-secure 99" "Secure,Non-secure"
|
||
bitfld.long 0x00 2. " ITNS98 ,Interrupt Targets Non-secure 98" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 1. " ITNS97 ,Interrupt Targets Non-secure 97" "Secure,Non-secure"
|
||
bitfld.long 0x00 0. " ITNS96 ,Interrupt Targets Non-secure 96" "Secure,Non-secure"
|
||
else
|
||
hgroup.long 0x38C++0x03
|
||
hide.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
|
||
endif
|
||
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
||
group.long 0x390++0x03
|
||
line.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
|
||
bitfld.long 0x00 31. " ITNS159 ,Interrupt Targets Non-secure 159" "Secure,Non-secure"
|
||
bitfld.long 0x00 30. " ITNS158 ,Interrupt Targets Non-secure 158" "Secure,Non-secure"
|
||
bitfld.long 0x00 29. " ITNS157 ,Interrupt Targets Non-secure 157" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 28. " ITNS156 ,Interrupt Targets Non-secure 156" "Secure,Non-secure"
|
||
bitfld.long 0x00 27. " ITNS155 ,Interrupt Targets Non-secure 155" "Secure,Non-secure"
|
||
bitfld.long 0x00 26. " ITNS154 ,Interrupt Targets Non-secure 154" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 25. " ITNS153 ,Interrupt Targets Non-secure 153" "Secure,Non-secure"
|
||
bitfld.long 0x00 24. " ITNS152 ,Interrupt Targets Non-secure 152" "Secure,Non-secure"
|
||
bitfld.long 0x00 23. " ITNS151 ,Interrupt Targets Non-secure 151" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 22. " ITNS150 ,Interrupt Targets Non-secure 150" "Secure,Non-secure"
|
||
bitfld.long 0x00 21. " ITNS149 ,Interrupt Targets Non-secure 149" "Secure,Non-secure"
|
||
bitfld.long 0x00 20. " ITNS148 ,Interrupt Targets Non-secure 148" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 19. " ITNS147 ,Interrupt Targets Non-secure 147" "Secure,Non-secure"
|
||
bitfld.long 0x00 18. " ITNS146 ,Interrupt Targets Non-secure 146" "Secure,Non-secure"
|
||
bitfld.long 0x00 17. " ITNS145 ,Interrupt Targets Non-secure 145" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 16. " ITNS144 ,Interrupt Targets Non-secure 144" "Secure,Non-secure"
|
||
bitfld.long 0x00 15. " ITNS143 ,Interrupt Targets Non-secure 143" "Secure,Non-secure"
|
||
bitfld.long 0x00 14. " ITNS142 ,Interrupt Targets Non-secure 142" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 13. " ITNS141 ,Interrupt Targets Non-secure 141" "Secure,Non-secure"
|
||
bitfld.long 0x00 12. " ITNS140 ,Interrupt Targets Non-secure 140" "Secure,Non-secure"
|
||
bitfld.long 0x00 11. " ITNS139 ,Interrupt Targets Non-secure 139" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 10. " ITNS138 ,Interrupt Targets Non-secure 138" "Secure,Non-secure"
|
||
bitfld.long 0x00 9. " ITNS137 ,Interrupt Targets Non-secure 137" "Secure,Non-secure"
|
||
bitfld.long 0x00 8. " ITNS136 ,Interrupt Targets Non-secure 136" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 7. " ITNS135 ,Interrupt Targets Non-secure 135" "Secure,Non-secure"
|
||
bitfld.long 0x00 6. " ITNS134 ,Interrupt Targets Non-secure 134" "Secure,Non-secure"
|
||
bitfld.long 0x00 5. " ITNS133 ,Interrupt Targets Non-secure 133" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 4. " ITNS132 ,Interrupt Targets Non-secure 132" "Secure,Non-secure"
|
||
bitfld.long 0x00 3. " ITNS131 ,Interrupt Targets Non-secure 131" "Secure,Non-secure"
|
||
bitfld.long 0x00 2. " ITNS130 ,Interrupt Targets Non-secure 130" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 1. " ITNS129 ,Interrupt Targets Non-secure 129" "Secure,Non-secure"
|
||
bitfld.long 0x00 0. " ITNS128 ,Interrupt Targets Non-secure 128" "Secure,Non-secure"
|
||
else
|
||
hgroup.long 0x390++0x03
|
||
hide.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
|
||
endif
|
||
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
||
group.long 0x394++0x03
|
||
line.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
|
||
bitfld.long 0x00 31. " ITNS191 ,Interrupt Targets Non-secure 191" "Secure,Non-secure"
|
||
bitfld.long 0x00 30. " ITNS190 ,Interrupt Targets Non-secure 190" "Secure,Non-secure"
|
||
bitfld.long 0x00 29. " ITNS189 ,Interrupt Targets Non-secure 189" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 28. " ITNS188 ,Interrupt Targets Non-secure 188" "Secure,Non-secure"
|
||
bitfld.long 0x00 27. " ITNS187 ,Interrupt Targets Non-secure 187" "Secure,Non-secure"
|
||
bitfld.long 0x00 26. " ITNS186 ,Interrupt Targets Non-secure 186" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 25. " ITNS185 ,Interrupt Targets Non-secure 185" "Secure,Non-secure"
|
||
bitfld.long 0x00 24. " ITNS184 ,Interrupt Targets Non-secure 184" "Secure,Non-secure"
|
||
bitfld.long 0x00 23. " ITNS183 ,Interrupt Targets Non-secure 183" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 22. " ITNS182 ,Interrupt Targets Non-secure 182" "Secure,Non-secure"
|
||
bitfld.long 0x00 21. " ITNS181 ,Interrupt Targets Non-secure 181" "Secure,Non-secure"
|
||
bitfld.long 0x00 20. " ITNS180 ,Interrupt Targets Non-secure 180" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 19. " ITNS179 ,Interrupt Targets Non-secure 179" "Secure,Non-secure"
|
||
bitfld.long 0x00 18. " ITNS178 ,Interrupt Targets Non-secure 178" "Secure,Non-secure"
|
||
bitfld.long 0x00 17. " ITNS177 ,Interrupt Targets Non-secure 177" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 16. " ITNS176 ,Interrupt Targets Non-secure 176" "Secure,Non-secure"
|
||
bitfld.long 0x00 15. " ITNS175 ,Interrupt Targets Non-secure 175" "Secure,Non-secure"
|
||
bitfld.long 0x00 14. " ITNS174 ,Interrupt Targets Non-secure 174" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 13. " ITNS173 ,Interrupt Targets Non-secure 173" "Secure,Non-secure"
|
||
bitfld.long 0x00 12. " ITNS172 ,Interrupt Targets Non-secure 172" "Secure,Non-secure"
|
||
bitfld.long 0x00 11. " ITNS171 ,Interrupt Targets Non-secure 171" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 10. " ITNS170 ,Interrupt Targets Non-secure 170" "Secure,Non-secure"
|
||
bitfld.long 0x00 9. " ITNS169 ,Interrupt Targets Non-secure 169" "Secure,Non-secure"
|
||
bitfld.long 0x00 8. " ITNS168 ,Interrupt Targets Non-secure 168" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 7. " ITNS167 ,Interrupt Targets Non-secure 167" "Secure,Non-secure"
|
||
bitfld.long 0x00 6. " ITNS166 ,Interrupt Targets Non-secure 166" "Secure,Non-secure"
|
||
bitfld.long 0x00 5. " ITNS165 ,Interrupt Targets Non-secure 165" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 4. " ITNS164 ,Interrupt Targets Non-secure 164" "Secure,Non-secure"
|
||
bitfld.long 0x00 3. " ITNS163 ,Interrupt Targets Non-secure 163" "Secure,Non-secure"
|
||
bitfld.long 0x00 2. " ITNS162 ,Interrupt Targets Non-secure 162" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 1. " ITNS161 ,Interrupt Targets Non-secure 161" "Secure,Non-secure"
|
||
bitfld.long 0x00 0. " ITNS160 ,Interrupt Targets Non-secure 160" "Secure,Non-secure"
|
||
else
|
||
hgroup.long 0x394++0x03
|
||
hide.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
|
||
endif
|
||
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
||
group.long 0x398++0x03
|
||
line.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
|
||
bitfld.long 0x00 31. " ITNS223 ,Interrupt Targets Non-secure 223" "Secure,Non-secure"
|
||
bitfld.long 0x00 30. " ITNS222 ,Interrupt Targets Non-secure 222" "Secure,Non-secure"
|
||
bitfld.long 0x00 29. " ITNS221 ,Interrupt Targets Non-secure 221" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 28. " ITNS220 ,Interrupt Targets Non-secure 220" "Secure,Non-secure"
|
||
bitfld.long 0x00 27. " ITNS219 ,Interrupt Targets Non-secure 219" "Secure,Non-secure"
|
||
bitfld.long 0x00 26. " ITNS218 ,Interrupt Targets Non-secure 218" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 25. " ITNS217 ,Interrupt Targets Non-secure 217" "Secure,Non-secure"
|
||
bitfld.long 0x00 24. " ITNS216 ,Interrupt Targets Non-secure 216" "Secure,Non-secure"
|
||
bitfld.long 0x00 23. " ITNS215 ,Interrupt Targets Non-secure 215" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 22. " ITNS214 ,Interrupt Targets Non-secure 214" "Secure,Non-secure"
|
||
bitfld.long 0x00 21. " ITNS213 ,Interrupt Targets Non-secure 213" "Secure,Non-secure"
|
||
bitfld.long 0x00 20. " ITNS212 ,Interrupt Targets Non-secure 212" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 19. " ITNS211 ,Interrupt Targets Non-secure 211" "Secure,Non-secure"
|
||
bitfld.long 0x00 18. " ITNS210 ,Interrupt Targets Non-secure 210" "Secure,Non-secure"
|
||
bitfld.long 0x00 17. " ITNS209 ,Interrupt Targets Non-secure 209" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 16. " ITNS208 ,Interrupt Targets Non-secure 208" "Secure,Non-secure"
|
||
bitfld.long 0x00 15. " ITNS207 ,Interrupt Targets Non-secure 207" "Secure,Non-secure"
|
||
bitfld.long 0x00 14. " ITNS206 ,Interrupt Targets Non-secure 206" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 13. " ITNS205 ,Interrupt Targets Non-secure 205" "Secure,Non-secure"
|
||
bitfld.long 0x00 12. " ITNS204 ,Interrupt Targets Non-secure 204" "Secure,Non-secure"
|
||
bitfld.long 0x00 11. " ITNS203 ,Interrupt Targets Non-secure 203" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 10. " ITNS202 ,Interrupt Targets Non-secure 202" "Secure,Non-secure"
|
||
bitfld.long 0x00 9. " ITNS201 ,Interrupt Targets Non-secure 201" "Secure,Non-secure"
|
||
bitfld.long 0x00 8. " ITNS200 ,Interrupt Targets Non-secure 200" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 7. " ITNS199 ,Interrupt Targets Non-secure 199" "Secure,Non-secure"
|
||
bitfld.long 0x00 6. " ITNS198 ,Interrupt Targets Non-secure 198" "Secure,Non-secure"
|
||
bitfld.long 0x00 5. " ITNS197 ,Interrupt Targets Non-secure 197" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 4. " ITNS196 ,Interrupt Targets Non-secure 196" "Secure,Non-secure"
|
||
bitfld.long 0x00 3. " ITNS195 ,Interrupt Targets Non-secure 195" "Secure,Non-secure"
|
||
bitfld.long 0x00 2. " ITNS194 ,Interrupt Targets Non-secure 194" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 1. " ITNS193 ,Interrupt Targets Non-secure 193" "Secure,Non-secure"
|
||
bitfld.long 0x00 0. " ITNS192 ,Interrupt Targets Non-secure 192" "Secure,Non-secure"
|
||
else
|
||
hgroup.long 0x398++0x03
|
||
hide.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
|
||
endif
|
||
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
||
group.long 0x39C++0x03
|
||
line.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
|
||
bitfld.long 0x00 15. " ITNS239 ,Interrupt Targets Non-secure 239" "Secure,Non-secure"
|
||
bitfld.long 0x00 14. " ITNS238 ,Interrupt Targets Non-secure 238" "Secure,Non-secure"
|
||
bitfld.long 0x00 13. " ITNS237 ,Interrupt Targets Non-secure 237" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 12. " ITNS236 ,Interrupt Targets Non-secure 236" "Secure,Non-secure"
|
||
bitfld.long 0x00 11. " ITNS235 ,Interrupt Targets Non-secure 235" "Secure,Non-secure"
|
||
bitfld.long 0x00 10. " ITNS234 ,Interrupt Targets Non-secure 234" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 9. " ITNS233 ,Interrupt Targets Non-secure 233" "Secure,Non-secure"
|
||
bitfld.long 0x00 8. " ITNS232 ,Interrupt Targets Non-secure 232" "Secure,Non-secure"
|
||
bitfld.long 0x00 7. " ITNS231 ,Interrupt Targets Non-secure 231" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 6. " ITNS230 ,Interrupt Targets Non-secure 230" "Secure,Non-secure"
|
||
bitfld.long 0x00 5. " ITNS229 ,Interrupt Targets Non-secure 229" "Secure,Non-secure"
|
||
bitfld.long 0x00 4. " ITNS228 ,Interrupt Targets Non-secure 228" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 3. " ITNS227 ,Interrupt Targets Non-secure 227" "Secure,Non-secure"
|
||
bitfld.long 0x00 2. " ITNS226 ,Interrupt Targets Non-secure 226" "Secure,Non-secure"
|
||
bitfld.long 0x00 1. " ITNS225 ,Interrupt Targets Non-secure 225" "Secure,Non-secure"
|
||
textline " "
|
||
bitfld.long 0x00 0. " ITNS224 ,Interrupt Targets Non-secure 224" "Secure,Non-secure"
|
||
else
|
||
hgroup.long 0x39C++0x03
|
||
hide.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
|
||
endif
|
||
tree.end
|
||
tree "Interrupt Priority Registers"
|
||
group.long 0x400++0x1F
|
||
line.long 0x0 "IPR0,Interrupt Priority Register"
|
||
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
||
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
||
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
||
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
||
line.long 0x4 "IPR1,Interrupt Priority Register"
|
||
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
||
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
||
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
||
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
||
line.long 0x8 "IPR2,Interrupt Priority Register"
|
||
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
||
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
||
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
||
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
||
line.long 0xC "IPR3,Interrupt Priority Register"
|
||
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
||
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
||
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
||
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
||
line.long 0x10 "IPR4,Interrupt Priority Register"
|
||
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
||
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
||
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
||
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
||
line.long 0x14 "IPR5,Interrupt Priority Register"
|
||
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
||
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
||
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
||
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
||
line.long 0x18 "IPR6,Interrupt Priority Register"
|
||
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
||
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
||
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
||
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
||
line.long 0x1C "IPR7,Interrupt Priority Register"
|
||
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
||
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
||
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
||
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
||
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
||
group.long 0x420++0x1F
|
||
line.long 0x0 "IPR8,Interrupt Priority Register"
|
||
hexmask.long.byte 0x0 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
||
hexmask.long.byte 0x0 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
||
hexmask.long.byte 0x0 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
||
hexmask.long.byte 0x0 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
||
line.long 0x4 "IPR9,Interrupt Priority Register"
|
||
hexmask.long.byte 0x4 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
||
hexmask.long.byte 0x4 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
||
hexmask.long.byte 0x4 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
||
hexmask.long.byte 0x4 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
||
line.long 0x8 "IPR10,Interrupt Priority Register"
|
||
hexmask.long.byte 0x8 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
||
hexmask.long.byte 0x8 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
||
hexmask.long.byte 0x8 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
||
hexmask.long.byte 0x8 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
||
line.long 0xC "IPR11,Interrupt Priority Register"
|
||
hexmask.long.byte 0xC 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
||
hexmask.long.byte 0xC 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
||
hexmask.long.byte 0xC 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
||
hexmask.long.byte 0xC 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
||
line.long 0x10 "IPR12,Interrupt Priority Register"
|
||
hexmask.long.byte 0x10 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
||
hexmask.long.byte 0x10 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
||
hexmask.long.byte 0x10 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
||
hexmask.long.byte 0x10 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
||
line.long 0x14 "IPR13,Interrupt Priority Register"
|
||
hexmask.long.byte 0x14 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
||
hexmask.long.byte 0x14 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
||
hexmask.long.byte 0x14 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
||
hexmask.long.byte 0x14 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
||
line.long 0x18 "IPR14,Interrupt Priority Register"
|
||
hexmask.long.byte 0x18 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
||
hexmask.long.byte 0x18 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
||
hexmask.long.byte 0x18 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
||
hexmask.long.byte 0x18 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
||
line.long 0x1C "IPR15,Interrupt Priority Register"
|
||
hexmask.long.byte 0x1C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
||
hexmask.long.byte 0x1C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
||
hexmask.long.byte 0x1C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
||
hexmask.long.byte 0x1C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
||
else
|
||
hgroup.long 0x420++0x1F
|
||
hide.long 0x0 "IPR8,Interrupt Priority Register"
|
||
hide.long 0x4 "IPR9,Interrupt Priority Register"
|
||
hide.long 0x8 "IPR10,Interrupt Priority Register"
|
||
hide.long 0xC "IPR11,Interrupt Priority Register"
|
||
hide.long 0x10 "IPR12,Interrupt Priority Register"
|
||
hide.long 0x14 "IPR13,Interrupt Priority Register"
|
||
hide.long 0x18 "IPR14,Interrupt Priority Register"
|
||
hide.long 0x1C "IPR15,Interrupt Priority Register"
|
||
endif
|
||
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
||
group.long 0x440++0x1F
|
||
line.long 0x0 "IPR16,Interrupt Priority Register"
|
||
hexmask.long.byte 0x0 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
||
hexmask.long.byte 0x0 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
||
hexmask.long.byte 0x0 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
||
hexmask.long.byte 0x0 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
||
line.long 0x4 "IPR17,Interrupt Priority Register"
|
||
hexmask.long.byte 0x4 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
||
hexmask.long.byte 0x4 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
||
hexmask.long.byte 0x4 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
||
hexmask.long.byte 0x4 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
||
line.long 0x8 "IPR18,Interrupt Priority Register"
|
||
hexmask.long.byte 0x8 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
||
hexmask.long.byte 0x8 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
||
hexmask.long.byte 0x8 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
||
hexmask.long.byte 0x8 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
||
line.long 0xC "IPR19,Interrupt Priority Register"
|
||
hexmask.long.byte 0xC 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
||
hexmask.long.byte 0xC 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
||
hexmask.long.byte 0xC 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
||
hexmask.long.byte 0xC 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
||
line.long 0x10 "IPR20,Interrupt Priority Register"
|
||
hexmask.long.byte 0x10 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
||
hexmask.long.byte 0x10 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
||
hexmask.long.byte 0x10 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
||
hexmask.long.byte 0x10 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
||
line.long 0x14 "IPR21,Interrupt Priority Register"
|
||
hexmask.long.byte 0x14 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
||
hexmask.long.byte 0x14 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
||
hexmask.long.byte 0x14 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
||
hexmask.long.byte 0x14 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
||
line.long 0x18 "IPR22,Interrupt Priority Register"
|
||
hexmask.long.byte 0x18 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
||
hexmask.long.byte 0x18 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
||
hexmask.long.byte 0x18 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
||
hexmask.long.byte 0x18 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
||
line.long 0x1C "IPR23,Interrupt Priority Register"
|
||
hexmask.long.byte 0x1C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
||
hexmask.long.byte 0x1C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
||
hexmask.long.byte 0x1C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
||
hexmask.long.byte 0x1C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
||
else
|
||
hgroup.long 0x440++0x1F
|
||
hide.long 0x0 "IPR16,Interrupt Priority Register"
|
||
hide.long 0x4 "IPR17,Interrupt Priority Register"
|
||
hide.long 0x8 "IPR18,Interrupt Priority Register"
|
||
hide.long 0xC "IPR19,Interrupt Priority Register"
|
||
hide.long 0x10 "IPR20,Interrupt Priority Register"
|
||
hide.long 0x14 "IPR21,Interrupt Priority Register"
|
||
hide.long 0x18 "IPR22,Interrupt Priority Register"
|
||
hide.long 0x1C "IPR23,Interrupt Priority Register"
|
||
endif
|
||
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
||
group.long 0x460++0x1F
|
||
line.long 0x0 "IPR24,Interrupt Priority Register"
|
||
hexmask.long.byte 0x0 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
||
hexmask.long.byte 0x0 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
||
hexmask.long.byte 0x0 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
||
hexmask.long.byte 0x0 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
||
line.long 0x4 "IPR25,Interrupt Priority Register"
|
||
hexmask.long.byte 0x4 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
||
hexmask.long.byte 0x4 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
||
hexmask.long.byte 0x4 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
||
hexmask.long.byte 0x4 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
||
line.long 0x8 "IPR26,Interrupt Priority Register"
|
||
hexmask.long.byte 0x8 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
||
hexmask.long.byte 0x8 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
||
hexmask.long.byte 0x8 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
||
hexmask.long.byte 0x8 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
||
line.long 0xC "IPR27,Interrupt Priority Register"
|
||
hexmask.long.byte 0xC 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
||
hexmask.long.byte 0xC 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
||
hexmask.long.byte 0xC 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
||
hexmask.long.byte 0xC 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
||
line.long 0x10 "IPR28,Interrupt Priority Register"
|
||
hexmask.long.byte 0x10 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
||
hexmask.long.byte 0x10 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
||
hexmask.long.byte 0x10 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
||
hexmask.long.byte 0x10 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
||
line.long 0x14 "IPR29,Interrupt Priority Register"
|
||
hexmask.long.byte 0x14 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
||
hexmask.long.byte 0x14 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
||
hexmask.long.byte 0x14 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
||
hexmask.long.byte 0x14 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
||
line.long 0x18 "IPR30,Interrupt Priority Register"
|
||
hexmask.long.byte 0x18 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
||
hexmask.long.byte 0x18 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
||
hexmask.long.byte 0x18 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
||
hexmask.long.byte 0x18 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
||
line.long 0x1C "IPR31,Interrupt Priority Register"
|
||
hexmask.long.byte 0x1C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
||
hexmask.long.byte 0x1C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
||
hexmask.long.byte 0x1C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
||
hexmask.long.byte 0x1C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
||
else
|
||
hgroup.long 0x460++0x1F
|
||
hide.long 0x0 "IPR24,Interrupt Priority Register"
|
||
hide.long 0x4 "IPR25,Interrupt Priority Register"
|
||
hide.long 0x8 "IPR26,Interrupt Priority Register"
|
||
hide.long 0xC "IPR27,Interrupt Priority Register"
|
||
hide.long 0x10 "IPR28,Interrupt Priority Register"
|
||
hide.long 0x14 "IPR29,Interrupt Priority Register"
|
||
hide.long 0x18 "IPR30,Interrupt Priority Register"
|
||
hide.long 0x1C "IPR31,Interrupt Priority Register"
|
||
endif
|
||
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
||
group.long 0x480++0x1F
|
||
line.long 0x0 "IPR32,Interrupt Priority Register"
|
||
hexmask.long.byte 0x0 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
||
hexmask.long.byte 0x0 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
||
hexmask.long.byte 0x0 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
||
hexmask.long.byte 0x0 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
||
line.long 0x4 "IPR33,Interrupt Priority Register"
|
||
hexmask.long.byte 0x4 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
||
hexmask.long.byte 0x4 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
||
hexmask.long.byte 0x4 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
||
hexmask.long.byte 0x4 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
||
line.long 0x8 "IPR34,Interrupt Priority Register"
|
||
hexmask.long.byte 0x8 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
||
hexmask.long.byte 0x8 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
||
hexmask.long.byte 0x8 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
||
hexmask.long.byte 0x8 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
||
line.long 0xC "IPR35,Interrupt Priority Register"
|
||
hexmask.long.byte 0xC 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
||
hexmask.long.byte 0xC 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
||
hexmask.long.byte 0xC 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
||
hexmask.long.byte 0xC 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
||
line.long 0x10 "IPR36,Interrupt Priority Register"
|
||
hexmask.long.byte 0x10 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
||
hexmask.long.byte 0x10 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
||
hexmask.long.byte 0x10 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
||
hexmask.long.byte 0x10 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
||
line.long 0x14 "IPR37,Interrupt Priority Register"
|
||
hexmask.long.byte 0x14 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
||
hexmask.long.byte 0x14 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
||
hexmask.long.byte 0x14 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
||
hexmask.long.byte 0x14 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
||
line.long 0x18 "IPR38,Interrupt Priority Register"
|
||
hexmask.long.byte 0x18 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
||
hexmask.long.byte 0x18 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
||
hexmask.long.byte 0x18 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
||
hexmask.long.byte 0x18 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
||
line.long 0x1C "IPR39,Interrupt Priority Register"
|
||
hexmask.long.byte 0x1C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
||
hexmask.long.byte 0x1C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
||
hexmask.long.byte 0x1C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
||
hexmask.long.byte 0x1C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
||
else
|
||
hgroup.long 0x480++0x1F
|
||
hide.long 0x0 "IPR32,Interrupt Priority Register"
|
||
hide.long 0x4 "IPR33,Interrupt Priority Register"
|
||
hide.long 0x8 "IPR34,Interrupt Priority Register"
|
||
hide.long 0xC "IPR35,Interrupt Priority Register"
|
||
hide.long 0x10 "IPR36,Interrupt Priority Register"
|
||
hide.long 0x14 "IPR37,Interrupt Priority Register"
|
||
hide.long 0x18 "IPR38,Interrupt Priority Register"
|
||
hide.long 0x1C "IPR39,Interrupt Priority Register"
|
||
endif
|
||
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
||
group.long 0x4A0++0x1F
|
||
line.long 0x0 "IPR40,Interrupt Priority Register"
|
||
hexmask.long.byte 0x0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
||
hexmask.long.byte 0x0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
||
hexmask.long.byte 0x0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
||
hexmask.long.byte 0x0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
||
line.long 0x4 "IPR41,Interrupt Priority Register"
|
||
hexmask.long.byte 0x4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
||
hexmask.long.byte 0x4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
||
hexmask.long.byte 0x4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
||
hexmask.long.byte 0x4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
||
line.long 0x8 "IPR42,Interrupt Priority Register"
|
||
hexmask.long.byte 0x8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
||
hexmask.long.byte 0x8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
||
hexmask.long.byte 0x8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
||
hexmask.long.byte 0x8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
||
line.long 0xC "IPR43,Interrupt Priority Register"
|
||
hexmask.long.byte 0xC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
||
hexmask.long.byte 0xC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
||
hexmask.long.byte 0xC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
||
hexmask.long.byte 0xC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
||
line.long 0x10 "IPR44,Interrupt Priority Register"
|
||
hexmask.long.byte 0x10 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
||
hexmask.long.byte 0x10 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
||
hexmask.long.byte 0x10 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
||
hexmask.long.byte 0x10 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
||
line.long 0x14 "IPR45,Interrupt Priority Register"
|
||
hexmask.long.byte 0x14 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
||
hexmask.long.byte 0x14 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
||
hexmask.long.byte 0x14 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
||
hexmask.long.byte 0x14 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
||
line.long 0x18 "IPR46,Interrupt Priority Register"
|
||
hexmask.long.byte 0x18 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
||
hexmask.long.byte 0x18 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
||
hexmask.long.byte 0x18 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
||
hexmask.long.byte 0x18 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
||
line.long 0x1C "IPR47,Interrupt Priority Register"
|
||
hexmask.long.byte 0x1C 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
||
hexmask.long.byte 0x1C 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
||
hexmask.long.byte 0x1C 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
||
hexmask.long.byte 0x1C 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
||
else
|
||
hgroup.long 0x4A0++0x1F
|
||
hide.long 0x0 "IPR40,Interrupt Priority Register"
|
||
hide.long 0x4 "IPR41,Interrupt Priority Register"
|
||
hide.long 0x8 "IPR42,Interrupt Priority Register"
|
||
hide.long 0xC "IPR43,Interrupt Priority Register"
|
||
hide.long 0x10 "IPR44,Interrupt Priority Register"
|
||
hide.long 0x14 "IPR45,Interrupt Priority Register"
|
||
hide.long 0x18 "IPR46,Interrupt Priority Register"
|
||
hide.long 0x1C "IPR47,Interrupt Priority Register"
|
||
endif
|
||
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
||
group.long 0x4C0++0x1F
|
||
line.long 0x0 "IPR48,Interrupt Priority Register"
|
||
hexmask.long.byte 0x0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
||
hexmask.long.byte 0x0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
||
hexmask.long.byte 0x0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
||
hexmask.long.byte 0x0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
||
line.long 0x4 "IPR49,Interrupt Priority Register"
|
||
hexmask.long.byte 0x4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
||
hexmask.long.byte 0x4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
||
hexmask.long.byte 0x4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
||
hexmask.long.byte 0x4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
||
line.long 0x8 "IPR50,Interrupt Priority Register"
|
||
hexmask.long.byte 0x8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
||
hexmask.long.byte 0x8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
||
hexmask.long.byte 0x8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
||
hexmask.long.byte 0x8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
||
line.long 0xC "IPR51,Interrupt Priority Register"
|
||
hexmask.long.byte 0xC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
||
hexmask.long.byte 0xC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
||
hexmask.long.byte 0xC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
||
hexmask.long.byte 0xC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
||
line.long 0x10 "IPR52,Interrupt Priority Register"
|
||
hexmask.long.byte 0x10 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
||
hexmask.long.byte 0x10 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
||
hexmask.long.byte 0x10 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
||
hexmask.long.byte 0x10 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
||
line.long 0x14 "IPR53,Interrupt Priority Register"
|
||
hexmask.long.byte 0x14 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
||
hexmask.long.byte 0x14 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
||
hexmask.long.byte 0x14 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
||
hexmask.long.byte 0x14 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
||
line.long 0x18 "IPR54,Interrupt Priority Register"
|
||
hexmask.long.byte 0x18 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
||
hexmask.long.byte 0x18 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
||
hexmask.long.byte 0x18 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
||
hexmask.long.byte 0x18 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
||
line.long 0x1C "IPR55,Interrupt Priority Register"
|
||
hexmask.long.byte 0x1C 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
||
hexmask.long.byte 0x1C 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
||
hexmask.long.byte 0x1C 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
||
hexmask.long.byte 0x1C 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
||
else
|
||
hgroup.long 0x4C0++0x1F
|
||
hide.long 0x0 "IPR48,Interrupt Priority Register"
|
||
hide.long 0x4 "IPR49,Interrupt Priority Register"
|
||
hide.long 0x8 "IPR50,Interrupt Priority Register"
|
||
hide.long 0xC "IPR51,Interrupt Priority Register"
|
||
hide.long 0x10 "IPR52,Interrupt Priority Register"
|
||
hide.long 0x14 "IPR53,Interrupt Priority Register"
|
||
hide.long 0x18 "IPR54,Interrupt Priority Register"
|
||
hide.long 0x1C "IPR55,Interrupt Priority Register"
|
||
endif
|
||
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
||
group.long 0x4E0++0x0F
|
||
line.long 0x0 "IPR56,Interrupt Priority Register"
|
||
hexmask.long.byte 0x0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
||
hexmask.long.byte 0x0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
||
hexmask.long.byte 0x0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
||
hexmask.long.byte 0x0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
||
line.long 0x4 "IPR57,Interrupt Priority Register"
|
||
hexmask.long.byte 0x4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
||
hexmask.long.byte 0x4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
||
hexmask.long.byte 0x4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
||
hexmask.long.byte 0x4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
||
line.long 0x8 "IPR58,Interrupt Priority Register"
|
||
hexmask.long.byte 0x8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
||
hexmask.long.byte 0x8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
||
hexmask.long.byte 0x8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
||
hexmask.long.byte 0x8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
||
line.long 0xC "IPR59,Interrupt Priority Register"
|
||
hexmask.long.byte 0xC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
||
hexmask.long.byte 0xC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
||
hexmask.long.byte 0xC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
||
hexmask.long.byte 0xC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
||
else
|
||
hgroup.long 0x4E0++0x0F
|
||
hide.long 0x0 "IPR56,Interrupt Priority Register"
|
||
hide.long 0x4 "IPR57,Interrupt Priority Register"
|
||
hide.long 0x8 "IPR58,Interrupt Priority Register"
|
||
hide.long 0xC "IPR59,Interrupt Priority Register"
|
||
endif
|
||
tree.end
|
||
width 0x0B
|
||
else
|
||
newline
|
||
textline "COREDEBUG component base address not specified"
|
||
newline
|
||
endif
|
||
tree.end
|
||
tree "Debug"
|
||
tree "Core Debug"
|
||
sif COMPonent.AVAILABLE("COREDEBUG")
|
||
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
||
width 7.
|
||
group.long 0xD30++0x03
|
||
line.long 0x00 "DFSR,Debug Fault Status Register"
|
||
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
||
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
||
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
||
textline " "
|
||
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
||
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
||
hgroup.long 0xDF0++0x03
|
||
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
||
in
|
||
wgroup.long 0xDF4++0x03
|
||
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
||
bitfld.long 0x00 16. " REGWNR ,Specifies the access type for the transfer" "Read,Write"
|
||
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register, special-purpose register or Floating-point extension register"
|
||
group.long 0xDF8++0x03
|
||
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
||
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
||
group.long 0xFC++0x03
|
||
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
||
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
||
rbitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
|
||
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
||
textline " "
|
||
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
||
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
||
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
||
textline " "
|
||
bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled"
|
||
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
||
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
|
||
textline " "
|
||
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
||
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
|
||
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
|
||
textline " "
|
||
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
||
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
||
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
||
else
|
||
group.long 0xDFC++0x03
|
||
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
||
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
||
rbitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
|
||
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
||
textline " "
|
||
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
||
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
||
bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled"
|
||
textline " "
|
||
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
||
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
|
||
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
||
textline " "
|
||
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
|
||
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
|
||
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
||
textline " "
|
||
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
||
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
||
endif
|
||
newline
|
||
width 13.
|
||
group.long 0xE04++0x07
|
||
line.long 0x00 "DAUTHCTRL,Debug Authentication Control Register"
|
||
bitfld.long 0x00 3. " INTSPNIDEN ,Internal secure non-invasive debug enable" "Disabled,Enabled"
|
||
bitfld.long 0x00 2. " SPNIDENSEL ,Secure non-invasive debug enable select.Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure non-invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPNIDEN"
|
||
bitfld.long 0x00 1. " INTSPIDEN ,Internal secure invasive debug enable" "Disabled,Enabled"
|
||
textline " "
|
||
bitfld.long 0x00 0. " SPIDENSEL ,Secure invasive debug enable select. Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPIDEN"
|
||
textline " "
|
||
line.long 0x04 "DSCSR,Debug Security Control and Status Register"
|
||
bitfld.long 0x04 17. " CDSKEY ,CDS write-enable key" "Not ignored,Ignored"
|
||
textline " "
|
||
bitfld.long 0x04 16. " CDS ,This field indicates the current security state of the processor" "Non-secure,Secure"
|
||
bitfld.long 0x04 1. " SBRSEL ,Secure banked register select" "Non-secure,Secure"
|
||
bitfld.long 0x04 0. " SBRSELEN ,Secure banked register select enable" "Disabled,Enabled"
|
||
rgroup.long 0xFB8++0x03
|
||
line.long 0x00 "DAUTHSTATUS,Debug Authentication Status Register"
|
||
bitfld.long 0x00 7. " SNI ,Secure non-invasive debug implemented" ",Implemented"
|
||
bitfld.long 0x00 6. " SNE ,Secure non-invasive debug enabled" "0,1"
|
||
bitfld.long 0x00 5. " SI ,Secure invasive debug features implemented" ",Implemented"
|
||
textline " "
|
||
bitfld.long 0x00 4. " SE ,Secure invasive debug enabled" "0,1"
|
||
bitfld.long 0x00 3. " NSNI ,Non-secure non-invasive debug features implemented" ",Implemented"
|
||
bitfld.long 0x00 2. " NSNE ,Non-secure non-invasive debug enabled" "0,1"
|
||
textline " "
|
||
bitfld.long 0x00 1. " NSI ,Non-secure invasive debug features implemented" ",Implemented"
|
||
bitfld.long 0x00 0. " NSE ,Non-secure invasive debug enabled" "0,1"
|
||
width 0x0B
|
||
else
|
||
newline
|
||
textline "COREDEBUG component base address not specified"
|
||
newline
|
||
endif
|
||
tree.end
|
||
tree "Flash Patch and Breakpoint Unit (FPB)"
|
||
sif COMPonent.AVAILABLE("FPB")
|
||
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
||
width 12.
|
||
group.long 0x00++0x03
|
||
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
||
rbitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Reserved,Version 2,?..."
|
||
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
||
rbitfld.long 0x00 8.--11. " NUM_LIT ,Number of literal comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
||
newline
|
||
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
||
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
||
newline
|
||
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
||
group.long 0x8++0x03
|
||
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
||
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
||
newline
|
||
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
||
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
||
else
|
||
group.long 0x8++0x03
|
||
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
||
newline
|
||
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
||
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
||
endif
|
||
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
||
group.long 0xC++0x03
|
||
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
||
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
||
newline
|
||
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
||
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
||
else
|
||
group.long 0xC++0x03
|
||
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
||
newline
|
||
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
||
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
||
endif
|
||
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
||
group.long 0x10++0x03
|
||
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
||
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
||
newline
|
||
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
||
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
||
else
|
||
group.long 0x10++0x03
|
||
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
||
newline
|
||
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
||
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
||
endif
|
||
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
||
group.long 0x14++0x03
|
||
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
||
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
||
newline
|
||
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
||
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
||
else
|
||
group.long 0x14++0x03
|
||
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
||
newline
|
||
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
||
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
||
endif
|
||
tree "CoreSight Identification Registers"
|
||
width 12.
|
||
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xFBC))&0x100000)==0x100000)
|
||
rgroup.long 0xFBC++0x03
|
||
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
|
||
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
|
||
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
||
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
||
newline
|
||
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
||
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
|
||
else
|
||
rgroup.long 0xFBC++0x03
|
||
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
|
||
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
||
endif
|
||
rgroup.long 0xFE0++0x0F
|
||
line.long 0x00 "FP_PIDR0,Peripheral ID0"
|
||
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
||
line.long 0x04 "FP_PIDR1,Peripheral ID1"
|
||
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
||
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
||
line.long 0x08 "FP_PIDR2,Peripheral ID2"
|
||
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
||
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
||
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
||
line.long 0x0C "FP_PIDR3,Peripheral ID3"
|
||
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
||
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
||
rgroup.long 0xFD0++0x03
|
||
line.long 0x00 "FP_PIDR4,Peripheral Identification Register 4"
|
||
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
||
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
||
rgroup.long 0xFF0++0x0F
|
||
line.long 0x00 "FP_CIDR0,Component ID0 (Preamble)"
|
||
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
|
||
line.long 0x04 "FP_CIDR1,Component ID1"
|
||
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
||
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
|
||
line.long 0x08 "FP_CIDR2,Component ID2"
|
||
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
|
||
line.long 0x0C "FP_CIDR3,Component ID3"
|
||
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
|
||
tree.end
|
||
width 0x0B
|
||
else
|
||
newline
|
||
textline "FPB component base address not specified"
|
||
newline
|
||
endif
|
||
tree.end
|
||
tree "Data Watchpoint and Trace Unit (DWT)"
|
||
sif COMPonent.AVAILABLE("DWT")
|
||
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
||
width 16.
|
||
group.long 0x00++0x1B
|
||
line.long 0x00 "DWT_CTRL,Control Register"
|
||
bitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
||
bitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
||
bitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
||
textline " "
|
||
bitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
||
bitfld.long 0x00 23. " CYCDISS ,Controls whether the cycle counter is prevented from incrementing while the PE is in Secure state" "No,Yes"
|
||
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
||
textline " "
|
||
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
||
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
||
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
||
textline " "
|
||
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
||
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
||
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
||
textline " "
|
||
bitfld.long 0x00 12. " PCSAMPLENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
||
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
||
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
||
textline " "
|
||
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
||
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
||
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
||
line.long 0x04 "DWT_CYCCNT,Cycle Count register"
|
||
line.long 0x08 "DWT_CPICNT,CPI Count register"
|
||
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,Base instruction overhead counter"
|
||
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
||
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
||
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
||
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
||
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
||
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store overhead counter"
|
||
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count register"
|
||
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
||
rgroup.long 0x1C++0x03
|
||
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
||
textline " "
|
||
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)==0x1)
|
||
group.long 0x20++0x03
|
||
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
||
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x4)
|
||
group.long 0x20++0x03
|
||
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
||
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xC)
|
||
group.long 0x20++0x03
|
||
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
||
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xF)
|
||
group.long 0x20++0x03
|
||
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
||
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
||
else
|
||
group.long 0x20++0x03
|
||
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
||
endif
|
||
group.long (0x20+0x08)++0x03
|
||
line.long 0x00 "DWT_FUNCTION0,DWT Function Register 0"
|
||
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
||
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
||
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
||
textline " "
|
||
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
||
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
||
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)==0x1)
|
||
group.long 0x30++0x03
|
||
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
||
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x4)
|
||
group.long 0x30++0x03
|
||
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
||
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xC)
|
||
group.long 0x30++0x03
|
||
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
||
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xF)
|
||
group.long 0x30++0x03
|
||
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
||
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
||
else
|
||
group.long 0x30++0x03
|
||
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
||
endif
|
||
group.long (0x30+0x08)++0x03
|
||
line.long 0x00 "DWT_FUNCTION1,DWT Function Register 1"
|
||
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
||
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
||
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
||
textline " "
|
||
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
||
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
||
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)==0x1)
|
||
group.long 0x40++0x03
|
||
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
||
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x4)
|
||
group.long 0x40++0x03
|
||
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
||
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xC)
|
||
group.long 0x40++0x03
|
||
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
||
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xF)
|
||
group.long 0x40++0x03
|
||
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
||
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
||
else
|
||
group.long 0x40++0x03
|
||
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
||
endif
|
||
group.long (0x40+0x08)++0x03
|
||
line.long 0x00 "DWT_FUNCTION2,DWT Function Register 2"
|
||
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
||
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
||
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
||
textline " "
|
||
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
||
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
||
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)==0x1)
|
||
group.long 0x50++0x03
|
||
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
||
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x4)
|
||
group.long 0x50++0x03
|
||
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
||
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xC)
|
||
group.long 0x50++0x03
|
||
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
||
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xF)
|
||
group.long 0x50++0x03
|
||
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
||
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
||
else
|
||
group.long 0x50++0x03
|
||
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
||
endif
|
||
group.long (0x50+0x08)++0x03
|
||
line.long 0x00 "DWT_FUNCTION3,DWT Function Register 3"
|
||
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
||
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
||
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
||
textline " "
|
||
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
||
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
||
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)==0x1)
|
||
group.long 0x60++0x03
|
||
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
||
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)<0x4)
|
||
group.long 0x60++0x03
|
||
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
||
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)<0xC)
|
||
group.long 0x60++0x03
|
||
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
||
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)<0xF)
|
||
group.long 0x60++0x03
|
||
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
||
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
||
else
|
||
group.long 0x60++0x03
|
||
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
||
endif
|
||
group.long (0x60+0x08)++0x03
|
||
line.long 0x00 "DWT_FUNCTION4,DWT Function Register 4"
|
||
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
||
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
||
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
||
textline " "
|
||
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
||
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
||
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)==0x1)
|
||
group.long 0x70++0x03
|
||
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
||
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)<0x4)
|
||
group.long 0x70++0x03
|
||
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
||
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)<0xC)
|
||
group.long 0x70++0x03
|
||
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
||
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)<0xF)
|
||
group.long 0x70++0x03
|
||
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
||
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
||
else
|
||
group.long 0x70++0x03
|
||
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
||
endif
|
||
group.long (0x70+0x08)++0x03
|
||
line.long 0x00 "DWT_FUNCTION5,DWT Function Register 5"
|
||
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
||
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
||
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
||
textline " "
|
||
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
||
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
||
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)==0x1)
|
||
group.long 0x80++0x03
|
||
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
||
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)<0x4)
|
||
group.long 0x80++0x03
|
||
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
||
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)<0xC)
|
||
group.long 0x80++0x03
|
||
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
||
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)<0xF)
|
||
group.long 0x80++0x03
|
||
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
||
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
||
else
|
||
group.long 0x80++0x03
|
||
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
||
endif
|
||
group.long (0x80+0x08)++0x03
|
||
line.long 0x00 "DWT_FUNCTION6,DWT Function Register 6"
|
||
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
||
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
||
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
||
textline " "
|
||
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
||
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
||
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)==0x1)
|
||
group.long 0x90++0x03
|
||
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
||
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)<0x4)
|
||
group.long 0x90++0x03
|
||
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
||
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)<0xC)
|
||
group.long 0x90++0x03
|
||
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
||
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)<0xF)
|
||
group.long 0x90++0x03
|
||
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
||
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
||
else
|
||
group.long 0x90++0x03
|
||
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
||
endif
|
||
group.long (0x90+0x08)++0x03
|
||
line.long 0x00 "DWT_FUNCTION7,DWT Function Register 7"
|
||
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
||
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
||
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
||
textline " "
|
||
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
||
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
||
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)==0x1)
|
||
group.long 0xA0++0x03
|
||
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
||
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)<0x4)
|
||
group.long 0xA0++0x03
|
||
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
||
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)<0xC)
|
||
group.long 0xA0++0x03
|
||
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
||
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)<0xF)
|
||
group.long 0xA0++0x03
|
||
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
||
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
||
else
|
||
group.long 0xA0++0x03
|
||
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
||
endif
|
||
group.long (0xA0+0x08)++0x03
|
||
line.long 0x00 "DWT_FUNCTION8,DWT Function Register 8"
|
||
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
||
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
||
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
||
textline " "
|
||
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
||
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
||
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)==0x1)
|
||
group.long 0xB0++0x03
|
||
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
||
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)<0x4)
|
||
group.long 0xB0++0x03
|
||
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
||
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)<0xC)
|
||
group.long 0xB0++0x03
|
||
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
||
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)<0xF)
|
||
group.long 0xB0++0x03
|
||
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
||
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
||
else
|
||
group.long 0xB0++0x03
|
||
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
||
endif
|
||
group.long (0xB0+0x08)++0x03
|
||
line.long 0x00 "DWT_FUNCTION9,DWT Function Register 9"
|
||
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
||
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
||
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
||
textline " "
|
||
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
||
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
||
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)==0x1)
|
||
group.long 0xC0++0x03
|
||
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
||
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)<0x4)
|
||
group.long 0xC0++0x03
|
||
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
||
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)<0xC)
|
||
group.long 0xC0++0x03
|
||
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
||
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)<0xF)
|
||
group.long 0xC0++0x03
|
||
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
||
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
||
else
|
||
group.long 0xC0++0x03
|
||
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
||
endif
|
||
group.long (0xC0+0x08)++0x03
|
||
line.long 0x00 "DWT_FUNCTION10,DWT Function Register 10"
|
||
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
||
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
||
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
||
textline " "
|
||
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
||
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
||
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)==0x1)
|
||
group.long 0xD0++0x03
|
||
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
||
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)<0x4)
|
||
group.long 0xD0++0x03
|
||
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
||
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)<0xC)
|
||
group.long 0xD0++0x03
|
||
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
||
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)<0xF)
|
||
group.long 0xD0++0x03
|
||
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
||
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
||
else
|
||
group.long 0xD0++0x03
|
||
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
||
endif
|
||
group.long (0xD0+0x08)++0x03
|
||
line.long 0x00 "DWT_FUNCTION11,DWT Function Register 11"
|
||
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
||
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
||
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
||
textline " "
|
||
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
||
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
||
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)==0x1)
|
||
group.long 0xE0++0x03
|
||
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
||
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)<0x4)
|
||
group.long 0xE0++0x03
|
||
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
||
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)<0xC)
|
||
group.long 0xE0++0x03
|
||
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
||
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)<0xF)
|
||
group.long 0xE0++0x03
|
||
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
||
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
||
else
|
||
group.long 0xE0++0x03
|
||
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
||
endif
|
||
group.long (0xE0+0x08)++0x03
|
||
line.long 0x00 "DWT_FUNCTION12,DWT Function Register 12"
|
||
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
||
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
||
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
||
textline " "
|
||
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
||
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
||
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)==0x1)
|
||
group.long 0xF0++0x03
|
||
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
||
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)<0x4)
|
||
group.long 0xF0++0x03
|
||
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
||
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)<0xC)
|
||
group.long 0xF0++0x03
|
||
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
||
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)<0xF)
|
||
group.long 0xF0++0x03
|
||
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
||
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
||
else
|
||
group.long 0xF0++0x03
|
||
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
||
endif
|
||
group.long (0xF0+0x08)++0x03
|
||
line.long 0x00 "DWT_FUNCTION13,DWT Function Register 13"
|
||
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
||
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
||
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
||
textline " "
|
||
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
||
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
||
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)==0x1)
|
||
group.long 0x100++0x03
|
||
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
||
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)<0x4)
|
||
group.long 0x100++0x03
|
||
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
||
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)<0xC)
|
||
group.long 0x100++0x03
|
||
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
||
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)<0xF)
|
||
group.long 0x100++0x03
|
||
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
||
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
||
else
|
||
group.long 0x100++0x03
|
||
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
||
endif
|
||
group.long (0x100+0x08)++0x03
|
||
line.long 0x00 "DWT_FUNCTION14,DWT Function Register 14"
|
||
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
||
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
||
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
||
textline " "
|
||
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
||
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
||
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)==0x1)
|
||
group.long 0x110++0x03
|
||
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
||
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)<0x4)
|
||
group.long 0x110++0x03
|
||
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
||
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)<0xC)
|
||
group.long 0x110++0x03
|
||
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
||
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
||
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)<0xF)
|
||
group.long 0x110++0x03
|
||
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
||
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
||
else
|
||
group.long 0x110++0x03
|
||
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
||
endif
|
||
group.long (0x110+0x08)++0x03
|
||
line.long 0x00 "DWT_FUNCTION15,DWT Function Register 15"
|
||
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
||
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
||
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
||
textline " "
|
||
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
||
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
||
tree "CoreSight Identification Registers"
|
||
width 13.
|
||
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xFBC))&0x100000)==0x100000)
|
||
rgroup.long 0xFBC++0x03
|
||
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
|
||
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
|
||
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
||
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
||
textline " "
|
||
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
||
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
|
||
else
|
||
rgroup.long 0xFBC++0x03
|
||
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
|
||
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
||
endif
|
||
rgroup.long 0xFE0++0x0F
|
||
line.long 0x00 "DWT_PIDR0,Peripheral ID0"
|
||
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
||
line.long 0x04 "DWT_PIDR1,Peripheral ID1"
|
||
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
||
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
||
line.long 0x08 "DWT_PIDR2,Peripheral ID2"
|
||
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
||
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
||
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
||
line.long 0x0c "DWT_PIDR3,Peripheral ID3"
|
||
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
||
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
||
rgroup.long 0xFD0++0x03
|
||
line.long 0x00 "DWT_PIDR4,Peripheral Identification Register 4"
|
||
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
||
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
||
rgroup.long 0xFF0++0x0F
|
||
line.long 0x00 "DWT_CIDR0,Component ID0 (Preamble)"
|
||
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
|
||
line.long 0x04 "DWT_CIDR1,Component ID1"
|
||
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
||
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
|
||
line.long 0x08 "DWT_CIDR2,Component ID2"
|
||
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
|
||
line.long 0x0c "DWT_CIDR3,Component ID3"
|
||
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
|
||
tree.end
|
||
width 0x0b
|
||
else
|
||
newline
|
||
textline "DWT component base address not specified"
|
||
newline
|
||
endif
|
||
tree.end
|
||
tree.end
|
||
AUTOINDENT.POP
|
||
tree.end
|
||
tree "ADC12 (12-bit A/D Converter)"
|
||
base ad:0x400A1800
|
||
group.byte 0x0++0x2
|
||
line.byte 0x0 "ADM0,A/D Converter Mode Register 0"
|
||
bitfld.byte 0x0 7. "ADCS,A/D Conversion Operation Control" "0: Stops conversion operation [When read]..,1: Enables conversion operation [When read] While.."
|
||
bitfld.byte 0x0 6. "ADMD,Specification of the A/D Conversion Channel Selection Mode" "0: Select mode,1: Scan mode"
|
||
newline
|
||
bitfld.byte 0x0 3.--5. "FR,Select Conversion Clock (fAD)" "0: Setting prohibited.,1: PCLKB/16,?,?,?,?,?,?"
|
||
bitfld.byte 0x0 1.--2. "LV,Select Operation Voltage Mode" "0: Normal 1 mode,1: Normal 2 mode,?,?"
|
||
newline
|
||
bitfld.byte 0x0 0. "ADCE,A/D Voltage Comparator Operation Control" "0: Stops A/D voltage comparator operation,1: Enables A/D voltage comparator operation"
|
||
line.byte 0x1 "ADS,Analog Input Channel Specification Register"
|
||
bitfld.byte 0x1 7. "ADISS,Select Internal or External of Analog Input (See to )" "0: External input,1: Internal circuit input"
|
||
hexmask.byte 0x1 0.--4. 1. "ADS,Selection of the Analog Input Channel (See to )"
|
||
line.byte 0x2 "ADM1,A/D Converter Mode Register 1"
|
||
bitfld.byte 0x2 6.--7. "ADTMD,Selection of the A/D Conversion Trigger Mode" "0: Software trigger no-wait mode or software..,?,?,?"
|
||
bitfld.byte 0x2 5. "ADSCM,Specification of the A/D Conversion Mode" "0: Sequential conversion mode,1: One-shot conversion mode"
|
||
newline
|
||
bitfld.byte 0x2 3. "ADLSP,PCLKB Input Frequency Setting" "0: 4 MHz < PCLKB ≤ 32 MHz,1: 1 MHz ≤ PCLKB ≤ 4 MHz"
|
||
bitfld.byte 0x2 0.--2. "ADTRS,Selection of the Hardware Trigger Signal" "0: Setting prohibited.,?,?,?,?,?,?,?"
|
||
rgroup.word 0x6++0x1
|
||
line.word 0x0 "ADCR,12-bit or 10-bit A/D Conversion Result Register"
|
||
rgroup.byte 0x7++0x0
|
||
line.byte 0x0 "ADCRH,8-bit A/D Conversion Result Register"
|
||
group.byte 0x110++0x3
|
||
line.byte 0x0 "ADM2,A/D Converter Mode Register 2"
|
||
bitfld.byte 0x0 6.--7. "ADREFP," "0: Supplied from VCC,1: Supplied from VREFH0/AN000,?,?"
|
||
bitfld.byte 0x0 5. "ADREFM," "0: Supplied from VSS,1: Supplied from VREFL0/AN001"
|
||
newline
|
||
bitfld.byte 0x0 3. "ADRCK," "0: The interrupt signal (ADC12_ADI) is output when..,1: The interrupt signal (ADC12_ADI) is output when.."
|
||
bitfld.byte 0x0 2. "AWC," "0: Do not use the Snooze mode function.,1: Use the Snooze mode function."
|
||
newline
|
||
bitfld.byte 0x0 0.--1. "ADTYP," "0: Setting prohibited.,1: 8-bit resolution,?,?"
|
||
line.byte 0x1 "ADUL,Conversion Result Comparison Upper Limit Setting Register"
|
||
line.byte 0x2 "ADLL,Conversion Result Comparison Lower Limit Setting Register"
|
||
line.byte 0x3 "ADTES,A/D Test Register"
|
||
bitfld.byte 0x3 0.--1. "ADTES,Selection of A/D Conversion Target for Testing" "0: Setting prohibited.,?,?,?"
|
||
rgroup.word 0x120++0x1
|
||
line.word 0x0 "ADCR0,12-bit or 10-bit A/D Conversion Result Register 0"
|
||
rgroup.byte 0x121++0x0
|
||
line.byte 0x0 "ADCR0H,8-bit A/D Conversion Result Register 0"
|
||
rgroup.word 0x122++0x1
|
||
line.word 0x0 "ADCR1,12-bit or 10-bit A/D Conversion Result Register 1"
|
||
rgroup.byte 0x123++0x0
|
||
line.byte 0x0 "ADCR1H,8-bit A/D Conversion Result Register 1"
|
||
rgroup.word 0x124++0x1
|
||
line.word 0x0 "ADCR2,12-bit or 10-bit A/D Conversion Result Register 2"
|
||
rgroup.byte 0x125++0x0
|
||
line.byte 0x0 "ADCR2H,8-bit A/D Conversion Result Register 2"
|
||
rgroup.word 0x126++0x1
|
||
line.word 0x0 "ADCR3,12-bit or 10-bit A/D Conversion Result Register 3"
|
||
rgroup.byte 0x127++0x0
|
||
line.byte 0x0 "ADCR3H,8-bit A/D Conversion Result Register 3"
|
||
tree.end
|
||
tree "BUS (BUS Control)"
|
||
base ad:0x40003000
|
||
group.word 0x1008++0x1
|
||
line.word 0x0 "BUSMCNTSYS,Master Bus Control Register SYS"
|
||
bitfld.word 0x0 15. "IERES,Ignore Error Responses" "0: A bus error is reported.,1: A bus error is not reported."
|
||
group.word 0x100C++0x1
|
||
line.word 0x0 "BUSMCNTDMA,Master Bus Control Register DMA"
|
||
bitfld.word 0x0 15. "IERES,Ignore Error Responses" "0: A bus error is reported.,1: A bus error is not reported."
|
||
rgroup.long 0x1820++0x3
|
||
line.long 0x0 "BUS3ERRADD,Bus Error Address Register 3"
|
||
hexmask.long 0x0 0.--31. 1. "BERAD,Bus Error Address"
|
||
rgroup.byte 0x1824++0x0
|
||
line.byte 0x0 "BUS3ERRSTAT,BUS Error Status Register 3"
|
||
bitfld.byte 0x0 7. "ERRSTAT,Bus Error Status flag" "0: No bus error occurred.,1: Bus error occurred."
|
||
bitfld.byte 0x0 0. "ACCSTAT,Error Access Status flag" "0: Read access,1: Write access"
|
||
rgroup.long 0x1830++0x3
|
||
line.long 0x0 "BUS4ERRADD,Bus Error Address Register 4"
|
||
hexmask.long 0x0 0.--31. 1. "BERAD,Bus Error Address"
|
||
rgroup.byte 0x1834++0x0
|
||
line.byte 0x0 "BUS4ERRSTAT,BUS Error Status Register 4"
|
||
bitfld.byte 0x0 7. "ERRSTAT,Bus Error Status flag" "0: No bus error occurred.,1: Bus error occurred."
|
||
bitfld.byte 0x0 0. "ACCSTAT,Error Access Status flag" "0: Read access,1: Write access"
|
||
tree.end
|
||
tree "CRC (Cyclic Redundancy Check)"
|
||
base ad:0x40074000
|
||
group.byte 0x0++0x0
|
||
line.byte 0x0 "CRCCR0,CRC Control Register 0"
|
||
bitfld.byte 0x0 7. "DORCLR,CRCDOR/CRCDOR_HA Register Clear" "0: No effect,1: Clear the CRCDOR/CRCDOR_HA register"
|
||
bitfld.byte 0x0 0.--2. "GPS,CRC Generating Polynomial Switching" "0: No calculation is executed,?,?,?,?,?,?,?"
|
||
group.long 0x4++0x3
|
||
line.long 0x0 "CRCDIR,CRC Data Input Register"
|
||
group.byte 0x4++0x0
|
||
line.byte 0x0 "CRCDIR_BY,CRC Data Input Register"
|
||
group.long 0x8++0x3
|
||
line.long 0x0 "CRCDOR,CRC Data Output Register"
|
||
group.word 0x8++0x1
|
||
line.word 0x0 "CRCDOR_HA,CRC Data Output Register"
|
||
tree.end
|
||
tree "DBG (Debug Function)"
|
||
base ad:0x4001B000
|
||
rgroup.long 0x0++0x3
|
||
line.long 0x0 "DBGSTR,Debug Status Register"
|
||
bitfld.long 0x0 29. "CDBGPWRUPACK,Debug Power-up Acknowledge" "0: Debug power-up request is not acknowledged,1: Debug power-up request is acknowledged"
|
||
bitfld.long 0x0 28. "CDBGPWRUPREQ,Debug Power-up Request" "0: OCD is not requesting debug power up,1: OCD is requesting debug power up"
|
||
group.long 0x10++0x3
|
||
line.long 0x0 "DBGSTOPCR,Debug Stop Control Register"
|
||
bitfld.long 0x0 24. "DBGSTOP_RPER,Mask Bit for SRAM Parity Error Reset/Interrupt" "0: Enable SRAM parity error reset/interrupt,1: Mask SRAM parity error reset/interrupt"
|
||
bitfld.long 0x0 17. "DBGSTOP_LVD1,Mask Bit for LVD1 Reset/Interrupt" "0: Enable LVD1 reset/interrupt,1: Mask LVD1 reset/interrupt"
|
||
newline
|
||
bitfld.long 0x0 16. "DBGSTOP_LVD0,Mask Bit for LVD0 Reset" "0: Enable LVD0 reset,1: Mask LVD0 reset"
|
||
bitfld.long 0x0 15. "DBGSTOP_SIR,Mask Bit for SAU IICA PORT_IRQ0-5 Reset/Interrupt" "0: Enable SAU IICA PORT_IRQ0-5 reset/interrupt,1: Mask SAU IICA PORT_IRQ0-5 reset/interrupt"
|
||
newline
|
||
bitfld.long 0x0 14. "DBGSTOP_TIM,Mask Bit for RTC TAU Reset/Interrupt" "0: Enable RTC TAU reset/interrupt,1: Mask RTC TAU reset/interrupt"
|
||
bitfld.long 0x0 0. "DBGSTOP_IWDT,Mask Bit for IWDT Reset/Interrupt in the OCD Run Mode" "0: Enable IWDT reset/interrupt,1: Mask IWDT reset/interrupt and stop IWDT counter"
|
||
tree.end
|
||
tree "DTC (Data Transfer Controller)"
|
||
base ad:0x40005400
|
||
group.byte 0x0++0x0
|
||
line.byte 0x0 "DTCCR,DTC Control Register"
|
||
bitfld.byte 0x0 4. "RRS,DTC Transfer Information Read Skip Enable" "0: Transfer information read is not skipped,1: Transfer information read is skipped when vector.."
|
||
group.long 0x4++0x3
|
||
line.long 0x0 "DTCVBR,DTC Vector Base Register"
|
||
group.byte 0xC++0x0
|
||
line.byte 0x0 "DTCST,DTC Module Start Register"
|
||
bitfld.byte 0x0 0. "DTCST,DTC Module Start" "0: DTC module stopped.,1: DTC module started."
|
||
rgroup.word 0xE++0x1
|
||
line.word 0x0 "DTCSTS,DTC Status Register"
|
||
bitfld.word 0x0 15. "ACT,DTC Active Flag" "0: DTC transfer operation is not in progress.,1: DTC transfer operation is in progress."
|
||
hexmask.word.byte 0x0 0.--7. 1. "VECN,DTC-Activating Vector Number Monitoring"
|
||
tree.end
|
||
tree "ELC (Event Link Controller)"
|
||
base ad:0x40041000
|
||
group.byte 0x0++0x0
|
||
line.byte 0x0 "ELCR,Event Link Controller Register"
|
||
bitfld.byte 0x0 7. "ELCON,All Event Link Enable" "0: All the event link operations are disabled.,1: All the event link operations are enabled."
|
||
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
||
group.byte ($2+0x2)++0x0
|
||
line.byte 0x0 "ELSEGR$1,Event Link Software Event Generation Register %s"
|
||
bitfld.byte 0x0 7. "WI,ELSEGR Register Write Disable" "0: Write to ELSEGR register enabled.,1: Write to ELSEGR register disabled."
|
||
bitfld.byte 0x0 6. "WE,SEG Bit Write Enable" "0: Write to SEG bit disabled.,1: Write to SEG bit enabled."
|
||
bitfld.byte 0x0 0. "SEG,Software Event Generation" "0: Not generate a software event.,1: Generate a software event."
|
||
repeat.end
|
||
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
||
group.word ($2+0x6C)++0x1
|
||
line.word 0x0 "ELSR$1,Event Link Setting Register %s"
|
||
hexmask.word.byte 0x0 0.--5. 1. "ELS,Event Link Select"
|
||
repeat.end
|
||
tree.end
|
||
tree "FLCN (Flash Memory)"
|
||
base ad:0x407EC000
|
||
group.byte 0x90++0x0
|
||
line.byte 0x0 "DFLCTL,Data Flash Control Register"
|
||
bitfld.byte 0x0 0. "DFLEN,Data Flash Access Enable" "0: Access to the data flash is disabled,1: Access to the data flash is enabled"
|
||
group.byte 0x100++0x0
|
||
line.byte 0x0 "FPMCR,Flash P/E Mode Control Register"
|
||
bitfld.byte 0x0 4. "FMS1,Flash Operating Mode Select 1" "0,1"
|
||
bitfld.byte 0x0 3. "RPDIS,Code Flash P/E Disable" "0: Programming of the code flash is enabled,1: Programming of the code flash is disabled."
|
||
newline
|
||
bitfld.byte 0x0 1. "FMS0,Flash Operating Mode Select 0" "0: FMS1 = 0: Read mode FMS1 = 1: Data flash P/E..,1: FMS1 = 0: Code flash P/E mode FMS1 = 1: Setting.."
|
||
group.byte 0x104++0x0
|
||
line.byte 0x0 "FASR,Flash Area Select Register"
|
||
bitfld.byte 0x0 0. "EXS,Extra Area Select" "0: User area or data area,1: Extra area."
|
||
group.word 0x108++0x1
|
||
line.word 0x0 "FSARL,Flash Processing Start Address Register L"
|
||
hexmask.word 0x0 0.--15. 1. "FSARL,Flash Processing Start Address L"
|
||
group.word 0x110++0x1
|
||
line.word 0x0 "FSARH,Flash Processing Start Address Register H"
|
||
hexmask.word 0x0 0.--15. 1. "FSARH,Flash Processing Start Address H"
|
||
group.byte 0x114++0x0
|
||
line.byte 0x0 "FCR,Flash Control Register"
|
||
bitfld.byte 0x0 7. "OPST,Processing Start" "0: Processing stops,1: Processing starts."
|
||
bitfld.byte 0x0 6. "STOP,Forced Processing Stop" "0,1"
|
||
newline
|
||
hexmask.byte 0x0 0.--3. 1. "CMD,Software Command Setting"
|
||
group.word 0x118++0x1
|
||
line.word 0x0 "FEARL,Flash Processing End Address Register L"
|
||
hexmask.word 0x0 0.--15. 1. "FEARL,Flash Processing End Address L"
|
||
group.word 0x120++0x1
|
||
line.word 0x0 "FEARH,Flash Processing End Address Register H"
|
||
hexmask.word 0x0 0.--15. 1. "FEARH,Flash Processing End Address H"
|
||
group.byte 0x124++0x0
|
||
line.byte 0x0 "FRESETR,Flash Reset Register"
|
||
bitfld.byte 0x0 0. "FRESET,Software Reset of the Registers" "0: The registers related to the flash programming..,1: The registers related to the flash programming.."
|
||
rgroup.byte 0x12C++0x0
|
||
line.byte 0x0 "FSTATR1,Flash Status Register 1"
|
||
bitfld.byte 0x0 7. "EXRDY,Extra Area Ready Flag" "0: The software command of the FEXCR register is..,1: The software command of the FEXCR register is.."
|
||
bitfld.byte 0x0 6. "FRDY,Flash Ready Flag" "0: The software command of the FCR register is not..,1: The software command of the FCR register is.."
|
||
group.word 0x130++0x1
|
||
line.word 0x0 "FWBL0,Flash Write Buffer Register L0"
|
||
hexmask.word 0x0 0.--15. 1. "WDATA,Flash Write Buffer L0"
|
||
group.word 0x138++0x1
|
||
line.word 0x0 "FWBH0,Flash Write Buffer Register H0"
|
||
hexmask.word 0x0 0.--15. 1. "WDATA,Flash Write Buffer H0"
|
||
wgroup.byte 0x180++0x0
|
||
line.byte 0x0 "FPR,Protection Unlock Register"
|
||
hexmask.byte 0x0 0.--7. 1. "FPR,Protection Unlock"
|
||
rgroup.byte 0x184++0x0
|
||
line.byte 0x0 "FPSR,Protection Unlock Status Register"
|
||
bitfld.byte 0x0 0. "PERR,Protect Error Flag" "0: No error,1: An error occurs"
|
||
rgroup.word 0x1C0++0x1
|
||
line.word 0x0 "FSCMR,Flash Start-up Setting Monitor Register"
|
||
bitfld.word 0x0 14. "FSPR,Access Window Protection Flag" "0: Access window setting disabled.,1: Access window setting enabled."
|
||
bitfld.word 0x0 8. "SASMF,Startup Area Setting Monitor Flag" "0: Setting to start up using the alternative area,1: Setting to start up using the default area"
|
||
rgroup.word 0x1C8++0x1
|
||
line.word 0x0 "FAWSMR,Flash Access Window Start Address Monitor Register"
|
||
bitfld.word 0x0 15. "FSPR,Access Window Protection Flag" "0,1"
|
||
hexmask.word 0x0 0.--10. 1. "FAWS,Access Window Start Address"
|
||
rgroup.word 0x1D0++0x1
|
||
line.word 0x0 "FAWEMR,Flash Access Window End Address Monitor Register"
|
||
bitfld.word 0x0 15. "SASMF,Startup Area Setting Monitor Flag" "0,1"
|
||
hexmask.word 0x0 0.--10. 1. "FAWE,Access Window End Address"
|
||
group.byte 0x1D8++0x0
|
||
line.byte 0x0 "FISR,Flash Initial Setting Register"
|
||
bitfld.byte 0x0 6.--7. "SAS,Startup Area Select" "0: The startup area is selected according to the..,?,?,?"
|
||
hexmask.byte 0x0 0.--4. 1. "PCKA,Flash-IF Clock Notification"
|
||
group.byte 0x1DC++0x0
|
||
line.byte 0x0 "FEXCR,Flash Extra Area Control Register"
|
||
bitfld.byte 0x0 7. "OPST,Processing Start" "0: Processing stops,1: Processing starts."
|
||
bitfld.byte 0x0 0.--2. "CMD,Software Command Setting" "0: Setting prohibited.,?,?,?,?,?,?,?"
|
||
rgroup.word 0x1E0++0x1
|
||
line.word 0x0 "FEAML,Flash Error Address Monitor Register L"
|
||
hexmask.word 0x0 0.--15. 1. "FEAML,Flash Error Address Monitor Register L"
|
||
rgroup.word 0x1E8++0x1
|
||
line.word 0x0 "FEAMH,Flash Error Address Monitor Register H"
|
||
hexmask.word 0x0 0.--15. 1. "FEAMH,Flash Error Address Monitor Register H"
|
||
rgroup.word 0x1F0++0x1
|
||
line.word 0x0 "FSTATR2,Flash Status Register 2"
|
||
bitfld.word 0x0 5. "EILGLERR,Extra Area Illegal Command Error Flag" "0: No illegal command or illegal access to the..,1: An illegal command or illegal access to the.."
|
||
bitfld.word 0x0 4. "ILGLERR,Illegal Command Error Flag" "0: No illegal software command or illegal access is..,1: An illegal command or illegal access is detected."
|
||
newline
|
||
bitfld.word 0x0 3. "BCERR,Blank Check Error Flag" "0: Blank checking terminates normally,1: An error occurs during blank checking."
|
||
bitfld.word 0x0 1. "PRGERR,Program Error Flag" "0: Programming terminates normally,1: An error occurs during programming."
|
||
newline
|
||
bitfld.word 0x0 0. "ERERR,Erase Error Flag" "0: Erasure terminates normally,1: An error occurs during erasure"
|
||
group.byte 0x200++0x0
|
||
line.byte 0x0 "HIOTRM,High-speed On-chip Oscillator Trimming Register"
|
||
hexmask.byte 0x0 0.--5. 1. "HIOTRM,HOCO User Trimming"
|
||
group.byte 0x20A++0x1
|
||
line.byte 0x0 "FLMODE,Flash Operating Mode Control Register"
|
||
bitfld.byte 0x0 6.--7. "MODE,Operating Mode Select" "0: Setting prohibited,1: Low-speed mode,?,?"
|
||
line.byte 0x1 "FLMWRP,Flash Operating Mode Protect Register"
|
||
bitfld.byte 0x1 0. "FLMWEN,Control of Flash Operation Mode Select Register" "0: Rewriting the FLMODE register is disabled,1: Rewriting the FLMODE register is enabled"
|
||
group.word 0x21A++0x1
|
||
line.word 0x0 "FENTRYR,Flash P/E Mode Entry Register"
|
||
hexmask.word.byte 0x0 8.--15. 1. "FEKEY,Key Code"
|
||
bitfld.word 0x0 7. "FENTRYD,Data Flash P/E Mode Entry" "0: The data flash is the read mode,1: The data flash is the P/E mode."
|
||
newline
|
||
bitfld.word 0x0 0. "FENTRY0,Code Flash P/E Mode Entry 0" "0: The code flash is the read mode,1: The code flash is the P/E mode."
|
||
tree.end
|
||
tree "ICU (Interrupt Controller)"
|
||
base ad:0x40006000
|
||
repeat 6. (increment 0x0 0x1)(increment 0x0 0x1)
|
||
group.byte ($2)++0x0
|
||
line.byte 0x0 "IRQCR$1,IRQ Control Register %s"
|
||
bitfld.byte 0x0 0.--1. "IRQMD,IRQi Detection Sense Select" "0: Falling edge,1: Rising edge,?,?"
|
||
repeat.end
|
||
group.byte 0x100++0x0
|
||
line.byte 0x0 "NMICR,NMI Pin Interrupt Control Register"
|
||
bitfld.byte 0x0 0. "NMIMD,NMI Detection Set" "0: Falling edge,1: Rising edge"
|
||
group.word 0x120++0x1
|
||
line.word 0x0 "NMIER,Non-maskable Interrupt Enable Register"
|
||
bitfld.word 0x0 8. "RPEEN,SRAM Parity Error Interrupt Enable" "0: Disabled,1: Enabled"
|
||
bitfld.word 0x0 7. "NMIEN,NMI Pin Interrupt Enable" "0: Disabled,1: Enabled"
|
||
newline
|
||
bitfld.word 0x0 2. "LVD1EN,Voltage Monitor 1 Interrupt Enable" "0: Disabled,1: Enabled"
|
||
bitfld.word 0x0 0. "IWDTEN,IWDT Underflow/Refresh Error Interrupt Enable" "0: Disabled,1: Enabled."
|
||
group.word 0x130++0x1
|
||
line.word 0x0 "NMICLR,Non-maskable Interrupt Status Clear Register"
|
||
bitfld.word 0x0 8. "RPECLR,SRAM Parity Error Interrupt Status Flag Clear" "0: No effect,1: Clear the NMISR.RPEST flag"
|
||
bitfld.word 0x0 7. "NMICLR,NMI Pin Interrupt Status Flag Clear" "0: No effect,1: Clear the NMISR.NMIST flag"
|
||
newline
|
||
bitfld.word 0x0 2. "LVD1CLR,Voltage Monitor 1 Interrupt Status Flag Clear" "0: No effect,1: Clear the NMISR.LVD1ST flag"
|
||
bitfld.word 0x0 0. "IWDTCLR,IWDT Underflow/Refresh Error Interrupt Status Flag Clear" "0: No effect,1: Clear the NMISR.IWDTST flag"
|
||
rgroup.word 0x140++0x1
|
||
line.word 0x0 "NMISR,Non-maskable Interrupt Status Register"
|
||
bitfld.word 0x0 8. "RPEST,SRAM Parity Error Interrupt Status Flag" "0: Interrupt not requested,1: Interrupt requested"
|
||
bitfld.word 0x0 7. "NMIST,NMI Pin Interrupt Status Flag" "0: Interrupt not requested,1: Interrupt requested"
|
||
newline
|
||
bitfld.word 0x0 2. "LVD1ST,Voltage Monitor 1 Interrupt Status Flag" "0: Interrupt not requested,1: Interrupt requested"
|
||
bitfld.word 0x0 0. "IWDTST,IWDT Underflow/Refresh Error Interrupt Status Flag" "0: Interrupt not requested,1: Interrupt requested"
|
||
rgroup.long 0x300++0x7
|
||
line.long 0x0 "DTCENST0,DTC Enable Status Register 0"
|
||
bitfld.long 0x0 31. "ST31,DTC Enable Status by Event Number i" "0: DTC Disable by Event number i,1: DTC Enable by Event number i"
|
||
bitfld.long 0x0 30. "ST30,DTC Enable Status by Event Number i" "0: DTC Disable by Event number i,1: DTC Enable by Event number i"
|
||
newline
|
||
bitfld.long 0x0 29. "ST29,DTC Enable Status by Event Number i" "0: DTC Disable by Event number i,1: DTC Enable by Event number i"
|
||
bitfld.long 0x0 28. "ST28,DTC Enable Status by Event Number i" "0: DTC Disable by Event number i,1: DTC Enable by Event number i"
|
||
newline
|
||
bitfld.long 0x0 27. "ST27,DTC Enable Status by Event Number i" "0: DTC Disable by Event number i,1: DTC Enable by Event number i"
|
||
bitfld.long 0x0 23. "ST23,DTC Enable Status by Event Number i" "0: DTC Disable by Event number i,1: DTC Enable by Event number i"
|
||
newline
|
||
bitfld.long 0x0 22. "ST22,DTC Enable Status by Event Number i" "0: DTC Disable by Event number i,1: DTC Enable by Event number i"
|
||
bitfld.long 0x0 19. "ST19,DTC Enable Status by Event Number i" "0: DTC Disable by Event number i,1: DTC Enable by Event number i"
|
||
newline
|
||
bitfld.long 0x0 18. "ST18,DTC Enable Status by Event Number i" "0: DTC Disable by Event number i,1: DTC Enable by Event number i"
|
||
bitfld.long 0x0 16. "ST16,DTC Enable Status by Event Number i" "0: DTC Disable by Event number i,1: DTC Enable by Event number i"
|
||
newline
|
||
bitfld.long 0x0 15. "ST15,DTC Enable Status by Event Number i" "0: DTC Disable by Event number i,1: DTC Enable by Event number i"
|
||
bitfld.long 0x0 13. "ST13,DTC Enable Status by Event Number i" "0: DTC Disable by Event number i,1: DTC Enable by Event number i"
|
||
newline
|
||
bitfld.long 0x0 12. "ST12,DTC Enable Status by Event Number i" "0: DTC Disable by Event number i,1: DTC Enable by Event number i"
|
||
bitfld.long 0x0 7. "ST7,DTC Enable Status by Event Number i" "0: DTC Disable by Event number i,1: DTC Enable by Event number i"
|
||
newline
|
||
bitfld.long 0x0 6. "ST6,DTC Enable Status by Event Number i" "0: DTC Disable by Event number i,1: DTC Enable by Event number i"
|
||
bitfld.long 0x0 5. "ST5,DTC Enable Status by Event Number i" "0: DTC Disable by Event number i,1: DTC Enable by Event number i"
|
||
newline
|
||
bitfld.long 0x0 4. "ST4,DTC Enable Status by Event Number i" "0: DTC Disable by Event number i,1: DTC Enable by Event number i"
|
||
bitfld.long 0x0 3. "ST3,DTC Enable Status by Event Number i" "0: DTC Disable by Event number i,1: DTC Enable by Event number i"
|
||
newline
|
||
bitfld.long 0x0 2. "ST2,DTC Enable Status by Event Number i" "0: DTC Disable by Event number i,1: DTC Enable by Event number i"
|
||
bitfld.long 0x0 1. "ST1,DTC Enable Status by Event Number i" "0: DTC Disable by Event number i,1: DTC Enable by Event number i"
|
||
line.long 0x4 "DTCENST1,DTC Enable Status Register 1"
|
||
bitfld.long 0x4 9. "ST41,DTC Enable Status by Event Number i" "0: DTC Disable by Event number i,1: DTC Enable by Event number i"
|
||
bitfld.long 0x4 8. "ST40,DTC Enable Status by Event Number i" "0: DTC Disable by Event number i,1: DTC Enable by Event number i"
|
||
newline
|
||
bitfld.long 0x4 6. "ST38,DTC Enable Status by Event Number i" "0: DTC Disable by Event number i,1: DTC Enable by Event number i"
|
||
bitfld.long 0x4 5. "ST37,DTC Enable Status by Event Number i" "0: DTC Disable by Event number i,1: DTC Enable by Event number i"
|
||
newline
|
||
bitfld.long 0x4 4. "ST36,DTC Enable Status by Event Number i" "0: DTC Disable by Event number i,1: DTC Enable by Event number i"
|
||
bitfld.long 0x4 3. "ST35,DTC Enable Status by Event Number i" "0: DTC Disable by Event number i,1: DTC Enable by Event number i"
|
||
newline
|
||
bitfld.long 0x4 2. "ST34,DTC Enable Status by Event Number i" "0: DTC Disable by Event number i,1: DTC Enable by Event number i"
|
||
bitfld.long 0x4 1. "ST33,DTC Enable Status by Event Number i" "0: DTC Disable by Event number i,1: DTC Enable by Event number i"
|
||
newline
|
||
bitfld.long 0x4 0. "ST32,DTC Enable Status by Event Number i" "0: DTC Disable by Event number i,1: DTC Enable by Event number i"
|
||
group.long 0x310++0x7
|
||
line.long 0x0 "DTCENSET0,DTC Enable Set Register 0"
|
||
bitfld.long 0x0 31. "SET31,DTC Enable Set by Event Number i" "0: No effect,1: DTC Enable by Event number i"
|
||
bitfld.long 0x0 30. "SET30,DTC Enable Set by Event Number i" "0: No effect,1: DTC Enable by Event number i"
|
||
newline
|
||
bitfld.long 0x0 29. "SET29,DTC Enable Set by Event Number i" "0: No effect,1: DTC Enable by Event number i"
|
||
bitfld.long 0x0 28. "SET28,DTC Enable Set by Event Number i" "0: No effect,1: DTC Enable by Event number i"
|
||
newline
|
||
bitfld.long 0x0 27. "SET27,DTC Enable Set by Event Number i" "0: No effect,1: DTC Enable by Event number i"
|
||
bitfld.long 0x0 23. "SET23,DTC Enable Set by Event Number i" "0: No effect,1: DTC Enable by Event number i"
|
||
newline
|
||
bitfld.long 0x0 22. "SET22,DTC Enable Set by Event Number i" "0: No effect,1: DTC Enable by Event number i"
|
||
bitfld.long 0x0 19. "SET19,DTC Enable Set by Event Number i" "0: No effect,1: DTC Enable by Event number i"
|
||
newline
|
||
bitfld.long 0x0 18. "SET18,DTC Enable Set by Event Number i" "0: No effect,1: DTC Enable by Event number i"
|
||
bitfld.long 0x0 16. "SET16,DTC Enable Set by Event Number i" "0: No effect,1: DTC Enable by Event number i"
|
||
newline
|
||
bitfld.long 0x0 15. "SET15,DTC Enable Set by Event Number i" "0: No effect,1: DTC Enable by Event number i"
|
||
bitfld.long 0x0 13. "SET13,DTC Enable Set by Event Number i" "0: No effect,1: DTC Enable by Event number i"
|
||
newline
|
||
bitfld.long 0x0 12. "SET12,DTC Enable Set by Event Number i" "0: No effect,1: DTC Enable by Event number i"
|
||
bitfld.long 0x0 7. "SET7,DTC Enable Set by Event Number i" "0: No effect,1: DTC Enable by Event number i"
|
||
newline
|
||
bitfld.long 0x0 6. "SET6,DTC Enable Set by Event Number i" "0: No effect,1: DTC Enable by Event number i"
|
||
bitfld.long 0x0 5. "SET5,DTC Enable Set by Event Number i" "0: No effect,1: DTC Enable by Event number i"
|
||
newline
|
||
bitfld.long 0x0 4. "SET4,DTC Enable Set by Event Number i" "0: No effect,1: DTC Enable by Event number i"
|
||
bitfld.long 0x0 3. "SET3,DTC Enable Set by Event Number i" "0: No effect,1: DTC Enable by Event number i"
|
||
newline
|
||
bitfld.long 0x0 2. "SET2,DTC Enable Set by Event Number i" "0: No effect,1: DTC Enable by Event number i"
|
||
bitfld.long 0x0 1. "SET1,DTC Enable Set by Event Number i" "0: No effect,1: DTC Enable by Event number i"
|
||
line.long 0x4 "DTCENSET1,DTC Enable Set Register 1"
|
||
bitfld.long 0x4 9. "SET41,DTC Enable Set by Event Number i" "0: No effect,1: DTC Enable by Event number i"
|
||
bitfld.long 0x4 8. "SET40,DTC Enable Set by Event Number i" "0: No effect,1: DTC Enable by Event number i"
|
||
newline
|
||
bitfld.long 0x4 6. "SET38,DTC Enable Set by Event Number i" "0: No effect,1: DTC Enable by Event number i"
|
||
bitfld.long 0x4 5. "SET37,DTC Enable Set by Event Number i" "0: No effect,1: DTC Enable by Event number i"
|
||
newline
|
||
bitfld.long 0x4 4. "SET36,DTC Enable Set by Event Number i" "0: No effect,1: DTC Enable by Event number i"
|
||
bitfld.long 0x4 3. "SET35,DTC Enable Set by Event Number i" "0: No effect,1: DTC Enable by Event number i"
|
||
newline
|
||
bitfld.long 0x4 2. "SET34,DTC Enable Set by Event Number i" "0: No effect,1: DTC Enable by Event number i"
|
||
bitfld.long 0x4 1. "SET33,DTC Enable Set by Event Number i" "0: No effect,1: DTC Enable by Event number i"
|
||
newline
|
||
bitfld.long 0x4 0. "SET32,DTC Enable Set by Event Number i" "0: No effect,1: DTC Enable by Event number i"
|
||
group.long 0x320++0x7
|
||
line.long 0x0 "DTCENCLR0,DTC Enable Clear Register 0"
|
||
bitfld.long 0x0 31. "CLR31,DTC Enable Clear by Event Number i" "0: No effect,1: DTC Disable by Event number i"
|
||
bitfld.long 0x0 30. "CLR30,DTC Enable Clear by Event Number i" "0: No effect,1: DTC Disable by Event number i"
|
||
newline
|
||
bitfld.long 0x0 29. "CLR29,DTC Enable Clear by Event Number i" "0: No effect,1: DTC Disable by Event number i"
|
||
bitfld.long 0x0 28. "CLR28,DTC Enable Clear by Event Number i" "0: No effect,1: DTC Disable by Event number i"
|
||
newline
|
||
bitfld.long 0x0 27. "CLR27,DTC Enable Clear by Event Number i" "0: No effect,1: DTC Disable by Event number i"
|
||
bitfld.long 0x0 23. "CLR23,DTC Enable Clear by Event Number i" "0: No effect,1: DTC Disable by Event number i"
|
||
newline
|
||
bitfld.long 0x0 22. "CLR22,DTC Enable Clear by Event Number i" "0: No effect,1: DTC Disable by Event number i"
|
||
bitfld.long 0x0 19. "CLR19,DTC Enable Clear by Event Number i" "0: No effect,1: DTC Disable by Event number i"
|
||
newline
|
||
bitfld.long 0x0 18. "CLR18,DTC Enable Clear by Event Number i" "0: No effect,1: DTC Disable by Event number i"
|
||
bitfld.long 0x0 16. "CLR16,DTC Enable Clear by Event Number i" "0: No effect,1: DTC Disable by Event number i"
|
||
newline
|
||
bitfld.long 0x0 15. "CLR15,DTC Enable Clear by Event Number i" "0: No effect,1: DTC Disable by Event number i"
|
||
bitfld.long 0x0 13. "CLR13,DTC Enable Clear by Event Number i" "0: No effect,1: DTC Disable by Event number i"
|
||
newline
|
||
bitfld.long 0x0 12. "CLR12,DTC Enable Clear by Event Number i" "0: No effect,1: DTC Disable by Event number i"
|
||
bitfld.long 0x0 7. "CLR7,DTC Enable Clear by Event Number i" "0: No effect,1: DTC Disable by Event number i"
|
||
newline
|
||
bitfld.long 0x0 6. "CLR6,DTC Enable Clear by Event Number i" "0: No effect,1: DTC Disable by Event number i"
|
||
bitfld.long 0x0 5. "CLR5,DTC Enable Clear by Event Number i" "0: No effect,1: DTC Disable by Event number i"
|
||
newline
|
||
bitfld.long 0x0 4. "CLR4,DTC Enable Clear by Event Number i" "0: No effect,1: DTC Disable by Event number i"
|
||
bitfld.long 0x0 3. "CLR3,DTC Enable Clear by Event Number i" "0: No effect,1: DTC Disable by Event number i"
|
||
newline
|
||
bitfld.long 0x0 2. "CLR2,DTC Enable Clear by Event Number i" "0: No effect,1: DTC Disable by Event number i"
|
||
bitfld.long 0x0 1. "CLR1,DTC Enable Clear by Event Number i" "0: No effect,1: DTC Disable by Event number i"
|
||
line.long 0x4 "DTCENCLR1,DTC Enable Clear Register 1"
|
||
bitfld.long 0x4 9. "CLR41,DTC Enable Clear by Event Number i" "0: No effect,1: DTC Disable by Event number i"
|
||
bitfld.long 0x4 8. "CLR40,DTC Enable Clear by Event Number i" "0: No effect,1: DTC Disable by Event number i"
|
||
newline
|
||
bitfld.long 0x4 6. "CLR38,DTC Enable Clear by Event Number i" "0: No effect,1: DTC Disable by Event number i"
|
||
bitfld.long 0x4 5. "CLR37,DTC Enable Clear by Event Number i" "0: No effect,1: DTC Disable by Event number i"
|
||
newline
|
||
bitfld.long 0x4 4. "CLR36,DTC Enable Clear by Event Number i" "0: No effect,1: DTC Disable by Event number i"
|
||
bitfld.long 0x4 3. "CLR35,DTC Enable Clear by Event Number i" "0: No effect,1: DTC Disable by Event number i"
|
||
newline
|
||
bitfld.long 0x4 2. "CLR34,DTC Enable Clear by Event Number i" "0: No effect,1: DTC Disable by Event number i"
|
||
bitfld.long 0x4 1. "CLR33,DTC Enable Clear by Event Number i" "0: No effect,1: DTC Disable by Event number i"
|
||
newline
|
||
bitfld.long 0x4 0. "CLR32,DTC Enable Clear by Event Number i" "0: No effect,1: DTC Disable by Event number i"
|
||
rgroup.long 0x330++0x7
|
||
line.long 0x0 "INTFLAG0,Interrupt Request Flag Monitor Register 0"
|
||
bitfld.long 0x0 31. "IF31,Interrupt Request Flag Monitor" "0: Interrupt request of event number i is not being..,1: Interrupt request of event number i is being.."
|
||
bitfld.long 0x0 30. "IF30,Interrupt Request Flag Monitor" "0: Interrupt request of event number i is not being..,1: Interrupt request of event number i is being.."
|
||
newline
|
||
bitfld.long 0x0 29. "IF29,Interrupt Request Flag Monitor" "0: Interrupt request of event number i is not being..,1: Interrupt request of event number i is being.."
|
||
bitfld.long 0x0 28. "IF28,Interrupt Request Flag Monitor" "0: Interrupt request of event number i is not being..,1: Interrupt request of event number i is being.."
|
||
newline
|
||
bitfld.long 0x0 27. "IF27,Interrupt Request Flag Monitor" "0: Interrupt request of event number i is not being..,1: Interrupt request of event number i is being.."
|
||
bitfld.long 0x0 26. "IF26,Interrupt Request Flag Monitor" "0: Interrupt request of event number i is not being..,1: Interrupt request of event number i is being.."
|
||
newline
|
||
bitfld.long 0x0 25. "IF25,Interrupt Request Flag Monitor" "0: Interrupt request of event number i is not being..,1: Interrupt request of event number i is being.."
|
||
bitfld.long 0x0 24. "IF24,Interrupt Request Flag Monitor" "0: Interrupt request of event number i is not being..,1: Interrupt request of event number i is being.."
|
||
newline
|
||
bitfld.long 0x0 23. "IF23,Interrupt Request Flag Monitor" "0: Interrupt request of event number i is not being..,1: Interrupt request of event number i is being.."
|
||
bitfld.long 0x0 22. "IF22,Interrupt Request Flag Monitor" "0: Interrupt request of event number i is not being..,1: Interrupt request of event number i is being.."
|
||
newline
|
||
bitfld.long 0x0 21. "IF21,Interrupt Request Flag Monitor" "0: Interrupt request of event number i is not being..,1: Interrupt request of event number i is being.."
|
||
bitfld.long 0x0 20. "IF20,Interrupt Request Flag Monitor" "0: Interrupt request of event number i is not being..,1: Interrupt request of event number i is being.."
|
||
newline
|
||
bitfld.long 0x0 19. "IF19,Interrupt Request Flag Monitor" "0: Interrupt request of event number i is not being..,1: Interrupt request of event number i is being.."
|
||
bitfld.long 0x0 18. "IF18,Interrupt Request Flag Monitor" "0: Interrupt request of event number i is not being..,1: Interrupt request of event number i is being.."
|
||
newline
|
||
bitfld.long 0x0 17. "IF17,Interrupt Request Flag Monitor" "0: Interrupt request of event number i is not being..,1: Interrupt request of event number i is being.."
|
||
bitfld.long 0x0 16. "IF16,Interrupt Request Flag Monitor" "0: Interrupt request of event number i is not being..,1: Interrupt request of event number i is being.."
|
||
newline
|
||
bitfld.long 0x0 15. "IF15,Interrupt Request Flag Monitor" "0: Interrupt request of event number i is not being..,1: Interrupt request of event number i is being.."
|
||
bitfld.long 0x0 14. "IF14,Interrupt Request Flag Monitor" "0: Interrupt request of event number i is not being..,1: Interrupt request of event number i is being.."
|
||
newline
|
||
bitfld.long 0x0 13. "IF13,Interrupt Request Flag Monitor" "0: Interrupt request of event number i is not being..,1: Interrupt request of event number i is being.."
|
||
bitfld.long 0x0 12. "IF12,Interrupt Request Flag Monitor" "0: Interrupt request of event number i is not being..,1: Interrupt request of event number i is being.."
|
||
newline
|
||
bitfld.long 0x0 11. "IF11,Interrupt Request Flag Monitor" "0: Interrupt request of event number i is not being..,1: Interrupt request of event number i is being.."
|
||
bitfld.long 0x0 10. "IF10,Interrupt Request Flag Monitor" "0: Interrupt request of event number i is not being..,1: Interrupt request of event number i is being.."
|
||
newline
|
||
bitfld.long 0x0 7. "IF7,Interrupt Request Flag Monitor" "0: Interrupt request of event number i is not being..,1: Interrupt request of event number i is being.."
|
||
bitfld.long 0x0 6. "IF6,Interrupt Request Flag Monitor" "0: Interrupt request of event number i is not being..,1: Interrupt request of event number i is being.."
|
||
newline
|
||
bitfld.long 0x0 5. "IF5,Interrupt Request Flag Monitor" "0: Interrupt request of event number i is not being..,1: Interrupt request of event number i is being.."
|
||
bitfld.long 0x0 4. "IF4,Interrupt Request Flag Monitor" "0: Interrupt request of event number i is not being..,1: Interrupt request of event number i is being.."
|
||
newline
|
||
bitfld.long 0x0 3. "IF3,Interrupt Request Flag Monitor" "0: Interrupt request of event number i is not being..,1: Interrupt request of event number i is being.."
|
||
bitfld.long 0x0 2. "IF2,Interrupt Request Flag Monitor" "0: Interrupt request of event number i is not being..,1: Interrupt request of event number i is being.."
|
||
newline
|
||
bitfld.long 0x0 1. "IF1,Interrupt Request Flag Monitor" "0: Interrupt request of event number i is not being..,1: Interrupt request of event number i is being.."
|
||
bitfld.long 0x0 0. "IF0,Interrupt Request Flag Monitor" "0: Interrupt request of event number i is not being..,1: Interrupt request of event number i is being.."
|
||
line.long 0x4 "INTFLAG1,Interrupt Request Flag Monitor Register 1"
|
||
bitfld.long 0x4 9. "IF41,Interrupt Request Flag Monitor" "0: Interrupt source of event number i is not..,1: Interrupt source of event number i is accepted.."
|
||
bitfld.long 0x4 8. "IF40,Interrupt Request Flag Monitor" "0: Interrupt source of event number i is not..,1: Interrupt source of event number i is accepted.."
|
||
newline
|
||
bitfld.long 0x4 7. "IF39,Interrupt Request Flag Monitor" "0: Interrupt source of event number i is not..,1: Interrupt source of event number i is accepted.."
|
||
bitfld.long 0x4 6. "IF38,Interrupt Request Flag Monitor" "0: Interrupt source of event number i is not..,1: Interrupt source of event number i is accepted.."
|
||
newline
|
||
bitfld.long 0x4 5. "IF37,Interrupt Request Flag Monitor" "0: Interrupt source of event number i is not..,1: Interrupt source of event number i is accepted.."
|
||
bitfld.long 0x4 4. "IF36,Interrupt Request Flag Monitor" "0: Interrupt source of event number i is not..,1: Interrupt source of event number i is accepted.."
|
||
newline
|
||
bitfld.long 0x4 3. "IF35,Interrupt Request Flag Monitor" "0: Interrupt source of event number i is not..,1: Interrupt source of event number i is accepted.."
|
||
bitfld.long 0x4 2. "IF34,Interrupt Request Flag Monitor" "0: Interrupt source of event number i is not..,1: Interrupt source of event number i is accepted.."
|
||
newline
|
||
bitfld.long 0x4 1. "IF33,Interrupt Request Flag Monitor" "0: Interrupt source of event number i is not..,1: Interrupt source of event number i is accepted.."
|
||
bitfld.long 0x4 0. "IF32,Interrupt Request Flag Monitor" "0: Interrupt source of event number i is not..,1: Interrupt source of event number i is accepted.."
|
||
group.long 0x340++0x7
|
||
line.long 0x0 "SBYEDCR0,Software Standby/Snooze End Control Register 0"
|
||
bitfld.long 0x0 31. "ADC12ED,End of A/D Conversion Interrupt Snooze Mode Returns Enable" "0: Snooze Mode returns by End of A/D conversion..,1: Snooze Mode returns by End of A/D conversion.."
|
||
bitfld.long 0x0 27. "UART0RXED,UART0 Reception Transfer End Interrupt Snooze Mode Returns Enable" "0: Snooze Mode returns by UART0 reception transfer..,1: Snooze Mode returns by UART0 reception transfer.."
|
||
newline
|
||
bitfld.long 0x0 26. "IICA0ED,IICA0 Address Match Interrupt Software Standby/Snooze Mode Returns Enable" "0: Software Standby/Snooze Mode returns by IICA0..,1: Software Standby/Snooze Mode returns by IICA0.."
|
||
bitfld.long 0x0 20. "UART0ERRED,UART0 Reception Communication Error Occurrence Interrupt Snooze Mode Returns Enable" "0: Snooze Mode returns by UART0 reception..,1: Snooze Mode returns by UART0 reception.."
|
||
newline
|
||
bitfld.long 0x0 18. "SPI00RXED,SPI00 Transfer End or Buffer Empty Interrupt Snooze Mode Returns Enable" "0: Snooze Mode returns by SPI00 transfer end or..,1: Snooze Mode returns by SPI00 transfer end or.."
|
||
bitfld.long 0x0 10. "DTCED,DTC Transfer Complete Interrupt Snooze Mode Returns Enable" "0: Snooze Mode returns by DTC transfer complete..,1: Snooze Mode returns by DTC transfer complete.."
|
||
newline
|
||
bitfld.long 0x0 7. "IRQ5ED," "0: Software Standby/Snooze mode returns by IRQ5..,1: Software Standby/Snooze mode returns by IRQ5.."
|
||
bitfld.long 0x0 6. "IRQ4ED," "0: Software Standby/Snooze mode returns by IRQ4..,1: Software Standby/Snooze mode returns by IRQ4.."
|
||
newline
|
||
bitfld.long 0x0 5. "IRQ3ED," "0: Software Standby/Snooze mode returns by IRQ3..,1: Software Standby/Snooze mode returns by IRQ3.."
|
||
bitfld.long 0x0 4. "IRQ2ED," "0: Software Standby/Snooze mode returns by IRQ2..,1: Software Standby/Snooze mode returns by IRQ2.."
|
||
newline
|
||
bitfld.long 0x0 3. "IRQ1ED," "0: Software Standby/Snooze mode returns by IRQ1..,1: Software Standby/Snooze mode returns by IRQ1.."
|
||
bitfld.long 0x0 2. "IRQ0ED," "0: Software Standby/Snooze mode returns by IRQ0..,1: Software Standby/Snooze mode returns by IRQ0.."
|
||
newline
|
||
bitfld.long 0x0 1. "LVD1ED,LVD1 Interrupt Software Standby/Snooze Mode Returns Enable" "0: Software Standby/Snooze Mode returns by LVD1..,1: Software Standby/Snooze Mode returns by LVD1.."
|
||
bitfld.long 0x0 0. "IWDTED,IWDT Interrupt Software Standby/Snooze Mode Returns Enable" "0: Software Standby/Snooze Mode returns by IWDT..,1: Software Standby/Snooze Mode returns by IWDT.."
|
||
line.long 0x4 "SBYEDCR1,Software Standby/Snooze End Control Register 1"
|
||
bitfld.long 0x4 9. "UR0ED,UARTA0 Reception Transfer End Interrupt Software Standby/Snooze Mode Returns Enable" "0: Software Standby/Snooze Mode returns by UARTA0..,1: Software Standby/Snooze Mode returns by UARTA0.."
|
||
bitfld.long 0x4 8. "UT0ED,UARTA0 Transmission Transfer End or Buffer Empty Interrupt Software Standby/Snooze Mode Returns Enable" "0: Software Standby/Snooze Mode returns by UARTA0..,1: Software Standby/Snooze Mode returns by UARTA0.."
|
||
newline
|
||
bitfld.long 0x4 7. "URE0ED,UARTA0 Reception Communication Error Interrupt Software Standby/Snooze Mode Returns Enable" "0: Software Standby/Snooze Mode returns by UARTA0..,1: Software Standby/Snooze Mode returns by UARTA0.."
|
||
bitfld.long 0x4 1. "ITLED,Interval Signal of 32-bit Interval Timer Interrupt Software Standby/Snooze Mode Returns Enable" "0: Software Standby/Snooze Mode returns by Interval..,1: Software Standby/Snooze Mode returns by Interval.."
|
||
newline
|
||
bitfld.long 0x4 0. "RTCED,RTC Interrupt Software Standby/Snooze Mode Returns Enable" "0: Software Standby/Snooze Mode returns by RTC..,1: Software Standby/Snooze Mode returns by RTC.."
|
||
tree.end
|
||
tree "IICA (I2C Bus Interface)"
|
||
base ad:0x400A3000
|
||
group.byte 0x0++0x0
|
||
line.byte 0x0 "IICA0,IICA Shift Register 0"
|
||
rgroup.byte 0x1++0x0
|
||
line.byte 0x0 "IICS0,IICA Status Register 0"
|
||
bitfld.byte 0x0 7. "MSTS,Master Status Check Flag" "0: Slave device status or communication standby..,1: Master device communication status"
|
||
bitfld.byte 0x0 6. "ALD,Detection of Arbitration Loss" "0: This status means either that there was no..,1: This status indicates the arbitration result was.."
|
||
newline
|
||
bitfld.byte 0x0 5. "EXC,Detection of Extension Code Reception" "0: Extension code was not received.,1: Extension code was received. Or the all address.."
|
||
bitfld.byte 0x0 4. "COI,Detection of Matching Addresses" "0: Addresses do not match.,1: Addresses match. Or the all address match.."
|
||
newline
|
||
bitfld.byte 0x0 3. "TRC,Detection of Transmit and Receive Status" "0: Receive status (other than transmit status). The..,1: Transmit status. The value in the SOn latch is.."
|
||
bitfld.byte 0x0 2. "ACKD,Detection of Acknowledge (ACK)" "0: Acknowledge was not detected.,1: Acknowledge was detected."
|
||
newline
|
||
bitfld.byte 0x0 1. "STD,Detection of Start Condition" "0: Start condition was not detected.,1: Start condition was detected. This indicates.."
|
||
bitfld.byte 0x0 0. "SPD,Detection of Stop Condition" "0: Stop condition was not detected.,1: Stop condition was detected. Communication of.."
|
||
group.byte 0x2++0x0
|
||
line.byte 0x0 "IICF0,IICA Flag Register 0"
|
||
rbitfld.byte 0x0 7. "STCF,IICCTL00.STT Clear Flag" "0: Generate start condition,1: Start condition generation unsuccessful: clear.."
|
||
rbitfld.byte 0x0 6. "IICBSY,I2C Bus Status Flag" "0: Bus release status (communication initial status..,1: Bus communication status (communication initial.."
|
||
newline
|
||
bitfld.byte 0x0 1. "STCEN,Initial Start Enable Trigger" "0: After operation is enabled (IICCTL00.IICE = 1)..,1: After operation is enabled (IICCTL00.IICE = 1).."
|
||
bitfld.byte 0x0 0. "IICRSV,Communication Reservation Function Disable Bit" "0: Enable communication reservation,1: Disable communication reservation"
|
||
group.byte 0x100++0x4
|
||
line.byte 0x0 "IICCTL00,IICA Control Register 00"
|
||
bitfld.byte 0x0 7. "IICE,I2C Operation Enable" "0: Stop operation. Reset the IICA status register 0..,1: Enable operation."
|
||
bitfld.byte 0x0 6. "LREL,Exit from Communications" "0: Normal operation,1: IICA exits from the current communications and.."
|
||
newline
|
||
bitfld.byte 0x0 5. "WREL,Release from the Clock Stretch State" "0: The interface is not released from the clock..,1: The interface is released from the clock stretch.."
|
||
bitfld.byte 0x0 4. "SPIE,Enable and Disable Generation of Interrupt Request when Stop Condition is Detected" "0: Disable,1: Enable"
|
||
newline
|
||
bitfld.byte 0x0 3. "WTIM,Control of Clock Stretching and Interrupt Request Generation" "0: An interrupt request is generated on the falling..,1: An interrupt request is generated on the falling.."
|
||
bitfld.byte 0x0 2. "ACKE,Acknowledgment Control" "0: Disable acknowledgment,1: Enable acknowledgment. During the 9th clock.."
|
||
newline
|
||
bitfld.byte 0x0 1. "STT,Start Condition Trigger" "0: Do not generate a start condition,1: When bus is released (in standby state when.."
|
||
bitfld.byte 0x0 0. "SPT,Stop Condition Trigger" "0: Stop condition is not generated,1: Stop condition is generated (termination of.."
|
||
line.byte 0x1 "IICCTL01,IICA Control Register 01"
|
||
bitfld.byte 0x1 7. "WUP,Control of Address Match Wakeup" "0: Stops operation of address match wakeup function..,1: Enables operation of address match wakeup.."
|
||
bitfld.byte 0x1 6. "SVADIS,Address Match Disabling Flag" "0: Disables the all address match function,1: Enables the all address match function"
|
||
newline
|
||
rbitfld.byte 0x1 5. "CLD,Detection of SCLA0 Pin Level (Valid Only when IICCTL00.IICE = 1)" "0: The SCLA0 pin was detected at low level,1: The SCLA0 pin was detected at high level"
|
||
rbitfld.byte 0x1 4. "DAD,Detection of SDAA0 Pin Level (Valid Only when IICCTL00.IICE = 1)" "0: The SDAA0 pin was detected at low level,1: The SDAA0 pin was detected at high level"
|
||
newline
|
||
bitfld.byte 0x1 3. "SMC,Operation Mode Switching" "0: Operates in standard mode (fastest transfer..,1: Operates in fast mode (fastest transfer rate:.."
|
||
bitfld.byte 0x1 2. "DFC,Digital Filter Operation Control" "0: Digital filter off,1: Digital filter on"
|
||
newline
|
||
bitfld.byte 0x1 0. "PRS,IICA Operation Clock (fMCK)" "0: Selects PCLKB (1 MHz ≤ PCLKB ≤ 20 MHz),1: Selects PCLKB/2 (20 MHz < PCLKB)"
|
||
line.byte 0x2 "IICWL0,IICA Low-level Width Setting Register 0"
|
||
line.byte 0x3 "IICWH0,IICA High-level Width Setting Register 0"
|
||
line.byte 0x4 "SVA0,Slave Address Register 0"
|
||
hexmask.byte 0x4 1.--7. 1. "A,7-bit Local Address when in Slave Mode of Unit 0"
|
||
tree.end
|
||
tree "IWDT (Independent Watchdog Timer)"
|
||
base ad:0x40044400
|
||
group.byte 0x0++0x0
|
||
line.byte 0x0 "IWDTRR,IWDT Refresh Register"
|
||
group.word 0x4++0x1
|
||
line.word 0x0 "IWDTSR,IWDT Status Register"
|
||
bitfld.word 0x0 15. "REFEF,Refresh Error Flag" "0: No refresh error occurred,1: Refresh error occurred"
|
||
bitfld.word 0x0 14. "UNDFF,Underflow Flag" "0: No underflow occurred,1: Underflow occurred"
|
||
hexmask.word 0x0 0.--13. 1. "CNTVAL,Down-counter Value"
|
||
tree.end
|
||
tree "MSTP (Module Stop Control)"
|
||
base ad:0x40047000
|
||
group.long 0x0++0xB
|
||
line.long 0x0 "MSTPCRB,Module Stop Control Register B"
|
||
bitfld.long 0x0 15. "MSTPB15,Serial Interface UARTA Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state"
|
||
bitfld.long 0x0 10. "MSTPB10,I2C Bus Interface Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state"
|
||
bitfld.long 0x0 7. "MSTPB7,Serial Array Unit 1 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state"
|
||
newline
|
||
bitfld.long 0x0 6. "MSTPB6,Serial Array Unit 0 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state"
|
||
line.long 0x4 "MSTPCRC,Module Stop Control Register C"
|
||
bitfld.long 0x4 28. "MSTPC28,True Random Number Generator Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state"
|
||
bitfld.long 0x4 14. "MSTPC14,Event Link Controller Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state"
|
||
bitfld.long 0x4 1. "MSTPC1,Cyclic Redundancy Check Calculator Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state"
|
||
line.long 0x8 "MSTPCRD,Module Stop Control Register D"
|
||
bitfld.long 0x8 23. "MSTPD23,Realtime Clock Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state"
|
||
bitfld.long 0x8 16. "MSTPD16,A/D Converter Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state"
|
||
bitfld.long 0x8 4. "MSTPD4,32-bit Interval Timer Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state"
|
||
newline
|
||
bitfld.long 0x8 0. "MSTPD0,Timer Array Unit 0 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state"
|
||
tree.end
|
||
tree "PCLBUZ (Clock Output/Buzzer Output Controller)"
|
||
base ad:0x400A3B00
|
||
group.byte 0x1++0x0
|
||
line.byte 0x0 "CKS0,Clock Out Control Register 0"
|
||
bitfld.byte 0x0 7. "PCLOE,Clock Out Enable" "0: Disable clock out,1: Enable clock out"
|
||
bitfld.byte 0x0 3. "CSEL,Clock Out Select" "0: FMAIN,1: FSUB"
|
||
bitfld.byte 0x0 0.--2. "CCS,Clock Out Divide Select" "0: value after reset FMAIN (When CKS0.CSEL = 0)..,1: FMAIN × 1/2 (When CKS0.CSEL = 0) FSUB × 1/2..,?,?,?,?,?,?"
|
||
tree.end
|
||
tree "PFS (Pmn Pin Function Select)"
|
||
base ad:0x400A0200
|
||
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
||
group.word ($2+0x10)++0x1
|
||
line.word 0x0 "P00$1PFS_A,Port 00%s Pin Function Select Register"
|
||
bitfld.word 0x0 15. "PMC,Pin mode control" "0: Digital I/O,1: Analog input function. Input to the input buffer.."
|
||
bitfld.word 0x0 8.--10. "PSEL,These bits select the peripheral function. For individual pin functions see the associated tables in this chapter." "0,1,2,3,4,5,6,7"
|
||
newline
|
||
bitfld.word 0x0 2. "PDR," "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
||
rbitfld.word 0x0 1. "PIDR,Pmn State" "0: Low output,1: High output"
|
||
newline
|
||
bitfld.word 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output"
|
||
repeat.end
|
||
repeat 5. (increment 0x0 0x1)(increment 0x0 0x2)
|
||
group.word ($2+0x14)++0x1
|
||
line.word 0x0 "P0$1PFS_A,Port 0%s Pin Function Select Register"
|
||
bitfld.word 0x0 15. "PMC,Pin mode control" "0: Digital I/O,1: Analog input function. Input to the input buffer.."
|
||
bitfld.word 0x0 8.--10. "PSEL,These bits select the peripheral function. For individual pin functions see the associated tables in this chapter." "0,1,2,3,4,5,6,7"
|
||
newline
|
||
bitfld.word 0x0 2. "PDR," "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
||
rbitfld.word 0x0 1. "PIDR,Pmn State" "0: Low output,1: High output"
|
||
newline
|
||
bitfld.word 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output"
|
||
repeat.end
|
||
group.word 0x1E++0x1
|
||
line.word 0x0 "P015PFS_A,Port 015 Pin Function Select Register"
|
||
bitfld.word 0x0 15. "PMC,Pin mode control" "0: Digital I/O,1: Analog input function. Input to the input buffer.."
|
||
bitfld.word 0x0 14. "ISEL,IRQ Input Enable" "0: Notused as an IRQn input pin,1: Used as an IRQn input pin"
|
||
newline
|
||
bitfld.word 0x0 8.--10. "PSEL,These bits select the peripheral function. For individual pin functions see the associated tables in this chapter." "0,1,2,3,4,5,6,7"
|
||
bitfld.word 0x0 2. "PDR," "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
||
newline
|
||
rbitfld.word 0x0 1. "PIDR,Pmn State" "0: Low output,1: High output"
|
||
bitfld.word 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output"
|
||
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
||
group.word ($2+0x20)++0x1
|
||
line.word 0x0 "P10$1PFS_A,Port 10%s Pin Function Select Register"
|
||
bitfld.word 0x0 15. "PMC,Pin mode control" "0: Digital I/O,1: Analog input function. Input to the input buffer.."
|
||
bitfld.word 0x0 14. "ISEL,IRQ Input Enable" "0: Notused as an IRQn input pin,1: Used as an IRQn input pin"
|
||
newline
|
||
bitfld.word 0x0 8.--10. "PSEL,These bits select the peripheral function. For individual pin functions see the associated tables in this chapter." "0,1,2,3,4,5,6,7"
|
||
bitfld.word 0x0 6. "NCODR," "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
||
newline
|
||
bitfld.word 0x0 5. "PIM," "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
||
bitfld.word 0x0 4. "PCR," "0: Disableinput pull-up,1: Enableinput pull-up"
|
||
newline
|
||
bitfld.word 0x0 2. "PDR," "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
||
rbitfld.word 0x0 1. "PIDR,Pmn State" "0: Low output,1: High output"
|
||
newline
|
||
bitfld.word 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output"
|
||
repeat.end
|
||
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
||
group.word ($2+0x24)++0x1
|
||
line.word 0x0 "P10$1PFS_A,Port 10%s Pin Function Select Register"
|
||
bitfld.word 0x0 15. "PMC,Pin mode control" "0: Digital I/O,1: Analog input function. Input to the input buffer.."
|
||
bitfld.word 0x0 14. "ISEL,IRQ Input Enable" "0: Notused as an IRQn input pin,1: Used as an IRQn input pin"
|
||
newline
|
||
bitfld.word 0x0 8.--10. "PSEL,These bits select the peripheral function. For individual pin functions see the associated tables in this chapter." "0,1,2,3,4,5,6,7"
|
||
bitfld.word 0x0 6. "NCODR," "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
||
newline
|
||
bitfld.word 0x0 5. "PIM," "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
||
bitfld.word 0x0 4. "PCR," "0: Disableinput pull-up,1: Enableinput pull-up"
|
||
newline
|
||
bitfld.word 0x0 2. "PDR," "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
||
rbitfld.word 0x0 1. "PIDR,Pmn State" "0: Low output,1: High output"
|
||
newline
|
||
bitfld.word 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output"
|
||
repeat.end
|
||
group.word 0x30++0x5
|
||
line.word 0x0 "P108PFS_A,Port 108 Pin Function Select Register"
|
||
bitfld.word 0x0 15. "PMC,Pin mode control" "0: Digital I/O,1: Analog input function. Input to the input buffer.."
|
||
bitfld.word 0x0 8.--10. "PSEL,These bits select the peripheral function. For individual pin functions see the associated tables in this chapter." "0,1,2,3,4,5,6,7"
|
||
newline
|
||
bitfld.word 0x0 5. "PIM," "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
||
bitfld.word 0x0 4. "PCR," "0: Disableinput pull-up,1: Enableinput pull-up"
|
||
newline
|
||
bitfld.word 0x0 2. "PDR," "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
||
rbitfld.word 0x0 1. "PIDR,Pmn State" "0: Low output,1: High output"
|
||
newline
|
||
bitfld.word 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output"
|
||
line.word 0x2 "P109PFS_A,Port 109 Pin Function Select Register"
|
||
bitfld.word 0x2 15. "PMC,Pin mode control" "0: Digital I/O,1: Analog input function. Input to the input buffer.."
|
||
bitfld.word 0x2 14. "ISEL,IRQ Input Enable" "0: Notused as an IRQn input pin,1: Used as an IRQn input pin"
|
||
newline
|
||
bitfld.word 0x2 8.--10. "PSEL,These bits select the peripheral function. For individual pin functions see the associated tables in this chapter." "0,1,2,3,4,5,6,7"
|
||
bitfld.word 0x2 6. "NCODR," "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
||
newline
|
||
bitfld.word 0x2 5. "PIM," "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
||
bitfld.word 0x2 4. "PCR," "0: Disableinput pull-up,1: Enableinput pull-up"
|
||
newline
|
||
bitfld.word 0x2 2. "PDR," "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
||
rbitfld.word 0x2 1. "PIDR,Pmn State" "0: Low output,1: High output"
|
||
newline
|
||
bitfld.word 0x2 0. "PODR,Port Output Data" "0: Low output,1: High output"
|
||
line.word 0x4 "P110PFS_A,Port 110 Pin Function Select Register"
|
||
bitfld.word 0x4 15. "PMC,Pin mode control" "0: Digital I/O,1: Analog input function. Input to the input buffer.."
|
||
bitfld.word 0x4 14. "ISEL,IRQ Input Enable" "0: Notused as an IRQn input pin,1: Used as an IRQn input pin"
|
||
newline
|
||
bitfld.word 0x4 8.--10. "PSEL,These bits select the peripheral function. For individual pin functions see the associated tables in this chapter." "0,1,2,3,4,5,6,7"
|
||
bitfld.word 0x4 6. "NCODR," "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
||
newline
|
||
bitfld.word 0x4 5. "PIM," "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
||
bitfld.word 0x4 4. "PCR," "0: Disableinput pull-up,1: Enableinput pull-up"
|
||
newline
|
||
bitfld.word 0x4 2. "PDR," "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
||
rbitfld.word 0x4 1. "PIDR,Pmn State" "0: Low output,1: High output"
|
||
newline
|
||
bitfld.word 0x4 0. "PODR,Port Output Data" "0: Low output,1: High output"
|
||
group.word 0x38++0x1
|
||
line.word 0x0 "P112PFS_A,Port 112 Pin Function Select Register"
|
||
bitfld.word 0x0 15. "PMC,Pin mode control" "0: Digital I/O,1: Analog input function. Input to the input buffer.."
|
||
bitfld.word 0x0 14. "ISEL,IRQ Input Enable" "0: Notused as an IRQn input pin,1: Used as an IRQn input pin"
|
||
newline
|
||
bitfld.word 0x0 8.--10. "PSEL,These bits select the peripheral function. For individual pin functions see the associated tables in this chapter." "0,1,2,3,4,5,6,7"
|
||
bitfld.word 0x0 6. "NCODR," "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
||
newline
|
||
bitfld.word 0x0 5. "PIM," "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
||
bitfld.word 0x0 4. "PCR," "0: Disableinput pull-up,1: Enableinput pull-up"
|
||
newline
|
||
bitfld.word 0x0 2. "PDR," "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
||
rbitfld.word 0x0 1. "PIDR,Pmn State" "0: Low output,1: High output"
|
||
newline
|
||
bitfld.word 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output"
|
||
group.word 0x40++0x3
|
||
line.word 0x0 "P200PFS_A,Port 200 Pin Function Select Register"
|
||
bitfld.word 0x0 15. "PMC,Pin mode control" "0: Digital I/O,1: Analog input function. Input to the input buffer.."
|
||
bitfld.word 0x0 14. "ISEL,IRQ Input Enable" "0: Notused as an IRQn input pin,1: Used as an IRQn input pin"
|
||
newline
|
||
rbitfld.word 0x0 1. "PIDR,Pmn State" "0: Low output,1: High output"
|
||
line.word 0x2 "P201PFS_A,Port 201 Pin Function Select Register"
|
||
bitfld.word 0x2 15. "PMC,Pin mode control" "0: Digital I/O,1: Analog input function. Input to the input buffer.."
|
||
bitfld.word 0x2 14. "ISEL,IRQ Input Enable" "0: Notused as an IRQn input pin,1: Used as an IRQn input pin"
|
||
newline
|
||
bitfld.word 0x2 8.--10. "PSEL,These bits select the peripheral function. For individual pin functions see the associated tables in this chapter." "0,1,2,3,4,5,6,7"
|
||
bitfld.word 0x2 6. "NCODR," "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
||
newline
|
||
bitfld.word 0x2 5. "PIM," "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
||
bitfld.word 0x2 4. "PCR," "0: Disableinput pull-up,1: Enableinput pull-up"
|
||
newline
|
||
bitfld.word 0x2 2. "PDR," "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
||
rbitfld.word 0x2 1. "PIDR,Pmn State" "0: Low output,1: High output"
|
||
newline
|
||
bitfld.word 0x2 0. "PODR,Port Output Data" "0: Low output,1: High output"
|
||
group.word 0x4C++0x1
|
||
line.word 0x0 "P206PFS_A,Port 206 Pin Function Select Register"
|
||
bitfld.word 0x0 4. "PCR," "0: Disableinput pull-up,1: Enableinput pull-up"
|
||
bitfld.word 0x0 2. "PDR," "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
||
newline
|
||
rbitfld.word 0x0 1. "PIDR,Pmn State" "0: Low output,1: High output"
|
||
bitfld.word 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output"
|
||
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
||
group.word ($2+0x4E)++0x1
|
||
line.word 0x0 "P20$1PFS_A,Port 20%s Pin Function Select Register"
|
||
bitfld.word 0x0 15. "PMC,Pin mode control" "0: Digital I/O,1: Analog input function. Input to the input buffer.."
|
||
bitfld.word 0x0 14. "ISEL,IRQ Input Enable" "0: Notused as an IRQn input pin,1: Used as an IRQn input pin"
|
||
newline
|
||
bitfld.word 0x0 8.--10. "PSEL,These bits select the peripheral function. For individual pin functions see the associated tables in this chapter." "0,1,2,3,4,5,6,7"
|
||
bitfld.word 0x0 6. "NCODR," "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
||
newline
|
||
bitfld.word 0x0 5. "PIM," "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
||
bitfld.word 0x0 4. "PCR," "0: Disableinput pull-up,1: Enableinput pull-up"
|
||
newline
|
||
bitfld.word 0x0 2. "PDR," "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
||
rbitfld.word 0x0 1. "PIDR,Pmn State" "0: Low output,1: High output"
|
||
newline
|
||
bitfld.word 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output"
|
||
repeat.end
|
||
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
||
group.word ($2+0x58)++0x1
|
||
line.word 0x0 "P2$1PFS_A,Port 2%s Pin Function Select Register"
|
||
bitfld.word 0x0 15. "PMC,Pin mode control" "0: Digital I/O,1: Analog input function. Input to the input buffer.."
|
||
bitfld.word 0x0 14. "ISEL,IRQ Input Enable" "0: Notused as an IRQn input pin,1: Used as an IRQn input pin"
|
||
newline
|
||
bitfld.word 0x0 8.--10. "PSEL,These bits select the peripheral function. For individual pin functions see the associated tables in this chapter." "0,1,2,3,4,5,6,7"
|
||
bitfld.word 0x0 6. "NCODR," "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
||
newline
|
||
bitfld.word 0x0 4. "PCR," "0: Input (functions as an input pin),1: Enableinput pull-up"
|
||
bitfld.word 0x0 2. "PDR," "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
||
newline
|
||
rbitfld.word 0x0 1. "PIDR,Pmn State" "0: Low output,1: High output"
|
||
bitfld.word 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output"
|
||
repeat.end
|
||
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
||
rgroup.word ($2+0x5C)++0x1
|
||
line.word 0x0 "P2$1PFS_A,Port 2%s Pin Function Select Register"
|
||
bitfld.word 0x0 1. "PIDR,Pmn State" "0: Input (functions as an input pin),1: High output"
|
||
repeat.end
|
||
group.word 0x60++0x1
|
||
line.word 0x0 "P300PFS_A,Port 300 Pin Function Select Register"
|
||
bitfld.word 0x0 15. "PMC,Pin mode control" "0: Digital I/O,1: Analog input function. Input to the input buffer.."
|
||
bitfld.word 0x0 8.--10. "PSEL,These bits select the peripheral function. For individual pin functions see the associated tables in this chapter." "0,1,2,3,4,5,6,7"
|
||
newline
|
||
bitfld.word 0x0 5. "PIM," "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
||
bitfld.word 0x0 4. "PCR," "0: Disableinput pull-up,1: Enableinput pull-up"
|
||
newline
|
||
bitfld.word 0x0 2. "PDR," "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
||
rbitfld.word 0x0 1. "PIDR,Pmn State" "0: Low output,1: High output"
|
||
newline
|
||
bitfld.word 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output"
|
||
group.word 0x8E++0x1
|
||
line.word 0x0 "P407PFS_A,Port 407 Pin Function Select Register"
|
||
bitfld.word 0x0 15. "PMC,Pin mode control" "0: Digital I/O,1: Analog input function. Input to the input buffer.."
|
||
bitfld.word 0x0 14. "ISEL,IRQ Input Enable" "0: Notused as an IRQn input pin,1: Used as an IRQn input pin"
|
||
newline
|
||
bitfld.word 0x0 8.--10. "PSEL,These bits select the peripheral function. For individual pin functions see the associated tables in this chapter." "0,1,2,3,4,5,6,7"
|
||
bitfld.word 0x0 6. "NCODR," "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
||
newline
|
||
bitfld.word 0x0 5. "PIM," "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
||
bitfld.word 0x0 4. "PCR," "0: Disableinput pull-up,1: Enableinput pull-up"
|
||
newline
|
||
bitfld.word 0x0 2. "PDR," "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
||
rbitfld.word 0x0 1. "PIDR,Pmn State" "0: Low output,1: High output"
|
||
newline
|
||
bitfld.word 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output"
|
||
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
||
group.word ($2+0x13A)++0x1
|
||
line.word 0x0 "P9$1PFS_A,Port 9%s Pin Function Select Register"
|
||
bitfld.word 0x0 15. "PMC,Pin Mode Control" "0: Digital I/O,1: Analog input function. Input to the input buffer.."
|
||
bitfld.word 0x0 8.--10. "PSEL,Peripheral Select" "0,1,2,3,4,5,6,7"
|
||
newline
|
||
bitfld.word 0x0 2. "PDR,P9n Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
||
rbitfld.word 0x0 1. "PIDR,P9n State" "0: Low output,1: High output"
|
||
newline
|
||
bitfld.word 0x0 0. "PODR,P9n Output Data" "0: Low output,1: High output"
|
||
repeat.end
|
||
group.byte 0x140++0x0
|
||
line.byte 0x0 "PWPR,Write-Protect Register"
|
||
bitfld.byte 0x0 7. "B0WI,PFSWE Bit Write Disable" "0: Writing to the PFSWE bit is enabled,1: Writing to the PFSWE bit is disabled"
|
||
bitfld.byte 0x0 6. "PFSWE,PmnPFS_A Register Write Enable" "0: Writing to the PmnPFS_A register is disable,1: Writing to the PmnPFS_A register is enable"
|
||
tree.end
|
||
tree "PORGA (Product Organize)"
|
||
base ad:0x400A1000
|
||
group.byte 0x0++0x1
|
||
line.byte 0x0 "SNFEN,SAU Noise Filter Enable Register"
|
||
bitfld.byte 0x0 4. "SNFEN20,Use of Noise Filter of RxD2 Pin" "0: Noise filter OFF,1: Noise filter ON"
|
||
bitfld.byte 0x0 2. "SNFEN10,Use of Noise Filter of RxD1 Pin" "0: Noise filter OFF,1: Noise filter ON"
|
||
newline
|
||
bitfld.byte 0x0 0. "SNFEN00,Use of Noise Filter of RxD0 Pin" "0: Noise filter OFF,1: Noise filter ON"
|
||
line.byte 0x1 "TNFEN,TAU Noise Filter Enable Register"
|
||
bitfld.byte 0x1 7. "TNFEN07,Enabling or Disabling Use of the Noise Filter for the TI07 Pin" "0: Turns the noise filter off.,1: Turns the noise filter on."
|
||
bitfld.byte 0x1 6. "TNFEN06,Enabling or Disabling Use of the Noise Filter for the TI06 Pin" "0: Turns the noise filter off.,1: Turns the noise filter on."
|
||
newline
|
||
bitfld.byte 0x1 5. "TNFEN05,Enabling or Disabling Use of the Noise Filter for the TI05 Pin" "0: Turns the noise filter off.,1: Turns the noise filter on."
|
||
bitfld.byte 0x1 4. "TNFEN04,Enabling or Disabling Use of the Noise Filter for the TI04 Pin" "0: Turns the noise filter off.,1: Turns the noise filter on."
|
||
newline
|
||
bitfld.byte 0x1 3. "TNFEN03,Enabling or Disabling Use of the Noise Filter for the TI03 Pin" "0: Turns the noise filter off.,1: Turns the noise filter on."
|
||
bitfld.byte 0x1 2. "TNFEN02,Enabling or Disabling Use of the Noise Filter for the TI02 Pin" "0: Turns the noise filter off.,1: Turns the noise filter on."
|
||
newline
|
||
bitfld.byte 0x1 1. "TNFEN01,Enabling or Disabling Use of the Noise Filter for the TI01 Pin" "0: Turns the noise filter off.,1: Turns the noise filter on."
|
||
bitfld.byte 0x1 0. "TNFEN00,Enabling or Disabling Use of the Noise Filter for the TI00 Pin" "0: Turns the noise filter off.,1: Turns the noise filter on."
|
||
group.byte 0x3++0x2
|
||
line.byte 0x0 "ISC,Input Switch Control Register"
|
||
bitfld.byte 0x0 2. "SSIE00,Setting of the SSI00 Input of Channel 0 in the Communications Through SPI00 in the Slave Mode" "0: The SSI00 input is disabled.,1: The SSI00 input is enabled."
|
||
bitfld.byte 0x0 1. "ISC1,Switching Channel 7 Input of Timer Array Unit" "0: Uses the input signal of the TI07 pin as a timer..,1: Input signal of the RXD2 pin is used as timer.."
|
||
newline
|
||
bitfld.byte 0x0 0. "ISC0,Switching External Interrupt (IRQ0) Input" "0: Uses the input signal of the IRQ0 pin as an..,1: Uses the input signal of the RXD2 pin as an.."
|
||
line.byte 0x1 "TIS0,Timer Input Select Register 0"
|
||
bitfld.byte 0x1 0.--2. "TIS,Selection of Timer Input Used with Channel 5" "0: Setting prohibited,?,?,?,?,?,?,?"
|
||
line.byte 0x2 "TIS1,Timer Input Select Register 1"
|
||
bitfld.byte 0x2 1. "TIS1,Selection of Timer Input Used with Channel 1" "0: Input signal of timer input pin (TI01),1: Event input signal from ELC"
|
||
bitfld.byte 0x2 0. "TIS0,Selection of Timer Input Used with Channel 0" "0: Input signal of timer input pin (TI00),1: Event input signal from ELC"
|
||
group.byte 0x9++0x0
|
||
line.byte 0x0 "ULBS,UART Loopback Select Register"
|
||
bitfld.byte 0x0 4. "ULBS4,Selection of the UARTA Loopback Function" "0: Inputs the states of the RxDA0 pin of serial..,1: Loops back output from the transmission shift.."
|
||
bitfld.byte 0x0 2. "ULBS2,Selection of the UART2 Loopback Function" "0: Inputs the states of the RxD2 pin of serial..,1: Loops back output from the transmission shift.."
|
||
newline
|
||
bitfld.byte 0x0 1. "ULBS1,Selection of the UART1 Loopback Function" "0: Inputs the states of the RxD1 pin of serial..,1: Loops back output from the transmission shift.."
|
||
bitfld.byte 0x0 0. "ULBS0,Selection of the UART0 Loopback Function" "0: Inputs the states of the RxD0 pin of serial..,1: Loops back output from the transmission shift.."
|
||
tree.end
|
||
tree "PORT (Port Control)"
|
||
base ad:0x0
|
||
tree "PORT0"
|
||
base ad:0x400A0000
|
||
group.word 0x0++0x3
|
||
line.word 0x0 "PODR0,Port 0 Output Data Register"
|
||
bitfld.word 0x0 15. "PODR15,P015 Output Data" "0: Low output,1: High output"
|
||
bitfld.word 0x0 14. "PODR14,P014 Output Data" "0: Low output,1: High output"
|
||
bitfld.word 0x0 13. "PODR13,P013 Output Data" "0: Low output,1: High output"
|
||
bitfld.word 0x0 12. "PODR12,P012 Output Data" "0: Low output,1: High output"
|
||
newline
|
||
bitfld.word 0x0 11. "PODR11,P011 Output Data" "0: Low output,1: High output"
|
||
bitfld.word 0x0 10. "PODR10,P010 Output Data" "0: Low output,1: High output"
|
||
bitfld.word 0x0 9. "PODR09,P009 Output Data" "0: Low output,1: High output"
|
||
bitfld.word 0x0 8. "PODR08,P008 Output Data" "0: Low output,1: High output"
|
||
line.word 0x2 "PDR0,Port 0 Direction Register"
|
||
bitfld.word 0x2 15. "PDR15,P015 Direction" "0: Output 0,1: Output 1"
|
||
bitfld.word 0x2 14. "PDR14,P014 Direction" "0: Output 0,1: Output 1"
|
||
bitfld.word 0x2 13. "PDR13,P013 Direction" "0: Output 0,1: Output 1"
|
||
bitfld.word 0x2 12. "PDR12,P012 Direction" "0: Output 0,1: Output 1"
|
||
newline
|
||
bitfld.word 0x2 11. "PDR11,P011 Direction" "0: Output 0,1: Output 1"
|
||
bitfld.word 0x2 10. "PDR10,P010 Direction" "0: Output 0,1: Output 1"
|
||
bitfld.word 0x2 9. "PDR09,P009 Direction" "0: Output 0,1: Output 1"
|
||
bitfld.word 0x2 8. "PDR08,P008 Direction" "0: Output 0,1: Output 1"
|
||
rgroup.word 0x6++0x1
|
||
line.word 0x0 "PIDR0,Port 0 State Register"
|
||
bitfld.word 0x0 15. "PIDR15,P015 State" "0: Low level,1: High level"
|
||
bitfld.word 0x0 14. "PIDR14,P014 State" "0: Low level,1: High level"
|
||
bitfld.word 0x0 13. "PIDR13,P013 State" "0: Low level,1: High level"
|
||
bitfld.word 0x0 12. "PIDR12,P012 State" "0: Low level,1: High level"
|
||
newline
|
||
bitfld.word 0x0 11. "PIDR11,P011 State" "0: Low level,1: High level"
|
||
bitfld.word 0x0 10. "PIDR10,P010 State" "0: Low level,1: High level"
|
||
bitfld.word 0x0 9. "PIDR09,P009 State" "0: Low level,1: High level"
|
||
bitfld.word 0x0 8. "PIDR08,P008 State" "0: Low level,1: High level"
|
||
wgroup.word 0x8++0x3
|
||
line.word 0x0 "PORR0,Port 0 Output Reset Register"
|
||
bitfld.word 0x0 15. "PORR15,P015 Output Reset" "0: No effect on output,1: Low output"
|
||
bitfld.word 0x0 14. "PORR14,P014 Output Reset" "0: No effect on output,1: Low output"
|
||
bitfld.word 0x0 13. "PORR13,P013 Output Reset" "0: No effect on output,1: Low output"
|
||
bitfld.word 0x0 12. "PORR12,P012 Output Reset" "0: No effect on output,1: Low output"
|
||
newline
|
||
bitfld.word 0x0 11. "PORR11,P011 Output Reset" "0: No effect on output,1: Low output"
|
||
bitfld.word 0x0 10. "PORR10,P010 Output Reset" "0: No effect on output,1: Low output"
|
||
bitfld.word 0x0 9. "PORR09,P009 Output Reset" "0: No effect on output,1: Low output"
|
||
bitfld.word 0x0 8. "PORR08,P008 Output Reset" "0: No effect on output,1: Low output"
|
||
line.word 0x2 "POSR0,Port 0 Output Set Register"
|
||
bitfld.word 0x2 15. "POSR15,P015 Output Set" "0: No effect on output,1: High output"
|
||
bitfld.word 0x2 14. "POSR14,P014 Output Set" "0: No effect on output,1: High output"
|
||
bitfld.word 0x2 13. "POSR13,P013 Output Set" "0: No effect on output,1: High output"
|
||
bitfld.word 0x2 12. "POSR12,P012 Output Set" "0: No effect on output,1: High output"
|
||
newline
|
||
bitfld.word 0x2 11. "POSR11,P011 Output Set" "0: No effect on output,1: High output"
|
||
bitfld.word 0x2 10. "POSR10,P010 Output Set" "0: No effect on output,1: High output"
|
||
bitfld.word 0x2 9. "POSR09,P009 Output Set" "0: No effect on output,1: High output"
|
||
bitfld.word 0x2 8. "POSR08,P008 Output Set" "0: No effect on output,1: High output"
|
||
tree.end
|
||
tree "PORT1"
|
||
base ad:0x400A0020
|
||
group.word 0x0++0x3
|
||
line.word 0x0 "PODR1,Port 1 Output Data Register"
|
||
bitfld.word 0x0 12. "PODR12,P112 Output Data" "0: Low output,1: High output"
|
||
bitfld.word 0x0 10. "PODR10,P110 Output Data" "0: Low output,1: High output"
|
||
bitfld.word 0x0 9. "PODR09,P109 Output Data" "0: Low output,1: High output"
|
||
bitfld.word 0x0 8. "PODR08,P108 Output Data" "0: Low output,1: High output"
|
||
newline
|
||
bitfld.word 0x0 3. "PODR03,P103 Output Data" "0: Low output,1: High output"
|
||
bitfld.word 0x0 2. "PODR02,P102 Output Data" "0: Low output,1: High output"
|
||
bitfld.word 0x0 1. "PODR01,P101 Output Data" "0: Low output,1: High output"
|
||
bitfld.word 0x0 0. "PODR00,P100 Output Data" "0: Low output,1: High output"
|
||
line.word 0x2 "PDR1,Port 1 Direction Register"
|
||
bitfld.word 0x2 12. "PDR12,P112 Direction" "0: Output 0,1: Output 1"
|
||
bitfld.word 0x2 10. "PDR10,P110 Direction" "0: Output 0,1: Output 1"
|
||
bitfld.word 0x2 9. "PDR09,P109 Direction" "0: Output 0,1: Output 1"
|
||
bitfld.word 0x2 8. "PDR08,P108 Direction" "0: Output 0,1: Output 1"
|
||
newline
|
||
bitfld.word 0x2 3. "PDR03,P103 Direction" "0: Output 0,1: Output 1"
|
||
bitfld.word 0x2 2. "PDR02,P102 Direction" "0: Output 0,1: Output 1"
|
||
bitfld.word 0x2 1. "PDR01,P101 Direction" "0: Output 0,1: Output 1"
|
||
bitfld.word 0x2 0. "PDR00,P100 Direction" "0: Output 0,1: Output 1"
|
||
rgroup.word 0x6++0x1
|
||
line.word 0x0 "PIDR1,Port 1 State Register"
|
||
bitfld.word 0x0 12. "PIDR12,P112 State" "0: Low level,1: High level"
|
||
bitfld.word 0x0 10. "PIDR10,P110 State" "0: Low level,1: High level"
|
||
bitfld.word 0x0 9. "PIDR09,P109 State" "0: Low level,1: High level"
|
||
bitfld.word 0x0 8. "PIDR08,P108 State" "0: Low level,1: High level"
|
||
newline
|
||
bitfld.word 0x0 3. "PIDR03,P103 State" "0: Low level,1: High level"
|
||
bitfld.word 0x0 2. "PIDR02,P102 State" "0: Low level,1: High level"
|
||
bitfld.word 0x0 1. "PIDR01,P101 State" "0: Low level,1: High level"
|
||
bitfld.word 0x0 0. "PIDR00,P100 State" "0: Low level,1: High level"
|
||
wgroup.word 0x8++0x3
|
||
line.word 0x0 "PORR1,Port 1 Output Reset Register"
|
||
bitfld.word 0x0 12. "PORR12,P112 Output Reset" "0: No effect on output,1: Low output"
|
||
bitfld.word 0x0 10. "PORR10,P110 Output Reset" "0: No effect on output,1: Low output"
|
||
bitfld.word 0x0 9. "PORR09,P109 Output Reset" "0: No effect on output,1: Low output"
|
||
bitfld.word 0x0 8. "PORR08,P108 Output Reset" "0: No effect on output,1: Low output"
|
||
newline
|
||
bitfld.word 0x0 3. "PORR03,P103 Output Reset" "0: No effect on output,1: Low output"
|
||
bitfld.word 0x0 2. "PORR02,P102 Output Reset" "0: No effect on output,1: Low output"
|
||
bitfld.word 0x0 1. "PORR01,P101 Output Reset" "0: No effect on output,1: Low output"
|
||
bitfld.word 0x0 0. "PORR00,P100 Output Reset" "0: No effect on output,1: Low output"
|
||
line.word 0x2 "POSR1,Port 1 Output Set Register"
|
||
bitfld.word 0x2 12. "POSR12,P112 Output Set" "0: No effect on output,1: High output"
|
||
bitfld.word 0x2 10. "POSR10,P110 Output Set" "0: No effect on output,1: High output"
|
||
bitfld.word 0x2 9. "POSR09,P109 Output Set" "0: No effect on output,1: High output"
|
||
bitfld.word 0x2 8. "POSR08,P108 Output Set" "0: No effect on output,1: High output"
|
||
newline
|
||
bitfld.word 0x2 3. "POSR03,P103 Output Set" "0: No effect on output,1: High output"
|
||
bitfld.word 0x2 2. "POSR02,P102 Output Set" "0: No effect on output,1: High output"
|
||
bitfld.word 0x2 1. "POSR01,P101 Output Set" "0: No effect on output,1: High output"
|
||
bitfld.word 0x2 0. "POSR00,P100 Output Set" "0: No effect on output,1: High output"
|
||
group.word 0xC++0x3
|
||
line.word 0x0 "EORR1,Port 1 Event Output Reset Register"
|
||
bitfld.word 0x0 12. "EORR12,P112 Event Output Reset" "0: No effect on output,1: Low output"
|
||
bitfld.word 0x0 10. "EORR10,P110 Event Output Reset" "0: No effect on output,1: Low output"
|
||
bitfld.word 0x0 9. "EORR09,P109 Event Output Reset" "0: No effect on output,1: Low output"
|
||
bitfld.word 0x0 8. "EORR08,P108 Event Output Reset" "0: No effect on output,1: Low output"
|
||
newline
|
||
bitfld.word 0x0 3. "EORR03,P103 Event Output Reset" "0: No effect on output,1: Low output"
|
||
bitfld.word 0x0 2. "EORR02,P102 Event Output Reset" "0: No effect on output,1: Low output"
|
||
bitfld.word 0x0 1. "EORR01,P101 Event Output Reset" "0: No effect on output,1: Low output"
|
||
bitfld.word 0x0 0. "EORR00,P100 Event Output Reset" "0: No effect on output,1: Low output"
|
||
line.word 0x2 "EOSR1,Port 1 Event Output Set Register"
|
||
bitfld.word 0x2 12. "EOSR12,P112 Event Output Set" "0: No effect on output,1: High output"
|
||
bitfld.word 0x2 10. "EOSR10,P110 Event Output Set" "0: No effect on output,1: High output"
|
||
bitfld.word 0x2 9. "EOSR09,P109 Event Output Set" "0: No effect on output,1: High output"
|
||
bitfld.word 0x2 8. "EOSR08,P108 Event Output Set" "0: No effect on output,1: High output"
|
||
newline
|
||
bitfld.word 0x2 3. "EOSR03,P103 Event Output Set" "0: No effect on output,1: High output"
|
||
bitfld.word 0x2 2. "EOSR02,P102 Event Output Set" "0: No effect on output,1: High output"
|
||
bitfld.word 0x2 1. "EOSR01,P101 Event Output Set" "0: No effect on output,1: High output"
|
||
bitfld.word 0x2 0. "EOSR00,P100 Event Output Set" "0: No effect on output,1: High output"
|
||
tree.end
|
||
tree "PORT2"
|
||
base ad:0x400A0040
|
||
group.word 0x0++0x3
|
||
line.word 0x0 "PODR2,Port 2 Output Data Register"
|
||
bitfld.word 0x0 13. "PODR13,P213 Output Data" "0: Low output,1: High output"
|
||
bitfld.word 0x0 12. "PODR12,P212 Output Data" "0: Low output,1: High output"
|
||
bitfld.word 0x0 8. "PODR08,P208 Output Data" "0: Low output,1: High output"
|
||
bitfld.word 0x0 7. "PODR07,P207 Output Data" "0: Low output,1: High output"
|
||
newline
|
||
bitfld.word 0x0 6. "PODR06,P206 Output Data" "0: Low output,1: High output"
|
||
bitfld.word 0x0 1. "PODR01,P201 Output Data" "0: Low output,1: High output"
|
||
line.word 0x2 "PDR2,Port 2 Direction Register"
|
||
bitfld.word 0x2 13. "PDR13,P213 Direction" "0: Output 0,1: Output 1"
|
||
bitfld.word 0x2 12. "PDR12,P212 Direction" "0: Output 0,1: Output 1"
|
||
bitfld.word 0x2 8. "PDR08,P208 Direction" "0: Output 0,1: Output 1"
|
||
bitfld.word 0x2 7. "PDR07,P207 Direction" "0: Output 0,1: Output 1"
|
||
newline
|
||
bitfld.word 0x2 6. "PDR06,P206 Direction" "0: Output 0,1: Output 1"
|
||
bitfld.word 0x2 1. "PDR01,P201 Direction" "0: Output 0,1: Output 1"
|
||
rgroup.word 0x6++0x1
|
||
line.word 0x0 "PIDR2,Port 2 State Register"
|
||
bitfld.word 0x0 15. "PIDR15,P215 State" "0: Low level,1: High level"
|
||
bitfld.word 0x0 14. "PIDR14,P214 State" "0: Low level,1: High level"
|
||
bitfld.word 0x0 13. "PIDR13,P213 State" "0: Low level,1: High level"
|
||
bitfld.word 0x0 12. "PIDR12,P212 State" "0: Low level,1: High level"
|
||
newline
|
||
bitfld.word 0x0 8. "PIDR08,P208 State" "0: Low level,1: High level"
|
||
bitfld.word 0x0 7. "PIDR07,P207 State" "0: Low level,1: High level"
|
||
bitfld.word 0x0 6. "PIDR06,P206 State" "0: Low level,1: High level"
|
||
bitfld.word 0x0 1. "PIDR01,P201 State" "0: Low level,1: High level"
|
||
newline
|
||
bitfld.word 0x0 0. "PIDR00,P200 State" "0: Low level,1: High level"
|
||
wgroup.word 0x8++0x3
|
||
line.word 0x0 "PORR2,Port 2 Output Reset Register"
|
||
bitfld.word 0x0 13. "PORR13,P213 Output Reset" "0: No effect on output,1: Low output"
|
||
bitfld.word 0x0 12. "PORR12,P212 Output Reset" "0: No effect on output,1: Low output"
|
||
bitfld.word 0x0 8. "PORR08,P208 Output Reset" "0: No effect on output,1: Low output"
|
||
bitfld.word 0x0 7. "PORR07,P207 Output Reset" "0: No effect on output,1: Low output"
|
||
newline
|
||
bitfld.word 0x0 6. "PORR06,P206 Output Reset" "0: No effect on output,1: Low output"
|
||
bitfld.word 0x0 1. "PORR01,P201 Output Reset" "0: No effect on output,1: Low output"
|
||
line.word 0x2 "POSR2,Port 2 Output Set Register"
|
||
bitfld.word 0x2 13. "POSR13,P213 Output Set" "0: No effect on output,1: High output"
|
||
bitfld.word 0x2 12. "POSR12,P212 Output Set" "0: No effect on output,1: High output"
|
||
bitfld.word 0x2 8. "POSR08,P208 Output Set" "0: No effect on output,1: High output"
|
||
bitfld.word 0x2 7. "POSR07,P207 Output Set" "0: No effect on output,1: High output"
|
||
newline
|
||
bitfld.word 0x2 6. "POSR06,P206 Output Set" "0: No effect on output,1: High output"
|
||
bitfld.word 0x2 1. "POSR01,P201 Output Set" "0: No effect on output,1: High output"
|
||
group.word 0xC++0x3
|
||
line.word 0x0 "EORR2,Port 2 Event Output Reset Register"
|
||
bitfld.word 0x0 15. "EORR15,P215 Event Output Reset" "0: No effect on output,1: Low output"
|
||
bitfld.word 0x0 14. "EORR14,P214 Event Output Reset" "0: No effect on output,1: Low output"
|
||
bitfld.word 0x0 13. "EORR13,P213 Event Output Reset" "0: No effect on output,1: Low output"
|
||
bitfld.word 0x0 12. "EORR12,P212 Event Output Reset" "0: No effect on output,1: Low output"
|
||
newline
|
||
bitfld.word 0x0 8. "EORR08,P208 Event Output Reset" "0: No effect on output,1: Low output"
|
||
bitfld.word 0x0 7. "EORR07,P207 Event Output Reset" "0: No effect on output,1: Low output"
|
||
bitfld.word 0x0 6. "EORR06,P206 Event Output Reset" "0: No effect on output,1: Low output"
|
||
bitfld.word 0x0 1. "EORR01,P201 Event Output Reset" "0: No effect on output,1: Low output"
|
||
newline
|
||
bitfld.word 0x0 0. "EORR00,P200 Event Output Reset" "0: No effect on output,1: Low output"
|
||
line.word 0x2 "EOSR2,Port 2 Event Output Set Register"
|
||
bitfld.word 0x2 15. "EOSR15,P215 Event Output Set" "0: No effect on output,1: High output"
|
||
bitfld.word 0x2 14. "EOSR14,P214 Event Output Set" "0: No effect on output,1: High output"
|
||
bitfld.word 0x2 13. "EOSR13,P213 Event Output Set" "0: No effect on output,1: High output"
|
||
bitfld.word 0x2 12. "EOSR12,P212 Event Output Set" "0: No effect on output,1: High output"
|
||
newline
|
||
bitfld.word 0x2 8. "EOSR08,P208 Event Output Set" "0: No effect on output,1: High output"
|
||
bitfld.word 0x2 7. "EOSR07,P207 Event Output Set" "0: No effect on output,1: High output"
|
||
bitfld.word 0x2 6. "EOSR06,P206 Event Output Set" "0: No effect on output,1: High output"
|
||
bitfld.word 0x2 1. "EOSR01,P201 Event Output Set" "0: No effect on output,1: High output"
|
||
newline
|
||
bitfld.word 0x2 0. "EOSR00,P200 Event Output Set" "0: No effect on output,1: High output"
|
||
tree.end
|
||
tree "PORT3"
|
||
base ad:0x400A0060
|
||
group.word 0x0++0x3
|
||
line.word 0x0 "PODR3,Port 3 Output Data Register"
|
||
bitfld.word 0x0 0. "PODR00,P300 Output Data" "0: Low output,1: High output"
|
||
line.word 0x2 "PDR3,Port 3 Direction Register"
|
||
bitfld.word 0x2 0. "PDR00,P300 Direction" "0: Output 0,1: Output 1"
|
||
rgroup.word 0x6++0x1
|
||
line.word 0x0 "PIDR3,Port 3 State Register"
|
||
bitfld.word 0x0 0. "PIDR00,P300 State" "0: Low level,1: High level"
|
||
wgroup.word 0x8++0x3
|
||
line.word 0x0 "PORR3,Port 3 Output Reset Register"
|
||
bitfld.word 0x0 0. "PORR00,P300 Output Reset" "0: No effect on output,1: Low output"
|
||
line.word 0x2 "POSR3,Port 3 Output Set Register"
|
||
bitfld.word 0x2 0. "POSR00,P300 Output Set" "0: No effect on output,1: High output"
|
||
tree.end
|
||
tree "PORT4"
|
||
base ad:0x400A0080
|
||
group.word 0x0++0x3
|
||
line.word 0x0 "PODR4,Port 4 Output Data Register"
|
||
bitfld.word 0x0 7. "PODR07,P407 Output Data" "0: Low output,1: High output"
|
||
line.word 0x2 "PDR4,Port 4 Direction Register"
|
||
bitfld.word 0x2 7. "PDR07,P407 Direction" "0: Output 0,1: Output 1"
|
||
rgroup.word 0x6++0x1
|
||
line.word 0x0 "PIDR4,Port 4 State Register"
|
||
bitfld.word 0x0 7. "PIDR07,P407 State" "0: Low level,1: High level"
|
||
wgroup.word 0x8++0x3
|
||
line.word 0x0 "PORR4,Port 4 Output Reset Register"
|
||
bitfld.word 0x0 7. "PORR07,P407 Output Reset" "0: No effect on output,1: Low output"
|
||
line.word 0x2 "POSR4,Port 4 Output Set Register"
|
||
bitfld.word 0x2 7. "POSR07,P407 Output Set" "0: No effect on output,1: High output"
|
||
tree.end
|
||
tree "PORT9"
|
||
base ad:0x400A0120
|
||
group.word 0x0++0x3
|
||
line.word 0x0 "PODR9,Port 9 Output Data Register"
|
||
bitfld.word 0x0 14. "PODR14,P914 Output Data" "0: Low output,1: High output"
|
||
bitfld.word 0x0 13. "PODR13,P913 Output Data" "0: Low output,1: High output"
|
||
line.word 0x2 "PDR9,Port 9 Direction Register"
|
||
bitfld.word 0x2 14. "PDR14,P914 Direction" "0: Output 0,1: Output 1"
|
||
bitfld.word 0x2 13. "PDR13,P913 Direction" "0: Output 0,1: Output 1"
|
||
rgroup.word 0x6++0x1
|
||
line.word 0x0 "PIDR9,Port 9 State Register"
|
||
bitfld.word 0x0 14. "PIDR14,P914 State" "0: Low level,1: High level"
|
||
bitfld.word 0x0 13. "PIDR13,P913 State" "0: Low level,1: High level"
|
||
wgroup.word 0x8++0x3
|
||
line.word 0x0 "PORR9,Port 9 Output Reset Register"
|
||
bitfld.word 0x0 14. "PORR14,P914 Output Reset" "0: No effect on output,1: Low output"
|
||
bitfld.word 0x0 13. "PORR13,P913 Output Reset" "0: No effect on output,1: Low output"
|
||
line.word 0x2 "POSR9,Port 9 Output Set Register"
|
||
bitfld.word 0x2 14. "POSR14,P914 Output Set" "0: No effect on output,1: High output"
|
||
bitfld.word 0x2 13. "POSR13,P913 Output Set" "0: No effect on output,1: High output"
|
||
tree.end
|
||
tree.end
|
||
tree "RTC (Realtime Clock)"
|
||
base ad:0x400A2C00
|
||
group.byte 0x0++0xC
|
||
line.byte 0x0 "SEC,Second Count Register"
|
||
bitfld.byte 0x0 4.--6. "SEC10,10-second count" "0,1,2,3,4,5,6,7"
|
||
hexmask.byte 0x0 0.--3. 1. "SEC1,1-second count"
|
||
line.byte 0x1 "MIN,Minute Count Register"
|
||
bitfld.byte 0x1 4.--6. "MIN10,10- minute count" "0,1,2,3,4,5,6,7"
|
||
hexmask.byte 0x1 0.--3. 1. "MIN1,1-minute count"
|
||
line.byte 0x2 "HOUR,Hour Count Register"
|
||
bitfld.byte 0x2 4.--5. "HOUR10,10-hour count" "0,1,2,3"
|
||
hexmask.byte 0x2 0.--3. 1. "HOUR1,1-hour count"
|
||
line.byte 0x3 "WEEK,Day-of-Week Count Register"
|
||
bitfld.byte 0x3 0.--2. "WEEK,Day-of-Week Counting" "0: Setting prohibited,1: Monday,?,?,?,?,?,?"
|
||
line.byte 0x4 "DAY,Day Count Register"
|
||
bitfld.byte 0x4 4.--5. "DAY10,10-day count" "0,1,2,3"
|
||
hexmask.byte 0x4 0.--3. 1. "DAY1,1-day count"
|
||
line.byte 0x5 "MONTH,Month Count Register"
|
||
bitfld.byte 0x5 4. "MONTH10,10-month count" "0,1"
|
||
hexmask.byte 0x5 0.--3. 1. "MONTH1,1-month count"
|
||
line.byte 0x6 "YEAR,Year Count Register"
|
||
hexmask.byte 0x6 4.--7. 1. "YEAR10,10-year count"
|
||
hexmask.byte 0x6 0.--3. 1. "YEAR1,1-year count"
|
||
line.byte 0x7 "SUBCUD,Time Error Correction Register"
|
||
bitfld.byte 0x7 7. "DEV,Setting of time error correction timing" "0: Corrects time error when the second digits are..,1: Corrects time error only when the second digits.."
|
||
bitfld.byte 0x7 6. "F6,Setting of time error correction value" "0: Increases by {F[5:0] – 1} × 2,1: Decreases by {/F[5:0] + 1} × 2"
|
||
newline
|
||
hexmask.byte 0x7 0.--5. 1. "F,Adjustment Value"
|
||
line.byte 0x8 "ALARMWM,Alarm Minute Register"
|
||
bitfld.byte 0x8 4.--6. "WM10,10-digit minute setting" "0,1,2,3,4,5,6,7"
|
||
hexmask.byte 0x8 0.--3. 1. "WM1,1-digit minute setting"
|
||
line.byte 0x9 "ALARMWH,Alarm Hour Register"
|
||
bitfld.byte 0x9 4.--5. "WH10,10-digit hour setting" "0,1,2,3"
|
||
hexmask.byte 0x9 0.--3. 1. "WH1,1-digit hour setting"
|
||
line.byte 0xA "ALARMWW,Alarm Day-of-Week Register"
|
||
bitfld.byte 0xA 6. "WW6,Alarm enabled setting 'Saturday'" "0: Disable alarm settings for that day of the week,1: Enable alarm settings for that day of the week"
|
||
bitfld.byte 0xA 5. "WW5,Alarm enabled setting 'Friday'" "0: Disable alarm settings for that day of the week,1: Enable alarm settings for that day of the week"
|
||
newline
|
||
bitfld.byte 0xA 4. "WW4,Alarm enabled setting 'Thursday'" "0: Disable alarm settings for that day of the week,1: Enable alarm settings for that day of the week"
|
||
bitfld.byte 0xA 3. "WW3,Alarm enabled setting 'Wednesday'" "0: Disable alarm settings for that day of the week,1: Enable alarm settings for that day of the week"
|
||
newline
|
||
bitfld.byte 0xA 2. "WW2,Alarm enabled setting 'Tuesday'" "0: Disable alarm settings for that day of the week,1: Enable alarm settings for that day of the week"
|
||
bitfld.byte 0xA 1. "WW1,Alarm enabled setting 'Monday'" "0: Disable alarm settings for that day of the week,1: Enable alarm settings for that day of the week"
|
||
newline
|
||
bitfld.byte 0xA 0. "WW0,Alarm enabled setting 'Sunday'" "0: Disable alarm settings for that day of the week,1: Enable alarm settings for that day of the week"
|
||
line.byte 0xB "RTCC0,Realtime Clock Control Register 0"
|
||
bitfld.byte 0xB 7. "RTCE,Realtime clock operation control" "0: Stops counter operation,1: Starts counter operation"
|
||
bitfld.byte 0xB 5. "RCLOE1,RTCOUT pin output control" "0: Disables output of the RTCOUT pin (1 Hz),1: Enables output of the RTCOUT pin (1 Hz)"
|
||
newline
|
||
bitfld.byte 0xB 4. "RTC128EN,Selection of the operating clock for the realtime clock (RTCCLK)" "0: SOSC (32.768 kHz),1: SOSC/256 (128 Hz)"
|
||
bitfld.byte 0xB 3. "AMPM,Selection of 12- or 24-hour system" "0: 12-hour system (a.m. and p.m. are displayed.),1: 24-hour system"
|
||
newline
|
||
bitfld.byte 0xB 0.--2. "CT,Fixed-cycle interrupt (RTC_ALM_OR_PRD) selection" "0: Once per 1 month (Day 1 hour 00 a.m. minute 00..,1: Once per 0.5 s (synchronized with second count up),?,?,?,?,?,?"
|
||
line.byte 0xC "RTCC1,Realtime Clock Control Register 1"
|
||
bitfld.byte 0xC 7. "WALE,Alarm operation control" "0: Match operation is invalid.,1: Match operation is valid."
|
||
bitfld.byte 0xC 6. "WALIE,Control of alarm interrupt (RTC_ALM_OR_PRD)" "0: Does not generate interrupt on matching of alarm.,1: Generates interrupt on matching of alarm."
|
||
newline
|
||
bitfld.byte 0xC 4. "WAFG,Alarm detection status flag" "0: Alarm mismatch,1: Detection of matching of alarm"
|
||
bitfld.byte 0xC 3. "RIFG,Fixed-cycle interrupt status flag" "0: Fixed-cycle interrupt is not generated.,1: Fixed-cycle interrupt is generated."
|
||
newline
|
||
rbitfld.byte 0xC 1. "RWST,Wait status flag of realtime clock" "0: Counting is in progress.,1: Counter values are readable and writable."
|
||
bitfld.byte 0xC 0. "RWAIT,Wait control of realtime clock" "0: Counting proceeds,1: Stops the SEC to YEAR counters. Counter values.."
|
||
tree.end
|
||
tree "SAU (Serial Array Unit)"
|
||
base ad:0x0
|
||
tree "SAU0"
|
||
base ad:0x400A2000
|
||
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
||
group.word ($2)++0x1
|
||
line.word 0x0 "SDR0$1,Serial Data Register 0%s"
|
||
hexmask.word.byte 0x0 9.--15. 1. "STCLK,Transfer Clock Setting by Dividing the Operation Clock"
|
||
hexmask.word 0x0 0.--8. 1. "DAT,Data Buffer for Transmit and Receive"
|
||
repeat.end
|
||
rgroup.word 0x100++0x7
|
||
line.word 0x0 "SSR00,Serial Status Register 00"
|
||
bitfld.word 0x0 6. "TSF,Flag Indicating the State of Communications for Channel n" "0: Communication is stopped or suspended,1: Communication is in progress"
|
||
bitfld.word 0x0 5. "BFF,Flag Indicating the State of the Buffer Register for Channel n" "0: Valid data is not stored in the SDRmn register,1: Valid data is stored in the SDRmn register"
|
||
newline
|
||
bitfld.word 0x0 1. "PEF,Parity or ACK Error Detection Flag of Channel n" "0: No error occurs,1: Parity error occurs (during UART reception) or.."
|
||
bitfld.word 0x0 0. "OVF,Overrun Error Detection Flag of Channel n" "0: No error occurs,1: An error occurs"
|
||
line.word 0x2 "SSR01,Serial Status Register 01"
|
||
bitfld.word 0x2 6. "TSF,Flag Indicating the State of Communications for Channel n" "0: Communication is stopped or suspended,1: Communication is in progress"
|
||
bitfld.word 0x2 5. "BFF,Flag Indicating the State of the Buffer Register for Channel n" "0: Valid data is not stored in the SDRmn register,1: Valid data is stored in the SDRmn register"
|
||
newline
|
||
bitfld.word 0x2 2. "FEF,Framing Error Detection Flag of Channel n" "0: No error occurs,1: An error occurs (during UART reception)"
|
||
bitfld.word 0x2 1. "PEF,Parity or ACK Error Detection Flag of Channel n" "0: No error occurs,1: Parity error occurs (during UART reception) or.."
|
||
newline
|
||
bitfld.word 0x2 0. "OVF,Overrun Error Detection Flag of Channel n" "0: No error occurs,1: An error occurs"
|
||
line.word 0x4 "SSR02,Serial Status Register 02"
|
||
bitfld.word 0x4 6. "TSF,Flag Indicating the State of Communications for Channel n" "0: Communication is stopped or suspended,1: Communication is in progress"
|
||
bitfld.word 0x4 5. "BFF,Flag Indicating the State of the Buffer Register for Channel n" "0: Valid data is not stored in the SDRmn register,1: Valid data is stored in the SDRmn register"
|
||
newline
|
||
bitfld.word 0x4 1. "PEF,Parity or ACK Error Detection Flag of Channel n" "0: No error occurs,1: Parity error occurs (during UART reception) or.."
|
||
bitfld.word 0x4 0. "OVF,Overrun Error Detection Flag of Channel n" "0: No error occurs,1: An error occurs"
|
||
line.word 0x6 "SSR03,Serial Status Register 03"
|
||
bitfld.word 0x6 6. "TSF,Flag Indicating the State of Communications for Channel n" "0: Communication is stopped or suspended,1: Communication is in progress"
|
||
bitfld.word 0x6 5. "BFF,Flag Indicating the State of the Buffer Register for Channel n" "0: Valid data is not stored in the SDRmn register,1: Valid data is stored in the SDRmn register"
|
||
newline
|
||
bitfld.word 0x6 2. "FEF,Framing Error Detection Flag of Channel n" "0: No error occurs,1: An error occurs (during UART reception)"
|
||
bitfld.word 0x6 1. "PEF,Parity or ACK Error Detection Flag of Channel n" "0: No error occurs,1: Parity error occurs (during UART reception) or.."
|
||
newline
|
||
bitfld.word 0x6 0. "OVF,Overrun Error Detection Flag of Channel n" "0: No error occurs,1: An error occurs"
|
||
group.word 0x108++0x17
|
||
line.word 0x0 "SIR00,Serial Flag Clear Trigger Register 00"
|
||
bitfld.word 0x0 1. "PECT,Clear Trigger of Parity Error Flag of Channel n" "0: Not cleared,1: Clears the PEF bit of the SSRmn register to 0."
|
||
bitfld.word 0x0 0. "OVCT,Clear Trigger of Overrun Error Flag of Channel n" "0: Not cleared,1: Clears the OVF bit of the SSRmn register to 0"
|
||
line.word 0x2 "SIR01,Serial Flag Clear Trigger Register 01"
|
||
bitfld.word 0x2 2. "FECT,Clear Trigger of Framing Error Flag of Channel n" "0: Not cleared,1: Clears the FEF bit of the SSRmn register to 0"
|
||
bitfld.word 0x2 1. "PECT,Clear Trigger of Parity Error Flag of Channel n" "0: Not cleared,1: Clears the PEF bit of the SSRmn register to 0"
|
||
newline
|
||
bitfld.word 0x2 0. "OVCT,Clear Trigger of Overrun Error Flag of Channel n" "0: Not cleared,1: Clears the OVF bit of the SSRmn register to 0"
|
||
line.word 0x4 "SIR02,Serial Flag Clear Trigger Register 02"
|
||
bitfld.word 0x4 1. "PECT,Clear Trigger of Parity Error Flag of Channel n" "0: Not cleared,1: Clears the PEF bit of the SSRmn register to 0."
|
||
bitfld.word 0x4 0. "OVCT,Clear Trigger of Overrun Error Flag of Channel n" "0: Not cleared,1: Clears the OVF bit of the SSRmn register to 0"
|
||
line.word 0x6 "SIR03,Serial Flag Clear Trigger Register 03"
|
||
bitfld.word 0x6 2. "FECT,Clear Trigger of Framing Error Flag of Channel n" "0: Not cleared,1: Clears the FEF bit of the SSRmn register to 0"
|
||
bitfld.word 0x6 1. "PECT,Clear Trigger of Parity Error Flag of Channel n" "0: Not cleared,1: Clears the PEF bit of the SSRmn register to 0"
|
||
newline
|
||
bitfld.word 0x6 0. "OVCT,Clear Trigger of Overrun Error Flag of Channel n" "0: Not cleared,1: Clears the OVF bit of the SSRmn register to 0"
|
||
line.word 0x8 "SMR00,Serial Mode Register 00"
|
||
bitfld.word 0x8 15. "CKS,Selection of Operation Clock (fMCK) of Channel n" "0: Operation clock CKm0 set by the SPSm register,1: Operation clock CKm1 set by the SPSm register"
|
||
bitfld.word 0x8 14. "CCS,Selection of Transfer Clock (fTCLK) of Channel n" "0: Divided operation clock fMCK specified by the..,1: Clock input fSCK from the SCKp pin (slave.."
|
||
newline
|
||
bitfld.word 0x8 1.--2. "MD1,Setting of Channel n Operation Mode" "0: Simplified SPI mode,1: UART mode,?,?"
|
||
bitfld.word 0x8 0. "MD0,Selection of Channel n Interrupt Source" "0: Transfer end interrupt,1: Buffer empty interrupt"
|
||
line.word 0xA "SMR01,Serial Mode Register 01"
|
||
bitfld.word 0xA 15. "CKS,Selection of Operation Clock (fMCK) of Channel n" "0: Operation clock CKm0 set by the SPSm register,1: Operation clock CKm1 set by the SPSm register"
|
||
bitfld.word 0xA 14. "CCS,Selection of Transfer Clock (fTCLK) of Channel n" "0: Divided operation clock fMCK specified by the..,1: Clock input fSCK from the SCKp pin (slave.."
|
||
newline
|
||
bitfld.word 0xA 8. "STS,Selection of Start Trigger Source" "0: Only software trigger is valid (selected for..,1: Valid edge of the RxDq pin (selected for UART.."
|
||
bitfld.word 0xA 6. "SIS0,Controls Inversion of Level of Channel n Receive Data in UART Mode" "0: Falling edge is detected as the start bit. The..,1: Rising edge is detected as the start bit. The.."
|
||
newline
|
||
bitfld.word 0xA 1.--2. "MD1,Setting of Channel n Operation Mode" "0: Simplified SPI mode,1: UART mode,?,?"
|
||
bitfld.word 0xA 0. "MD0,Selection of Channel n Interrupt Source" "0: Transfer end interrupt,1: Buffer empty interrupt"
|
||
line.word 0xC "SMR02,Serial Mode Register 02"
|
||
bitfld.word 0xC 15. "CKS,Selection of Operation Clock (fMCK) of Channel n" "0: Operation clock CKm0 set by the SPSm register,1: Operation clock CKm1 set by the SPSm register"
|
||
bitfld.word 0xC 14. "CCS,Selection of Transfer Clock (fTCLK) of Channel n" "0: Divided operation clock fMCK specified by the..,1: Clock input fSCK from the SCKp pin (slave.."
|
||
newline
|
||
bitfld.word 0xC 1.--2. "MD1,Setting of Channel n Operation Mode" "0: Simplified SPI mode,1: UART mode,?,?"
|
||
bitfld.word 0xC 0. "MD0,Selection of Channel n Interrupt Source" "0: Transfer end interrupt,1: Buffer empty interrupt"
|
||
line.word 0xE "SMR03,Serial Mode Register 03"
|
||
bitfld.word 0xE 15. "CKS,Selection of Operation Clock (fMCK) of Channel n" "0: Operation clock CKm0 set by the SPSm register,1: Operation clock CKm1 set by the SPSm register"
|
||
bitfld.word 0xE 14. "CCS,Selection of Transfer Clock (fTCLK) of Channel n" "0: Divided operation clock fMCK specified by the..,1: Clock input fSCK from the SCKp pin (slave.."
|
||
newline
|
||
bitfld.word 0xE 8. "STS,Selection of Start Trigger Source" "0: Only software trigger is valid (selected for..,1: Valid edge of the RxDq pin (selected for UART.."
|
||
bitfld.word 0xE 6. "SIS0,Controls Inversion of Level of Channel n Receive Data in UART Mode" "0: Falling edge is detected as the start bit. The..,1: Rising edge is detected as the start bit. The.."
|
||
newline
|
||
bitfld.word 0xE 1.--2. "MD1,Setting of Channel n Operation Mode" "0: Simplified SPI mode,1: UART mode,?,?"
|
||
bitfld.word 0xE 0. "MD0,Selection of Channel n Interrupt Source" "0: Transfer end interrupt,1: Buffer empty interrupt"
|
||
line.word 0x10 "SCR00,Serial Communication Operation Setting Register 00"
|
||
bitfld.word 0x10 14.--15. "TRXE,Setting of Channel 0 Operation Mode" "0: Disable communication,1: Reception only,?,?"
|
||
bitfld.word 0x10 12.--13. "DCP,Selection of Data and Clock Phase in Simplified SPI Mode" "0: Type1 (SCK: inverted Input timing: rising edge),1: Type2 (SCK: non-inverted Input timing: falling..,?,?"
|
||
newline
|
||
bitfld.word 0x10 8.--9. "PTC,Setting of Parity Bit in UART Mode" "0: Transmission: Does not output the parity bit..,1: Transmission: Outputs 0 parity Reception: No..,?,?"
|
||
bitfld.word 0x10 7. "DIR,Selection of Data Transfer Sequence in Simplified SPI and UART Modes" "0: Inputs or outputs data with MSB first,1: Inputs or outputs data with LSB first"
|
||
newline
|
||
bitfld.word 0x10 4.--5. "SLC,Setting of Stop Bit in UART Mode" "0: No stop bit,1: Stop bit length = 1 bit,?,?"
|
||
bitfld.word 0x10 0.--1. "DLS,Setting of Data Length in Simplified SPI and UART Modes" "0: Setting prohibited,1: 9-bit data length (stored in bits 0 to 8 of the..,?,?"
|
||
line.word 0x12 "SCR01,Serial Communication Operation Setting Register 01"
|
||
bitfld.word 0x12 14.--15. "TRXE,Setting of Channel 1 Operation Mode" "0: Disable communication,1: Reception only,?,?"
|
||
bitfld.word 0x12 12.--13. "DCP,Selection of Data and Clock Phase in Simplified SPI Mode" "0: Type1 (SCK: inverted Input timing: rising edge),1: Type2 (SCK: non-inverted Input timing: falling..,?,?"
|
||
newline
|
||
bitfld.word 0x12 10. "EOC,Mask Control of Error Interrupt Signal SAU0_UART_ERRI0 (m = 0) SAU1_UART_ERRI2 (m = 1)" "0: Disables generation of error interrupt..,1: Enables generation of error interrupt.."
|
||
bitfld.word 0x12 8.--9. "PTC,Setting of Parity Bit in UART Mode" "0: Transmission: Does not output the parity bit..,1: Transmission: Outputs 0 parity Reception: No..,?,?"
|
||
newline
|
||
bitfld.word 0x12 7. "DIR,Selection of Data Transfer Sequence in Simplified SPI and UART Modes" "0: Inputs or outputs data with MSB first,1: Inputs or outputs data with LSB first"
|
||
bitfld.word 0x12 4. "SLC,Setting of Stop Bit in UART Mode" "0: No stop bit,1: Stop bit length = 1 bit"
|
||
newline
|
||
bitfld.word 0x12 0.--1. "DLS,Setting of Data Length in Simplified SPI and UART Modes" "0: Setting prohibited,1: 9-bit data length (stored in bits 0 to 8 of the..,?,?"
|
||
line.word 0x14 "SCR02,Serial Communication Operation Setting Register 02"
|
||
bitfld.word 0x14 14.--15. "TRXE,Setting of Channel 2 Operation Mode" "0: Disables communication,1: Reception only,?,?"
|
||
bitfld.word 0x14 12.--13. "DCP,Selection of Data and Clock Phase in Simplified SPI Mode" "0: Type1 (SCK: inverted Input timing: rising edge),1: Type2 (SCK: non-inverted Input timing: falling..,?,?"
|
||
newline
|
||
bitfld.word 0x14 8.--9. "PTC,Setting of Parity Bit in UART Mode" "0: Transmission: Does not output the parity bit..,1: Transmission: Outputs 0 parity Reception: No..,?,?"
|
||
bitfld.word 0x14 7. "DIR,Selection of Data Transfer Sequence in Simplified SPI and UART Modes" "0: Inputs or outputs data with MSB first,1: Inputs or outputs data with LSB first"
|
||
newline
|
||
bitfld.word 0x14 4.--5. "SLC,Setting of Stop Bit in UART Mode" "0: No stop bit,1: Stop bit length = 1 bit,?,?"
|
||
bitfld.word 0x14 0. "DLS,Setting of Data Length in Simplified SPI and UART Modes" "0: 7-bit data length (stored in bits 0 to 6 of the..,1: 8-bit data length (stored in bits 0 to 7 of the.."
|
||
line.word 0x16 "SCR03,Serial Communication Operation Setting Register 03"
|
||
bitfld.word 0x16 14.--15. "TRXE,Setting of Operation Mode of Channel 3" "0: Disable communication,1: Reception only,?,?"
|
||
bitfld.word 0x16 12.--13. "DCP,Selection of Data and Clock Phase in Simplified SPI Mode" "0: Type1 (SCK: inverted Input timing: rising edge),1: Type2 (SCK: non-inverted Input timing: falling..,?,?"
|
||
newline
|
||
bitfld.word 0x16 10. "EOC,Mask Control of Error Interrupt Signal SAU0_UART_ERRI1" "0: Disables generation of error interrupt..,1: Enables generation of error interrupt.."
|
||
bitfld.word 0x16 8.--9. "PTC,Setting of Parity Bit in UART Mode" "0: Transmission: Does not output the parity bit..,1: Transmission: Outputs 0 parity Reception: No..,?,?"
|
||
newline
|
||
bitfld.word 0x16 7. "DIR,Selection of Data Transfer Sequence in Simplified SPI and UART Modes" "0: Inputs or outputs data with MSB first,1: Inputs or outputs data with LSB first"
|
||
bitfld.word 0x16 4. "SLC,Setting of Stop Bit in UART Mode" "0: No stop bit,1: Stop bit length = 1 bit"
|
||
newline
|
||
bitfld.word 0x16 0. "DLS,Setting of Data Length in Simplified SPI and UART Modes" "0: 7-bit data length (stored in bits 0 to 6 of the..,1: 8-bit data length (stored in bits 0 to 7 of the.."
|
||
rgroup.word 0x120++0x1
|
||
line.word 0x0 "SE0,Serial Channel Enable Status Register 0"
|
||
hexmask.word.byte 0x0 0.--3. 1. "SE,Indication of whether Operation of Channel n is Enabled or Stopped."
|
||
group.word 0x122++0x9
|
||
line.word 0x0 "SS0,Serial Channel Start Register 0"
|
||
hexmask.word.byte 0x0 0.--3. 1. "SS,Operation Start Trigger of Channel n"
|
||
line.word 0x2 "ST0,Serial Channel Stop Register 0"
|
||
hexmask.word.byte 0x2 0.--3. 1. "ST,Operation Stop Trigger of Channel n"
|
||
line.word 0x4 "SPS0,Serial Clock Select Register 0"
|
||
hexmask.word.byte 0x4 4.--7. 1. "PRS1,Selection of Operation Clock (CKm1)"
|
||
hexmask.word.byte 0x4 0.--3. 1. "PRS0,Selection of Operation Clock (CKm0)"
|
||
line.word 0x6 "SO0,Serial Output Register 0"
|
||
hexmask.word.byte 0x6 8.--11. 1. "CKO,Serial Clock Output of Channel n"
|
||
hexmask.word.byte 0x6 0.--3. 1. "SO,Serial Data Output of Channel n"
|
||
line.word 0x8 "SOE0,Serial Output Enable Register 0"
|
||
hexmask.word.byte 0x8 0.--3. 1. "SOE,Serial Output Enable or Stop of Channel n"
|
||
group.word 0x134++0x1
|
||
line.word 0x0 "SOL0,Serial Output Level Register 0"
|
||
bitfld.word 0x0 2. "SOL2,Selects Inversion of the Level of the Transmit Data of Channel 2 in UART Mode" "0: Communication data is output as is,1: Communication data is inverted and output"
|
||
bitfld.word 0x0 0. "SOL0,Selects Inversion of the Level of the Transmit Data of Channel 0 in UART Mode" "0: Communication data is output as is,1: Communication data is inverted and output"
|
||
group.word 0x138++0x1
|
||
line.word 0x0 "SSC0,Serial Standby Control Register 0"
|
||
bitfld.word 0x0 1. "SSEC,Selection of whether to Enable or Disable the Generation of Communication Error Interrupts in the Snooze Mode" "0: Enable the generation of error interrupts..,1: Disable the generation of error interrupts.."
|
||
bitfld.word 0x0 0. "SWC,Setting of the Snooze Mode" "0: Do not use the Snooze mode function,1: Use the Snooze mode function"
|
||
tree.end
|
||
tree "SAU1"
|
||
base ad:0x400A2200
|
||
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
||
group.word ($2)++0x1
|
||
line.word 0x0 "SDR1$1,Serial Data Register 1%s"
|
||
hexmask.word.byte 0x0 9.--15. 1. "STCLK,Transfer Clock Setting by Dividing the Operation Clock"
|
||
hexmask.word 0x0 0.--8. 1. "DAT,Data Buffer for Transmit and Receive"
|
||
repeat.end
|
||
rgroup.word 0x100++0x3
|
||
line.word 0x0 "SSR10,Serial Status Register 10"
|
||
bitfld.word 0x0 6. "TSF,Flag Indicating the State of Communications for Channel n" "0: Communication is stopped or suspended,1: Communication is in progress"
|
||
bitfld.word 0x0 5. "BFF,Flag Indicating the State of the Buffer Register for Channel n" "0: Valid data is not stored in the SDRmn register,1: Valid data is stored in the SDRmn register"
|
||
newline
|
||
bitfld.word 0x0 1. "PEF,Parity or ACK Error Detection Flag of Channel n" "0: No error occurs,1: Parity error occurs (during UART reception) or.."
|
||
bitfld.word 0x0 0. "OVF,Overrun Error Detection Flag of Channel n" "0: No error occurs,1: An error occurs"
|
||
line.word 0x2 "SSR11,Serial Status Register 11"
|
||
bitfld.word 0x2 6. "TSF,Flag Indicating the State of Communications for Channel n" "0: Communication is stopped or suspended,1: Communication is in progress"
|
||
bitfld.word 0x2 5. "BFF,Flag Indicating the State of the Buffer Register for Channel n" "0: Valid data is not stored in the SDRmn register,1: Valid data is stored in the SDRmn register"
|
||
newline
|
||
bitfld.word 0x2 2. "FEF,Framing Error Detection Flag of Channel n" "0: No error occurs,1: An error occurs (during UART reception)"
|
||
bitfld.word 0x2 1. "PEF,Parity or ACK Error Detection Flag of Channel n" "0: No error occurs,1: Parity error occurs (during UART reception) or.."
|
||
newline
|
||
bitfld.word 0x2 0. "OVF,Overrun Error Detection Flag of Channel n" "0: No error occurs,1: An error occurs"
|
||
group.word 0x108++0x3
|
||
line.word 0x0 "SIR10,Serial Flag Clear Trigger Register 10"
|
||
bitfld.word 0x0 1. "PECT,Clear Trigger of Parity Error Flag of Channel n" "0: Not cleared,1: Clears the PEF bit of the SSRmn register to 0."
|
||
bitfld.word 0x0 0. "OVCT,Clear Trigger of Overrun Error Flag of Channel n" "0: Not cleared,1: Clears the OVF bit of the SSRmn register to 0"
|
||
line.word 0x2 "SIR11,Serial Flag Clear Trigger Register 11"
|
||
bitfld.word 0x2 2. "FECT,Clear Trigger of Framing Error Flag of Channel n" "0: Not cleared,1: Clears the FEF bit of the SSRmn register to 0"
|
||
bitfld.word 0x2 1. "PECT,Clear Trigger of Parity Error Flag of Channel n" "0: Not cleared,1: Clears the PEF bit of the SSRmn register to 0"
|
||
newline
|
||
bitfld.word 0x2 0. "OVCT,Clear Trigger of Overrun Error Flag of Channel n" "0: Not cleared,1: Clears the OVF bit of the SSRmn register to 0"
|
||
group.word 0x110++0x3
|
||
line.word 0x0 "SMR10,Serial Mode Register 10"
|
||
bitfld.word 0x0 15. "CKS,Selection of Operation Clock (fMCK) of Channel n" "0: Operation clock CKm0 set by the SPSm register,1: Operation clock CKm1 set by the SPSm register"
|
||
bitfld.word 0x0 14. "CCS,Selection of Transfer Clock (fTCLK) of Channel n" "0: Divided operation clock fMCK specified by the..,1: Clock input fSCK from the SCKp pin (slave.."
|
||
newline
|
||
bitfld.word 0x0 1.--2. "MD1,Setting of Channel n Operation Mode" "0: Simplified SPI mode,1: UART mode,?,?"
|
||
bitfld.word 0x0 0. "MD0,Selection of Channel n Interrupt Source" "0: Transfer end interrupt,1: Buffer empty interrupt"
|
||
line.word 0x2 "SMR11,Serial Mode Register 11"
|
||
bitfld.word 0x2 15. "CKS,Selection of Operation Clock (fMCK) of Channel n" "0: Operation clock CKm0 set by the SPSm register,1: Operation clock CKm1 set by the SPSm register"
|
||
bitfld.word 0x2 14. "CCS,Selection of Transfer Clock (fTCLK) of Channel n" "0: Divided operation clock fMCK specified by the..,1: Clock input fSCK from the SCKp pin (slave.."
|
||
newline
|
||
bitfld.word 0x2 8. "STS,Selection of Start Trigger Source" "0: Only software trigger is valid (selected for..,1: Valid edge of the RxDq pin (selected for UART.."
|
||
bitfld.word 0x2 6. "SIS0,Controls Inversion of Level of Channel n Receive Data in UART Mode" "0: Falling edge is detected as the start bit. The..,1: Rising edge is detected as the start bit. The.."
|
||
newline
|
||
bitfld.word 0x2 1.--2. "MD1,Setting of Channel n Operation Mode" "0: Simplified SPI mode,1: UART mode,?,?"
|
||
bitfld.word 0x2 0. "MD0,Selection of Channel n Interrupt Source" "0: Transfer end interrupt,1: Buffer empty interrupt"
|
||
group.word 0x118++0x3
|
||
line.word 0x0 "SCR10,Serial Communication Operation Setting Register 10"
|
||
bitfld.word 0x0 14.--15. "TRXE,Setting of Channel 0 Operation Mode" "0: Disable communication,1: Reception only,?,?"
|
||
bitfld.word 0x0 12.--13. "DCP,Selection of Data and Clock Phase in Simplified SPI Mode" "0: Type1 (SCK: inverted Input timing: rising edge),1: Type2 (SCK: non-inverted Input timing: falling..,?,?"
|
||
newline
|
||
bitfld.word 0x0 8.--9. "PTC,Setting of Parity Bit in UART Mode" "0: Transmission: Does not output the parity bit..,1: Transmission: Outputs 0 parity Reception: No..,?,?"
|
||
bitfld.word 0x0 7. "DIR,Selection of Data Transfer Sequence in Simplified SPI and UART Modes" "0: Inputs or outputs data with MSB first,1: Inputs or outputs data with LSB first"
|
||
newline
|
||
bitfld.word 0x0 4.--5. "SLC,Setting of Stop Bit in UART Mode" "0: No stop bit,1: Stop bit length = 1 bit,?,?"
|
||
bitfld.word 0x0 0.--1. "DLS,Setting of Data Length in Simplified SPI and UART Modes" "0: Setting prohibited,1: 9-bit data length (stored in bits 0 to 8 of the..,?,?"
|
||
line.word 0x2 "SCR11,Serial Communication Operation Setting Register 11"
|
||
bitfld.word 0x2 14.--15. "TRXE,Setting of Channel 1 Operation Mode" "0: Disable communication,1: Reception only,?,?"
|
||
bitfld.word 0x2 12.--13. "DCP,Selection of Data and Clock Phase in Simplified SPI Mode" "0: Type1 (SCK: inverted Input timing: rising edge),1: Type2 (SCK: non-inverted Input timing: falling..,?,?"
|
||
newline
|
||
bitfld.word 0x2 10. "EOC,Mask Control of Error Interrupt Signal SAU0_UART_ERRI0 (m = 0) SAU1_UART_ERRI2 (m = 1)" "0: Disables generation of error interrupt..,1: Enables generation of error interrupt.."
|
||
bitfld.word 0x2 8.--9. "PTC,Setting of Parity Bit in UART Mode" "0: Transmission: Does not output the parity bit..,1: Transmission: Outputs 0 parity Reception: No..,?,?"
|
||
newline
|
||
bitfld.word 0x2 7. "DIR,Selection of Data Transfer Sequence in Simplified SPI and UART Modes" "0: Inputs or outputs data with MSB first,1: Inputs or outputs data with LSB first"
|
||
bitfld.word 0x2 4. "SLC,Setting of Stop Bit in UART Mode" "0: No stop bit,1: Stop bit length = 1 bit"
|
||
newline
|
||
bitfld.word 0x2 0.--1. "DLS,Setting of Data Length in Simplified SPI and UART Modes" "0: Setting prohibited,1: 9-bit data length (stored in bits 0 to 8 of the..,?,?"
|
||
rgroup.word 0x120++0x1
|
||
line.word 0x0 "SE1,Serial Channel Enable Status Register 1"
|
||
bitfld.word 0x0 0.--1. "SE,Indication of whether Operation of Channel n is Enabled or Stopped." "0: Operation stops,1: Operation is enabled,?,?"
|
||
group.word 0x122++0x9
|
||
line.word 0x0 "SS1,Serial Channel Start Register 1"
|
||
bitfld.word 0x0 0.--1. "SS,Operation Start Trigger of Channel n" "0: No trigger operation,1: Set the SE1.SE[n] bit to 1 to place the channel..,?,?"
|
||
line.word 0x2 "ST1,Serial Channel Stop Register 1"
|
||
bitfld.word 0x2 0.--1. "ST,Operation Stop Trigger of Channel n" "0: No trigger operation,1: Clears the SE1.SE[n] bit to 0 and stops the..,?,?"
|
||
line.word 0x4 "SPS1,Serial Clock Select Register 1"
|
||
hexmask.word.byte 0x4 4.--7. 1. "PRS1,Selection of Operation Clock (CKm1)"
|
||
hexmask.word.byte 0x4 0.--3. 1. "PRS0,Selection of Operation Clock (CKm0)"
|
||
line.word 0x6 "SO1,Serial Output Register 1"
|
||
bitfld.word 0x6 8.--9. "CKO,Serial Clock Output of Channel n" "0: Serial clock output value is 0,1: Serial clock output value is 1,?,?"
|
||
bitfld.word 0x6 0.--1. "SO,Serial Data Output of Channel n" "0: Serial data output value is 0,1: Serial data output value is 1,?,?"
|
||
line.word 0x8 "SOE1,Serial Output Enable Register 1"
|
||
bitfld.word 0x8 0.--1. "SOE,Serial Output Enable or Stop of Channel n" "0: Stops output by serial communication operation,1: Enables output by serial communication operation,?,?"
|
||
group.word 0x134++0x1
|
||
line.word 0x0 "SOL1,Serial Output Level Register 1"
|
||
bitfld.word 0x0 0. "SOL0,Selects Inversion of the Level of the Transmit Data of Channel 0 in UART Mode" "0: Communication data is output as is,1: Communication data is inverted and output"
|
||
tree.end
|
||
tree.end
|
||
tree "SRAM (SRAM Control)"
|
||
base ad:0x40002000
|
||
group.byte 0x0++0x0
|
||
line.byte 0x0 "PARIOAD,SRAM Parity Error Operation After Detection Register"
|
||
bitfld.byte 0x0 0. "OAD,Operation After Detection" "0: Non-maskable interrupt,1: Reset"
|
||
group.byte 0x4++0x0
|
||
line.byte 0x0 "SRAMPRCR,SRAM Protection Register"
|
||
hexmask.byte 0x0 1.--7. 1. "KW,Write Key Code"
|
||
bitfld.byte 0x0 0. "SRAMPRCR,Register Write Control" "0: Disable writes to protected registers,1: Enable writes to protected registers"
|
||
tree.end
|
||
tree "SYSC (System Control)"
|
||
base ad:0x4001E000
|
||
group.byte 0x800++0x0
|
||
line.byte 0x0 "CMC,Clock Operation Mode Control Register"
|
||
bitfld.byte 0x0 6.--7. "MOSEL,Main Clock Oscillator Switching" "0: Port mode,1: Resonator,?,?"
|
||
bitfld.byte 0x0 4. "SOSEL,Sub Clock Oscillator Switching" "0: Input port mode,1: Resonator"
|
||
newline
|
||
bitfld.byte 0x0 3. "XTSEL,Selecting Clock Oscillator" "0: Select MOSEL Contents,1: Select SOSEL Contents"
|
||
bitfld.byte 0x0 1.--2. "SODRV,Sub-Clock Oscillator Drive Capability Switching" "0: Low Power Mode 1,1: Normal Mode,?,?"
|
||
newline
|
||
bitfld.byte 0x0 0. "MODRV,Main Clock Oscillator Drive Capability Switching" "0: 1 MHz to 10 MHz,1: 10 MHz to 20 MHz"
|
||
group.byte 0x803++0x2
|
||
line.byte 0x0 "SOMRG,Sub-clock Oscillator Margin Check Register"
|
||
bitfld.byte 0x0 0.--1. "SOSCMRG,Sub Clock Oscillator Margin Check Switching" "0: Normal Current,1: Lower Margin check,?,?"
|
||
line.byte 0x1 "MIOTRM,Middle-speed On-chip Oscillator Trimming Register"
|
||
hexmask.byte 0x1 0.--7. 1. "MIOTRM,MOCO User Trimming"
|
||
line.byte 0x2 "LIOTRM,Low-speed On-chip Oscillator Trimming Register"
|
||
hexmask.byte 0x2 0.--7. 1. "LIOTRM,LOCO User Trimming"
|
||
group.byte 0x808++0x4
|
||
line.byte 0x0 "HOCOCR,High-speed On-chip Oscillator Control Register"
|
||
bitfld.byte 0x0 0. "HCSTP,HOCO Stop" "0: Operate the HOCO clock,1: Stop the HOCO clock"
|
||
line.byte 0x1 "MOCOCR,Middle-speed On-chip Oscillator Control Register"
|
||
bitfld.byte 0x1 0. "MCSTP,MOCO Stop" "0: MOCO clock is operating,1: MOCO clock is stopped"
|
||
line.byte 0x2 "LOCOCR,Low-speed On-chip Oscillator Control Register"
|
||
bitfld.byte 0x2 0. "LCSTP,LOCO Stop" "0: Operate the LOCO clock,1: Stop the LOCO clock"
|
||
line.byte 0x3 "MOSCCR,Main Clock Oscillator Control Register"
|
||
bitfld.byte 0x3 0. "MOSTP,Main Clock Oscillator Stop" "0: Operate the main clock oscillator,1: Stop the main clock oscillator"
|
||
line.byte 0x4 "SOSCCR,Sub-clock Oscillator Control Register"
|
||
bitfld.byte 0x4 0. "SOSTP,Sub Clock Oscillator Stop" "0: Operate the sub-clock oscillator,1: Stop the sub-clock oscillator"
|
||
rgroup.byte 0x810++0x0
|
||
line.byte 0x0 "OSTC,Oscillation Stabilization Time Counter Status Register"
|
||
hexmask.byte 0x0 0.--7. 1. "MOST,Selection of the Oscillation Stabilization Time"
|
||
group.byte 0x811++0x0
|
||
line.byte 0x0 "OSTS,Oscillation Stabilization Time Select Register"
|
||
bitfld.byte 0x0 0.--2. "OSTSB,Selection of the Oscillation Stabilization Time" "0: 28/fMOSC,1: 29/fMOSC,?,?,?,?,?,?"
|
||
rgroup.byte 0x812++0x0
|
||
line.byte 0x0 "OSCSF,Oscillation Stabilization Flag Register"
|
||
bitfld.byte 0x0 0. "HOCOSF,HOCO Clock Oscillation Stabilization Flag" "0: The HOCO clock is being started at high speed..,1: The HOCO clock is operating with high precision."
|
||
group.byte 0x818++0x2
|
||
line.byte 0x0 "HOCODIV,High-speed On-chip Oscillator Frequency Select Register"
|
||
bitfld.byte 0x0 0.--2. "DIV,High-speed On-chip Oscillator Clock Division Ratio" "0: Setting prohibited,1: × 1/2,?,?,?,?,?,?"
|
||
line.byte 0x1 "MOCODIV,Middle-speed On-chip Oscillator Frequency Select Register"
|
||
bitfld.byte 0x1 0.--1. "DIV,Selection of the Middle-speed On-chip Oscillator Clock Frequency" "0: Setting prohibited,1: × 1/2,?,?"
|
||
line.byte 0x2 "MOSCDIV,Main System Clock Division Register"
|
||
bitfld.byte 0x2 0.--2. "DIV,Selection Division Ratio for the Main System Clock" "0: Setting prohibited,1: × 1/2,?,?,?,?,?,?"
|
||
group.byte 0x820++0x4
|
||
line.byte 0x0 "FOCOSCR,FOCO Clock Source Control Register"
|
||
rbitfld.byte 0x0 1. "CKST,FOCO Clock Source Status" "0: HOCO,1: MOCO"
|
||
bitfld.byte 0x0 0. "CKSEL,FOCO Clock Source Select" "0: HOCO,1: MOCO"
|
||
line.byte 0x1 "FMAINSCR,FMAIN Clock Source Control Register"
|
||
rbitfld.byte 0x1 1. "CKST,FMAIN Clock Source Status" "0: FOCO,1: MOSC"
|
||
bitfld.byte 0x1 0. "CKSEL,FMAIN Clock Source Select" "0: FOCO,1: MOSC"
|
||
line.byte 0x2 "FSUBSCR,FSUB Clock Source Control Register"
|
||
bitfld.byte 0x2 0. "CKSEL,FSUB Clock Source Select" "0: SOSC,1: LOCO"
|
||
line.byte 0x3 "ICLKSCR,ICLK Clock Source Control Register"
|
||
rbitfld.byte 0x3 1. "CKST,ICLK Clock Source Status" "0: FMAIN,1: FSUB"
|
||
bitfld.byte 0x3 0. "CKSEL,ICLK Clock Source Select" "0: FMAIN,1: FSUB"
|
||
line.byte 0x4 "OSMC,Subsystem Clock Supply Mode Control Register"
|
||
bitfld.byte 0x4 4. "WUTMMCK0,Selection of the Operating Clock for the Realtime Clock 32-bit Interval Timer Serial Interfaces UARTA0" "0: SOSC,1: LOCO"
|
||
rgroup.byte 0x830++0x0
|
||
line.byte 0x0 "RESF,Reset Control Flag Register"
|
||
bitfld.byte 0x0 5. "SWRF,Internal Reset Request by Software Reset" "0: Internal reset request is not generated or the..,1: Internal reset request is generated."
|
||
bitfld.byte 0x0 4. "IWDTRF,Internal Reset Request by Independent Watchdog Timer (IWDT)" "0: Internal reset request is not generated or the..,1: Internal reset request is generated."
|
||
newline
|
||
bitfld.byte 0x0 2. "RPERF,Internal Reset Request by RAM Parity Error" "0: Internal reset request is not generated or the..,1: Internal reset request is generated."
|
||
bitfld.byte 0x0 0. "LVIRF,Internal Reset Request by Voltage Detector (LVD0 or LVD1)" "0: Internal reset request is not generated or the..,1: Internal reset request is generated."
|
||
group.byte 0x831++0x0
|
||
line.byte 0x0 "PORSR,Power-On Reset Status Register"
|
||
bitfld.byte 0x0 0. "PORF,Checking Occurrence of Power-on Reset" "0: A value 1 has not been written or a power-on..,1: No power-on reset has occurred."
|
||
group.byte 0x840++0x1
|
||
line.byte 0x0 "LVD1CR,Voltage Monitor 1 Circuit Control Register"
|
||
bitfld.byte 0x0 7. "LVD1EN,Enabling Operation of LVD1" "0: Operation stopped,1: Operation enabled"
|
||
bitfld.byte 0x0 6. "LVD1SEL,Operation mode of LVD1" "0: Interrupt mode,1: Reset mode"
|
||
newline
|
||
bitfld.byte 0x0 5. "IRQSEL,Voltage Monitor 1 Interrupt Type Select" "0: Non-maskable interrupt,1: Maskable interrupt"
|
||
hexmask.byte 0x0 0.--4. 1. "LVD1V,Voltage Detection 1 Level Select"
|
||
line.byte 0x1 "LVD1MKR,Voltage Monitor 1 Circuit Mask Register"
|
||
bitfld.byte 0x1 0. "MK,Specification of Whether to Enable or Disable Rewriting th LVD1CR Register" "0: Rewriting of the LVD1CR register is disabled.,1: Rewriting of the LVD1CR register is enabled.."
|
||
group.byte 0x843++0x0
|
||
line.byte 0x0 "LVD1SR,Voltage Monitor 1 Circuit Status Register"
|
||
rbitfld.byte 0x0 1. "MON,Voltage Monitor 1 Signal Monitor Flag" "0: VCC < Vdet1,1: VCC ≥ Vdet1 or MON is disabled"
|
||
bitfld.byte 0x0 0. "DET,Voltage Monitor 1 Voltage Variation Detection Flag" "0: Not detected,1: Vdet1 crossing is detected"
|
||
group.word 0x860++0x1
|
||
line.word 0x0 "SBYCR,Standby Control Register"
|
||
bitfld.word 0x0 15. "SSBY,Software Standby Mode Select" "0: Sleep mode,1: Software Standby mode."
|
||
bitfld.word 0x0 9. "RTCLPC,SOSC Setting in Software Standby Mode or in Snooze Mode" "0: Enables supply of SOSC clock to peripheral..,1: Stops supply SOSC clock to peripheral functions.."
|
||
newline
|
||
bitfld.word 0x0 8. "FWKUP,Setting for Starting the High-speed On-chip Oscillator at the Times of Release from Software Standby Mode and of Transitions to Snooze Mode" "0: Starting of the high-speed on-chip oscillator is..,1: Starting of the high-speed on-chip oscillator is.."
|
||
bitfld.word 0x0 7. "FLSTP,Flash Mode in Sleep Mode or in Snooze Mode" "0: Flash active,1: Flash stop"
|
||
group.byte 0x862++0x1
|
||
line.byte 0x0 "PSMCR,Power Save Memory Control Register"
|
||
bitfld.byte 0x0 0.--1. "RAMSD,Operating Mode of the RAM" "0: Normal mode (continues to operate),1: Setting prohibited,?,?"
|
||
line.byte 0x1 "SYOCDCR,System Control OCD Control Register"
|
||
bitfld.byte 0x1 7. "DBGEN,Debugger Enable bit" "0: On-chip debugger is disabled,1: On-chip debugger is enabled"
|
||
group.word 0x8FE++0x1
|
||
line.word 0x0 "PRCR,Protect Register"
|
||
hexmask.word.byte 0x0 8.--15. 1. "PRKEY,PRC Key Code"
|
||
bitfld.word 0x0 3. "PRC3,Enable writing to the registers related to the LVD" "0: Disable writes,1: Enable writes"
|
||
newline
|
||
bitfld.word 0x0 1. "PRC1,Enable writing to the registers related to the low power modes" "0: Disable writes,1: Enable writes"
|
||
bitfld.word 0x0 0. "PRC0,Enable writing to the registers related to the clock generation circuit" "0: Disable writes,1: Enable writes"
|
||
group.word 0xC02++0x1
|
||
line.word 0x0 "MSTPCRA,Module Stop Control Register A"
|
||
bitfld.word 0x0 6. "MSTPA22,DTC Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state"
|
||
group.byte 0xC04++0x0
|
||
line.byte 0x0 "LPOPT,Lower Power Operation Control Register"
|
||
bitfld.byte 0x0 7. "LPOPTEN,Lower Power Operation Enable" "0: All lower power counter measure disable,1: All lower power counter measure enable"
|
||
bitfld.byte 0x0 3. "BPFCLKDIS,BPF Clock Disable Control" "0: Flash register R/W clock operates as normal,1: Flash register R/W clock stops."
|
||
newline
|
||
bitfld.byte 0x0 1.--2. "DCLKDIS,Debug Clock Disable Control" "0: Debug clock stops (valid only when LPOPT.LPOPTEN..,?,?,?"
|
||
tree.end
|
||
tree "TAU (Timer Array Unit)"
|
||
base ad:0x400A2600
|
||
group.word 0x0++0x3
|
||
line.word 0x0 "TDR00,Timer Data Register 00"
|
||
line.word 0x2 "TDR01,Timer Data Register 01"
|
||
group.byte 0x2++0x1
|
||
line.byte 0x0 "TDR01L,Timer Data Register 01"
|
||
line.byte 0x1 "TDR01H,Timer Data Register 01"
|
||
group.word 0x4++0x3
|
||
line.word 0x0 "TDR02,Timer Data Register 02"
|
||
line.word 0x2 "TDR03,Timer Data Register 03"
|
||
group.byte 0x6++0x1
|
||
line.byte 0x0 "TDR03L,Timer Data Register 03"
|
||
line.byte 0x1 "TDR03H,Timer Data Register 03"
|
||
group.word 0x8++0x7
|
||
line.word 0x0 "TDR04,Timer Data Register 04"
|
||
line.word 0x2 "TDR05,Timer Data Register 05"
|
||
line.word 0x4 "TDR06,Timer Data Register 06"
|
||
line.word 0x6 "TDR07,Timer Data Register 07"
|
||
repeat 8. (increment 0x0 0x1)(increment 0x0 0x2)
|
||
rgroup.word ($2+0x100)++0x1
|
||
line.word 0x0 "TCR0$1,Timer Counter Register 0%s"
|
||
repeat.end
|
||
group.word 0x110++0xF
|
||
line.word 0x0 "TMR00,Timer Mode Register 00"
|
||
bitfld.word 0x0 14.--15. "CKS,Selection of Operation Clock (fMCK) of Channel n" "0: Operation clock CK00 set by timer clock select..,1: Operation clock CK02 set by timer clock select..,?,?"
|
||
bitfld.word 0x0 12. "CCS,Selection of Counter Clock (fTCLK) of Channel n" "0: Operating clock (fMCK)specified by the CKS[1:0]..,1: Valid edge of input signal input from the TI0n.."
|
||
newline
|
||
bitfld.word 0x0 8.--10. "STS,Setting of Start Trigger or Capture Trigger of Channel n" "0: Setting prohibited,1: Valid edge of the TI0n pin input is used as both..,?,?,?,?,?,?"
|
||
bitfld.word 0x0 6.--7. "CIS,Selection of TI0n Pin Input Valid Edge" "0: Falling edge,1: Rising edge,?,?"
|
||
newline
|
||
bitfld.word 0x0 1.--3. "MD,Selection of Operation Mode at Channel n" "0: Setting prohibited,?,?,?,?,?,?,?"
|
||
bitfld.word 0x0 0. "OPIRQ,Setting of Starting Count and Interrupt" "0,1"
|
||
line.word 0x2 "TMR01,Timer Mode Register 01"
|
||
bitfld.word 0x2 14.--15. "CKS,Selection of Operation Clock (fMCK) of Channel n" "0: Operation clock CK00 set by timer clock select..,1: Operation clock CK02 set by timer clock select..,?,?"
|
||
bitfld.word 0x2 12. "CCS,Selection of Counter Clock (fTCLK) of Channel n" "0: Operating clock (fMCK) specified by the CKS[1:0]..,1: Valid edge of input signal input from the Ti0n.."
|
||
newline
|
||
bitfld.word 0x2 11. "SPLIT,Selection of 8 or 16-bit Timer Operation for Channels 1 and 3" "0: Operates as 16-bit timer (Operates in..,1: Operates as 8-bit timer"
|
||
bitfld.word 0x2 8.--10. "STS,Setting of Start Trigger or Capture Trigger of Channel n" "0: Setting prohibited,1: Valid edge of the Ti0n pin input is used as both..,?,?,?,?,?,?"
|
||
newline
|
||
bitfld.word 0x2 6.--7. "CIS,Selection of TI0n Pin Input Valid Edge" "0: Falling edge,1: Rising edge,?,?"
|
||
bitfld.word 0x2 1.--3. "MD,Selection of Operation Mode at Channel n" "0: Setting prohibited,?,?,?,?,?,?,?"
|
||
newline
|
||
bitfld.word 0x2 0. "OPIRQ,Setting of Starting Count and Interrupt" "0,1"
|
||
line.word 0x4 "TMR02,Timer Mode Register 02"
|
||
bitfld.word 0x4 14.--15. "CKS,Selection of Operation Clock (fMCK) of Channel n" "0: Operation clock CK00 set by timer clock select..,1: Operation clock CK02 set by timer clock select..,?,?"
|
||
bitfld.word 0x4 12. "CCS,Selection of Counter Clock (fTCLK) of Channel n" "0: Operating clock (fMCK)specified by the CKS[1:0]..,1: Valid edge of input signal input from the TI0n.."
|
||
newline
|
||
bitfld.word 0x4 11. "MASTER,Selection Between Using Channel n Independently or Simultaneously with Another Channel (as a Slave or Master)" "0: Operates in independent channel operation..,1: Operates as master channel in simultaneous.."
|
||
bitfld.word 0x4 8.--10. "STS,Setting of Start Trigger or Capture Trigger of Channel n" "0: Setting prohibited,1: Valid edge of the TI0n pin input is used as both..,?,?,?,?,?,?"
|
||
newline
|
||
bitfld.word 0x4 6.--7. "CIS,Selection of TI0n Pin Input Valid Edge" "0: Falling edge,1: Rising edge,?,?"
|
||
bitfld.word 0x4 1.--3. "MD,Selection of Operation Mode at Channel n" "0: Setting prohibited,?,?,?,?,?,?,?"
|
||
newline
|
||
bitfld.word 0x4 0. "OPIRQ,Setting of Starting Count and Interrupt" "0,1"
|
||
line.word 0x6 "TMR03,Timer Mode Register 03"
|
||
bitfld.word 0x6 14.--15. "CKS,Selection of Operation Clock (fMCK) of Channel n" "0: Operation clock CK00 set by timer clock select..,1: Operation clock CK02 set by timer clock select..,?,?"
|
||
bitfld.word 0x6 12. "CCS,Selection of Counter Clock (fTCLK) of Channel n" "0: Operating clock (fMCK) specified by the CKS[1:0]..,1: Valid edge of input signal input from the Ti0n.."
|
||
newline
|
||
bitfld.word 0x6 11. "SPLIT,Selection of 8 or 16-bit Timer Operation for Channels 1 and 3" "0: Operates as 16-bit timer (Operates in..,1: Operates as 8-bit timer"
|
||
bitfld.word 0x6 8.--10. "STS,Setting of Start Trigger or Capture Trigger of Channel n" "0: Setting prohibited,1: Valid edge of the Ti0n pin input is used as both..,?,?,?,?,?,?"
|
||
newline
|
||
bitfld.word 0x6 6.--7. "CIS,Selection of TI0n Pin Input Valid Edge" "0: Falling edge,1: Rising edge,?,?"
|
||
bitfld.word 0x6 1.--3. "MD,Selection of Operation Mode at Channel n" "0: Setting prohibited,?,?,?,?,?,?,?"
|
||
newline
|
||
bitfld.word 0x6 0. "OPIRQ,Setting of Starting Count and Interrupt" "0,1"
|
||
line.word 0x8 "TMR04,Timer Mode Register 04"
|
||
bitfld.word 0x8 14.--15. "CKS,Selection of Operation Clock (fMCK) of Channel n" "0: Operation clock CK00 set by timer clock select..,1: Operation clock CK02 set by timer clock select..,?,?"
|
||
bitfld.word 0x8 12. "CCS,Selection of Counter Clock (fTCLK) of Channel n" "0: Operating clock (fMCK)specified by the CKS[1:0]..,1: Valid edge of input signal input from the TI0n.."
|
||
newline
|
||
bitfld.word 0x8 11. "MASTER,Selection Between Using Channel n Independently or Simultaneously with Another Channel (as a Slave or Master)" "0: Operates in independent channel operation..,1: Operates as master channel in simultaneous.."
|
||
bitfld.word 0x8 8.--10. "STS,Setting of Start Trigger or Capture Trigger of Channel n" "0: Setting prohibited,1: Valid edge of the TI0n pin input is used as both..,?,?,?,?,?,?"
|
||
newline
|
||
bitfld.word 0x8 6.--7. "CIS,Selection of TI0n Pin Input Valid Edge" "0: Falling edge,1: Rising edge,?,?"
|
||
bitfld.word 0x8 1.--3. "MD,Selection of Operation Mode at Channel n" "0: Setting prohibited,?,?,?,?,?,?,?"
|
||
newline
|
||
bitfld.word 0x8 0. "OPIRQ,Setting of Starting Count and Interrupt" "0,1"
|
||
line.word 0xA "TMR05,Timer Mode Register 05"
|
||
bitfld.word 0xA 14.--15. "CKS,Selection of Operation Clock (fMCK) of Channel n" "0: Operation clock CK00 set by timer clock select..,1: Operation clock CK02 set by timer clock select..,?,?"
|
||
bitfld.word 0xA 12. "CCS,Selection of Counter Clock (fTCLK) of Channel n" "0: Operating clock (fMCK)specified by the CKS[1:0]..,1: Valid edge of input signal input from the TI0n.."
|
||
newline
|
||
bitfld.word 0xA 8.--10. "STS,Setting of Start Trigger or Capture Trigger of Channel n" "0: Setting prohibited,1: Valid edge of the TI0n pin input is used as both..,?,?,?,?,?,?"
|
||
bitfld.word 0xA 6.--7. "CIS,Selection of TI0n Pin Input Valid Edge" "0: Falling edge,1: Rising edge,?,?"
|
||
newline
|
||
bitfld.word 0xA 1.--3. "MD,Selection of Operation Mode at Channel n" "0: Setting prohibited,?,?,?,?,?,?,?"
|
||
bitfld.word 0xA 0. "OPIRQ,Setting of Starting Count and Interrupt" "0,1"
|
||
line.word 0xC "TMR06,Timer Mode Register 06"
|
||
bitfld.word 0xC 14.--15. "CKS,Selection of Operation Clock (fMCK) of Channel n" "0: Operation clock CK00 set by timer clock select..,1: Operation clock CK02 set by timer clock select..,?,?"
|
||
bitfld.word 0xC 12. "CCS,Selection of Counter Clock (fTCLK) of Channel n" "0: Operating clock (fMCK)specified by the CKS[1:0]..,1: Valid edge of input signal input from the TI0n.."
|
||
newline
|
||
bitfld.word 0xC 11. "MASTER,Selection Between Using Channel n Independently or Simultaneously with Another Channel (as a Slave or Master)" "0: Operates in independent channel operation..,1: Operates as master channel in simultaneous.."
|
||
bitfld.word 0xC 8.--10. "STS,Setting of Start Trigger or Capture Trigger of Channel n" "0: Setting prohibited,1: Valid edge of the TI0n pin input is used as both..,?,?,?,?,?,?"
|
||
newline
|
||
bitfld.word 0xC 6.--7. "CIS,Selection of TI0n Pin Input Valid Edge" "0: Falling edge,1: Rising edge,?,?"
|
||
bitfld.word 0xC 1.--3. "MD,Selection of Operation Mode at Channel n" "0: Setting prohibited,?,?,?,?,?,?,?"
|
||
newline
|
||
bitfld.word 0xC 0. "OPIRQ,Setting of Starting Count and Interrupt" "0,1"
|
||
line.word 0xE "TMR07,Timer Mode Register 07"
|
||
bitfld.word 0xE 14.--15. "CKS,Selection of Operation Clock (fMCK) of Channel n" "0: Operation clock CK00 set by timer clock select..,1: Operation clock CK02 set by timer clock select..,?,?"
|
||
bitfld.word 0xE 12. "CCS,Selection of Counter Clock (fTCLK) of Channel n" "0: Operating clock (fMCK)specified by the CKS[1:0]..,1: Valid edge of input signal input from the TI0n.."
|
||
newline
|
||
bitfld.word 0xE 8.--10. "STS,Setting of Start Trigger or Capture Trigger of Channel n" "0: Setting prohibited,1: Valid edge of the TI0n pin input is used as both..,?,?,?,?,?,?"
|
||
bitfld.word 0xE 6.--7. "CIS,Selection of TI0n Pin Input Valid Edge" "0: Falling edge,1: Rising edge,?,?"
|
||
newline
|
||
bitfld.word 0xE 1.--3. "MD,Selection of Operation Mode at Channel n" "0: Setting prohibited,?,?,?,?,?,?,?"
|
||
bitfld.word 0xE 0. "OPIRQ,Setting of Starting Count and Interrupt" "0,1"
|
||
repeat 8. (increment 0x0 0x1)(increment 0x0 0x2)
|
||
rgroup.word ($2+0x120)++0x1
|
||
line.word 0x0 "TSR0$1,Timer Status Register 0%s"
|
||
bitfld.word 0x0 0. "OVF,Counter Overflow State of Channel n" "0: Overflow does not occur,1: Overflow occurs"
|
||
repeat.end
|
||
rgroup.word 0x130++0x1
|
||
line.word 0x0 "TE0,Timer Channel Enable Status Register 0"
|
||
bitfld.word 0x0 11. "TEH3,Indication of whether Operation of the Higher 8-bit Timer is Enabled or Stopped when Channel 3 is in the 8-bit Timer Mode" "0: Operation is stopped,1: Operation is enabled"
|
||
bitfld.word 0x0 9. "TEH1,Indication of whether Operation of the Higher 8-bit Timer is Enabled or Stopped when Channel 1 is in the 8-bit Timer Mode" "0: Operation is stopped,1: Operation is enabled"
|
||
newline
|
||
hexmask.word.byte 0x0 0.--7. 1. "TE,Indication of Operation Enabled or Stopped State of Channel n"
|
||
group.word 0x132++0xD
|
||
line.word 0x0 "TS0,Timer Channel Start Register 0"
|
||
bitfld.word 0x0 11. "TSH3,Trigger to Enable Operation (Start Operation) of the Higher 8-bit Timer when Channel 3 is in the 8-bit Timer Mode" "0: No trigger operation,1: The TE0.TEH3 bit is set to 1 and the count.."
|
||
bitfld.word 0x0 9. "TSH1,Trigger to Enable Operation (Start Operation) of the Higher 8-bit Timer when Channel 1 is in the 8-bit Timer Mode" "0: No trigger operation,1: The TE0.TEH1 bit is set to 1 and the count.."
|
||
newline
|
||
hexmask.word.byte 0x0 0.--7. 1. "TS,Operation Enable (Start) Trigger of Channel n"
|
||
line.word 0x2 "TT0,Timer Channel Stop Register 0"
|
||
bitfld.word 0x2 11. "TTH3,Trigger to Stop Operation of the Higher 8-bit Timer when Channel 3 is in the 8-bit Timer Mode" "0: No trigger operation,1: The TE0.TEH3 bit is cleared to 0 and the count.."
|
||
bitfld.word 0x2 9. "TTH1,Trigger to Stop Operation of the Higher 8-bit Timer when Channel 1 is in the 8-bit Timer Mode" "0: No trigger operation,1: The TE0.TEH1 bit is cleared to 0 and the count.."
|
||
newline
|
||
hexmask.word.byte 0x2 0.--7. 1. "TT,Operation Stop Trigger of Channel n"
|
||
line.word 0x4 "TPS0,Timer Clock Select Register 0"
|
||
bitfld.word 0x4 12.--13. "PRS3,Selection of Operation Clock (CK03)" "0: PCLKB/28,1: PCLKB/210,2: PCLKB/212,3: PCLKB/214"
|
||
bitfld.word 0x4 8.--9. "PRS2,Selection of Operation Clock (CK02)" "0: PCLKB/2,1: PCLKB/22,2: PCLKB/24,3: PCLKB/26"
|
||
newline
|
||
hexmask.word.byte 0x4 4.--7. 1. "PRS1,Selection of Operation Clock (CK01)"
|
||
hexmask.word.byte 0x4 0.--3. 1. "PRS0,Selection of Operation Clock (CK00)"
|
||
line.word 0x6 "TO0,Timer Output Register 0"
|
||
hexmask.word.byte 0x6 0.--7. 1. "TO,Timer Output of Channel n"
|
||
line.word 0x8 "TOE0,Timer Output Enable Register 0"
|
||
hexmask.word.byte 0x8 0.--7. 1. "TOE,Enabling or Disabling Timer Output for Channel n"
|
||
line.word 0xA "TOL0,Timer Output Level Register 0"
|
||
hexmask.word.byte 0xA 1.--7. 1. "TOL,Control of Timer Output of Channel n"
|
||
line.word 0xC "TOM0,Timer Output Mode Register 0"
|
||
hexmask.word.byte 0xC 1.--7. 1. "TOM,Control of Timer Output Mode of Channel n"
|
||
tree.end
|
||
tree "TML32 (32-bit Interval Timer)"
|
||
base ad:0x400A3800
|
||
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
||
group.word ($2)++0x1
|
||
line.word 0x0 "ITLCMP0$1,Interval Timer Compare Registers 0%s"
|
||
repeat.end
|
||
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
||
group.byte ($2)++0x0
|
||
line.byte 0x0 "ITLCMP0$1_L,Interval Timer Compare Registers 0%s"
|
||
repeat.end
|
||
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
||
group.byte ($2+0x1)++0x0
|
||
line.byte 0x0 "ITLCMP0$1_H,Interval Timer Compare Registers 0%s"
|
||
repeat.end
|
||
rgroup.word 0x4++0x1
|
||
line.word 0x0 "ITLCAP00,Interval Timer Capture Register 00"
|
||
group.byte 0x6++0x6
|
||
line.byte 0x0 "ITLCTL0,Interval Timer Control Register"
|
||
bitfld.byte 0x0 6.--7. "MD,Selection of 8-bit 16-bit or 32-bit Counter Mode" "0: The interval timer operates in 8-bit counter mode.,1: The interval timer operates in 16-bit counter..,?,?"
|
||
bitfld.byte 0x0 3. "EN3,8-bit Counter Mode: ITL013 Count Enable" "0: Counting stops,1: Counting begins"
|
||
newline
|
||
bitfld.byte 0x0 2. "EN2,8-bit Counter Mode: ITL012 Count Enable" "0: Counting stops,1: Counting begins"
|
||
bitfld.byte 0x0 1. "EN1,8-bit Counter Mode: ITL001 Count Enable" "0: Counting stops,1: Counting begins"
|
||
newline
|
||
bitfld.byte 0x0 0. "EN0,8-bit Counter Mode: ITL000 Count Enable" "0: Counting stops,1: Counting begins"
|
||
line.byte 0x1 "ITLCSEL0,Interval Timer Clock Select Register 0"
|
||
bitfld.byte 0x1 4.--6. "CSEL,Selection of Interval Timer Count Clock for Capturing (fITL1)" "0: Setting prohibited,1: HOCO,?,?,?,?,?,?"
|
||
bitfld.byte 0x1 0.--2. "ISEL,Selection of Interval Timer Count Clock (fITL0)" "0: Setting prohibited,1: HOCO,?,?,?,?,?,?"
|
||
line.byte 0x2 "ITLFDIV00,Interval Timer Frequency Division Register 0"
|
||
bitfld.byte 0x2 4.--6. "FDIV1,8-bit Counter Mode: Counter Clock for ITL001" "0: fITL0,1: fITL0/2,?,?,?,?,?,?"
|
||
bitfld.byte 0x2 0.--2. "FDIV0,8-bit Counter Mode: Counter Clock for ITL000" "0: fITL0,1: fITL0/2,?,?,?,?,?,?"
|
||
line.byte 0x3 "ITLFDIV01,Interval Timer Frequency Division Register 1"
|
||
bitfld.byte 0x3 4.--6. "FDIV3,8-bit Counter Mode: Counter Clock for ITL013" "0: fITL0,1: fITL0/2,?,?,?,?,?,?"
|
||
bitfld.byte 0x3 0.--2. "FDIV2,8-bit Counter Mode: Counter Clock for ITL012" "0: fITL0,1: fITL0/2,?,?,?,?,?,?"
|
||
line.byte 0x4 "ITLCC0,Interval Timer Capture Control Register 0"
|
||
bitfld.byte 0x4 7. "CAPEN,Capture Enable" "0: Capturing is disabled.,1: Capturing is enabled."
|
||
bitfld.byte 0x4 6. "CAPFCR,Capture Completion Flag Clear" "0: The value of the capture completion flag CAPF is..,1: The value of the capture completion flag CAPF is.."
|
||
newline
|
||
rbitfld.byte 0x4 5. "CAPF,Capture Completion Flag" "0: Capturing has not been completed.,1: Capturing has been completed."
|
||
bitfld.byte 0x4 4. "CAPR,Software Capture Trigger" "0: Trigger operation does not proceed.,1: A software trigger for capturing is generated."
|
||
newline
|
||
bitfld.byte 0x4 3. "CAPCCR,Selection of Capture Counter Clearing After Capturing" "0: The capture counter value is held after the..,1: The capture counter value is cleared after the.."
|
||
bitfld.byte 0x4 0.--1. "CTRS,Selection of Capture Trigger" "0: Software trigger,1: Interrupt on compare match with ITLCMP01,?,?"
|
||
line.byte 0x5 "ITLS0,Interval Timer Status Register"
|
||
bitfld.byte 0x5 4. "ITF0C,Capture Detection Flag" "0: Completion of capturing has not been detected.,1: Completion of capturing has been detected."
|
||
bitfld.byte 0x5 3. "ITF03,Compare Match Detection Flag for Channel 3" "0: A compare match signal has not been detected in..,1: A compare match signal has been detected in.."
|
||
newline
|
||
bitfld.byte 0x5 2. "ITF02,Compare Match Detection Flag for Channel 2" "0: A compare match signal has not been detected in..,1: A compare match signal has been detected in.."
|
||
bitfld.byte 0x5 1. "ITF01,Compare Match Detection Flag for Channel 1" "0: A compare match signal has not been detected in..,1: A compare match signal has been detected in.."
|
||
newline
|
||
bitfld.byte 0x5 0. "ITF00,Compare Match Detection Flag for Channel 0" "0: A compare match signal has not been detected in..,1: A compare match signal has been detected in.."
|
||
line.byte 0x6 "ITLMKF0,Interval Timer Match Detection Mask Register"
|
||
bitfld.byte 0x6 4. "MKF0C,Mask for Capture Detection Status Flag" "0: ITLS0.ITF0C is not masked,1: ITLS0.ITF0C is masked"
|
||
bitfld.byte 0x6 3. "MKF03,Mask for Compare Match Status Flag for Channel 3" "0: ITLS0.ITF03 is not masked,1: ITLS0.ITF03 is masked"
|
||
newline
|
||
bitfld.byte 0x6 2. "MKF02,Mask for Compare Match Status Flag for Channel 2" "0: ITLS0.ITF02 is not masked,1: ITLS0.ITF02 is masked"
|
||
bitfld.byte 0x6 1. "MKF01,Mask for Compare Match Status Flag for Channel 1" "0: ITLS0.ITF01 is not masked,1: ITLS0.ITF01 is masked"
|
||
newline
|
||
bitfld.byte 0x6 0. "MKF00,Mask for Compare Match Status Flag for Channel 0" "0: ITLS0.ITF00 is not masked,1: ITLS0.ITF00 is masked"
|
||
tree.end
|
||
tree "TRNG (True Random Number Generator)"
|
||
base ad:0x400D1000
|
||
rgroup.byte 0x0++0x0
|
||
line.byte 0x0 "TRNGSDR,TRNG Seed Data Register"
|
||
group.byte 0x2++0x1
|
||
line.byte 0x0 "TRNGSCR0,TRNG Seed Command Register 0"
|
||
rbitfld.byte 0x0 7. "RDRDY,Read Ready" "0,1"
|
||
bitfld.byte 0x0 3. "SGCEN,Seed Generation Circuit Enable" "0: Seed generation circuit is disable.,1: Seed generation circuit is enable."
|
||
bitfld.byte 0x0 2. "SGSTART,Seed Generation Start" "0: No effect,1: Start to generate the seed data"
|
||
line.byte 0x1 "TRNGSCR1,TRNG Seed Command Register 1"
|
||
bitfld.byte 0x1 0. "INTEN,TRNG Interrupt Enable" "0: TRNG interrupt is disabled.,1: TRNG interrupt is enabled."
|
||
tree.end
|
||
tree "UARTA (Serial Interface UARTA)"
|
||
base ad:0x400A3400
|
||
group.byte 0x0++0x0
|
||
line.byte 0x0 "TXBA0,Transmit Buffer Register 0"
|
||
rgroup.byte 0x1++0x0
|
||
line.byte 0x0 "RXBA0,Receive Buffer Register 0"
|
||
group.byte 0x2++0x2
|
||
line.byte 0x0 "ASIMA00,Operation Mode Setting Register 00"
|
||
bitfld.byte 0x0 7. "EN,UART Operation Enable" "0: Disables the UART operation clock (resets the..,1: Enables the UART operation clock"
|
||
bitfld.byte 0x0 6. "TXEA,Transmission Enable" "0: Disables transmission (resets the transmission..,1: Enables transmission"
|
||
newline
|
||
bitfld.byte 0x0 5. "RXEA,Reception Enable" "0: Disables reception (reset the reception circuit),1: Enables reception"
|
||
bitfld.byte 0x0 1. "ISSMA,Transmit Interrupt Mode Select" "0: The UARTA0_TXI interrupt is generated on..,1: The UARTA0_TXI interrupt is generated when the.."
|
||
newline
|
||
bitfld.byte 0x0 0. "ISRMA,Receive Interrupt Mode Select" "0: The UARTA0_ERRI interrupt is generated when a..,1: The UARTA0_RXI interrupt is generated when a.."
|
||
line.byte 0x1 "ASIMA01,Operation Mode Setting Register 01"
|
||
bitfld.byte 0x1 5.--6. "PS,Transmission and Reception Parity Bit Setting" "0: Transmission: No parity bit is output.,1: Transmission: 0 parity is output. Reception:..,?,?"
|
||
bitfld.byte 0x1 3.--4. "CL,Transmission and Reception Character Length Setting" "0: Character length of data = 5 bits,1: Setting prohibited,?,?"
|
||
newline
|
||
bitfld.byte 0x1 2. "SL,Transmission Stop Bit Length Setting" "0: Stop bit length = 1 bit,1: Stop bit length = 2 bits"
|
||
bitfld.byte 0x1 1. "DIR,Transmission and Reception Order Setting" "0: MSB first,1: LSB first"
|
||
newline
|
||
bitfld.byte 0x1 0. "ALV,Transmission and Reception Level Setting" "0: Positive logic (wait state = high level start..,1: Negative logic (wait state = low level start bit.."
|
||
line.byte 0x2 "BRGCA0,Baud Rate Generator Control Register 0"
|
||
rgroup.byte 0x5++0x0
|
||
line.byte 0x0 "ASISA0,Status Register 0"
|
||
bitfld.byte 0x0 5. "TXBFA,Transmit Buffer Data Flag" "0: No valid data exists in the TXBA0 register,1: Valid data exists in the TXBA0 register"
|
||
bitfld.byte 0x0 4. "TXSFA,Transmit Shift Register Data Flag" "0: Data is not being transmitted,1: Data is being transmitted"
|
||
newline
|
||
bitfld.byte 0x0 2. "PEA,Parity Error Flag" "0: No error has occurred,1: An error has occurred"
|
||
bitfld.byte 0x0 1. "FEA,Framing Error Flag" "0: No error has occurred,1: An error has occurred"
|
||
newline
|
||
bitfld.byte 0x0 0. "OVEA,Overrun Error Flag" "0: No error has occurred,1: An error has occurred"
|
||
group.byte 0x6++0x0
|
||
line.byte 0x0 "ASCTA0,Status Clear Trigger Register 0"
|
||
bitfld.byte 0x0 2. "PECTA,Parity Error Flag Clear Trigger" "0: Does not clear the ASISA0.PEA flag (the flag is..,1: Clears the ASISA0.PEA flag"
|
||
bitfld.byte 0x0 1. "FECTA,Framing Error Flag Clear Trigger" "0: Does not clear the ASISA0.FEA flag (the flag is..,1: Clears the ASISA0.FEA flag"
|
||
newline
|
||
bitfld.byte 0x0 0. "OVECTA,Overrun Error Flag Clear Trigger" "0: Does not clear the ASISA0.OVEA flag (the flag is..,1: Clears the ASISA0.OVEA flag"
|
||
group.byte 0x100++0x0
|
||
line.byte 0x0 "UTA0CK,UARTA Clock Select Register 0"
|
||
bitfld.byte 0x0 4.--5. "SEL,fSEL Clock Select" "0: Stop,1: MOSC,?,?"
|
||
hexmask.byte 0x0 0.--3. 1. "CK,UARTA0 Operation Clock Select (fUTA0)"
|
||
tree.end
|
||
AUTOINDENT.OFF
|