; -------------------------------------------------------------------------------- ; @Title: MEC172x On-Chip Peripherals ; @Props: Released ; @Author: KRZ ; @Changelog: 2025-05-19 KRZ ; @Manufacturer: MICROCHIP - Microchip Technology Inc. ; @Doc: Generated (TRACE32, build: 180057.), based on: ; MEC1721N.svd, MEC1723N.svd, MEC1724N.svd, MEC1727N.svd ; @Core: Cortex-M4F ; @Chip: MEC1721N, MEC1723N, MEC1724N, MEC1727N ; @Copyright: (C) 1989-2025 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: permec172x.per 19518 2025-05-19 12:11:21Z kwisniewski $ AUTOINDENT.ON CENTER TREE ENUMDELIMITER "," base ad:0x0 tree.close "Core Registers (Cortex-M4F)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. group.long 0x08++0x03 line.long 0x00 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes" bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes" bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes" textline " " bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes" bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes" group.long 0x10++0x0B line.long 0x00 "SYST_CSR,SysTick Control and Status Register" rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted" bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core" bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick" textline " " bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled" line.long 0x04 "SYST_RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0" line.long 0x08 "SYST_CVR,SysTick Current Value Register" rgroup.long 0x1C++0x03 line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing" rgroup.long 0xD00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited" bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15" bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,0xC,0xD,0xE,ARMv7-M" newline abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC24=Cortex-M4" bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15" group.long 0xD04++0x23 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active" bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending" bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed" textline " " bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending" bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed" bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active" textline " " bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending" hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field" bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active" textline " " hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception" line.long 0x04 "VTOR,Vector Table Offset Register" hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address" line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key" rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big" bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" textline " " bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested" bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear" bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset" line.long 0x0C "SCR,System Control Register" bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" line.long 0x10 "CCR,Configuration Control Register" bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled" bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled" bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled" textline " " bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment" bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled" bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled" bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed" bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level" line.long 0x14 "SHPR1,SSystem Handler Priority Register 1" hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7" hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)" hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)" textline " " hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)" line.long 0x18 "SHPR2,System Handler Priority Register 2" hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)" hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10" hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9" textline " " hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8" line.long 0x1C "SHPR3,System Handler Priority Register 3" hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)" hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)" hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13" textline " " hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)" line.long 0x20 "SHCSR,System Handler Control and State Register" bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled" bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled" bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled" textline " " bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending" bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending" bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending" textline " " bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending" bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active" bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active" textline " " bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active" bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active" bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active" textline " " bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active" bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active" group.byte 0xD28++0x1 line.byte 0x00 "MMFSR,MemManage Status Register" bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred" textline " " bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred" bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred" line.byte 0x01 "BFSR,Bus Fault Status Register" bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred" textline " " bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred" bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred" bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred" textline " " bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred" group.word 0xD2A++0x1 line.word 0x00 "USAFAULT,Usage Fault Status Register" bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error" bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error" bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error" textline " " bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error" bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error" bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error" group.long 0xD2C++0x07 line.long 0x00 "HFSR,Hard Fault Status Register" bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred" bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred" bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred" line.long 0x04 "DFSR,Debug Fault Status Register" bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted" bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred" bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred" textline " " bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed" bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested" group.long 0xD34++0x0B line.long 0x00 "MMFAR,MemManage Fault Address Register" line.long 0x04 "BFAR,BusFault Address Register" line.long 0x08 "AFSR,Auxiliary Fault Status Register" group.long 0xD88++0x03 line.long 0x00 "CPACR,Coprocessor Access Control Register" bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access" wgroup.long 0xF00++0x03 line.long 0x00 "STIR,Software Trigger Interrupt Register" hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered" width 10. tree "Feature Registers" rgroup.long 0xD40++0x0B line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..." line.long 0x04 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..." line.long 0x08 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..." hgroup.long 0xD4C++0x03 hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long 0xD50++0x03 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..." bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..." textline " " bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored" bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..." hgroup.long 0xD54++0x03 hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" rgroup.long 0xD58++0x03 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..." rgroup.long 0xD60++0x13 line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..." bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..." bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..." textline " " bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..." bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..." line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..." bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..." bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..." textline " " bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..." line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..." bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..." bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..." bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..." bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..." textline " " bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..." line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..." bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..." bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..." textline " " bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..." bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..." textline " " bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..." line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..." bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..." textline " " bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..." bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..." bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..." tree.end width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0C "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0C "CID3,Component ID3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported" group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8 group.long 0xD9C++0x03 "Region 8" saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 8 (not implemented)" saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9 group.long 0xD9C++0x03 "Region 9" saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 9 (not implemented)" saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA group.long 0xD9C++0x03 "Region 10" saveout 0xD98 %l 0xA line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xA line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 10 (not implemented)" saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB group.long 0xD9C++0x03 "Region 11" saveout 0xD98 %l 0xB line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xB line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 11 (not implemented)" saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC group.long 0xD9C++0x03 "Region 12" saveout 0xD98 %l 0xC line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xC line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 12 (not implemented)" saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD group.long 0xD9C++0x03 "Region 13" saveout 0xD98 %l 0xD line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xD line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 13 (not implemented)" saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE group.long 0xD9C++0x03 "Region 14" saveout 0xD98 %l 0xE line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xE line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 14 (not implemented)" saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF group.long 0xD9C++0x03 "Region 15" saveout 0xD98 %l 0xF line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xF line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 15 (not implemented)" saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" textline " " textline " " endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 6. rgroup.long 0x04++0x03 line.long 0x00 "ICTR,Interrupt Controller Type Register" bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..." tree "Interrupt Enable Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x100++0x03 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x100++0x7 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x100++0x0B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x100++0x0F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x100++0x13 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x100++0x17 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x100++0x1B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x100++0x1F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x100++0x1F hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" endif tree.end tree "Interrupt Pending Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x200++0x03 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x200++0x07 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x200++0x0B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x200++0x0F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x200++0x13 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x200++0x17 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x200++0x1B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x200++0x1F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x200++0x1F hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" endif tree.end tree "Interrupt Active Bit Registers" width 9. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) rgroup.long 0x300++0x03 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) rgroup.long 0x300++0x07 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) rgroup.long 0x300++0x0B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) rgroup.long 0x300++0x0F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) rgroup.long 0x300++0x13 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) rgroup.long 0x300++0x17 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) rgroup.long 0x300++0x1B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) rgroup.long 0x300++0x1F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" line.long 0x1c "ACTIVE8,Active Bit Register 8" bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x300++0x1F hide.long 0x00 "ACTIVE1,Active Bit Register 1" hide.long 0x04 "ACTIVE2,Active Bit Register 2" hide.long 0x08 "ACTIVE3,Active Bit Register 3" hide.long 0x0c "ACTIVE4,Active Bit Register 4" hide.long 0x10 "ACTIVE5,Active Bit Register 5" hide.long 0x14 "ACTIVE6,Active Bit Register 6" hide.long 0x18 "ACTIVE7,Active Bit Register 7" hide.long 0x1c "ACTIVE8,Active Bit Register 8" endif tree.end tree "Interrupt Priority Registers" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x400++0x1F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x400++0x3F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x400++0x5F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x400++0x7F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x400++0x9F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x400++0xBF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x400++0xDF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x400++0xEF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" line.long 0xE0 "IPR56,Interrupt Priority Register" hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority" hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority" hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority" hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority" line.long 0xE4 "IPR57,Interrupt Priority Register" hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority" hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority" hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority" hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority" line.long 0xE8 "IPR58,Interrupt Priority Register" hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority" hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority" hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority" hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority" line.long 0xEC "IPR59,Interrupt Priority Register" hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority" hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority" hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority" hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority" else hgroup.long 0x400++0xEF hide.long 0x0 "IPR0,Interrupt Priority Register" hide.long 0x4 "IPR1,Interrupt Priority Register" hide.long 0x8 "IPR2,Interrupt Priority Register" hide.long 0xC "IPR3,Interrupt Priority Register" hide.long 0x10 "IPR4,Interrupt Priority Register" hide.long 0x14 "IPR5,Interrupt Priority Register" hide.long 0x18 "IPR6,Interrupt Priority Register" hide.long 0x1C "IPR7,Interrupt Priority Register" hide.long 0x20 "IPR8,Interrupt Priority Register" hide.long 0x24 "IPR9,Interrupt Priority Register" hide.long 0x28 "IPR10,Interrupt Priority Register" hide.long 0x2C "IPR11,Interrupt Priority Register" hide.long 0x30 "IPR12,Interrupt Priority Register" hide.long 0x34 "IPR13,Interrupt Priority Register" hide.long 0x38 "IPR14,Interrupt Priority Register" hide.long 0x3C "IPR15,Interrupt Priority Register" hide.long 0x40 "IPR16,Interrupt Priority Register" hide.long 0x44 "IPR17,Interrupt Priority Register" hide.long 0x48 "IPR18,Interrupt Priority Register" hide.long 0x4C "IPR19,Interrupt Priority Register" hide.long 0x50 "IPR20,Interrupt Priority Register" hide.long 0x54 "IPR21,Interrupt Priority Register" hide.long 0x58 "IPR22,Interrupt Priority Register" hide.long 0x5C "IPR23,Interrupt Priority Register" hide.long 0x60 "IPR24,Interrupt Priority Register" hide.long 0x64 "IPR25,Interrupt Priority Register" hide.long 0x68 "IPR26,Interrupt Priority Register" hide.long 0x6C "IPR27,Interrupt Priority Register" hide.long 0x70 "IPR28,Interrupt Priority Register" hide.long 0x74 "IPR29,Interrupt Priority Register" hide.long 0x78 "IPR30,Interrupt Priority Register" hide.long 0x7C "IPR31,Interrupt Priority Register" hide.long 0x80 "IPR32,Interrupt Priority Register" hide.long 0x84 "IPR33,Interrupt Priority Register" hide.long 0x88 "IPR34,Interrupt Priority Register" hide.long 0x8C "IPR35,Interrupt Priority Register" hide.long 0x90 "IPR36,Interrupt Priority Register" hide.long 0x94 "IPR37,Interrupt Priority Register" hide.long 0x98 "IPR38,Interrupt Priority Register" hide.long 0x9C "IPR39,Interrupt Priority Register" hide.long 0xA0 "IPR40,Interrupt Priority Register" hide.long 0xA4 "IPR41,Interrupt Priority Register" hide.long 0xA8 "IPR42,Interrupt Priority Register" hide.long 0xAC "IPR43,Interrupt Priority Register" hide.long 0xB0 "IPR44,Interrupt Priority Register" hide.long 0xB4 "IPR45,Interrupt Priority Register" hide.long 0xB8 "IPR46,Interrupt Priority Register" hide.long 0xBC "IPR47,Interrupt Priority Register" hide.long 0xC0 "IPR48,Interrupt Priority Register" hide.long 0xC4 "IPR49,Interrupt Priority Register" hide.long 0xC8 "IPR50,Interrupt Priority Register" hide.long 0xCC "IPR51,Interrupt Priority Register" hide.long 0xD0 "IPR52,Interrupt Priority Register" hide.long 0xD4 "IPR53,Interrupt Priority Register" hide.long 0xD8 "IPR54,Interrupt Priority Register" hide.long 0xDC "IPR55,Interrupt Priority Register" hide.long 0xE0 "IPR56,Interrupt Priority Register" hide.long 0xE4 "IPR57,Interrupt Priority Register" hide.long 0xE8 "IPR58,Interrupt Priority Register" hide.long 0xEC "IPR59,Interrupt Priority Register" endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end sif CORENAME()=="CORTEXM4F" tree "Floating-point Unit (FPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 8. group.long 0xF34++0x0B line.long 0x00 "FPCCR,Floating-Point Context Control Register" bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled" bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled" bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able" textline " " bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able" bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able" bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able" textline " " bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread" bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged" bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active" line.long 0x04 "FPCAR,Floating-Point Context Address Register" hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame" line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register" bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative" bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation" bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode" textline " " bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero" rgroup.long 0xF40++0x07 line.long 0x00 "MVFR0,Media and FP Feature Register 0" bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..." bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..." bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..." textline " " bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..." bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..." bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..." bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..." line.long 0x04 "MVFR1,Media and FP Feature Register 1" bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..." bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..." textline " " bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..." bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..." width 0xB else newline textline "COREDEBUG component base address not specified" newline endif tree.end endif tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 7. group.long 0xD30++0x03 line.long 0x00 "DFSR,Debug Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated" eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered" eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated" newline eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated" eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated" newline hgroup.long 0xDF0++0x03 hide.long 0x00 "DHCSR,Debug Halting Control and Status Register" in newline wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Register Selector Register" bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write" hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register" group.long 0xDF8++0x03 line.long 0x00 "DCRDR,Debug Core Register Data Register" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000) group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" else group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" endif width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Flash Patch and Breakpoint Unit (FPB)" sif COMPonent.AVAILABLE("FPB") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1)) width 10. group.long 0x00++0x07 line.long 0x00 "FP_CTRL,Flash Patch Control Register" bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..." rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127" bitfld.long 0x00 1. " KEY ,Key Field" "Low,High" bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled" textline "" line.long 0x04 "FP_REMAP,Flash Patch Remap Register" bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region" hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0xB else newline textline "FPB component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 15. group.long 0x00++0x1B line.long 0x00 "DWT_CTRL,Control Register" rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported" rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported" textline " " rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported" rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported" bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled" bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled" bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled" bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled" bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled" bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]" bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]" textline " " bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled" line.long 0x04 "DWT_CYCCNT,Cycle Count Register" line.long 0x08 "DWT_CPICNT,CPI Count Register" hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter" line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register" hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter" line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register" hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter" line.long 0x14 "DWT_LSUCNT,LSU Count Register" hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter" line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register" hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter" rgroup.long 0x1C++0x03 line.long 0x00 "DWT_PCSR,Program Counter Sample register" textline " " group.long 0x20++0x07 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" line.long 0x04 "DWT_MASK0,DWT Mask Registers 0" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" else group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x30)++0x07 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" line.long 0x04 "DWT_MASK1,DWT Mask Registers 1" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x40)++0x07 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" line.long 0x04 "DWT_MASK2,DWT Mask Registers 2" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x50)++0x07 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" line.long 0x04 "DWT_MASK3,DWT Mask Registers 3" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0x0B else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end tree "ACPI_EC (ACPI Embedded Controller)" base ad:0x0 tree "ACPI_EC0" base ad:0x400F0800 group.long 0x0++0x3 line.long 0x0 "OS_DATA,This is byte n of the 32-bit ACPI-OS DATA BYTES[3:0]. Writes by the ACPI_OS to the ACPI-OS DATA BYTES[n] are aliased to the OS2EC DATA BYTES[n]. Reads by the ACPI_OS from the ACPI-OS DATA BYTES[n] are aliased to the EC2OS DATA BYTES[n]." wgroup.byte 0x4++0x0 line.byte 0x0 "OS_CMD,Writes to the this register are aliased in the OS2EC Data EC Byte 0 Register. Writes to this register also set the CMD and IBF bits in the OS STATUS OS Register" rgroup.byte 0x4++0x1 line.byte 0x0 "OS_STS,OS STATUS" bitfld.byte 0x0 7. "UD0B,User Defined" "0,1" bitfld.byte 0x0 6. "SMI_EVT,This bit is set when an SMI event is pending; i.e. the ACPI_EC is requesting an SMI query; This bit is cleared when no SMI events are pending. This bit is an ACPI_EC-maintained software flag that is set when the ACPI_EC has detected an.." "0,1" bitfld.byte 0x0 5. "SCI_EVT,This bit is set by software when an SCI event is pending; i.e. the ACPI_EC is requesting an SCI query; SCI Event flag is clear when no SCI events are pending. This bit is an ACPI_EC-maintained software flag that is set when the embedded.." "0,1" bitfld.byte 0x0 4. "BURST,The BURST bit is set when the ACPI_EC is in Burst Mode for polled command processing; the BURST bit is cleared when the ACPI_EC is in Normal mode for interrupt-driven command processing. The BURST bit is is an ACPI_EC-maintained software flag.." "0,1" bitfld.byte 0x0 3. "CMD,This bit is set when the OS2EC Data EC Byte 0 Register contains a command byte written into ACPI OS COMMAND Register; this bit is cleared when the OS2EC DATA BYTES[3:0] contains a data byte written into the ACPI-OS DATA BYTES[3:0]. This bit.." "0,1" bitfld.byte 0x0 2. "UD1B,User Defined" "0,1" newline bitfld.byte 0x0 1. "IBF,The Input Buffer Full bit is set to indicate that a the ACPI_OS has written a command or data to the ACPI_EC and that data is ready. This bit is automatically cleared when data has been read by the ACPI_EC. Note: The setting and clearing of.." "0,1" bitfld.byte 0x0 0. "OBF,The Output Buffer Full bit is set to indicate that a the ACPI_EC has written a data to the ACPI_OS and that data is ready. This bit is automatically cleared when all the data has been read by the ACPI_OS. Note: The setting and clearing of.." "0,1" line.byte 0x1 "OS_BYTE_CTRL,OS Byte Control Register" bitfld.byte 0x1 0. "FOUR_BYTE_ACCESS,When this bit is set to '1' the ACPI Embedded Controller Interface (ACPI-ECI) accesses four bytes through the ACPI-OS DATA BYTES[3:0]. When this bit is cleared to '0' the ACPI Embedded Controller Interface (ACPI-ECI) accesses one.." "0,1" group.long 0x100++0x3 line.long 0x0 "EC2OS_DATA,This is byte n of the 32-bit EC2OS DATA BYTES[3:0]. Writes by the ACPI_EC to the EC2OS DATA BYTES[3:0] are aliased to the ACPI-OS DATA BYTES[3:0]." group.byte 0x104++0x1 line.byte 0x0 "EC_STATUS,EC STATUS" bitfld.byte 0x0 7. "UD0A,User Defined" "0,1" bitfld.byte 0x0 6. "SMI_EVT,This bit is set when an SMI event is pending" "0,1" bitfld.byte 0x0 5. "SCI_EVT,This bit is set by software when an SCI event is pending" "0,1" bitfld.byte 0x0 4. "BURST,The BURST bit is set when the ACPI_EC is in Burst Mode" "0,1" bitfld.byte 0x0 3. "CMD,This bit is set when the OS2EC Data EC Byte 0 Register contains a command byte written into ACPI OS COMMAND Register" "0,1" bitfld.byte 0x0 2. "UD1A,UD1A User Defined" "0,1" newline bitfld.byte 0x0 1. "IBF,The Input Buffer Full bit is set to indicate that a the ACPI_OS has written a command or data to the ACPI_EC and that data is ready." "0,1" bitfld.byte 0x0 0. "OBF,The Output Buffer Full bit is set to indicate that a the ACPI_EC has written a data to the ACPI_OS and that data is ready." "0,1" line.byte 0x1 "EC_BYTE_CTRL,Byte Control EC-Register" bitfld.byte 0x1 0. "FOUR_BYTE_ACCESS,When this bit is set to '1' the ACPI Embedded Controller Interface (ACPI-ECI) accesses four bytes through the ACPI-OS DATA BYTES[3:0]. When this bit is cleared to '0' the ACPI Embedded Controller Interface (ACPI-ECI) accesses one.." "0,1" group.long 0x108++0x3 line.long 0x0 "OS2EC_DATA,OS_TO_EC_DATA_BYTE_n. This is byte n of the 32-bit OS2EC DATA BYTES[3:0]. When the CMD bit in the OS STATUS OS Register is cleared to '0'. reads by the ACPI_EC from the OS2EC DATA BYTES[3:0] are aliased to the ACPI-OS DATA BYTES[3:0]." tree.end tree "ACPI_EC1" base ad:0x400F0C00 group.long 0x0++0x3 line.long 0x0 "OS_DATA,This is byte n of the 32-bit ACPI-OS DATA BYTES[3:0]. Writes by the ACPI_OS to the ACPI-OS DATA BYTES[n] are aliased to the OS2EC DATA BYTES[n]. Reads by the ACPI_OS from the ACPI-OS DATA BYTES[n] are aliased to the EC2OS DATA BYTES[n]." wgroup.byte 0x4++0x0 line.byte 0x0 "OS_CMD,Writes to the this register are aliased in the OS2EC Data EC Byte 0 Register. Writes to this register also set the CMD and IBF bits in the OS STATUS OS Register" rgroup.byte 0x4++0x1 line.byte 0x0 "OS_STS,OS STATUS" bitfld.byte 0x0 7. "UD0B,User Defined" "0,1" bitfld.byte 0x0 6. "SMI_EVT,This bit is set when an SMI event is pending; i.e. the ACPI_EC is requesting an SMI query; This bit is cleared when no SMI events are pending. This bit is an ACPI_EC-maintained software flag that is set when the ACPI_EC has detected an.." "0,1" bitfld.byte 0x0 5. "SCI_EVT,This bit is set by software when an SCI event is pending; i.e. the ACPI_EC is requesting an SCI query; SCI Event flag is clear when no SCI events are pending. This bit is an ACPI_EC-maintained software flag that is set when the embedded.." "0,1" bitfld.byte 0x0 4. "BURST,The BURST bit is set when the ACPI_EC is in Burst Mode for polled command processing; the BURST bit is cleared when the ACPI_EC is in Normal mode for interrupt-driven command processing. The BURST bit is is an ACPI_EC-maintained software flag.." "0,1" bitfld.byte 0x0 3. "CMD,This bit is set when the OS2EC Data EC Byte 0 Register contains a command byte written into ACPI OS COMMAND Register; this bit is cleared when the OS2EC DATA BYTES[3:0] contains a data byte written into the ACPI-OS DATA BYTES[3:0]. This bit.." "0,1" bitfld.byte 0x0 2. "UD1B,User Defined" "0,1" newline bitfld.byte 0x0 1. "IBF,The Input Buffer Full bit is set to indicate that a the ACPI_OS has written a command or data to the ACPI_EC and that data is ready. This bit is automatically cleared when data has been read by the ACPI_EC. Note: The setting and clearing of.." "0,1" bitfld.byte 0x0 0. "OBF,The Output Buffer Full bit is set to indicate that a the ACPI_EC has written a data to the ACPI_OS and that data is ready. This bit is automatically cleared when all the data has been read by the ACPI_OS. Note: The setting and clearing of.." "0,1" line.byte 0x1 "OS_BYTE_CTRL,OS Byte Control Register" bitfld.byte 0x1 0. "FOUR_BYTE_ACCESS,When this bit is set to '1' the ACPI Embedded Controller Interface (ACPI-ECI) accesses four bytes through the ACPI-OS DATA BYTES[3:0]. When this bit is cleared to '0' the ACPI Embedded Controller Interface (ACPI-ECI) accesses one.." "0,1" group.long 0x100++0x3 line.long 0x0 "EC2OS_DATA,This is byte n of the 32-bit EC2OS DATA BYTES[3:0]. Writes by the ACPI_EC to the EC2OS DATA BYTES[3:0] are aliased to the ACPI-OS DATA BYTES[3:0]." group.byte 0x104++0x1 line.byte 0x0 "EC_STATUS,EC STATUS" bitfld.byte 0x0 7. "UD0A,User Defined" "0,1" bitfld.byte 0x0 6. "SMI_EVT,This bit is set when an SMI event is pending" "0,1" bitfld.byte 0x0 5. "SCI_EVT,This bit is set by software when an SCI event is pending" "0,1" bitfld.byte 0x0 4. "BURST,The BURST bit is set when the ACPI_EC is in Burst Mode" "0,1" bitfld.byte 0x0 3. "CMD,This bit is set when the OS2EC Data EC Byte 0 Register contains a command byte written into ACPI OS COMMAND Register" "0,1" bitfld.byte 0x0 2. "UD1A,UD1A User Defined" "0,1" newline bitfld.byte 0x0 1. "IBF,The Input Buffer Full bit is set to indicate that a the ACPI_OS has written a command or data to the ACPI_EC and that data is ready." "0,1" bitfld.byte 0x0 0. "OBF,The Output Buffer Full bit is set to indicate that a the ACPI_EC has written a data to the ACPI_OS and that data is ready." "0,1" line.byte 0x1 "EC_BYTE_CTRL,Byte Control EC-Register" bitfld.byte 0x1 0. "FOUR_BYTE_ACCESS,When this bit is set to '1' the ACPI Embedded Controller Interface (ACPI-ECI) accesses four bytes through the ACPI-OS DATA BYTES[3:0]. When this bit is cleared to '0' the ACPI Embedded Controller Interface (ACPI-ECI) accesses one.." "0,1" group.long 0x108++0x3 line.long 0x0 "OS2EC_DATA,OS_TO_EC_DATA_BYTE_n. This is byte n of the 32-bit OS2EC DATA BYTES[3:0]. When the CMD bit in the OS STATUS OS Register is cleared to '0'. reads by the ACPI_EC from the OS2EC DATA BYTES[3:0] are aliased to the ACPI-OS DATA BYTES[3:0]." tree.end tree "ACPI_EC2" base ad:0x400F1000 group.long 0x0++0x3 line.long 0x0 "OS_DATA,This is byte n of the 32-bit ACPI-OS DATA BYTES[3:0]. Writes by the ACPI_OS to the ACPI-OS DATA BYTES[n] are aliased to the OS2EC DATA BYTES[n]. Reads by the ACPI_OS from the ACPI-OS DATA BYTES[n] are aliased to the EC2OS DATA BYTES[n]." wgroup.byte 0x4++0x0 line.byte 0x0 "OS_CMD,Writes to the this register are aliased in the OS2EC Data EC Byte 0 Register. Writes to this register also set the CMD and IBF bits in the OS STATUS OS Register" rgroup.byte 0x4++0x1 line.byte 0x0 "OS_STS,OS STATUS" bitfld.byte 0x0 7. "UD0B,User Defined" "0,1" bitfld.byte 0x0 6. "SMI_EVT,This bit is set when an SMI event is pending; i.e. the ACPI_EC is requesting an SMI query; This bit is cleared when no SMI events are pending. This bit is an ACPI_EC-maintained software flag that is set when the ACPI_EC has detected an.." "0,1" bitfld.byte 0x0 5. "SCI_EVT,This bit is set by software when an SCI event is pending; i.e. the ACPI_EC is requesting an SCI query; SCI Event flag is clear when no SCI events are pending. This bit is an ACPI_EC-maintained software flag that is set when the embedded.." "0,1" bitfld.byte 0x0 4. "BURST,The BURST bit is set when the ACPI_EC is in Burst Mode for polled command processing; the BURST bit is cleared when the ACPI_EC is in Normal mode for interrupt-driven command processing. The BURST bit is is an ACPI_EC-maintained software flag.." "0,1" bitfld.byte 0x0 3. "CMD,This bit is set when the OS2EC Data EC Byte 0 Register contains a command byte written into ACPI OS COMMAND Register; this bit is cleared when the OS2EC DATA BYTES[3:0] contains a data byte written into the ACPI-OS DATA BYTES[3:0]. This bit.." "0,1" bitfld.byte 0x0 2. "UD1B,User Defined" "0,1" newline bitfld.byte 0x0 1. "IBF,The Input Buffer Full bit is set to indicate that a the ACPI_OS has written a command or data to the ACPI_EC and that data is ready. This bit is automatically cleared when data has been read by the ACPI_EC. Note: The setting and clearing of.." "0,1" bitfld.byte 0x0 0. "OBF,The Output Buffer Full bit is set to indicate that a the ACPI_EC has written a data to the ACPI_OS and that data is ready. This bit is automatically cleared when all the data has been read by the ACPI_OS. Note: The setting and clearing of.." "0,1" line.byte 0x1 "OS_BYTE_CTRL,OS Byte Control Register" bitfld.byte 0x1 0. "FOUR_BYTE_ACCESS,When this bit is set to '1' the ACPI Embedded Controller Interface (ACPI-ECI) accesses four bytes through the ACPI-OS DATA BYTES[3:0]. When this bit is cleared to '0' the ACPI Embedded Controller Interface (ACPI-ECI) accesses one.." "0,1" group.long 0x100++0x3 line.long 0x0 "EC2OS_DATA,This is byte n of the 32-bit EC2OS DATA BYTES[3:0]. Writes by the ACPI_EC to the EC2OS DATA BYTES[3:0] are aliased to the ACPI-OS DATA BYTES[3:0]." group.byte 0x104++0x1 line.byte 0x0 "EC_STATUS,EC STATUS" bitfld.byte 0x0 7. "UD0A,User Defined" "0,1" bitfld.byte 0x0 6. "SMI_EVT,This bit is set when an SMI event is pending" "0,1" bitfld.byte 0x0 5. "SCI_EVT,This bit is set by software when an SCI event is pending" "0,1" bitfld.byte 0x0 4. "BURST,The BURST bit is set when the ACPI_EC is in Burst Mode" "0,1" bitfld.byte 0x0 3. "CMD,This bit is set when the OS2EC Data EC Byte 0 Register contains a command byte written into ACPI OS COMMAND Register" "0,1" bitfld.byte 0x0 2. "UD1A,UD1A User Defined" "0,1" newline bitfld.byte 0x0 1. "IBF,The Input Buffer Full bit is set to indicate that a the ACPI_OS has written a command or data to the ACPI_EC and that data is ready." "0,1" bitfld.byte 0x0 0. "OBF,The Output Buffer Full bit is set to indicate that a the ACPI_EC has written a data to the ACPI_OS and that data is ready." "0,1" line.byte 0x1 "EC_BYTE_CTRL,Byte Control EC-Register" bitfld.byte 0x1 0. "FOUR_BYTE_ACCESS,When this bit is set to '1' the ACPI Embedded Controller Interface (ACPI-ECI) accesses four bytes through the ACPI-OS DATA BYTES[3:0]. When this bit is cleared to '0' the ACPI Embedded Controller Interface (ACPI-ECI) accesses one.." "0,1" group.long 0x108++0x3 line.long 0x0 "OS2EC_DATA,OS_TO_EC_DATA_BYTE_n. This is byte n of the 32-bit OS2EC DATA BYTES[3:0]. When the CMD bit in the OS STATUS OS Register is cleared to '0'. reads by the ACPI_EC from the OS2EC DATA BYTES[3:0] are aliased to the ACPI-OS DATA BYTES[3:0]." tree.end tree "ACPI_EC3" base ad:0x400F1400 group.long 0x0++0x3 line.long 0x0 "OS_DATA,This is byte n of the 32-bit ACPI-OS DATA BYTES[3:0]. Writes by the ACPI_OS to the ACPI-OS DATA BYTES[n] are aliased to the OS2EC DATA BYTES[n]. Reads by the ACPI_OS from the ACPI-OS DATA BYTES[n] are aliased to the EC2OS DATA BYTES[n]." wgroup.byte 0x4++0x0 line.byte 0x0 "OS_CMD,Writes to the this register are aliased in the OS2EC Data EC Byte 0 Register. Writes to this register also set the CMD and IBF bits in the OS STATUS OS Register" rgroup.byte 0x4++0x1 line.byte 0x0 "OS_STS,OS STATUS" bitfld.byte 0x0 7. "UD0B,User Defined" "0,1" bitfld.byte 0x0 6. "SMI_EVT,This bit is set when an SMI event is pending; i.e. the ACPI_EC is requesting an SMI query; This bit is cleared when no SMI events are pending. This bit is an ACPI_EC-maintained software flag that is set when the ACPI_EC has detected an.." "0,1" bitfld.byte 0x0 5. "SCI_EVT,This bit is set by software when an SCI event is pending; i.e. the ACPI_EC is requesting an SCI query; SCI Event flag is clear when no SCI events are pending. This bit is an ACPI_EC-maintained software flag that is set when the embedded.." "0,1" bitfld.byte 0x0 4. "BURST,The BURST bit is set when the ACPI_EC is in Burst Mode for polled command processing; the BURST bit is cleared when the ACPI_EC is in Normal mode for interrupt-driven command processing. The BURST bit is is an ACPI_EC-maintained software flag.." "0,1" bitfld.byte 0x0 3. "CMD,This bit is set when the OS2EC Data EC Byte 0 Register contains a command byte written into ACPI OS COMMAND Register; this bit is cleared when the OS2EC DATA BYTES[3:0] contains a data byte written into the ACPI-OS DATA BYTES[3:0]. This bit.." "0,1" bitfld.byte 0x0 2. "UD1B,User Defined" "0,1" newline bitfld.byte 0x0 1. "IBF,The Input Buffer Full bit is set to indicate that a the ACPI_OS has written a command or data to the ACPI_EC and that data is ready. This bit is automatically cleared when data has been read by the ACPI_EC. Note: The setting and clearing of.." "0,1" bitfld.byte 0x0 0. "OBF,The Output Buffer Full bit is set to indicate that a the ACPI_EC has written a data to the ACPI_OS and that data is ready. This bit is automatically cleared when all the data has been read by the ACPI_OS. Note: The setting and clearing of.." "0,1" line.byte 0x1 "OS_BYTE_CTRL,OS Byte Control Register" bitfld.byte 0x1 0. "FOUR_BYTE_ACCESS,When this bit is set to '1' the ACPI Embedded Controller Interface (ACPI-ECI) accesses four bytes through the ACPI-OS DATA BYTES[3:0]. When this bit is cleared to '0' the ACPI Embedded Controller Interface (ACPI-ECI) accesses one.." "0,1" group.long 0x100++0x3 line.long 0x0 "EC2OS_DATA,This is byte n of the 32-bit EC2OS DATA BYTES[3:0]. Writes by the ACPI_EC to the EC2OS DATA BYTES[3:0] are aliased to the ACPI-OS DATA BYTES[3:0]." group.byte 0x104++0x1 line.byte 0x0 "EC_STATUS,EC STATUS" bitfld.byte 0x0 7. "UD0A,User Defined" "0,1" bitfld.byte 0x0 6. "SMI_EVT,This bit is set when an SMI event is pending" "0,1" bitfld.byte 0x0 5. "SCI_EVT,This bit is set by software when an SCI event is pending" "0,1" bitfld.byte 0x0 4. "BURST,The BURST bit is set when the ACPI_EC is in Burst Mode" "0,1" bitfld.byte 0x0 3. "CMD,This bit is set when the OS2EC Data EC Byte 0 Register contains a command byte written into ACPI OS COMMAND Register" "0,1" bitfld.byte 0x0 2. "UD1A,UD1A User Defined" "0,1" newline bitfld.byte 0x0 1. "IBF,The Input Buffer Full bit is set to indicate that a the ACPI_OS has written a command or data to the ACPI_EC and that data is ready." "0,1" bitfld.byte 0x0 0. "OBF,The Output Buffer Full bit is set to indicate that a the ACPI_EC has written a data to the ACPI_OS and that data is ready." "0,1" line.byte 0x1 "EC_BYTE_CTRL,Byte Control EC-Register" bitfld.byte 0x1 0. "FOUR_BYTE_ACCESS,When this bit is set to '1' the ACPI Embedded Controller Interface (ACPI-ECI) accesses four bytes through the ACPI-OS DATA BYTES[3:0]. When this bit is cleared to '0' the ACPI Embedded Controller Interface (ACPI-ECI) accesses one.." "0,1" group.long 0x108++0x3 line.long 0x0 "OS2EC_DATA,OS_TO_EC_DATA_BYTE_n. This is byte n of the 32-bit OS2EC DATA BYTES[3:0]. When the CMD bit in the OS STATUS OS Register is cleared to '0'. reads by the ACPI_EC from the OS2EC DATA BYTES[3:0] are aliased to the ACPI-OS DATA BYTES[3:0]." tree.end tree "ACPI_EC4" base ad:0x400F1800 group.long 0x0++0x3 line.long 0x0 "OS_DATA,This is byte n of the 32-bit ACPI-OS DATA BYTES[3:0]. Writes by the ACPI_OS to the ACPI-OS DATA BYTES[n] are aliased to the OS2EC DATA BYTES[n]. Reads by the ACPI_OS from the ACPI-OS DATA BYTES[n] are aliased to the EC2OS DATA BYTES[n]." wgroup.byte 0x4++0x0 line.byte 0x0 "OS_CMD,Writes to the this register are aliased in the OS2EC Data EC Byte 0 Register. Writes to this register also set the CMD and IBF bits in the OS STATUS OS Register" rgroup.byte 0x4++0x1 line.byte 0x0 "OS_STS,OS STATUS" bitfld.byte 0x0 7. "UD0B,User Defined" "0,1" bitfld.byte 0x0 6. "SMI_EVT,This bit is set when an SMI event is pending; i.e. the ACPI_EC is requesting an SMI query; This bit is cleared when no SMI events are pending. This bit is an ACPI_EC-maintained software flag that is set when the ACPI_EC has detected an.." "0,1" bitfld.byte 0x0 5. "SCI_EVT,This bit is set by software when an SCI event is pending; i.e. the ACPI_EC is requesting an SCI query; SCI Event flag is clear when no SCI events are pending. This bit is an ACPI_EC-maintained software flag that is set when the embedded.." "0,1" bitfld.byte 0x0 4. "BURST,The BURST bit is set when the ACPI_EC is in Burst Mode for polled command processing; the BURST bit is cleared when the ACPI_EC is in Normal mode for interrupt-driven command processing. The BURST bit is is an ACPI_EC-maintained software flag.." "0,1" bitfld.byte 0x0 3. "CMD,This bit is set when the OS2EC Data EC Byte 0 Register contains a command byte written into ACPI OS COMMAND Register; this bit is cleared when the OS2EC DATA BYTES[3:0] contains a data byte written into the ACPI-OS DATA BYTES[3:0]. This bit.." "0,1" bitfld.byte 0x0 2. "UD1B,User Defined" "0,1" newline bitfld.byte 0x0 1. "IBF,The Input Buffer Full bit is set to indicate that a the ACPI_OS has written a command or data to the ACPI_EC and that data is ready. This bit is automatically cleared when data has been read by the ACPI_EC. Note: The setting and clearing of.." "0,1" bitfld.byte 0x0 0. "OBF,The Output Buffer Full bit is set to indicate that a the ACPI_EC has written a data to the ACPI_OS and that data is ready. This bit is automatically cleared when all the data has been read by the ACPI_OS. Note: The setting and clearing of.." "0,1" line.byte 0x1 "OS_BYTE_CTRL,OS Byte Control Register" bitfld.byte 0x1 0. "FOUR_BYTE_ACCESS,When this bit is set to '1' the ACPI Embedded Controller Interface (ACPI-ECI) accesses four bytes through the ACPI-OS DATA BYTES[3:0]. When this bit is cleared to '0' the ACPI Embedded Controller Interface (ACPI-ECI) accesses one.." "0,1" group.long 0x100++0x3 line.long 0x0 "EC2OS_DATA,This is byte n of the 32-bit EC2OS DATA BYTES[3:0]. Writes by the ACPI_EC to the EC2OS DATA BYTES[3:0] are aliased to the ACPI-OS DATA BYTES[3:0]." group.byte 0x104++0x1 line.byte 0x0 "EC_STATUS,EC STATUS" bitfld.byte 0x0 7. "UD0A,User Defined" "0,1" bitfld.byte 0x0 6. "SMI_EVT,This bit is set when an SMI event is pending" "0,1" bitfld.byte 0x0 5. "SCI_EVT,This bit is set by software when an SCI event is pending" "0,1" bitfld.byte 0x0 4. "BURST,The BURST bit is set when the ACPI_EC is in Burst Mode" "0,1" bitfld.byte 0x0 3. "CMD,This bit is set when the OS2EC Data EC Byte 0 Register contains a command byte written into ACPI OS COMMAND Register" "0,1" bitfld.byte 0x0 2. "UD1A,UD1A User Defined" "0,1" newline bitfld.byte 0x0 1. "IBF,The Input Buffer Full bit is set to indicate that a the ACPI_OS has written a command or data to the ACPI_EC and that data is ready." "0,1" bitfld.byte 0x0 0. "OBF,The Output Buffer Full bit is set to indicate that a the ACPI_EC has written a data to the ACPI_OS and that data is ready." "0,1" line.byte 0x1 "EC_BYTE_CTRL,Byte Control EC-Register" bitfld.byte 0x1 0. "FOUR_BYTE_ACCESS,When this bit is set to '1' the ACPI Embedded Controller Interface (ACPI-ECI) accesses four bytes through the ACPI-OS DATA BYTES[3:0]. When this bit is cleared to '0' the ACPI Embedded Controller Interface (ACPI-ECI) accesses one.." "0,1" group.long 0x108++0x3 line.long 0x0 "OS2EC_DATA,OS_TO_EC_DATA_BYTE_n. This is byte n of the 32-bit OS2EC DATA BYTES[3:0]. When the CMD bit in the OS STATUS OS Register is cleared to '0'. reads by the ACPI_EC from the OS2EC DATA BYTES[3:0] are aliased to the ACPI-OS DATA BYTES[3:0]." tree.end tree.end tree "ADC (Analog to Digital Converter)" base ad:0x40007C00 group.long 0x0++0x13 line.long 0x0 "CTRL,The ADC Control Register is used to control the behavior of the Analog to Digital Converter." bitfld.long 0x0 7. "SIN_DONE_STS,0: ADC single-sample conversion is not complete. 1: ADC single-sample conversion is completed. (R/WC)" "0: ADC single-sample conversion is not complete,1: ADC single-sample conversion is completed" bitfld.long 0x0 6. "RPT_DONE_STS,0: ADC repeat-sample conversion is not complete. 1: ADC repeat-sample conversion is completed. (R/WC)" "0: ADC repeat-sample conversion is not complete,1: ADC repeat-sample conversion is completed" newline bitfld.long 0x0 4. "SFT_RST,(SOFT_RESET) 1: writing one causes a reset of the ADC block hardware (not the registers) 0: writing zero takes the ADC block out of reset" "0: writing zero takes the ADC block out of reset,1: writing one causes a reset of the ADC block.." bitfld.long 0x0 3. "PWR_SAV_DIS,0: Power saving feature is enabled. 1: Power saving feature is disabled." "0: Power saving feature is enabled,1: Power saving feature is disabled" newline bitfld.long 0x0 2. "STRT_RPT,0: The ADC Repeat Mode is disabled. 1: The ADC Repeat Mode is enabled." "0: The ADC Repeat Mode is disabled,1: The ADC Repeat Mode is enabled" bitfld.long 0x0 1. "STRT_SIN,(START_SINGLE) 0: The ADC Single Mode is disabled. 1: The ADC Single Mode is enabled. Note: This bit is self-clearing" "0: The ADC Single Mode is disabled,1: The ADC Single Mode is enabled" newline bitfld.long 0x0 0. "ACT,0: The ADC is disabled and placed in its lowest power state. 1: ADC block is enabled for operation." "0: The ADC is disabled and placed in its lowest..,1: ADC block is enabled for operation" line.long 0x4 "DELAY,The ADC Delay register determines the delay from setting Start_Repeat in the ADC Control Register and the start of a conversion cycle. This register also controls the interval between conversion cycles in repeat mode." hexmask.long.word 0x4 16.--31. 1. "RPT_DLY,This field determines the interval between conversion cycles when Start_Repeat is 1." hexmask.long.word 0x4 0.--15. 1. "STRT_DLY,This field determines the starting delay before a conversion cycle is begun when Start_Repeat is written with a 1." line.long 0x8 "CHAN_STS,The ADC Status Register indicates whether the ADC has completed a conversion cycle. All bits are cleared by being written with a 1. 0: conversion of the corresponding ADC channel is not complete 1: conversion of the.." hexmask.long.word 0x8 0.--15. 1. "STS,All bits are cleared by being written with a '1'. 1=conversion of the corresponding ADC channel is complete; 0=conversion of the corresponding ADC channel is not complete. For enabled single cycles the SINGLE_DONE_STATUS bit in the ADC.." line.long 0xC "SNG_EN,The ADC Single Register is used to control which ADC channel is captured during a Single-Sample conversion cycle initiated by the Start_Single bit in the ADC Control Register. APPLICATION NOTE: Do not change the bits in this register.." hexmask.long.word 0xC 0.--15. 1. "S_EN,Each bit in this field enables the corresponding ADC channel when a single cycle of conversions is started when the START_SINGLE bit in the ADC Control Register is written with a 1. 1=single cycle conversions for this channel are enabled.." line.long 0x10 "REPT_EN,The ADC Repeat Register is used to control which ADC channels are captured during a repeat conversion cycle initiated by the Start_Repeat bit in the ADC Control Register." hexmask.long.word 0x10 0.--15. 1. "R_EN,Each bit in this field enables the corresponding ADC channel for each pass of the Repeated ADC Conversion that is controlled by bit START_REPEAT in the ADC Control Register. 1=repeat conversions for this channel are enabled; 0=repeat.." repeat 16. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x14)++0x3 line.long 0x0 "CHAN_RD[$1],All 16 ADC channels return their results into a 32-bit reading register. In each case the low 10 bits of the reading register return the result of the Analog to Digital conversion and the upper 22 bits return 0." repeat.end group.long 0x7C++0x13 line.long 0x0 "CFG,The ADC Configuration Register is used to configure the ADC clock timing." hexmask.long.byte 0x0 24.--31. 1. "DUMYCYC_GAP,These bits define the number of micro-seconds between consective Starts." hexmask.long.byte 0x0 20.--23. 1. "PWRUP_DLY,These bits define the power up delay in number of micro-seconds. Valid Values are from 0x0 to 0xF." newline hexmask.long.byte 0x0 16.--19. 1. "CLKDUMY_TIM,These bits define the dummy cycles of the ADC clock. Valid Values are from 0x0 to 0xF." hexmask.long.byte 0x0 8.--15. 1. "CLKHIGH_TIM,These bits define the high time count of the ADC clock. 0= not used. 1= 1 System Clock. 2= 2 System Clock." newline hexmask.long.byte 0x0 0.--7. 1. "CLKLW_TIM,These bits define the low time count of the ADC clock. 0= not used. 1= 1 System Clock. 2= 2 System Clock." line.long 0x4 "VREF_CHAN,The ADC Channel Register is used to configure the reference voltage to the clock timing." bitfld.long 0x4 30.--31. "SEL15,These bits define the reference voltage for Channel 15. 0h= VREF0 1h= VREF1 2h= Reserved 3h= Reserved" "0,1,2,3" bitfld.long 0x4 28.--29. "SEL14,These bits define the reference voltage for Channel 14. 0h= VREF0 1h= VREF1 2h= Reserved 3h= Reserved" "0,1,2,3" newline bitfld.long 0x4 26.--27. "SEL13,These bits define the reference voltage for Channel 13. 0h= VREF0 1h= VREF1 2h= Reserved 3h= Reserved" "0,1,2,3" bitfld.long 0x4 24.--25. "SEL12,These bits define the reference voltage for Channel 12. 0h= VREF0 1h= VREF1 2h= Reserved 3h= Reserved" "0,1,2,3" newline bitfld.long 0x4 22.--23. "SEL11,These bits define the reference voltage for Channel 11. 0h= VREF0 1h= VREF1 2h= Reserved 3h= Reserved" "0,1,2,3" bitfld.long 0x4 20.--21. "SEL10,These bits define the reference voltage for Channel 10. 0h= VREF0 1h= VREF1 2h= Reserved 3h= Reserved" "0,1,2,3" newline bitfld.long 0x4 18.--19. "SEL9,These bits define the reference voltage for Channel 9. 0h= VREF0 1h= VREF1 2h= Reserved 3h= Reserved" "0,1,2,3" bitfld.long 0x4 16.--17. "SEL8,These bits define the reference voltage for Channel 8. 0h= VREF0 1h= VREF1 2h= Reserved 3h= Reserved" "0,1,2,3" newline bitfld.long 0x4 14.--15. "SEL7,These bits define the reference voltage for Channel 7. 0h= VREF0 1h= VREF1 2h= Reserved 3h= Reserved" "0,1,2,3" bitfld.long 0x4 12.--13. "SEL6,These bits define the reference voltage for Channel 6. 0h= VREF0 1h= VREF1 2h= Reserved 3h= Reserved" "0,1,2,3" newline bitfld.long 0x4 10.--11. "SEL5,These bits define the reference voltage for Channel 5. 0h= VREF0 1h= VREF1 2h= Reserved 3h= Reserved" "0,1,2,3" bitfld.long 0x4 8.--9. "SEL4,These bits define the reference voltage for Channel 4. 0h= VREF0 1h= VREF1 2h= Reserved 3h= Reserved" "0,1,2,3" newline bitfld.long 0x4 6.--7. "SEL3,These bits define the reference voltage for Channel 3. 0h= VREF0 1h= VREF1 2h= Reserved 3h= Reserved" "0,1,2,3" bitfld.long 0x4 4.--5. "SEL2,These bits define the reference voltage for Channel 2. 0h= VREF0 1h= VREF1 2h= Reserved 3h= Reserved" "0,1,2,3" newline bitfld.long 0x4 2.--3. "SEL1,These bits define the reference voltage for Channel 1. 0h= VREF0 1h= VREF1 2h= Reserved 3h= Reserved" "0,1,2,3" bitfld.long 0x4 0.--1. "SEL0,These bits define the reference voltage for Channel 0. 0h= VREF0 1h= VREF1 2h= Reserved 3h= Reserved" "0,1,2,3" line.long 0x8 "VREF_CTRL,This is the VREF Control Register" bitfld.long 0x8 30.--31. "SELSTAT,This fields gives information about the current VREF selected. 0x0= VREF0 0x1= VREF1 0x2= Reserved 0x3= Reserved" "0: VREF0,1: VREF1,2: Reserved,3: Reserved" bitfld.long 0x8 29. "PADCTRL,This fields give the choice to the application whether to float the unused PAD's or to Drive them to 0. 1= Drive unused PAD's Low 0b 0= Leave unused PAD's Floating." "0: Leave unused PAD's Floating,1: Drive unused PAD's Low 0b" newline hexmask.long.word 0x8 16.--28. 1. "SWITCH_DLY,This field represnts the delay time interval between switching VREF Selects." hexmask.long.word 0x8 0.--15. 1. "CHRG_DLY,This field represnts the delay time to charge up the external VREF capacitor." line.long 0xC "SAR_CTRL,This is the SAR ADC Control Register." hexmask.long.word 0xC 7.--15. 1. "WARM_UP_DLY,This field represents the warmup delay number in microseconds." bitfld.long 0xC 5. "EN_SERIAL,This field enables serial output (dout) from ADC. 0= Parallel dout. 1= Serial dout." "0: Parallel dout,1: Serial dout" newline bitfld.long 0xC 4. "EN_ASYN_SMPL,This field enables asynchronous sampling. 0= Async Sampling Disabled. 1= Async Sampling Enabled." "0: Async Sampling Disabled,1: Async Sampling Enabled" bitfld.long 0xC 3. "SHIFT_DAT,This field defined if the ADC output is Right or Left Justified. 1= adc_dout is not shifted and lower bits are set to 0. 0= adc_dout is shifted right following resolution selected." "0: adc_dout is shifted right following resolution..,1: adc_dout is not shifted and lower bits are set.." newline bitfld.long 0xC 1.--2. "SEL_RES,This field select the ADC Resolution (10/12 bits). 0x0= Reserved. 0x1= Reserved. 0x2= 10 bit ADC resolution. 0x3= 12 bit ADC resolution." "0: Reserved,1: Reserved,2: 10 bit ADC resolution,3: 12 bit ADC resolution" bitfld.long 0xC 0. "SEL_DIFF,This field select between Single ended / Differential input. 0= ADC core is enabled for single ended input operation. 1= ADC core is enabled for differential input operation." "0: ADC core is enabled for single ended input..,1: ADC core is enabled for differential input.." line.long 0x10 "SAR_CFG,This is the SAR ADC Configuration Register." bitfld.long 0x10 31. "EN_EXT_BIAS,EN external bias. 1 = Disables internal switched cap bias circuit. 0 = Enables internal switched cap bias circuit." "0: Enables internal switched cap bias circuit,1: Disables internal switched cap bias circuit" bitfld.long 0x10 28.--29. "ICMBF,This register controls the bias current for common mode buffer amplifier." "0,1,2,3" newline bitfld.long 0x10 26.--27. "ICMBF_STG2,This register controls the bias current for the 2nd stage of the comparator." "0,1,2,3" bitfld.long 0x10 24.--25. "ICMBF_STG1,This register controls the bias current for the 1st stage of the comparator." "0,1,2,3" newline bitfld.long 0x10 22.--23. "IADC_RANGE1,This register controls the current consumption for the whole ADC." "0,1,2,3" bitfld.long 0x10 20.--21. "IADC_RANGE2,This register controls the current consumption for the whole ADC." "0,1,2,3" newline hexmask.long.byte 0x10 11.--15. 1. "CLK_DIV,This register defines the programmable ADC Clock divider value. Divider ratios of 256 128 64 32 16 are supported." bitfld.long 0x10 9.--10. "REGEN_DLY,This register defines the delay between regen and latch." "0,1,2,3" newline bitfld.long 0x10 6. "EN_RADC,Enable RADC. 1 = RDAC remains high during power cycling. 0 = Controls RDAC during power cycling." "0: Controls RDAC during power cycling,1: RDAC remains high during power cycling" bitfld.long 0x10 5. "LAZ_AU_ZERO,Enable L_AZ AUTOZEROING. 1= Disable L_AZ autozeroing. 0= Enable L_AZ autozeroing." "0: Enable L_AZ autozeroing,1: Disable L_AZ autozeroing" newline bitfld.long 0x10 4. "SAZ_AU_ZERO,Enable S_AZ AUTOZEROING. 1= Disable S_AZ autozeroing. 0= Enable S_AZ autozeroing." "0: Enable S_AZ autozeroing,1: Disable S_AZ autozeroing" bitfld.long 0x10 3. "FAZ_AU_ZERO,Enable F_AZ AUTOZEROING. 1= Disable f_az autozeroing. 0= Enable f_az autozeroing." "0: Enable f_az autozeroing,1: Disable f_az autozeroing" newline bitfld.long 0x10 2. "EN_DITHER,Enable Dithering. 0= Disable Dither. 1= Enable Dither." "0: Disable Dither,1: Enable Dither" bitfld.long 0x10 1. "DIS_DOUT,Disable Parallel Output. 0= Enable Parallel Output. 1= Disable Parallel Output." "0: Enable Parallel Output,1: Disable Parallel Output" newline bitfld.long 0x10 0. "EN_CMBF,Enable Common Mode Buffer Amplifier. 0= Common Mode Buffer Amplifier is high all the time. 1= Controls Common Mode Buffer Amplifier during power cycling." "0: Common Mode Buffer Amplifier is high all the time,1: Controls Common Mode Buffer Amplifier during.." tree.end tree "ASIF" base ad:0x400FC000 group.byte 0x0++0x1 line.byte 0x0 "HOST_BAL,LPC BAL Register" hexmask.byte 0x0 0.--7. 1. "LPC_BAL,Nominally the low-byte of the block's LPC base address. This register has no function. It is provided for legacy reasons." line.byte 0x1 "HOST_BAH,LPC BAH Register." hexmask.byte 0x1 0.--7. 1. "LPC_BAH,Nominally the high-byte of the block's LPC base address. This register has no function. It is provided for legacy reasons." repeat 10. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2+0x2)++0x0 line.byte 0x0 "SCRATCH[$1],Scratch 0 Register" hexmask.byte 0x0 0.--7. 1. "SCR,This field has no functionality other than storage. This register is aliased to EC-Only Register." repeat.end group.byte 0xC++0x1 line.byte 0x0 "HOST_AIXL,LPC AIXL Register" hexmask.byte 0x0 0.--7. 1. "LPC_IND_LOW,Low-byte of the 10-bit index from the LPC interface." line.byte 0x1 "HOST_AIXH,LPC AIXH Register" bitfld.byte 0x1 7. "LPC_ACCESS_MODE,1=Synchronous mode: the host would poll the LPC Status Register after issuing a command. When the LPC_IF_BUSY bit is cleared write data has been latched by the external IC or read data has been fetched into the LPC Data In Register." "0: Atomic access mode,1: Synchronous mode: the host would poll the LPC.." bitfld.byte 0x1 0.--1. "LPC_IND_HI,Most significant two bits of the 10-bit index from the LPC interface." "0,1,2,3" rgroup.byte 0xE++0x0 line.byte 0x0 "HOST_DATA_IN,LPC Data In Register" hexmask.byte 0x0 0.--7. 1. "LPC_DATA_IN,This register contains data read from the external ASIC. This register shares an offset with LPC Data Out Register. After a read command is issued software reads from this register when LPC_IF_BUSY='0' and LPC_OBF= 1." wgroup.byte 0xE++0x0 line.byte 0x0 "HOST_DATA_OUT,LPC Data Out Register" hexmask.byte 0x0 0.--7. 1. "LPC_DATA_OUT,This register contains write data targeting the external ASIC. This register shares an offset with LPC Data In Register. Writes to this register are ignored while LPC_IF_BUSY is 1 i.e. until write data has been transferred to the.." group.byte 0xF++0x0 line.byte 0x0 "HOST_STS,LPC Status Register" bitfld.byte 0x0 3. "LPC_IBF,LPC Input Buffer Full. This bit is set to 1 after the host issues a write command. The bit is reset to 0 when the SPI write transfer to the external IC has completed." "0,1" bitfld.byte 0x0 2. "LPC_OBF,LPC Output Buffer Full. This bit is set to 1 after read data from the external IC has been latched into the LPC Data In Register. Cleared after the ASIF returns read data to the host. This register is aliased to EC-Only Register." "0,1" newline bitfld.byte 0x0 1. "LPC_IF_BUSY,LPC Interface Busy also known as Host Command in Progress. The bit is set to 1 when the Host issues a command to the LPC interface by either reading from the LPC Data In Register or writing to the LPC Data Out Register. The bit is.." "0,1" bitfld.byte 0x0 0. "EC_IF_BUSY,EC Interface Busy. Set to 1 when the EC issues a read or write to the EC_DAT Register. Set to 0 when the SPI transfer to the external ASIC that is triggered by the EC register access is completed. This is the same bit as EC_IF_BUSY in the.." "0,1" group.byte 0x100++0x1 line.byte 0x0 "EC_AIXL,EC AIXL Register" hexmask.byte 0x0 0.--7. 1. "IND_LOW,Low-byte of the 10-bit index from the EC interface." line.byte 0x1 "EC_AIXH,EC AIXH Register" bitfld.byte 0x1 7. "EC_ACCESS_MODE,0: Atomic access mode. EC cycles to Data register will be blocked until current LPC request is serviced 1: Synchronous mode: EC polls the EC Status Register after issuing a command. When EC-IF Busy bit is cleared write data has.." "0: Atomic access mode,1: Synchronous mode: EC polls the EC Status.." bitfld.byte 0x1 0.--1. "EC_IND_HI,Most significant two bits of the 10-bit index from the EC interface." "0,1,2,3" rgroup.byte 0x102++0x0 line.byte 0x0 "EC_DATA_IN,EC Data In Register" hexmask.byte 0x0 0.--7. 1. "DATA,This register contains data read from the external ASIC. This register shares an offset with EC Data Out Register. After a read command is issued software reads from this register when EC_IF_BUSY='0' and EC_OBF= 1." wgroup.byte 0x102++0x0 line.byte 0x0 "EC_DATA_OUT,EC Data Out Register" hexmask.byte 0x0 0.--7. 1. "EC_DATA_OUT,This register contains write data targeting the external ASIC. This register shares an offset with EC Data In Register. Writes to this register are ignored while EC_IF_BUSY is 1 i.e. until write data has been transferred to the.." group.byte 0x103++0x2 line.byte 0x0 "EC_STS,EC Status Register" bitfld.byte 0x0 4. "EC_TX_DONE,EC Transmission Done. This bit is set to 1 when a write transfer to the external IC is completed. It is cleared when it is written with a 0." "0,1" bitfld.byte 0x0 3. "EC_IBF,EC Input Buffer Full. This bit is set to 1 when the EC issues a write command to the Auxiliary SPI Interface. This bit is cleared to 0 after transfer to the external IC has completed." "0,1" newline bitfld.byte 0x0 2. "EC_OBF,EC Output Buffer Full. This bit is set to 1 after read data from the external IC has been latched into the EC Data In Register. This bit is cleared to 0 after the register has been read." "0,1" bitfld.byte 0x0 1. "EC_IF_BUSY,This bit is set to 1 when the EC issues a command to the Auxiliary SPI Interface. This bit is cleared to 0 when the corresponding SPI transfer to the external IC is completed. This bit is the same as EC_IF_BUSY in the LPC Status Register." "0,1" newline bitfld.byte 0x0 0. "LPC_IF_BUSY,This bit is set to 1 when the Host issues a command to the Auxiliary SPI Interface. This bit is cleared to 0 when the corresponding SPI transfer to the external IC is completed. This bit is the same as the LPC_IF_BUSY bit in the LPC.." "0,1" line.byte 0x1 "EC_BAL,EC BAL Register" hexmask.byte 0x1 0.--7. 1. "LPC_BAL,Nominally the low-byte of the block's LPC base address. This register is a writable alias of the LPC BAL Register. This register has no function. It is provided for legacy reasons." line.byte 0x2 "EC_BAH,EC BAH Register." hexmask.byte 0x2 0.--7. 1. "LPC_BAH,Nominally the high-byte of the block's LPC base address. This register is a writable alias of the LPC BAH Register. This register has no function. It is provided for legacy reasons." group.long 0x110++0xB line.long 0x0 "EC_IEN,EC Interrupt Enable Register" bitfld.long 0x0 7. "TIMEOUT_IE,Timeout Interrupt Enable. 1=Enable interrupt when Timeout Counter expires 0=Timeout interrupts disabled." "0: Timeout interrupts disabled,1: Enable interrupt when Timeout Counter expires" bitfld.long 0x0 6. "WR_DONE_IE,Write Done Interrupt Enable. 1=Enable interrupt when transfer of write data to the external IC is complete (when the status bit EC_WR_DONE is 1) 0=Write Done interrupts disabled." "0: Write Done interrupts disabled,1: Enable interrupt when transfer of write data to.." newline bitfld.long 0x0 5. "RD_DONE_IE,Read Done Interrupt Enable. 1=Enable interrupt when read data from the external IC is available for the EC (when the status bit EC_RD_DONE is 1) 0=Read Done interrupts disabled" "0: Read Done interrupts disabled,1: Enable interrupt when read data from the.." bitfld.long 0x0 4. "EC_CMDDONE_IE,EC Command Done Interrupt Enable. 1=Enable interrupt when the transaction to the external IC is complete (when the status bit EC_CMD_DONE is 1) 0=Command Done interrupts disabled." "0: Command Done interrupts disabled,1: Enable interrupt when the transaction to the.." line.long 0x4 "EC_ISTS,EC Interrupt Status Register" bitfld.long 0x4 7. "LOCKED_TO,Locked Timeout. This bit is set to 1 when the Timeout Counter Register counts down to 0 indicating the Auxiliary Serial Interface is reset due to a time-out event. Although this bit is cleared to 0 on a Soft Reset that is generated by a.." "0,1" bitfld.long 0x4 6. "WR_DONE,Write Done Status.This bit is set to 1 when EC write data has been transfered to the external IC (when EC_IF_BUSY is cleared). This bit is cleared when written with a 1. Writes of a 0 have no effect." "0,1" newline bitfld.long 0x4 5. "RD_DONE,Read Done Status.This bit is set to 1 when the external IC returns data to the EC as a result of an EC read command. This bit is cleared when written with a 1. Writes of a 0 have no effect." "0,1" bitfld.long 0x4 4. "CMD_DONE,EC Command Done Status. This bit is set to 1 when the SPI transfer to service an EC command to the external IC either read or write has completed. This bit is cleared when written with a 1. Writes of a 0 have no effect." "0,1" line.long 0x8 "EC_TMOUT_CNTR,Timeout Counter Register." hexmask.long.byte 0x8 0.--7. 1. "TIMEOUT_CNT,Timeout period in number of 100KHz cycles -1. Reads return the current count value." group.long 0x120++0x3 line.long 0x0 "EC_BLK_CFG,Block Configuration Register" bitfld.long 0x0 1. "SOFT_RST,Set to 1 to issue a soft reset to the block. Soft reset has similar effect as a hardware power-on reset except that register settings other than status bits remain unchanged. This bit is self-clearing. The interface bus signals after a soft.." "0,1" bitfld.long 0x0 0. "ACT,1=Block is operational 0=Block is disabled. Clocks are gated to conserve power and output signals are set to their inactive state. The block must finish all outstanding transactions on both SPI and LPC/EC logical interfaces before it can.." "0: Block is disabled,1: Block is operational" group.long 0x130++0xF line.long 0x0 "EC_SPI_CLK_GEN,SPI Clock Generator Register." hexmask.long.byte 0x0 0.--5. 1. "PRELD,SPI Clock Generator Preload value." line.long 0x4 "EC_SPI_CTRL,SPI Control Register" bitfld.long 0x4 2.--3. "SPDIN_SEL,The SPDIN Select which SPI input signals are enabled when the BIOEN bit is configured as an input. 1xb=SPDIN1 and SPDIN2. Select this option for Dual Mode 01b=SPDIN2 only. Select this option for Half Duplex 00b=SPDIN1 only." "0,1,2,3" bitfld.long 0x4 1. "BIOEN,Bidirectional Output Enable control. When the SPI is configured for Half Duplex mode or Dual Mode the SPDOUT pin operates as a bidirectional signal. The BIOEN bit is used by the internal DIRECTION bit to control the direction of the SPDOUT.." "0: The SPDOUT_Direction signal configures the..,1: The SPDOUT_Direction signal configures the.." newline bitfld.long 0x4 0. "LSBF,Least Significant Bit First. 1= The data is transferred in LSB-first order. 0= The data is transferred in MSB-first order. (default)." "0: The data is transferred in MSB-first order,1: The data is transferred in LSB-first order" line.long 0x8 "EC_SPI_CLK_CTRL,SPI Clock Control Register" bitfld.long 0x8 5. "TEST,This bit must remain at 1 its reset default for correct operation." "0,1" bitfld.long 0x8 4. "CLKSRC,Clock Source for the SPI Clock Generator. This bit should not be changed during a SPI transaction. When the field PRELOAD in the SPI Clock Generator Register is 0 this bit is ignored and the Clock Source is always the main system clock (the.." "0: 48MHz,1: 2MHz" newline bitfld.long 0x8 2. "CLKPOL,SPI Clock Polarity. 1=The SPI_CLK signal is high when the interface is idle and the first clock edge is a falling edge 0=The SPI_CLK is low when the interface is idle and the first clock edge is a rising edge." "0: The SPI_CLK is low when the interface is idle..,1: The SPI_CLK signal is high when the interface is.." bitfld.long 0x8 1. "RCLKPH,Receive Clock Phase the SPI_CLK edge on which the master will sample data. The receive clock phase is not affected by the SPI Clock Polarity. 1=Valid data on SPDIN signal is expected after the first SPI_CLK edge. This data is sampled on the.." "0: Valid data is expected on the SPDIN signal on..,1: Valid data on SPDIN signal is expected after the.." newline bitfld.long 0x8 0. "TCLKPH,Transmit Clock Phase the SPCLK edge on which the master will clock data out. The transmit clock phase is not affected by the SPI Clock Polarity. 1=Valid data is clocked out on the first SPI_CLK edge on SPDOUT signal. The slave device should.." "0: Valid data is clocked out on the SPDOUT signal..,1: Valid data is clocked out on the first SPI_CLK.." line.long 0xC "EC_SPI_EN,SPI Enable Register" bitfld.long 0xC 7. "TXBUSY,Transmit Busy. 1=Set when a SPI write transfer to external IC is started. Cleared when the transfer is completed 0=Transmit channel idle." "0: Transmit channel idle,1: Set when a SPI write transfer to external IC is.." bitfld.long 0xC 6. "RXBUSY,Receive Busy. 1=Set when a SPI read transfer to external IC is started. Cleared when the transfer is completed 0=Receive channel idle." "0: Receive channel idle,1: Set when a SPI read transfer to external IC is.." newline bitfld.long 0xC 3. "TXEN,SPI Transmit transfer enable. 1=SPI write transfer is enabled 0=SPI write transfer is disabled. Write commands received at the LPC and EC interfaces will not result in SPI transfers to IC i.e. address and write data are not shifted out." "0: SPI write transfer is disabled,1: SPI write transfer is enabled" bitfld.long 0xC 2. "RXEN,SPI Receive transfer enable. 1=SPI read transfer is enabled 0=SPI read transfer is disabled. Read commands received at the LPC and EC interfaces will not result in SPI transfers to IC i.e. address is not shifted out and read data not.." "0: SPI read transfer is disabled,1: SPI read transfer is enabled" tree.end tree "BC_LINK" base ad:0x0 tree "BC_LINK0" base ad:0x4000CD00 group.long 0x0++0xF line.long 0x0 "STS,BC-Link Status" bitfld.long 0x0 7. "RESET,When this bit is '1'the BC_Link Master Interface will be placed in reset and be held in reset until this bit is cleared to '0'. Setting RESET to '1' causes the BUSY bit to be set to '1'. The BUSY remains set to '1' until the reset operation of the.." "0,1" bitfld.long 0x0 6. "ERROR,This bit indicates that a BC Bus Error has occurred. (R/WC)" "0,1" bitfld.long 0x0 5. "ERR_INT_EN,This bit is an enable for generating an interrupt when the BC_ERR bit is set by hardware. When this bit is '1' the interrupt signal is enabled. When this bit is '0' the interrupt is disabled." "0,1" bitfld.long 0x0 4. "BUSY_CLR_INT_EN,This bit is an enable for generating an interrupt when the BUSY bit in this register is cleared by hardware. When this bit is set to '1' the interrupt signal is enabled. When the this bit is cleared to '0' the interrupt is disabled." "0,1" bitfld.long 0x0 0. "BUSY,This bit is asserted to '1' when the BC interface is transferring data and on reset." "0,1" line.long 0x4 "ADDR,BC-Link Address Register [7:0] Address in the Companion for the BC-Link transaction." line.long 0x8 "DATA,BC-Link Data Register [7:0] this register hold data used in a BC-Link transaction." line.long 0xC "CLK_SEL,BC-Link Clock Select Register [7:0] DIVIDER The BC Clock is set to the Master Clock divided by this field. or 48MHz/ (Divider +1). The clock divider bits can only can be changed when the BC Bus is in soft RESET (when either the Reset bit is set.." tree.end tree.end tree "CACHE (CACHE Controller)" base ad:0x40010000 group.long 0x0++0x3 line.long 0x0 "MODE,CACHE MODE register." bitfld.long 0x0 5. "INVALIDATE_ALL,INVALIDATE all CACHE lines." "0,1" bitfld.long 0x0 4. "FULL_LINE_RD_EN,Full line read enable. 0: Critical section first and early termination enabled. 1: Critical section first and early termination disabled." "0: Critical section,1: Critical section" newline bitfld.long 0x0 3. "CONNECT_MODE,CACHE connection mode. 0: eSPI SAF EC." "0: eSPI SAF EC,?" bitfld.long 0x0 2. "SPI_ENABLE,CACHE SPI Enable. 0: Standard register access. 1: Cache takes over the register interface of eSPI SAF EC" "0: Standard register access,1: Cache takes over the register interface of eSPI.." newline bitfld.long 0x0 1. "SOFT_RESET,Soft reset the Cache Controller module. This is self clearing bit. Write Only bit" "0,1" bitfld.long 0x0 0. "ACTIVATE,ACTIVATE 0: Disable block. 1: Enable block." "0: Disable block,1: Enable block" group.long 0xC++0x3 line.long 0x0 "SPI_BANK,CSPI Bank. This is ORed into the access address from the processor to create the address sent over to the SPI Flash." wgroup.long 0x10++0x3 line.long 0x0 "TAG_VLDT,CACHE TAG VALIDATE register." bitfld.long 0x0 3. "TAG_FORCE_INVALIID,Tag Force Invalid. Will invalidate the address pointed by Tag Validate Address register. 0: No action. 1: Invalidate address." "0: No action,1: Invalidate address" bitfld.long 0x0 2. "TAG_FORCE_FILL,Tag Force Fill. Will cause the cache to immediately fill this cache line. 0: Line will not be filled until it is Miss/Fill. 1: Line will auto fill immediately" "0: Line will not be filled until it is Miss/Fill,1: Line will auto fill immediately" newline bitfld.long 0x0 1. "TAG_FORCE_LOCK,Tag Force Lock. Will lock the cache line. 0: Line will not be locked. 1: Line will be locked." "0: Line will not be locked,1: Line will be locked" bitfld.long 0x0 0. "TAG_FORCE,Tag Force. This bit will allow the cache select a Tag line and allocate the Cache Tag Validate Address to it. 0: No action. 1: A tag line will be allocated" "0: No action,1: A tag line will be allocated" group.long 0x14++0x3 line.long 0x0 "TAG_VLDT_ADDR,Tag Force Address. This is the address that will be stored in the Tag Line and accessed over SPI if a Tag Force is issued. This address is still used in conjunction with the Cache SPI Bank.This is meant to be an address from the.." group.long 0x20++0x3 line.long 0x0 "STS,CACHE STATUS register" bitfld.long 0x0 2. "SPI_ERR,Indicates CACHE Line Fill error from Flash memory" "0,1" bitfld.long 0x0 1. "INVALIDATE_DONE,Invalidate Done. This bit is set when invalidate command has completed." "0,1" newline bitfld.long 0x0 0. "VALIDATE_DONE,Validate Done. This bit is set when Validate command has completed." "0,1" group.long 0x40++0x7 line.long 0x0 "HIT_HI,Hit count Hi. Stores the Hit Count [63:32] of the Cache" line.long 0x4 "HIT_LOW,Hit count low. Stores the Hit Count [31:0] of the Cache" group.long 0x50++0x7 line.long 0x0 "MISS_HI,Miss count Hi. Stores the Miss Count [63:32] of the Cache" line.long 0x4 "MISS_LOW,Miss count low. Stores the Miss Count [31:0] of the Cache" group.long 0x60++0x7 line.long 0x0 "FILL_HI,Fill count Hi. Stores the Fill Count [63:32] of the Cache" line.long 0x4 "FILL_LOW,Fill count low. Stores the Fill Count [31:0] of the Cache" repeat 16. (increment 0x0 0x1)(increment 0x0 0x4) wgroup.long ($2+0xC0)++0x3 line.long 0x0 "RX_BUFFER[$1],Rx Buffer0." repeat.end group.long 0x800++0x7 line.long 0x0 "TAG_LOCK0,Tag Lock0. 0: Tag is not Locked. 1: Tag is Locked." line.long 0x4 "TAG_LOCK1,Tag Lock1. 0: Tag is not Locked. 1: Tag is Locked." rgroup.long 0xC00++0x7 line.long 0x0 "TAG_VALID0,Tag Valid0. Tells Line has valid data in the cache. 0: Line is empty. 1: Line is full." line.long 0x4 "TAG_VALID1,Tag Valid1. Tells Line has valid data in the cache. 0: Line is empty. 1: Line is full." repeat 64. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x1000)++0x3 line.long 0x0 "TAG_ADDR[$1],Tag Address0." repeat.end tree.end tree "CCT (Capture Compare Timer)" base ad:0x40001000 group.long 0x0++0x33 line.long 0x0 "CTRL,This register controls the capture and compare timer." bitfld.long 0x0 25. "CMP_CLR0,When read returns the current value off the Compare Timer Output 0 state." "0,1" bitfld.long 0x0 24. "CMP_CLR1,When read returns the current value off the Compare Timer Output 1 state." "0,1" bitfld.long 0x0 17. "CMP_SET0,When read returns the current value off the Compare Timer Output 0 state." "0,1" bitfld.long 0x0 16. "CMP_SET1,When read returns the current value off the Compare Timer Output 1 state." "0,1" bitfld.long 0x0 9. "CMP_EN1,Compare Enable for Compare 1 Register." "0,1" bitfld.long 0x0 8. "CMP_EN0,Compare Enable for Compare 0 Register." "0,1" bitfld.long 0x0 4.--6. "TCLK,This 3-bit field sets the clock source for the Free-Running Counter." "0,1,2,3,4,5,6,7" bitfld.long 0x0 2. "FREE_RST,Free Running Timer Reset. This bit stops the timer and resets the internal counter to 0000_0000h." "0,1" newline bitfld.long 0x0 1. "FREE_EN,Free-Running Timer Enable. This bit is used to start and stop the free running timer." "0,1" bitfld.long 0x0 0. "ACT,This bit is used to start the capture and compare timer running and power it down." "0,1" line.long 0x4 "CAP0_CTRL,This register is used to configure capture and compare timers 0-3." bitfld.long 0x4 29.--31. "FCLK_SEL3,This 3-bit field sets the clock source for the input filter for Capture Register 3." "0,1,2,3,4,5,6,7" bitfld.long 0x4 26. "FILTER_BYP3,This bit enables bypassing the input noise filter for Capture Register 3 so that the input signal goes directly into the timer." "0,1" bitfld.long 0x4 24.--25. "CAP_EDGE3,This field selects the edge type that triggers the capture of the Free Running Counter into Capture Register 3." "0,1,2,3" bitfld.long 0x4 21.--23. "FCLK_SEL2,This 3-bit field sets the clock source for the input filter for Capture Register 2." "0,1,2,3,4,5,6,7" bitfld.long 0x4 18. "FILTER_BYP2,This bit enables bypassing the input noise filter for Capture Register 2 so that the input signal goes directly into the timer." "0,1" bitfld.long 0x4 16.--17. "CAP_EDGE2,This field selects the edge type that triggers the capture of the Free Running Counter into Capture Register 2." "0,1,2,3" bitfld.long 0x4 13.--15. "FCLK_SEL1,This 3-bit field sets the clock source for the input filter for Capture Register 1." "0,1,2,3,4,5,6,7" bitfld.long 0x4 10. "FILTER_BYP1,This bit enables bypassing the input noise filter for Capture Register 1 so that the input signal goes directly into the timer." "0,1" newline bitfld.long 0x4 8.--9. "CAP_EDGE1,This field selects the edge type that triggers the capture of the Free Running Counter into Capture Register 1." "0,1,2,3" bitfld.long 0x4 5.--7. "FCLK_SEL0,This 3-bit field sets the clock source for the input filter for Capture Register 0." "0,1,2,3,4,5,6,7" bitfld.long 0x4 2. "FILTER_BYP0,This bit enables bypassing the input noise filter for Capture Register 0 so that the input signal goes directly into the timer." "0,1" bitfld.long 0x4 0.--1. "CAP_EDGE0,This field selects the edge type that triggers the capture of the Free Running Counter into Capture Register 0." "0,1,2,3" line.long 0x8 "CAP1_CTRL,This register is used to configure capture and compare timers 4-5." bitfld.long 0x8 13.--15. "FCLK_SEL5,This 3-bit field sets the clock source for the input filter for Capture Register 5." "0,1,2,3,4,5,6,7" bitfld.long 0x8 10. "FILTER_BYP5,This bit enables bypassing the input noise filter for Capture Register 5 so that the input signal goes directly into the timer." "0,1" bitfld.long 0x8 8.--9. "CAP_EDGE5,This field selects the edge type that triggers the capture of the Free Running Counter into Capture Register 5." "0,1,2,3" bitfld.long 0x8 5.--7. "FCLK_SEL4,This 3-bit field sets the clock source for the input filter for Capture Register 4." "0,1,2,3,4,5,6,7" bitfld.long 0x8 2. "FILTER_BYP4,This bit enables bypassing the input noise filter for Capture Register 4 so that the input signal goes directly into the timer." "0,1" bitfld.long 0x8 0.--1. "CAP_EDGE4,This field selects the edge type that triggers the capture of the Free Running Counter into Capture Register 4." "0,1,2,3" line.long 0xC "FREE_RUN,This register contains the current value of the Free Running Timer." hexmask.long 0xC 0.--31. 1. "TMR,This register contains the current value of the Free Running Timer." line.long 0x10 "CAP0,This register saves the value copied from the Free Running timer on a programmed edge of ICT0." hexmask.long 0x10 0.--31. 1. "CAP_0,This register saves the value copied from the Free Running timer on a programmed edge of ICT0." line.long 0x14 "CAP1,This register saves the value copied from the Free Running timer on a programmed edge of ICT1." hexmask.long 0x14 0.--31. 1. "CAP_1,This register saves the value copied from the Free Running timer on a programmed edge of ICT1." line.long 0x18 "CAP2,This register saves the value copied from the Free Running timer on a programmed edge of ICT0." hexmask.long 0x18 0.--31. 1. "CAP_2,This register saves the value copied from the Free Running timer on a programmed edge of ICT2." line.long 0x1C "CAP3,This register saves the value copied from the Free Running timer on a programmed edge of ICT0." hexmask.long 0x1C 0.--31. 1. "CAP_3,This register saves the value copied from the Free Running timer on a programmed edge of ICT3." line.long 0x20 "CAP4,This register saves the value copied from the Free Running timer on a programmed edge of ICT4." hexmask.long 0x20 0.--31. 1. "CAP_4,This register saves the value copied from the Free Running timer on a programmed edge of ICT4." line.long 0x24 "CAP5,This register saves the value copied from the Free Running timer on a programmed edge of ICT5." hexmask.long 0x24 0.--31. 1. "CAP_5,This register saves the value copied from the Free Running timer on a programmed edge of ICT5." line.long 0x28 "COMP0,A COMPARE 0 interrupt is generated when this register matches the value in the Free Running Timer." hexmask.long 0x28 0.--31. 1. "COMP_0,A COMPARE 0 interrupt is generated when this register matches the value in the Free Running Timer." line.long 0x2C "COMP1,A COMPARE 1 interrupt is generated when this register matches the value in the Free Running Timer." hexmask.long 0x2C 0.--31. 1. "COMP_1,A COMPARE 1 interrupt is generated when this register matches the value in the Free Running Timer." line.long 0x30 "MUX_SEL,This register selects the pin mapping to the capture register." hexmask.long.byte 0x30 20.--23. 1. "CAP5,Mux Select for Capture 5 register." hexmask.long.byte 0x30 16.--19. 1. "CAP4,Mux Select for Capture 4 register." hexmask.long.byte 0x30 12.--15. 1. "CAP3,Mux Select for Capture 3 register." hexmask.long.byte 0x30 8.--11. 1. "CAP2,Mux Select for Capture 2 register." hexmask.long.byte 0x30 4.--7. 1. "CAP1,Mux Select for Capture 1 register." hexmask.long.byte 0x30 0.--3. 1. "CAP0,Mux Select for Capture 0 register." tree.end tree "CNTR_TMR (16-bit Counter-Timer Interface)" base ad:0x0 tree "CNTR_TMR0" base ad:0x40000D00 group.long 0x0++0xF line.long 0x0 "TIMERX_CONTROL,This bit reflects the current state of the timer's Clock_Required output signal." bitfld.long 0x0 12. "TIMERX_CLK_REQ,This bit reflects the current state of the timer's Clock_Required output signal. 1=The main clock is required by this block; 0=The main clock is not required by this block." "0: The main clock is not required by this block,1: The main clock is required by this block" bitfld.long 0x0 11. "SLEEP_ENABLE,This bit reflects the current state of the timer's Sleep_Enable input signal. 1=Normal operation; 0=Sleep Mode is requested." "0: Sleep Mode is requested,1: Normal operation" newline bitfld.long 0x0 10. "TOUT_POLARITY,This bit determines the polarity of the TOUTx output signal. In timer modes that toggle the TOUTx signal this polarity bit will not have a perceivable difference except to determine the inactive state. In One-Shot mode.." "0: Active high,1: Active low" bitfld.long 0x0 9. "PD,Power Down. 1=The timer is powered down and all clocks are gated; 0=The timer is in a running state." "0: The timer is in a running state,1: The timer is powered down and all clocks are gated" newline bitfld.long 0x0 8. "FILTER_BYPASS,This bit is used to enable or disable the noise filter on the TINx input signal. 1=Bypass Mode: input filter disabled. The TINx input directly affects the timer; 0=Filter Mode: input filter enabled. The TINx input is.." "0: Filter Mode: input filter enabled,1: Bypass Mode: input filter disabled" bitfld.long 0x0 7. "RLOAD,Reload Control. This bit controls how the timer is reloaded on overflow or underflow in Event and Timer modes. It has no effect in One shot mode. 1=Reload timer from Timer Reload Register and continue counting;.." "0: Roll timer over to FFFFh and continue counting..,1: Reload timer from Timer Reload Register and.." newline bitfld.long 0x0 6. "TOUT_EN,This bit enables the TOUTx pin. 1=TOUTx pin function is enabled; 0=TOUTx pin is inactive." "0: TOUTx pin is inactive,1: TOUTx pin function is enabled" bitfld.long 0x0 5. "UPDN,In Event Mode this bit selects the timer count direction. In Timer Mode enables timer control by the TINx input pin. Event Mode: 1=The timer counts up; 0=The timer counts down. Timer Mode:; 1=TINx pin pauses the timer when.." "0: TINx pin has no effect on the timer,1: TINx pin pauses the timer when de-asserted" newline bitfld.long 0x0 4. "INPOL,This bit selects the polarity of the TINx input. 1=TINx is active low; 0=TINx is active high." "0: TINx is active high,1: TINx is active low" bitfld.long 0x0 2.--3. "MODE,Timer Mode. 3=Measurement Mode; 2=One Shot Mode; 1=Event Mode; 0=Timer Mode." "0: Timer Mode,1: Event Mode,2: One Shot Mode,3: Measurement Mode" newline bitfld.long 0x0 1. "RESET,This bit stops the timer and resets the internal counter to the value in the Timer Reload Register. This bit also clears the ENABLE bit if it is set. This bit is self-clearing after the timer is reset. Firmware must poll the.." "0: Normal timer operation,1: Timer reset" bitfld.long 0x0 0. "ENABLE,This bit is used to start and stop the timer. This bit does not reset the timer count but does reset the timer pulse output. This bit will be cleared when the timer stops counting in One-Shot mode. The ENABLE bit is cleared.." "0: Timer is disabled,1: Timer is enabled" line.long 0x4 "CLK_EVNT_CTRL,This is the Timer Clock and Event Control Register." hexmask.long.byte 0x4 8.--11. 1. "FCLK,Timer Clock Select. This field determines the clock source for the TINx noise filter. The available frequencies are the same as for TCLK." bitfld.long 0x4 7. "EVENT,Event Select. This bit is used to select the count source when the timer is operating in Event Mode. 1=TINx is count source; 0=Timer x-1 overflow is count source." "0: Timer x-1 overflow is count source,1: TINx is count source" newline bitfld.long 0x4 5.--6. "EDGE,This field selects which edge of the TINx input signal affects the timer in Event Mode One-Shot Mode and Measurement Mode. Event Mode: 11b=No event selected; 10b=Counts rising and falling edges; 01b=Counts rising edges; 00b=Counts falling.." "0,1,2,3" hexmask.long.byte 0x4 0.--3. 1. "TCLK,Timer Clock Select. This field determines the clock source for the 16-bit counter in the timer." line.long 0x8 "TIMERX_RELOAD,This register is used in Timer and One-Shot modes to set the lower limit of the timer." hexmask.long.word 0x8 0.--15. 1. "TIMER_RELOAD,The Timer Reload register is used in Timer and One-Shot modes to set the lower limit of the timer. In Event mode the Timer Reload register sets either the upper or lower limit of the timer depending on if the timer.." line.long 0xC "TIMERX_COUNT,This register returns the current value of the timer in all modes." hexmask.long.word 0xC 0.--15. 1. "TIMER_COUNT,This is the current value of the timer in all modes." tree.end tree "CNTR_TMR1" base ad:0x40000D20 group.long 0x0++0xF line.long 0x0 "TIMERX_CONTROL,This bit reflects the current state of the timer's Clock_Required output signal." bitfld.long 0x0 12. "TIMERX_CLK_REQ,This bit reflects the current state of the timer's Clock_Required output signal. 1=The main clock is required by this block; 0=The main clock is not required by this block." "0: The main clock is not required by this block,1: The main clock is required by this block" bitfld.long 0x0 11. "SLEEP_ENABLE,This bit reflects the current state of the timer's Sleep_Enable input signal. 1=Normal operation; 0=Sleep Mode is requested." "0: Sleep Mode is requested,1: Normal operation" newline bitfld.long 0x0 10. "TOUT_POLARITY,This bit determines the polarity of the TOUTx output signal. In timer modes that toggle the TOUTx signal this polarity bit will not have a perceivable difference except to determine the inactive state. In One-Shot mode.." "0: Active high,1: Active low" bitfld.long 0x0 9. "PD,Power Down. 1=The timer is powered down and all clocks are gated; 0=The timer is in a running state." "0: The timer is in a running state,1: The timer is powered down and all clocks are gated" newline bitfld.long 0x0 8. "FILTER_BYPASS,This bit is used to enable or disable the noise filter on the TINx input signal. 1=Bypass Mode: input filter disabled. The TINx input directly affects the timer; 0=Filter Mode: input filter enabled. The TINx input is.." "0: Filter Mode: input filter enabled,1: Bypass Mode: input filter disabled" bitfld.long 0x0 7. "RLOAD,Reload Control. This bit controls how the timer is reloaded on overflow or underflow in Event and Timer modes. It has no effect in One shot mode. 1=Reload timer from Timer Reload Register and continue counting;.." "0: Roll timer over to FFFFh and continue counting..,1: Reload timer from Timer Reload Register and.." newline bitfld.long 0x0 6. "TOUT_EN,This bit enables the TOUTx pin. 1=TOUTx pin function is enabled; 0=TOUTx pin is inactive." "0: TOUTx pin is inactive,1: TOUTx pin function is enabled" bitfld.long 0x0 5. "UPDN,In Event Mode this bit selects the timer count direction. In Timer Mode enables timer control by the TINx input pin. Event Mode: 1=The timer counts up; 0=The timer counts down. Timer Mode:; 1=TINx pin pauses the timer when.." "0: TINx pin has no effect on the timer,1: TINx pin pauses the timer when de-asserted" newline bitfld.long 0x0 4. "INPOL,This bit selects the polarity of the TINx input. 1=TINx is active low; 0=TINx is active high." "0: TINx is active high,1: TINx is active low" bitfld.long 0x0 2.--3. "MODE,Timer Mode. 3=Measurement Mode; 2=One Shot Mode; 1=Event Mode; 0=Timer Mode." "0: Timer Mode,1: Event Mode,2: One Shot Mode,3: Measurement Mode" newline bitfld.long 0x0 1. "RESET,This bit stops the timer and resets the internal counter to the value in the Timer Reload Register. This bit also clears the ENABLE bit if it is set. This bit is self-clearing after the timer is reset. Firmware must poll the.." "0: Normal timer operation,1: Timer reset" bitfld.long 0x0 0. "ENABLE,This bit is used to start and stop the timer. This bit does not reset the timer count but does reset the timer pulse output. This bit will be cleared when the timer stops counting in One-Shot mode. The ENABLE bit is cleared.." "0: Timer is disabled,1: Timer is enabled" line.long 0x4 "CLK_EVNT_CTRL,This is the Timer Clock and Event Control Register." hexmask.long.byte 0x4 8.--11. 1. "FCLK,Timer Clock Select. This field determines the clock source for the TINx noise filter. The available frequencies are the same as for TCLK." bitfld.long 0x4 7. "EVENT,Event Select. This bit is used to select the count source when the timer is operating in Event Mode. 1=TINx is count source; 0=Timer x-1 overflow is count source." "0: Timer x-1 overflow is count source,1: TINx is count source" newline bitfld.long 0x4 5.--6. "EDGE,This field selects which edge of the TINx input signal affects the timer in Event Mode One-Shot Mode and Measurement Mode. Event Mode: 11b=No event selected; 10b=Counts rising and falling edges; 01b=Counts rising edges; 00b=Counts falling.." "0,1,2,3" hexmask.long.byte 0x4 0.--3. 1. "TCLK,Timer Clock Select. This field determines the clock source for the 16-bit counter in the timer." line.long 0x8 "TIMERX_RELOAD,This register is used in Timer and One-Shot modes to set the lower limit of the timer." hexmask.long.word 0x8 0.--15. 1. "TIMER_RELOAD,The Timer Reload register is used in Timer and One-Shot modes to set the lower limit of the timer. In Event mode the Timer Reload register sets either the upper or lower limit of the timer depending on if the timer.." line.long 0xC "TIMERX_COUNT,This register returns the current value of the timer in all modes." hexmask.long.word 0xC 0.--15. 1. "TIMER_COUNT,This is the current value of the timer in all modes." tree.end tree "CNTR_TMR2" base ad:0x40000D40 group.long 0x0++0xF line.long 0x0 "TIMERX_CONTROL,This bit reflects the current state of the timer's Clock_Required output signal." bitfld.long 0x0 12. "TIMERX_CLK_REQ,This bit reflects the current state of the timer's Clock_Required output signal. 1=The main clock is required by this block; 0=The main clock is not required by this block." "0: The main clock is not required by this block,1: The main clock is required by this block" bitfld.long 0x0 11. "SLEEP_ENABLE,This bit reflects the current state of the timer's Sleep_Enable input signal. 1=Normal operation; 0=Sleep Mode is requested." "0: Sleep Mode is requested,1: Normal operation" newline bitfld.long 0x0 10. "TOUT_POLARITY,This bit determines the polarity of the TOUTx output signal. In timer modes that toggle the TOUTx signal this polarity bit will not have a perceivable difference except to determine the inactive state. In One-Shot mode.." "0: Active high,1: Active low" bitfld.long 0x0 9. "PD,Power Down. 1=The timer is powered down and all clocks are gated; 0=The timer is in a running state." "0: The timer is in a running state,1: The timer is powered down and all clocks are gated" newline bitfld.long 0x0 8. "FILTER_BYPASS,This bit is used to enable or disable the noise filter on the TINx input signal. 1=Bypass Mode: input filter disabled. The TINx input directly affects the timer; 0=Filter Mode: input filter enabled. The TINx input is.." "0: Filter Mode: input filter enabled,1: Bypass Mode: input filter disabled" bitfld.long 0x0 7. "RLOAD,Reload Control. This bit controls how the timer is reloaded on overflow or underflow in Event and Timer modes. It has no effect in One shot mode. 1=Reload timer from Timer Reload Register and continue counting;.." "0: Roll timer over to FFFFh and continue counting..,1: Reload timer from Timer Reload Register and.." newline bitfld.long 0x0 6. "TOUT_EN,This bit enables the TOUTx pin. 1=TOUTx pin function is enabled; 0=TOUTx pin is inactive." "0: TOUTx pin is inactive,1: TOUTx pin function is enabled" bitfld.long 0x0 5. "UPDN,In Event Mode this bit selects the timer count direction. In Timer Mode enables timer control by the TINx input pin. Event Mode: 1=The timer counts up; 0=The timer counts down. Timer Mode:; 1=TINx pin pauses the timer when.." "0: TINx pin has no effect on the timer,1: TINx pin pauses the timer when de-asserted" newline bitfld.long 0x0 4. "INPOL,This bit selects the polarity of the TINx input. 1=TINx is active low; 0=TINx is active high." "0: TINx is active high,1: TINx is active low" bitfld.long 0x0 2.--3. "MODE,Timer Mode. 3=Measurement Mode; 2=One Shot Mode; 1=Event Mode; 0=Timer Mode." "0: Timer Mode,1: Event Mode,2: One Shot Mode,3: Measurement Mode" newline bitfld.long 0x0 1. "RESET,This bit stops the timer and resets the internal counter to the value in the Timer Reload Register. This bit also clears the ENABLE bit if it is set. This bit is self-clearing after the timer is reset. Firmware must poll the.." "0: Normal timer operation,1: Timer reset" bitfld.long 0x0 0. "ENABLE,This bit is used to start and stop the timer. This bit does not reset the timer count but does reset the timer pulse output. This bit will be cleared when the timer stops counting in One-Shot mode. The ENABLE bit is cleared.." "0: Timer is disabled,1: Timer is enabled" line.long 0x4 "CLK_EVNT_CTRL,This is the Timer Clock and Event Control Register." hexmask.long.byte 0x4 8.--11. 1. "FCLK,Timer Clock Select. This field determines the clock source for the TINx noise filter. The available frequencies are the same as for TCLK." bitfld.long 0x4 7. "EVENT,Event Select. This bit is used to select the count source when the timer is operating in Event Mode. 1=TINx is count source; 0=Timer x-1 overflow is count source." "0: Timer x-1 overflow is count source,1: TINx is count source" newline bitfld.long 0x4 5.--6. "EDGE,This field selects which edge of the TINx input signal affects the timer in Event Mode One-Shot Mode and Measurement Mode. Event Mode: 11b=No event selected; 10b=Counts rising and falling edges; 01b=Counts rising edges; 00b=Counts falling.." "0,1,2,3" hexmask.long.byte 0x4 0.--3. 1. "TCLK,Timer Clock Select. This field determines the clock source for the 16-bit counter in the timer." line.long 0x8 "TIMERX_RELOAD,This register is used in Timer and One-Shot modes to set the lower limit of the timer." hexmask.long.word 0x8 0.--15. 1. "TIMER_RELOAD,The Timer Reload register is used in Timer and One-Shot modes to set the lower limit of the timer. In Event mode the Timer Reload register sets either the upper or lower limit of the timer depending on if the timer.." line.long 0xC "TIMERX_COUNT,This register returns the current value of the timer in all modes." hexmask.long.word 0xC 0.--15. 1. "TIMER_COUNT,This is the current value of the timer in all modes." tree.end tree "CNTR_TMR3" base ad:0x40000D60 group.long 0x0++0xF line.long 0x0 "TIMERX_CONTROL,This bit reflects the current state of the timer's Clock_Required output signal." bitfld.long 0x0 12. "TIMERX_CLK_REQ,This bit reflects the current state of the timer's Clock_Required output signal. 1=The main clock is required by this block; 0=The main clock is not required by this block." "0: The main clock is not required by this block,1: The main clock is required by this block" bitfld.long 0x0 11. "SLEEP_ENABLE,This bit reflects the current state of the timer's Sleep_Enable input signal. 1=Normal operation; 0=Sleep Mode is requested." "0: Sleep Mode is requested,1: Normal operation" newline bitfld.long 0x0 10. "TOUT_POLARITY,This bit determines the polarity of the TOUTx output signal. In timer modes that toggle the TOUTx signal this polarity bit will not have a perceivable difference except to determine the inactive state. In One-Shot mode.." "0: Active high,1: Active low" bitfld.long 0x0 9. "PD,Power Down. 1=The timer is powered down and all clocks are gated; 0=The timer is in a running state." "0: The timer is in a running state,1: The timer is powered down and all clocks are gated" newline bitfld.long 0x0 8. "FILTER_BYPASS,This bit is used to enable or disable the noise filter on the TINx input signal. 1=Bypass Mode: input filter disabled. The TINx input directly affects the timer; 0=Filter Mode: input filter enabled. The TINx input is.." "0: Filter Mode: input filter enabled,1: Bypass Mode: input filter disabled" bitfld.long 0x0 7. "RLOAD,Reload Control. This bit controls how the timer is reloaded on overflow or underflow in Event and Timer modes. It has no effect in One shot mode. 1=Reload timer from Timer Reload Register and continue counting;.." "0: Roll timer over to FFFFh and continue counting..,1: Reload timer from Timer Reload Register and.." newline bitfld.long 0x0 6. "TOUT_EN,This bit enables the TOUTx pin. 1=TOUTx pin function is enabled; 0=TOUTx pin is inactive." "0: TOUTx pin is inactive,1: TOUTx pin function is enabled" bitfld.long 0x0 5. "UPDN,In Event Mode this bit selects the timer count direction. In Timer Mode enables timer control by the TINx input pin. Event Mode: 1=The timer counts up; 0=The timer counts down. Timer Mode:; 1=TINx pin pauses the timer when.." "0: TINx pin has no effect on the timer,1: TINx pin pauses the timer when de-asserted" newline bitfld.long 0x0 4. "INPOL,This bit selects the polarity of the TINx input. 1=TINx is active low; 0=TINx is active high." "0: TINx is active high,1: TINx is active low" bitfld.long 0x0 2.--3. "MODE,Timer Mode. 3=Measurement Mode; 2=One Shot Mode; 1=Event Mode; 0=Timer Mode." "0: Timer Mode,1: Event Mode,2: One Shot Mode,3: Measurement Mode" newline bitfld.long 0x0 1. "RESET,This bit stops the timer and resets the internal counter to the value in the Timer Reload Register. This bit also clears the ENABLE bit if it is set. This bit is self-clearing after the timer is reset. Firmware must poll the.." "0: Normal timer operation,1: Timer reset" bitfld.long 0x0 0. "ENABLE,This bit is used to start and stop the timer. This bit does not reset the timer count but does reset the timer pulse output. This bit will be cleared when the timer stops counting in One-Shot mode. The ENABLE bit is cleared.." "0: Timer is disabled,1: Timer is enabled" line.long 0x4 "CLK_EVNT_CTRL,This is the Timer Clock and Event Control Register." hexmask.long.byte 0x4 8.--11. 1. "FCLK,Timer Clock Select. This field determines the clock source for the TINx noise filter. The available frequencies are the same as for TCLK." bitfld.long 0x4 7. "EVENT,Event Select. This bit is used to select the count source when the timer is operating in Event Mode. 1=TINx is count source; 0=Timer x-1 overflow is count source." "0: Timer x-1 overflow is count source,1: TINx is count source" newline bitfld.long 0x4 5.--6. "EDGE,This field selects which edge of the TINx input signal affects the timer in Event Mode One-Shot Mode and Measurement Mode. Event Mode: 11b=No event selected; 10b=Counts rising and falling edges; 01b=Counts rising edges; 00b=Counts falling.." "0,1,2,3" hexmask.long.byte 0x4 0.--3. 1. "TCLK,Timer Clock Select. This field determines the clock source for the 16-bit counter in the timer." line.long 0x8 "TIMERX_RELOAD,This register is used in Timer and One-Shot modes to set the lower limit of the timer." hexmask.long.word 0x8 0.--15. 1. "TIMER_RELOAD,The Timer Reload register is used in Timer and One-Shot modes to set the lower limit of the timer. In Event mode the Timer Reload register sets either the upper or lower limit of the timer depending on if the timer.." line.long 0xC "TIMERX_COUNT,This register returns the current value of the timer in all modes." hexmask.long.word 0xC 0.--15. 1. "TIMER_COUNT,This is the current value of the timer in all modes." tree.end tree.end tree "DMA_CHAN" base ad:0x0 tree "DMA_CHAN00" base ad:0x40002440 group.byte 0x0++0x0 line.byte 0x0 "ACTIVATE,Enable this channel for operation. The DMA Main Control: Activate must also be enabled for this channel to be operational." bitfld.byte 0x0 0. "CHN,Enable this channel for operation. The DMA Main Control:Activate must also be enabled for this channel to be operational. 1=Enable channel(block). Each individual channel must be enabled separately. 0=Disable.." "0: Disable channel,1: Enable channel" group.long 0x4++0xF line.long 0x0 "MSTART,This is the starting address for the Memory device." line.long 0x4 "MEND,This is the ending address for the Memory device." line.long 0x8 "DSTART,This is the Master Device address." line.long 0xC "CTRL,DMA Channel N Control" bitfld.long 0xC 25. "TRANS_ABORT,This is used to abort the current transfer on this DMA Channel. The aborted transfer will be forced to terminate immediately." "0,1" bitfld.long 0xC 24. "TRANS_GO,This is used for the Firmware Flow Control DMA transfer." "0,1" newline bitfld.long 0xC 20.--22. "TRANS_SIZE,This is the transfer size in Bytes of each Data Packet transfer. Note: The transfer size must be a legal AMBA transfer size. Valid sizes are 1 2 and 4 Bytes." "0,1,2,3,4,5,6,7" bitfld.long 0xC 19. "DIS_HW_FLOW_CTRL,This will Disable the Hardware Flow Control. When disabled any DMA Master device attempting to communicate to the DMA over the DMA Flow Control Interface (Ports: dma_req dma_term and dma_done) will be ignored. This should be set.." "0,1" newline bitfld.long 0xC 18. "LOCK,This is used to lock the arbitration of the Channel Arbiter on this channel once this channel is granted. Once this is locked it will remain on the arbiter until it has completed it transfer (either the Transfer Aborted Transfer Done or Transfer.." "0,1" bitfld.long 0xC 17. "INC_DEV_ADDR,This will enable an auto-increment to the DMA Channel Device Address. 1: Increment the DMA Channel Device Address by DMA Channel Control:Transfer Size after every Data Packet transfer 0: Do nothing" "0: Do nothing,1: Increment the DMA Channel Device Address by DMA.." newline bitfld.long 0xC 16. "INC_MEM_ADDR,This will enable an auto-increment to the DMA Channel Memory Address. 1=Increment the DMA Channel Memory Address by DMA Channel Control:Transfer Size after every Data Packet transfer 0=Do nothing" "0: Do nothing,1: Increment the DMA Channel Memory Address by DMA.." hexmask.long.byte 0xC 9.--15. 1. "HW_FLOW_CTRL_DEV,This is the device that is connected to this channel as its Hardware Flow Control master. The Flow Control Interface is a bus with each master concatenated onto it. This selects which bus index of the.." newline bitfld.long 0xC 8. "TX_DIR,This determines the direction of the DMA Transfer. 1=Data Packet Read from Memory Start Address followed by Data Packet Write to Device Address 0=Data Packet Read from Device Address followed by Data Packet Write.." "0: Data Packet Read from Device Address followed by..,1: Data Packet Read from Memory Start Address.." bitfld.long 0xC 5. "BUSY,This is a status signal. 1=The DMA Channel is busy (FSM is not IDLE) 0=The DMA Channel is not busy (FSM is IDLE)" "0: The DMA Channel is not busy,1: The DMA Channel is busy" newline bitfld.long 0xC 3.--4. "STS,This is a status signal. The status decode is listed in priority order with the highest priority first. 3: Error detected by the DMA 2: The DMA Channel is externally done in that the Device has terminated the.." "0: DMA Channel Control:Run is Disabled,1: The DMA Channel is locally done,2: The DMA Channel is externally done,3: Error detected by the DMA" bitfld.long 0xC 2. "DONE,This is a status signal. It is only valid while DMA Channel Control: Run is Enabled. This is the inverse of the DMA Channel Control: Busy field except this is qualified with the DMA Channel Control:Run field." "0: Channel is not done or it is OFF,1: Channel is done" newline bitfld.long 0xC 1. "REQ,This is a status field. 1= There is a transfer request from the Master Device 0= There is no transfer request from the Master Device" "0: There is no transfer request from the Master..,1: There is a transfer request from the Master Device" bitfld.long 0xC 0. "RUN,This is a control field. Note: This bit only applies to Hardware Flow Control mode. 1= This channel is enabled and will service transfer requests 0=This channel is disabled. All transfer requests are ignored." "0: This channel is disabled,1: This channel is enabled and will service.." group.byte 0x14++0x0 line.byte 0x0 "ISTS,DMA Channel N Interrupt Status" bitfld.byte 0x0 2. "DONE,This is an interrupt source register. This flags when the DMA Channel has completed a transfer successfully on its side. A completed transfer is defined as when the DMA Channel reaches its limit; Memory Start Address equals Memory End Address." "0: Memory Start Address does not equal Memory End..,1: Memory Start Address equals Memory End Address" bitfld.byte 0x0 1. "FLOW_CTRL,This is an interrupt source register. This flags when the DMA Channel has encountered a Hardware Flow Control Request after the DMA Channel has completed the transfer. This means the Master Device is attempting to overflow the DMA." "0: No Hardware Flow Control event,1: Hardware Flow Control is requesting after the.." newline bitfld.byte 0x0 0. "BUS_ERR,This is an interrupt source register. This flags when there is an Error detected over the internal 32-bit Bus. 1: Error detected. (R/WC)" "?,1: Error detected" group.byte 0x18++0x0 line.byte 0x0 "IEN,DMA CHANNEL N INTERRUPT ENABLE" bitfld.byte 0x0 2. "STS_EN_DONE,This is an interrupt enable for DMA Channel Interrupt:Status Done. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" bitfld.byte 0x0 1. "STS_EN_FLOW_CTRL,This is an interrupt enable for DMA Channel Interrupt:Status Flow Control Error. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" newline bitfld.byte 0x0 0. "STS_EN_BUS_ERR,This is an interrupt enable for DMA Channel Interrupt:Status Bus Error. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" group.long 0x20++0xB line.long 0x0 "CRC_EN,DMA CHANNEL N CRC ENABLE" bitfld.long 0x0 1. "POST_TRANS,The bit enables the transfer of the calculated CRC-32 after the completion of the DMA transaction. If the DMA transaction is aborted by either firmware or an internal bus error the transfer will not occur. If the target of the DMA.." "0: Disable the automatic transfer of the CRC,1: Enable the transfer of CRC-32 for DMA Channel N.." bitfld.long 0x0 0. "MODE,1=Enable the calculation of CRC-32 for DMA Channel N 0=Disable the calculation of CRC-32 for DMA Channel N" "0: Disable the calculation of CRC-32 for DMA..,1: Enable the calculation of CRC-32 for DMA Channel N" line.long 0x4 "CRC_DATA,DMA CHANNEL N CRC DATA" hexmask.long 0x4 0.--31. 1. "CRC,Writes to this register initialize the CRC generator. Reads from this register return the output of the CRC that is calculated from the data transferred by DMA Channel N. The output of the CRC generator is bit-reversed and inverted on reads .." line.long 0x8 "CRC_POST_STS,DMA CHANNEL N CRC POST STATUS" bitfld.long 0x8 3. "CRC_DATA_READY,This bit is set to '1b' when the DMA controller is processing the post-transfer of the CRC data. This bit is cleared to '0b' when the post-transfer completes." "0,1" bitfld.long 0x8 2. "CRC_DATA_DONE,This bit is set to '1b' when the DMA controller has completed the post-transfer of the CRC data. This bit is cleared to '0b' when the a new DMA transfer starts." "0,1" newline bitfld.long 0x8 1. "CRC_RUNNING,This bit is set to '1b' when the DMA controller starts the post-transfer transmission of the CRC. It is only set when the post-transfer is enabled by the CRC_POST_TRANSFER_ENABLE field. This bit is cleared to '0b' when the.." "0,1" bitfld.long 0x8 0. "CRC_DONE,This bit is set to '1b' when the CRC calculation has completed from either normal or forced termination. It is cleared to '0b' when the DMA controller starts a new transfer on the channel." "0,1" tree.end tree "DMA_CHAN01" base ad:0x40002480 group.byte 0x0++0x0 line.byte 0x0 "ACTIVATE,Enable this channel for operation. The DMA Main Control: Activate must also be enabled for this channel to be operational." bitfld.byte 0x0 0. "CHN,Enable this channel for operation. The DMA Main Control:Activate must also be enabled for this channel to be operational. 1=Enable channel(block). Each individual channel must be enabled separately. 0=Disable.." "0: Disable channel,1: Enable channel" group.long 0x4++0xF line.long 0x0 "MSTART,This is the starting address for the Memory device." line.long 0x4 "MEND,This is the ending address for the Memory device." line.long 0x8 "DSTART,This is the Master Device address." line.long 0xC "CTRL,DMA Channel N Control" bitfld.long 0xC 25. "TRANS_ABORT,This is used to abort the current transfer on this DMA Channel. The aborted transfer will be forced to terminate immediately." "0,1" bitfld.long 0xC 24. "TRANS_GO,This is used for the Firmware Flow Control DMA transfer." "0,1" newline bitfld.long 0xC 20.--22. "TRANS_SIZE,This is the transfer size in Bytes of each Data Packet transfer. Note: The transfer size must be a legal AMBA transfer size. Valid sizes are 1 2 and 4 Bytes." "0,1,2,3,4,5,6,7" bitfld.long 0xC 19. "DIS_HW_FLOW_CTRL,This will Disable the Hardware Flow Control. When disabled any DMA Master device attempting to communicate to the DMA over the DMA Flow Control Interface (Ports: dma_req dma_term and dma_done) will be ignored. This should be set.." "0,1" newline bitfld.long 0xC 18. "LOCK,This is used to lock the arbitration of the Channel Arbiter on this channel once this channel is granted. Once this is locked it will remain on the arbiter until it has completed it transfer (either the Transfer Aborted Transfer Done or Transfer.." "0,1" bitfld.long 0xC 17. "INC_DEV_ADDR,This will enable an auto-increment to the DMA Channel Device Address. 1: Increment the DMA Channel Device Address by DMA Channel Control:Transfer Size after every Data Packet transfer 0: Do nothing" "0: Do nothing,1: Increment the DMA Channel Device Address by DMA.." newline bitfld.long 0xC 16. "INC_MEM_ADDR,This will enable an auto-increment to the DMA Channel Memory Address. 1=Increment the DMA Channel Memory Address by DMA Channel Control:Transfer Size after every Data Packet transfer 0=Do nothing" "0: Do nothing,1: Increment the DMA Channel Memory Address by DMA.." hexmask.long.byte 0xC 9.--15. 1. "HW_FLOW_CTRL_DEV,This is the device that is connected to this channel as its Hardware Flow Control master. The Flow Control Interface is a bus with each master concatenated onto it. This selects which bus index of the.." newline bitfld.long 0xC 8. "TX_DIR,This determines the direction of the DMA Transfer. 1=Data Packet Read from Memory Start Address followed by Data Packet Write to Device Address 0=Data Packet Read from Device Address followed by Data Packet Write.." "0: Data Packet Read from Device Address followed by..,1: Data Packet Read from Memory Start Address.." bitfld.long 0xC 5. "BUSY,This is a status signal. 1=The DMA Channel is busy (FSM is not IDLE) 0=The DMA Channel is not busy (FSM is IDLE)" "0: The DMA Channel is not busy,1: The DMA Channel is busy" newline bitfld.long 0xC 3.--4. "STS,This is a status signal. The status decode is listed in priority order with the highest priority first. 3: Error detected by the DMA 2: The DMA Channel is externally done in that the Device has terminated the.." "0: DMA Channel Control:Run is Disabled,1: The DMA Channel is locally done,2: The DMA Channel is externally done,3: Error detected by the DMA" bitfld.long 0xC 2. "DONE,This is a status signal. It is only valid while DMA Channel Control: Run is Enabled. This is the inverse of the DMA Channel Control: Busy field except this is qualified with the DMA Channel Control:Run field." "0: Channel is not done or it is OFF,1: Channel is done" newline bitfld.long 0xC 1. "REQ,This is a status field. 1= There is a transfer request from the Master Device 0= There is no transfer request from the Master Device" "0: There is no transfer request from the Master..,1: There is a transfer request from the Master Device" bitfld.long 0xC 0. "RUN,This is a control field. Note: This bit only applies to Hardware Flow Control mode. 1= This channel is enabled and will service transfer requests 0=This channel is disabled. All transfer requests are ignored." "0: This channel is disabled,1: This channel is enabled and will service.." group.byte 0x14++0x0 line.byte 0x0 "ISTS,DMA Channel N Interrupt Status" bitfld.byte 0x0 2. "DONE,This is an interrupt source register. This flags when the DMA Channel has completed a transfer successfully on its side. A completed transfer is defined as when the DMA Channel reaches its limit; Memory Start Address equals Memory End Address." "0: Memory Start Address does not equal Memory End..,1: Memory Start Address equals Memory End Address" bitfld.byte 0x0 1. "FLOW_CTRL,This is an interrupt source register. This flags when the DMA Channel has encountered a Hardware Flow Control Request after the DMA Channel has completed the transfer. This means the Master Device is attempting to overflow the DMA." "0: No Hardware Flow Control event,1: Hardware Flow Control is requesting after the.." newline bitfld.byte 0x0 0. "BUS_ERROR,This is an interrupt source register. This flags when there is an Error detected over the internal 32-bit Bus. 1: Error detected. (R/WC)" "?,1: Error detected" group.byte 0x18++0x0 line.byte 0x0 "IEN,DMA CHANNEL N INTERRUPT ENABLE" bitfld.byte 0x0 2. "STS_EN_DONE,This is an interrupt enable for DMA Channel Interrupt:Status Done. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" bitfld.byte 0x0 1. "STS_EN_FLOW_CTRL,This is an interrupt enable for DMA Channel Interrupt:Status Flow Control Error. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" newline bitfld.byte 0x0 0. "STS_EN_BUS_ERR,This is an interrupt enable for DMA Channel Interrupt:Status Bus Error. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" group.long 0x20++0xB line.long 0x0 "FILL_EN,DMA CHANNEL N FILL ENABLE" bitfld.long 0x0 0. "MODE,1=Enable the DMA Channel Fill Engine N 0=Disable the DMA Channel Fill Engine" "0: Disable the DMA Channel Fill Engine,1: Enable the DMA Channel Fill Engine N" line.long 0x4 "FILL_DATA,DMA CHANNEL N FILL DATA" hexmask.long 0x4 0.--31. 1. "DATA,This is the data pattern used to fill memory." line.long 0x8 "FILL_STS,DMA CHANNEL N FILL STATUS" bitfld.long 0x8 1. "RUNNING,This bit is set to '1b' when the DMA controller starts the post-transfer transmission of the CRC. It is only set when the post-transfer is enabled by the CRC_POST_TRANSFER_ENABLE field. This bit is cleared to '0b' when the post-transfer.." "0,1" bitfld.long 0x8 0. "DONE,This bit is set to '1b' when the CRC calculation has completed from either normal or forced termination. It is cleared to '0b' when the DMA controller starts a new transfer on the channel." "0,1" tree.end tree "DMA_CHAN02" base ad:0x400024C0 group.byte 0x0++0x0 line.byte 0x0 "ACTIVATE,Enable this channel for operation. The DMA Main Control: Activate must also be enabled for this channel to be operational." bitfld.byte 0x0 0. "CHN,Enable this channel for operation. The DMA Main Control:Activate must also be enabled for this channel to be operational. 1=Enable channel(block). Each individual channel must be enabled separately. 0=Disable.." "0: Disable channel,1: Enable channel" group.long 0x4++0xF line.long 0x0 "MSTART,This is the starting address for the Memory device." line.long 0x4 "MEND,This is the ending address for the Memory device." line.long 0x8 "DSTART,This is the Master Device address." line.long 0xC "CTRL,DMA Channel N Control" bitfld.long 0xC 25. "TRANS_ABORT,This is used to abort the current transfer on this DMA Channel. The aborted transfer will be forced to terminate immediately." "0,1" bitfld.long 0xC 24. "TRANS_GO,This is used for the Firmware Flow Control DMA transfer." "0,1" newline bitfld.long 0xC 20.--22. "TRANS_SIZE,This is the transfer size in Bytes of each Data Packet transfer. Note: The transfer size must be a legal AMBA transfer size. Valid sizes are 1 2 and 4 Bytes." "0,1,2,3,4,5,6,7" bitfld.long 0xC 19. "DIS_HW_FLOW_CTRL,This will Disable the Hardware Flow Control. When disabled any DMA Master device attempting to communicate to the DMA over the DMA Flow Control Interface (Ports: dma_req dma_term and dma_done) will be ignored. This should be set.." "0,1" newline bitfld.long 0xC 18. "LOCK,This is used to lock the arbitration of the Channel Arbiter on this channel once this channel is granted. Once this is locked it will remain on the arbiter until it has completed it transfer (either the Transfer Aborted Transfer Done or Transfer.." "0,1" bitfld.long 0xC 17. "INC_DEV_ADDR,This will enable an auto-increment to the DMA Channel Device Address. 1: Increment the DMA Channel Device Address by DMA Channel Control:Transfer Size after every Data Packet transfer 0: Do nothing" "0: Do nothing,1: Increment the DMA Channel Device Address by DMA.." newline bitfld.long 0xC 16. "INC_MEM_ADDR,This will enable an auto-increment to the DMA Channel Memory Address. 1=Increment the DMA Channel Memory Address by DMA Channel Control:Transfer Size after every Data Packet transfer 0=Do nothing" "0: Do nothing,1: Increment the DMA Channel Memory Address by DMA.." hexmask.long.byte 0xC 9.--15. 1. "HW_FLOW_CTRL_DEV,This is the device that is connected to this channel as its Hardware Flow Control master. The Flow Control Interface is a bus with each master concatenated onto it. This selects which bus index of the.." newline bitfld.long 0xC 8. "TX_DIR,This determines the direction of the DMA Transfer. 1=Data Packet Read from Memory Start Address followed by Data Packet Write to Device Address 0=Data Packet Read from Device Address followed by Data Packet Write.." "0: Data Packet Read from Device Address followed by..,1: Data Packet Read from Memory Start Address.." bitfld.long 0xC 5. "BUSY,This is a status signal. 1=The DMA Channel is busy (FSM is not IDLE) 0=The DMA Channel is not busy (FSM is IDLE)" "0: The DMA Channel is not busy,1: The DMA Channel is busy" newline bitfld.long 0xC 3.--4. "STS,This is a status signal. The status decode is listed in priority order with the highest priority first. 3: Error detected by the DMA 2: The DMA Channel is externally done in that the Device has terminated the.." "0: DMA Channel Control:Run is Disabled,1: The DMA Channel is locally done,2: The DMA Channel is externally done,3: Error detected by the DMA" bitfld.long 0xC 2. "DONE,This is a status signal. It is only valid while DMA Channel Control: Run is Enabled. This is the inverse of the DMA Channel Control: Busy field except this is qualified with the DMA Channel Control:Run field." "0: Channel is not done or it is OFF,1: Channel is done" newline bitfld.long 0xC 1. "REQ,This is a status field. 1= There is a transfer request from the Master Device 0= There is no transfer request from the Master Device" "0: There is no transfer request from the Master..,1: There is a transfer request from the Master Device" bitfld.long 0xC 0. "RUN,This is a control field. Note: This bit only applies to Hardware Flow Control mode. 1= This channel is enabled and will service transfer requests 0=This channel is disabled. All transfer requests are ignored." "0: This channel is disabled,1: This channel is enabled and will service.." group.byte 0x14++0x0 line.byte 0x0 "ISTS,DMA Channel N Interrupt Status" bitfld.byte 0x0 2. "DONE,This is an interrupt source register. This flags when the DMA Channel has completed a transfer successfully on its side. A completed transfer is defined as when the DMA Channel reaches its limit; Memory Start Address equals Memory End Address." "0: Memory Start Address does not equal Memory End..,1: Memory Start Address equals Memory End Address" bitfld.byte 0x0 1. "FLOW_CTRL,This is an interrupt source register. This flags when the DMA Channel has encountered a Hardware Flow Control Request after the DMA Channel has completed the transfer. This means the Master Device is attempting to overflow the DMA." "0: No Hardware Flow Control event,1: Hardware Flow Control is requesting after the.." newline bitfld.byte 0x0 0. "BUS_ERR,This is an interrupt source register. This flags when there is an Error detected over the internal 32-bit Bus. 1: Error detected. (R/WC)" "?,1: Error detected" group.byte 0x18++0x0 line.byte 0x0 "IEN,DMA CHANNEL N INTERRUPT ENABLE" bitfld.byte 0x0 2. "STS_EN_DONE,This is an interrupt enable for DMA Channel Interrupt:Status Done. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" bitfld.byte 0x0 1. "STS_EN_FLOW_CTRL,This is an interrupt enable for DMA Channel Interrupt:Status Flow Control Error. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" newline bitfld.byte 0x0 0. "STS_EN_BUS_ERR,This is an interrupt enable for DMA Channel Interrupt:Status Bus Error. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" tree.end tree "DMA_CHAN03" base ad:0x40002500 group.byte 0x0++0x0 line.byte 0x0 "ACTIVATE,Enable this channel for operation. The DMA Main Control: Activate must also be enabled for this channel to be operational." bitfld.byte 0x0 0. "CHN,Enable this channel for operation. The DMA Main Control:Activate must also be enabled for this channel to be operational. 1=Enable channel(block). Each individual channel must be enabled separately. 0=Disable.." "0: Disable channel,1: Enable channel" group.long 0x4++0xF line.long 0x0 "MSTART,This is the starting address for the Memory device." line.long 0x4 "MEND,This is the ending address for the Memory device." line.long 0x8 "DSTART,This is the Master Device address." line.long 0xC "CTRL,DMA Channel N Control" bitfld.long 0xC 25. "TRANS_ABORT,This is used to abort the current transfer on this DMA Channel. The aborted transfer will be forced to terminate immediately." "0,1" bitfld.long 0xC 24. "TRANS_GO,This is used for the Firmware Flow Control DMA transfer." "0,1" newline bitfld.long 0xC 20.--22. "TRANS_SIZE,This is the transfer size in Bytes of each Data Packet transfer. Note: The transfer size must be a legal AMBA transfer size. Valid sizes are 1 2 and 4 Bytes." "0,1,2,3,4,5,6,7" bitfld.long 0xC 19. "DIS_HW_FLOW_CTRL,This will Disable the Hardware Flow Control. When disabled any DMA Master device attempting to communicate to the DMA over the DMA Flow Control Interface (Ports: dma_req dma_term and dma_done) will be ignored. This should be set.." "0,1" newline bitfld.long 0xC 18. "LOCK,This is used to lock the arbitration of the Channel Arbiter on this channel once this channel is granted. Once this is locked it will remain on the arbiter until it has completed it transfer (either the Transfer Aborted Transfer Done or Transfer.." "0,1" bitfld.long 0xC 17. "INC_DEV_ADDR,This will enable an auto-increment to the DMA Channel Device Address. 1: Increment the DMA Channel Device Address by DMA Channel Control:Transfer Size after every Data Packet transfer 0: Do nothing" "0: Do nothing,1: Increment the DMA Channel Device Address by DMA.." newline bitfld.long 0xC 16. "INC_MEM_ADDR,This will enable an auto-increment to the DMA Channel Memory Address. 1=Increment the DMA Channel Memory Address by DMA Channel Control:Transfer Size after every Data Packet transfer 0=Do nothing" "0: Do nothing,1: Increment the DMA Channel Memory Address by DMA.." hexmask.long.byte 0xC 9.--15. 1. "HW_FLOW_CTRL_DEV,This is the device that is connected to this channel as its Hardware Flow Control master. The Flow Control Interface is a bus with each master concatenated onto it. This selects which bus index of the.." newline bitfld.long 0xC 8. "TX_DIR,This determines the direction of the DMA Transfer. 1=Data Packet Read from Memory Start Address followed by Data Packet Write to Device Address 0=Data Packet Read from Device Address followed by Data Packet Write.." "0: Data Packet Read from Device Address followed by..,1: Data Packet Read from Memory Start Address.." bitfld.long 0xC 5. "BUSY,This is a status signal. 1=The DMA Channel is busy (FSM is not IDLE) 0=The DMA Channel is not busy (FSM is IDLE)" "0: The DMA Channel is not busy,1: The DMA Channel is busy" newline bitfld.long 0xC 3.--4. "STS,This is a status signal. The status decode is listed in priority order with the highest priority first. 3: Error detected by the DMA 2: The DMA Channel is externally done in that the Device has terminated the.." "0: DMA Channel Control:Run is Disabled,1: The DMA Channel is locally done,2: The DMA Channel is externally done,3: Error detected by the DMA" bitfld.long 0xC 2. "DONE,This is a status signal. It is only valid while DMA Channel Control: Run is Enabled. This is the inverse of the DMA Channel Control: Busy field except this is qualified with the DMA Channel Control:Run field." "0: Channel is not done or it is OFF,1: Channel is done" newline bitfld.long 0xC 1. "REQ,This is a status field. 1= There is a transfer request from the Master Device 0= There is no transfer request from the Master Device" "0: There is no transfer request from the Master..,1: There is a transfer request from the Master Device" bitfld.long 0xC 0. "RUN,This is a control field. Note: This bit only applies to Hardware Flow Control mode. 1= This channel is enabled and will service transfer requests 0=This channel is disabled. All transfer requests are ignored." "0: This channel is disabled,1: This channel is enabled and will service.." group.byte 0x14++0x0 line.byte 0x0 "ISTS,DMA Channel N Interrupt Status" bitfld.byte 0x0 2. "DONE,This is an interrupt source register. This flags when the DMA Channel has completed a transfer successfully on its side. A completed transfer is defined as when the DMA Channel reaches its limit; Memory Start Address equals Memory End Address." "0: Memory Start Address does not equal Memory End..,1: Memory Start Address equals Memory End Address" bitfld.byte 0x0 1. "FLOW_CTRL,This is an interrupt source register. This flags when the DMA Channel has encountered a Hardware Flow Control Request after the DMA Channel has completed the transfer. This means the Master Device is attempting to overflow the DMA." "0: No Hardware Flow Control event,1: Hardware Flow Control is requesting after the.." newline bitfld.byte 0x0 0. "BUS_ERR,This is an interrupt source register. This flags when there is an Error detected over the internal 32-bit Bus. 1: Error detected. (R/WC)" "?,1: Error detected" group.byte 0x18++0x0 line.byte 0x0 "IEN,DMA CHANNEL N INTERRUPT ENABLE" bitfld.byte 0x0 2. "STS_EN_DONE,This is an interrupt enable for DMA Channel Interrupt:Status Done. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" bitfld.byte 0x0 1. "STS_EN_FLOW_CTRL,This is an interrupt enable for DMA Channel Interrupt:Status Flow Control Error. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" newline bitfld.byte 0x0 0. "STS_EN_BUS_ERR,This is an interrupt enable for DMA Channel Interrupt:Status Bus Error. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" tree.end tree "DMA_CHAN04" base ad:0x40002540 group.byte 0x0++0x0 line.byte 0x0 "ACTIVATE,Enable this channel for operation. The DMA Main Control: Activate must also be enabled for this channel to be operational." bitfld.byte 0x0 0. "CHN,Enable this channel for operation. The DMA Main Control:Activate must also be enabled for this channel to be operational. 1=Enable channel(block). Each individual channel must be enabled separately. 0=Disable.." "0: Disable channel,1: Enable channel" group.long 0x4++0xF line.long 0x0 "MSTART,This is the starting address for the Memory device." line.long 0x4 "MEND,This is the ending address for the Memory device." line.long 0x8 "DSTART,This is the Master Device address." line.long 0xC "CTRL,DMA Channel N Control" bitfld.long 0xC 25. "TRANS_ABORT,This is used to abort the current transfer on this DMA Channel. The aborted transfer will be forced to terminate immediately." "0,1" bitfld.long 0xC 24. "TRANS_GO,This is used for the Firmware Flow Control DMA transfer." "0,1" newline bitfld.long 0xC 20.--22. "TRANS_SIZE,This is the transfer size in Bytes of each Data Packet transfer. Note: The transfer size must be a legal AMBA transfer size. Valid sizes are 1 2 and 4 Bytes." "0,1,2,3,4,5,6,7" bitfld.long 0xC 19. "DIS_HW_FLOW_CTRL,This will Disable the Hardware Flow Control. When disabled any DMA Master device attempting to communicate to the DMA over the DMA Flow Control Interface (Ports: dma_req dma_term and dma_done) will be ignored. This should be set.." "0,1" newline bitfld.long 0xC 18. "LOCK,This is used to lock the arbitration of the Channel Arbiter on this channel once this channel is granted. Once this is locked it will remain on the arbiter until it has completed it transfer (either the Transfer Aborted Transfer Done or Transfer.." "0,1" bitfld.long 0xC 17. "INC_DEV_ADDR,This will enable an auto-increment to the DMA Channel Device Address. 1: Increment the DMA Channel Device Address by DMA Channel Control:Transfer Size after every Data Packet transfer 0: Do nothing" "0: Do nothing,1: Increment the DMA Channel Device Address by DMA.." newline bitfld.long 0xC 16. "INC_MEM_ADDR,This will enable an auto-increment to the DMA Channel Memory Address. 1=Increment the DMA Channel Memory Address by DMA Channel Control:Transfer Size after every Data Packet transfer 0=Do nothing" "0: Do nothing,1: Increment the DMA Channel Memory Address by DMA.." hexmask.long.byte 0xC 9.--15. 1. "HW_FLOW_CTRL_DEV,This is the device that is connected to this channel as its Hardware Flow Control master. The Flow Control Interface is a bus with each master concatenated onto it. This selects which bus index of the.." newline bitfld.long 0xC 8. "TX_DIR,This determines the direction of the DMA Transfer. 1=Data Packet Read from Memory Start Address followed by Data Packet Write to Device Address 0=Data Packet Read from Device Address followed by Data Packet Write.." "0: Data Packet Read from Device Address followed by..,1: Data Packet Read from Memory Start Address.." bitfld.long 0xC 5. "BUSY,This is a status signal. 1=The DMA Channel is busy (FSM is not IDLE) 0=The DMA Channel is not busy (FSM is IDLE)" "0: The DMA Channel is not busy,1: The DMA Channel is busy" newline bitfld.long 0xC 3.--4. "STS,This is a status signal. The status decode is listed in priority order with the highest priority first. 3: Error detected by the DMA 2: The DMA Channel is externally done in that the Device has terminated the.." "0: DMA Channel Control:Run is Disabled,1: The DMA Channel is locally done,2: The DMA Channel is externally done,3: Error detected by the DMA" bitfld.long 0xC 2. "DONE,This is a status signal. It is only valid while DMA Channel Control: Run is Enabled. This is the inverse of the DMA Channel Control: Busy field except this is qualified with the DMA Channel Control:Run field." "0: Channel is not done or it is OFF,1: Channel is done" newline bitfld.long 0xC 1. "REQ,This is a status field. 1= There is a transfer request from the Master Device 0= There is no transfer request from the Master Device" "0: There is no transfer request from the Master..,1: There is a transfer request from the Master Device" bitfld.long 0xC 0. "RUN,This is a control field. Note: This bit only applies to Hardware Flow Control mode. 1= This channel is enabled and will service transfer requests 0=This channel is disabled. All transfer requests are ignored." "0: This channel is disabled,1: This channel is enabled and will service.." group.byte 0x14++0x0 line.byte 0x0 "ISTS,DMA Channel N Interrupt Status" bitfld.byte 0x0 2. "DONE,This is an interrupt source register. This flags when the DMA Channel has completed a transfer successfully on its side. A completed transfer is defined as when the DMA Channel reaches its limit; Memory Start Address equals Memory End Address." "0: Memory Start Address does not equal Memory End..,1: Memory Start Address equals Memory End Address" bitfld.byte 0x0 1. "FLOW_CTRL,This is an interrupt source register. This flags when the DMA Channel has encountered a Hardware Flow Control Request after the DMA Channel has completed the transfer. This means the Master Device is attempting to overflow the DMA." "0: No Hardware Flow Control event,1: Hardware Flow Control is requesting after the.." newline bitfld.byte 0x0 0. "BUS_ERR,This is an interrupt source register. This flags when there is an Error detected over the internal 32-bit Bus. 1: Error detected. (R/WC)" "?,1: Error detected" group.byte 0x18++0x0 line.byte 0x0 "IEN,DMA CHANNEL N INTERRUPT ENABLE" bitfld.byte 0x0 2. "STS_EN_DONE,This is an interrupt enable for DMA Channel Interrupt:Status Done. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" bitfld.byte 0x0 1. "STS_EN_FLOW_CTRL,This is an interrupt enable for DMA Channel Interrupt:Status Flow Control Error. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" newline bitfld.byte 0x0 0. "STS_EN_BUS_ERR,This is an interrupt enable for DMA Channel Interrupt:Status Bus Error. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" tree.end tree "DMA_CHAN05" base ad:0x40002580 group.byte 0x0++0x0 line.byte 0x0 "ACTIVATE,Enable this channel for operation. The DMA Main Control: Activate must also be enabled for this channel to be operational." bitfld.byte 0x0 0. "CHN,Enable this channel for operation. The DMA Main Control:Activate must also be enabled for this channel to be operational. 1=Enable channel(block). Each individual channel must be enabled separately. 0=Disable.." "0: Disable channel,1: Enable channel" group.long 0x4++0xF line.long 0x0 "MSTART,This is the starting address for the Memory device." line.long 0x4 "MEND,This is the ending address for the Memory device." line.long 0x8 "DSTART,This is the Master Device address." line.long 0xC "CTRL,DMA Channel N Control" bitfld.long 0xC 25. "TRANS_ABORT,This is used to abort the current transfer on this DMA Channel. The aborted transfer will be forced to terminate immediately." "0,1" bitfld.long 0xC 24. "TRANS_GO,This is used for the Firmware Flow Control DMA transfer." "0,1" newline bitfld.long 0xC 20.--22. "TRANS_SIZE,This is the transfer size in Bytes of each Data Packet transfer. Note: The transfer size must be a legal AMBA transfer size. Valid sizes are 1 2 and 4 Bytes." "0,1,2,3,4,5,6,7" bitfld.long 0xC 19. "DIS_HW_FLOW_CTRL,This will Disable the Hardware Flow Control. When disabled any DMA Master device attempting to communicate to the DMA over the DMA Flow Control Interface (Ports: dma_req dma_term and dma_done) will be ignored. This should be set.." "0,1" newline bitfld.long 0xC 18. "LOCK,This is used to lock the arbitration of the Channel Arbiter on this channel once this channel is granted. Once this is locked it will remain on the arbiter until it has completed it transfer (either the Transfer Aborted Transfer Done or Transfer.." "0,1" bitfld.long 0xC 17. "INC_DEV_ADDR,This will enable an auto-increment to the DMA Channel Device Address. 1: Increment the DMA Channel Device Address by DMA Channel Control:Transfer Size after every Data Packet transfer 0: Do nothing" "0: Do nothing,1: Increment the DMA Channel Device Address by DMA.." newline bitfld.long 0xC 16. "INC_MEM_ADDR,This will enable an auto-increment to the DMA Channel Memory Address. 1=Increment the DMA Channel Memory Address by DMA Channel Control:Transfer Size after every Data Packet transfer 0=Do nothing" "0: Do nothing,1: Increment the DMA Channel Memory Address by DMA.." hexmask.long.byte 0xC 9.--15. 1. "HW_FLOW_CTRL_DEV,This is the device that is connected to this channel as its Hardware Flow Control master. The Flow Control Interface is a bus with each master concatenated onto it. This selects which bus index of the.." newline bitfld.long 0xC 8. "TX_DIR,This determines the direction of the DMA Transfer. 1=Data Packet Read from Memory Start Address followed by Data Packet Write to Device Address 0=Data Packet Read from Device Address followed by Data Packet Write.." "0: Data Packet Read from Device Address followed by..,1: Data Packet Read from Memory Start Address.." bitfld.long 0xC 5. "BUSY,This is a status signal. 1=The DMA Channel is busy (FSM is not IDLE) 0=The DMA Channel is not busy (FSM is IDLE)" "0: The DMA Channel is not busy,1: The DMA Channel is busy" newline bitfld.long 0xC 3.--4. "STS,This is a status signal. The status decode is listed in priority order with the highest priority first. 3: Error detected by the DMA 2: The DMA Channel is externally done in that the Device has terminated the.." "0: DMA Channel Control:Run is Disabled,1: The DMA Channel is locally done,2: The DMA Channel is externally done,3: Error detected by the DMA" bitfld.long 0xC 2. "DONE,This is a status signal. It is only valid while DMA Channel Control: Run is Enabled. This is the inverse of the DMA Channel Control: Busy field except this is qualified with the DMA Channel Control:Run field." "0: Channel is not done or it is OFF,1: Channel is done" newline bitfld.long 0xC 1. "REQ,This is a status field. 1= There is a transfer request from the Master Device 0= There is no transfer request from the Master Device" "0: There is no transfer request from the Master..,1: There is a transfer request from the Master Device" bitfld.long 0xC 0. "RUN,This is a control field. Note: This bit only applies to Hardware Flow Control mode. 1= This channel is enabled and will service transfer requests 0=This channel is disabled. All transfer requests are ignored." "0: This channel is disabled,1: This channel is enabled and will service.." group.byte 0x14++0x0 line.byte 0x0 "ISTS,DMA Channel N Interrupt Status" bitfld.byte 0x0 2. "DONE,This is an interrupt source register. This flags when the DMA Channel has completed a transfer successfully on its side. A completed transfer is defined as when the DMA Channel reaches its limit; Memory Start Address equals Memory End Address." "0: Memory Start Address does not equal Memory End..,1: Memory Start Address equals Memory End Address" bitfld.byte 0x0 1. "FLOW_CTRL,This is an interrupt source register. This flags when the DMA Channel has encountered a Hardware Flow Control Request after the DMA Channel has completed the transfer. This means the Master Device is attempting to overflow the DMA." "0: No Hardware Flow Control event,1: Hardware Flow Control is requesting after the.." newline bitfld.byte 0x0 0. "BUS_ERR,This is an interrupt source register. This flags when there is an Error detected over the internal 32-bit Bus. 1: Error detected. (R/WC)" "?,1: Error detected" group.byte 0x18++0x0 line.byte 0x0 "IEN,DMA CHANNEL N INTERRUPT ENABLE" bitfld.byte 0x0 2. "STS_EN_DONE,This is an interrupt enable for DMA Channel Interrupt:Status Done. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" bitfld.byte 0x0 1. "STS_EN_FLOW_CTRL,This is an interrupt enable for DMA Channel Interrupt:Status Flow Control Error. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" newline bitfld.byte 0x0 0. "STS_EN_BUS_ERR,This is an interrupt enable for DMA Channel Interrupt:Status Bus Error. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" tree.end tree "DMA_CHAN06" base ad:0x400025C0 group.byte 0x0++0x0 line.byte 0x0 "ACTIVATE,Enable this channel for operation. The DMA Main Control: Activate must also be enabled for this channel to be operational." bitfld.byte 0x0 0. "CHN,Enable this channel for operation. The DMA Main Control:Activate must also be enabled for this channel to be operational. 1=Enable channel(block). Each individual channel must be enabled separately. 0=Disable.." "0: Disable channel,1: Enable channel" group.long 0x4++0xF line.long 0x0 "MSTART,This is the starting address for the Memory device." line.long 0x4 "MEND,This is the ending address for the Memory device." line.long 0x8 "DSTART,This is the Master Device address." line.long 0xC "CTRL,DMA Channel N Control" bitfld.long 0xC 25. "TRANS_ABORT,This is used to abort the current transfer on this DMA Channel. The aborted transfer will be forced to terminate immediately." "0,1" bitfld.long 0xC 24. "TRANS_GO,This is used for the Firmware Flow Control DMA transfer." "0,1" newline bitfld.long 0xC 20.--22. "TRANS_SIZE,This is the transfer size in Bytes of each Data Packet transfer. Note: The transfer size must be a legal AMBA transfer size. Valid sizes are 1 2 and 4 Bytes." "0,1,2,3,4,5,6,7" bitfld.long 0xC 19. "DIS_HW_FLOW_CTRL,This will Disable the Hardware Flow Control. When disabled any DMA Master device attempting to communicate to the DMA over the DMA Flow Control Interface (Ports: dma_req dma_term and dma_done) will be ignored. This should be set.." "0,1" newline bitfld.long 0xC 18. "LOCK,This is used to lock the arbitration of the Channel Arbiter on this channel once this channel is granted. Once this is locked it will remain on the arbiter until it has completed it transfer (either the Transfer Aborted Transfer Done or Transfer.." "0,1" bitfld.long 0xC 17. "INC_DEV_ADDR,This will enable an auto-increment to the DMA Channel Device Address. 1: Increment the DMA Channel Device Address by DMA Channel Control:Transfer Size after every Data Packet transfer 0: Do nothing" "0: Do nothing,1: Increment the DMA Channel Device Address by DMA.." newline bitfld.long 0xC 16. "INC_MEM_ADDR,This will enable an auto-increment to the DMA Channel Memory Address. 1=Increment the DMA Channel Memory Address by DMA Channel Control:Transfer Size after every Data Packet transfer 0=Do nothing" "0: Do nothing,1: Increment the DMA Channel Memory Address by DMA.." hexmask.long.byte 0xC 9.--15. 1. "HW_FLOW_CTRL_DEV,This is the device that is connected to this channel as its Hardware Flow Control master. The Flow Control Interface is a bus with each master concatenated onto it. This selects which bus index of the.." newline bitfld.long 0xC 8. "TX_DIR,This determines the direction of the DMA Transfer. 1=Data Packet Read from Memory Start Address followed by Data Packet Write to Device Address 0=Data Packet Read from Device Address followed by Data Packet Write.." "0: Data Packet Read from Device Address followed by..,1: Data Packet Read from Memory Start Address.." bitfld.long 0xC 5. "BUSY,This is a status signal. 1=The DMA Channel is busy (FSM is not IDLE) 0=The DMA Channel is not busy (FSM is IDLE)" "0: The DMA Channel is not busy,1: The DMA Channel is busy" newline bitfld.long 0xC 3.--4. "STS,This is a status signal. The status decode is listed in priority order with the highest priority first. 3: Error detected by the DMA 2: The DMA Channel is externally done in that the Device has terminated the.." "0: DMA Channel Control:Run is Disabled,1: The DMA Channel is locally done,2: The DMA Channel is externally done,3: Error detected by the DMA" bitfld.long 0xC 2. "DONE,This is a status signal. It is only valid while DMA Channel Control: Run is Enabled. This is the inverse of the DMA Channel Control: Busy field except this is qualified with the DMA Channel Control:Run field." "0: Channel is not done or it is OFF,1: Channel is done" newline bitfld.long 0xC 1. "REQ,This is a status field. 1= There is a transfer request from the Master Device 0= There is no transfer request from the Master Device" "0: There is no transfer request from the Master..,1: There is a transfer request from the Master Device" bitfld.long 0xC 0. "RUN,This is a control field. Note: This bit only applies to Hardware Flow Control mode. 1= This channel is enabled and will service transfer requests 0=This channel is disabled. All transfer requests are ignored." "0: This channel is disabled,1: This channel is enabled and will service.." group.byte 0x14++0x0 line.byte 0x0 "ISTS,DMA Channel N Interrupt Status" bitfld.byte 0x0 2. "DONE,This is an interrupt source register. This flags when the DMA Channel has completed a transfer successfully on its side. A completed transfer is defined as when the DMA Channel reaches its limit; Memory Start Address equals Memory End Address." "0: Memory Start Address does not equal Memory End..,1: Memory Start Address equals Memory End Address" bitfld.byte 0x0 1. "FLOW_CTRL,This is an interrupt source register. This flags when the DMA Channel has encountered a Hardware Flow Control Request after the DMA Channel has completed the transfer. This means the Master Device is attempting to overflow the DMA." "0: No Hardware Flow Control event,1: Hardware Flow Control is requesting after the.." newline bitfld.byte 0x0 0. "BUS_ERR,This is an interrupt source register. This flags when there is an Error detected over the internal 32-bit Bus. 1: Error detected. (R/WC)" "?,1: Error detected" group.byte 0x18++0x0 line.byte 0x0 "IEN,DMA CHANNEL N INTERRUPT ENABLE" bitfld.byte 0x0 2. "STS_EN_DONE,This is an interrupt enable for DMA Channel Interrupt:Status Done. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" bitfld.byte 0x0 1. "STS_EN_FLOW_CTRL,This is an interrupt enable for DMA Channel Interrupt:Status Flow Control Error. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" newline bitfld.byte 0x0 0. "STS_EN_BUS_ERR,This is an interrupt enable for DMA Channel Interrupt:Status Bus Error. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" tree.end tree "DMA_CHAN07" base ad:0x40002600 group.byte 0x0++0x0 line.byte 0x0 "ACTIVATE,Enable this channel for operation. The DMA Main Control: Activate must also be enabled for this channel to be operational." bitfld.byte 0x0 0. "CHN,Enable this channel for operation. The DMA Main Control:Activate must also be enabled for this channel to be operational. 1=Enable channel(block). Each individual channel must be enabled separately. 0=Disable.." "0: Disable channel,1: Enable channel" group.long 0x4++0xF line.long 0x0 "MSTART,This is the starting address for the Memory device." line.long 0x4 "MEND,This is the ending address for the Memory device." line.long 0x8 "DSTART,This is the Master Device address." line.long 0xC "CTRL,DMA Channel N Control" bitfld.long 0xC 25. "TRANS_ABORT,This is used to abort the current transfer on this DMA Channel. The aborted transfer will be forced to terminate immediately." "0,1" bitfld.long 0xC 24. "TRANS_GO,This is used for the Firmware Flow Control DMA transfer." "0,1" newline bitfld.long 0xC 20.--22. "TRANS_SIZE,This is the transfer size in Bytes of each Data Packet transfer. Note: The transfer size must be a legal AMBA transfer size. Valid sizes are 1 2 and 4 Bytes." "0,1,2,3,4,5,6,7" bitfld.long 0xC 19. "DIS_HW_FLOW_CTRL,This will Disable the Hardware Flow Control. When disabled any DMA Master device attempting to communicate to the DMA over the DMA Flow Control Interface (Ports: dma_req dma_term and dma_done) will be ignored. This should be set.." "0,1" newline bitfld.long 0xC 18. "LOCK,This is used to lock the arbitration of the Channel Arbiter on this channel once this channel is granted. Once this is locked it will remain on the arbiter until it has completed it transfer (either the Transfer Aborted Transfer Done or Transfer.." "0,1" bitfld.long 0xC 17. "INC_DEV_ADDR,This will enable an auto-increment to the DMA Channel Device Address. 1: Increment the DMA Channel Device Address by DMA Channel Control:Transfer Size after every Data Packet transfer 0: Do nothing" "0: Do nothing,1: Increment the DMA Channel Device Address by DMA.." newline bitfld.long 0xC 16. "INC_MEM_ADDR,This will enable an auto-increment to the DMA Channel Memory Address. 1=Increment the DMA Channel Memory Address by DMA Channel Control:Transfer Size after every Data Packet transfer 0=Do nothing" "0: Do nothing,1: Increment the DMA Channel Memory Address by DMA.." hexmask.long.byte 0xC 9.--15. 1. "HW_FLOW_CTRL_DEV,This is the device that is connected to this channel as its Hardware Flow Control master. The Flow Control Interface is a bus with each master concatenated onto it. This selects which bus index of the.." newline bitfld.long 0xC 8. "TX_DIR,This determines the direction of the DMA Transfer. 1=Data Packet Read from Memory Start Address followed by Data Packet Write to Device Address 0=Data Packet Read from Device Address followed by Data Packet Write.." "0: Data Packet Read from Device Address followed by..,1: Data Packet Read from Memory Start Address.." bitfld.long 0xC 5. "BUSY,This is a status signal. 1=The DMA Channel is busy (FSM is not IDLE) 0=The DMA Channel is not busy (FSM is IDLE)" "0: The DMA Channel is not busy,1: The DMA Channel is busy" newline bitfld.long 0xC 3.--4. "STS,This is a status signal. The status decode is listed in priority order with the highest priority first. 3: Error detected by the DMA 2: The DMA Channel is externally done in that the Device has terminated the.." "0: DMA Channel Control:Run is Disabled,1: The DMA Channel is locally done,2: The DMA Channel is externally done,3: Error detected by the DMA" bitfld.long 0xC 2. "DONE,This is a status signal. It is only valid while DMA Channel Control: Run is Enabled. This is the inverse of the DMA Channel Control: Busy field except this is qualified with the DMA Channel Control:Run field." "0: Channel is not done or it is OFF,1: Channel is done" newline bitfld.long 0xC 1. "REQ,This is a status field. 1= There is a transfer request from the Master Device 0= There is no transfer request from the Master Device" "0: There is no transfer request from the Master..,1: There is a transfer request from the Master Device" bitfld.long 0xC 0. "RUN,This is a control field. Note: This bit only applies to Hardware Flow Control mode. 1= This channel is enabled and will service transfer requests 0=This channel is disabled. All transfer requests are ignored." "0: This channel is disabled,1: This channel is enabled and will service.." group.byte 0x14++0x0 line.byte 0x0 "ISTS,DMA Channel N Interrupt Status" bitfld.byte 0x0 2. "DONE,This is an interrupt source register. This flags when the DMA Channel has completed a transfer successfully on its side. A completed transfer is defined as when the DMA Channel reaches its limit; Memory Start Address equals Memory End Address." "0: Memory Start Address does not equal Memory End..,1: Memory Start Address equals Memory End Address" bitfld.byte 0x0 1. "FLOW_CTRL,This is an interrupt source register. This flags when the DMA Channel has encountered a Hardware Flow Control Request after the DMA Channel has completed the transfer. This means the Master Device is attempting to overflow the DMA." "0: No Hardware Flow Control event,1: Hardware Flow Control is requesting after the.." newline bitfld.byte 0x0 0. "BUS_ERR,This is an interrupt source register. This flags when there is an Error detected over the internal 32-bit Bus. 1: Error detected. (R/WC)" "?,1: Error detected" group.byte 0x18++0x0 line.byte 0x0 "IEN,DMA CHANNEL N INTERRUPT ENABLE" bitfld.byte 0x0 2. "STS_EN_DONE,This is an interrupt enable for DMA Channel Interrupt:Status Done. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" bitfld.byte 0x0 1. "STS_EN_FLOW_CTRL,This is an interrupt enable for DMA Channel Interrupt:Status Flow Control Error. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" newline bitfld.byte 0x0 0. "STS_EN_BUS_ERR,This is an interrupt enable for DMA Channel Interrupt:Status Bus Error. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" tree.end tree "DMA_CHAN08" base ad:0x40002640 group.byte 0x0++0x0 line.byte 0x0 "ACTIVATE,Enable this channel for operation. The DMA Main Control: Activate must also be enabled for this channel to be operational." bitfld.byte 0x0 0. "CHN,Enable this channel for operation. The DMA Main Control:Activate must also be enabled for this channel to be operational. 1=Enable channel(block). Each individual channel must be enabled separately. 0=Disable.." "0: Disable channel,1: Enable channel" group.long 0x4++0xF line.long 0x0 "MSTART,This is the starting address for the Memory device." line.long 0x4 "MEND,This is the ending address for the Memory device." line.long 0x8 "DSTART,This is the Master Device address." line.long 0xC "CTRL,DMA Channel N Control" bitfld.long 0xC 25. "TRANS_ABORT,This is used to abort the current transfer on this DMA Channel. The aborted transfer will be forced to terminate immediately." "0,1" bitfld.long 0xC 24. "TRANS_GO,This is used for the Firmware Flow Control DMA transfer." "0,1" newline bitfld.long 0xC 20.--22. "TRANS_SIZE,This is the transfer size in Bytes of each Data Packet transfer. Note: The transfer size must be a legal AMBA transfer size. Valid sizes are 1 2 and 4 Bytes." "0,1,2,3,4,5,6,7" bitfld.long 0xC 19. "DIS_HW_FLOW_CTRL,This will Disable the Hardware Flow Control. When disabled any DMA Master device attempting to communicate to the DMA over the DMA Flow Control Interface (Ports: dma_req dma_term and dma_done) will be ignored. This should be set.." "0,1" newline bitfld.long 0xC 18. "LOCK,This is used to lock the arbitration of the Channel Arbiter on this channel once this channel is granted. Once this is locked it will remain on the arbiter until it has completed it transfer (either the Transfer Aborted Transfer Done or Transfer.." "0,1" bitfld.long 0xC 17. "INC_DEV_ADDR,This will enable an auto-increment to the DMA Channel Device Address. 1: Increment the DMA Channel Device Address by DMA Channel Control:Transfer Size after every Data Packet transfer 0: Do nothing" "0: Do nothing,1: Increment the DMA Channel Device Address by DMA.." newline bitfld.long 0xC 16. "INC_MEM_ADDR,This will enable an auto-increment to the DMA Channel Memory Address. 1=Increment the DMA Channel Memory Address by DMA Channel Control:Transfer Size after every Data Packet transfer 0=Do nothing" "0: Do nothing,1: Increment the DMA Channel Memory Address by DMA.." hexmask.long.byte 0xC 9.--15. 1. "HW_FLOW_CTRL_DEV,This is the device that is connected to this channel as its Hardware Flow Control master. The Flow Control Interface is a bus with each master concatenated onto it. This selects which bus index of the.." newline bitfld.long 0xC 8. "TX_DIR,This determines the direction of the DMA Transfer. 1=Data Packet Read from Memory Start Address followed by Data Packet Write to Device Address 0=Data Packet Read from Device Address followed by Data Packet Write.." "0: Data Packet Read from Device Address followed by..,1: Data Packet Read from Memory Start Address.." bitfld.long 0xC 5. "BUSY,This is a status signal. 1=The DMA Channel is busy (FSM is not IDLE) 0=The DMA Channel is not busy (FSM is IDLE)" "0: The DMA Channel is not busy,1: The DMA Channel is busy" newline bitfld.long 0xC 3.--4. "STS,This is a status signal. The status decode is listed in priority order with the highest priority first. 3: Error detected by the DMA 2: The DMA Channel is externally done in that the Device has terminated the.." "0: DMA Channel Control:Run is Disabled,1: The DMA Channel is locally done,2: The DMA Channel is externally done,3: Error detected by the DMA" bitfld.long 0xC 2. "DONE,This is a status signal. It is only valid while DMA Channel Control: Run is Enabled. This is the inverse of the DMA Channel Control: Busy field except this is qualified with the DMA Channel Control:Run field." "0: Channel is not done or it is OFF,1: Channel is done" newline bitfld.long 0xC 1. "REQ,This is a status field. 1= There is a transfer request from the Master Device 0= There is no transfer request from the Master Device" "0: There is no transfer request from the Master..,1: There is a transfer request from the Master Device" bitfld.long 0xC 0. "RUN,This is a control field. Note: This bit only applies to Hardware Flow Control mode. 1= This channel is enabled and will service transfer requests 0=This channel is disabled. All transfer requests are ignored." "0: This channel is disabled,1: This channel is enabled and will service.." group.byte 0x14++0x0 line.byte 0x0 "ISTS,DMA Channel N Interrupt Status" bitfld.byte 0x0 2. "DONE,This is an interrupt source register. This flags when the DMA Channel has completed a transfer successfully on its side. A completed transfer is defined as when the DMA Channel reaches its limit; Memory Start Address equals Memory End Address." "0: Memory Start Address does not equal Memory End..,1: Memory Start Address equals Memory End Address" bitfld.byte 0x0 1. "FLOW_CTRL,This is an interrupt source register. This flags when the DMA Channel has encountered a Hardware Flow Control Request after the DMA Channel has completed the transfer. This means the Master Device is attempting to overflow the DMA." "0: No Hardware Flow Control event,1: Hardware Flow Control is requesting after the.." newline bitfld.byte 0x0 0. "BUS_ERR,This is an interrupt source register. This flags when there is an Error detected over the internal 32-bit Bus. 1: Error detected. (R/WC)" "?,1: Error detected" group.byte 0x18++0x0 line.byte 0x0 "IEN,DMA CHANNEL N INTERRUPT ENABLE" bitfld.byte 0x0 2. "STS_EN_DONE,This is an interrupt enable for DMA Channel Interrupt:Status Done. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" bitfld.byte 0x0 1. "STS_EN_FLOW_CTRL,This is an interrupt enable for DMA Channel Interrupt:Status Flow Control Error. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" newline bitfld.byte 0x0 0. "STS_EN_BUS_ERR,This is an interrupt enable for DMA Channel Interrupt:Status Bus Error. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" tree.end tree "DMA_CHAN09" base ad:0x40002680 group.byte 0x0++0x0 line.byte 0x0 "ACTIVATE,Enable this channel for operation. The DMA Main Control: Activate must also be enabled for this channel to be operational." bitfld.byte 0x0 0. "CHN,Enable this channel for operation. The DMA Main Control:Activate must also be enabled for this channel to be operational. 1=Enable channel(block). Each individual channel must be enabled separately. 0=Disable.." "0: Disable channel,1: Enable channel" group.long 0x4++0xF line.long 0x0 "MSTART,This is the starting address for the Memory device." line.long 0x4 "MEND,This is the ending address for the Memory device." line.long 0x8 "DSTART,This is the Master Device address." line.long 0xC "CTRL,DMA Channel N Control" bitfld.long 0xC 25. "TRANS_ABORT,This is used to abort the current transfer on this DMA Channel. The aborted transfer will be forced to terminate immediately." "0,1" bitfld.long 0xC 24. "TRANS_GO,This is used for the Firmware Flow Control DMA transfer." "0,1" newline bitfld.long 0xC 20.--22. "TRANS_SIZE,This is the transfer size in Bytes of each Data Packet transfer. Note: The transfer size must be a legal AMBA transfer size. Valid sizes are 1 2 and 4 Bytes." "0,1,2,3,4,5,6,7" bitfld.long 0xC 19. "DIS_HW_FLOW_CTRL,This will Disable the Hardware Flow Control. When disabled any DMA Master device attempting to communicate to the DMA over the DMA Flow Control Interface (Ports: dma_req dma_term and dma_done) will be ignored. This should be set.." "0,1" newline bitfld.long 0xC 18. "LOCK,This is used to lock the arbitration of the Channel Arbiter on this channel once this channel is granted. Once this is locked it will remain on the arbiter until it has completed it transfer (either the Transfer Aborted Transfer Done or Transfer.." "0,1" bitfld.long 0xC 17. "INC_DEV_ADDR,This will enable an auto-increment to the DMA Channel Device Address. 1: Increment the DMA Channel Device Address by DMA Channel Control:Transfer Size after every Data Packet transfer 0: Do nothing" "0: Do nothing,1: Increment the DMA Channel Device Address by DMA.." newline bitfld.long 0xC 16. "INC_MEM_ADDR,This will enable an auto-increment to the DMA Channel Memory Address. 1=Increment the DMA Channel Memory Address by DMA Channel Control:Transfer Size after every Data Packet transfer 0=Do nothing" "0: Do nothing,1: Increment the DMA Channel Memory Address by DMA.." hexmask.long.byte 0xC 9.--15. 1. "HW_FLOW_CTRL_DEV,This is the device that is connected to this channel as its Hardware Flow Control master. The Flow Control Interface is a bus with each master concatenated onto it. This selects which bus index of the.." newline bitfld.long 0xC 8. "TX_DIR,This determines the direction of the DMA Transfer. 1=Data Packet Read from Memory Start Address followed by Data Packet Write to Device Address 0=Data Packet Read from Device Address followed by Data Packet Write.." "0: Data Packet Read from Device Address followed by..,1: Data Packet Read from Memory Start Address.." bitfld.long 0xC 5. "BUSY,This is a status signal. 1=The DMA Channel is busy (FSM is not IDLE) 0=The DMA Channel is not busy (FSM is IDLE)" "0: The DMA Channel is not busy,1: The DMA Channel is busy" newline bitfld.long 0xC 3.--4. "STS,This is a status signal. The status decode is listed in priority order with the highest priority first. 3: Error detected by the DMA 2: The DMA Channel is externally done in that the Device has terminated the.." "0: DMA Channel Control:Run is Disabled,1: The DMA Channel is locally done,2: The DMA Channel is externally done,3: Error detected by the DMA" bitfld.long 0xC 2. "DONE,This is a status signal. It is only valid while DMA Channel Control: Run is Enabled. This is the inverse of the DMA Channel Control: Busy field except this is qualified with the DMA Channel Control:Run field." "0: Channel is not done or it is OFF,1: Channel is done" newline bitfld.long 0xC 1. "REQ,This is a status field. 1= There is a transfer request from the Master Device 0= There is no transfer request from the Master Device" "0: There is no transfer request from the Master..,1: There is a transfer request from the Master Device" bitfld.long 0xC 0. "RUN,This is a control field. Note: This bit only applies to Hardware Flow Control mode. 1= This channel is enabled and will service transfer requests 0=This channel is disabled. All transfer requests are ignored." "0: This channel is disabled,1: This channel is enabled and will service.." group.byte 0x14++0x0 line.byte 0x0 "ISTS,DMA Channel N Interrupt Status" bitfld.byte 0x0 2. "DONE,This is an interrupt source register. This flags when the DMA Channel has completed a transfer successfully on its side. A completed transfer is defined as when the DMA Channel reaches its limit; Memory Start Address equals Memory End Address." "0: Memory Start Address does not equal Memory End..,1: Memory Start Address equals Memory End Address" bitfld.byte 0x0 1. "FLOW_CTRL,This is an interrupt source register. This flags when the DMA Channel has encountered a Hardware Flow Control Request after the DMA Channel has completed the transfer. This means the Master Device is attempting to overflow the DMA." "0: No Hardware Flow Control event,1: Hardware Flow Control is requesting after the.." newline bitfld.byte 0x0 0. "BUS_ERR,This is an interrupt source register. This flags when there is an Error detected over the internal 32-bit Bus. 1: Error detected. (R/WC)" "?,1: Error detected" group.byte 0x18++0x0 line.byte 0x0 "IEN,DMA CHANNEL N INTERRUPT ENABLE" bitfld.byte 0x0 2. "STS_EN_DONE,This is an interrupt enable for DMA Channel Interrupt:Status Done. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" bitfld.byte 0x0 1. "STS_EN_FLOW_CTRL,This is an interrupt enable for DMA Channel Interrupt:Status Flow Control Error. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" newline bitfld.byte 0x0 0. "STS_EN_BUS_ERR,This is an interrupt enable for DMA Channel Interrupt:Status Bus Error. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" tree.end tree "DMA_CHAN10" base ad:0x400026C0 group.byte 0x0++0x0 line.byte 0x0 "ACTIVATE,Enable this channel for operation. The DMA Main Control: Activate must also be enabled for this channel to be operational." bitfld.byte 0x0 0. "CHN,Enable this channel for operation. The DMA Main Control:Activate must also be enabled for this channel to be operational. 1=Enable channel(block). Each individual channel must be enabled separately. 0=Disable.." "0: Disable channel,1: Enable channel" group.long 0x4++0xF line.long 0x0 "MSTART,This is the starting address for the Memory device." line.long 0x4 "MEND,This is the ending address for the Memory device." line.long 0x8 "DSTART,This is the Master Device address." line.long 0xC "CTRL,DMA Channel N Control" bitfld.long 0xC 25. "TRANS_ABORT,This is used to abort the current transfer on this DMA Channel. The aborted transfer will be forced to terminate immediately." "0,1" bitfld.long 0xC 24. "TRANS_GO,This is used for the Firmware Flow Control DMA transfer." "0,1" newline bitfld.long 0xC 20.--22. "TRANS_SIZE,This is the transfer size in Bytes of each Data Packet transfer. Note: The transfer size must be a legal AMBA transfer size. Valid sizes are 1 2 and 4 Bytes." "0,1,2,3,4,5,6,7" bitfld.long 0xC 19. "DIS_HW_FLOW_CTRL,This will Disable the Hardware Flow Control. When disabled any DMA Master device attempting to communicate to the DMA over the DMA Flow Control Interface (Ports: dma_req dma_term and dma_done) will be ignored. This should be set.." "0,1" newline bitfld.long 0xC 18. "LOCK,This is used to lock the arbitration of the Channel Arbiter on this channel once this channel is granted. Once this is locked it will remain on the arbiter until it has completed it transfer (either the Transfer Aborted Transfer Done or Transfer.." "0,1" bitfld.long 0xC 17. "INC_DEV_ADDR,This will enable an auto-increment to the DMA Channel Device Address. 1: Increment the DMA Channel Device Address by DMA Channel Control:Transfer Size after every Data Packet transfer 0: Do nothing" "0: Do nothing,1: Increment the DMA Channel Device Address by DMA.." newline bitfld.long 0xC 16. "INC_MEM_ADDR,This will enable an auto-increment to the DMA Channel Memory Address. 1=Increment the DMA Channel Memory Address by DMA Channel Control:Transfer Size after every Data Packet transfer 0=Do nothing" "0: Do nothing,1: Increment the DMA Channel Memory Address by DMA.." hexmask.long.byte 0xC 9.--15. 1. "HW_FLOW_CTRL_DEV,This is the device that is connected to this channel as its Hardware Flow Control master. The Flow Control Interface is a bus with each master concatenated onto it. This selects which bus index of the.." newline bitfld.long 0xC 8. "TX_DIR,This determines the direction of the DMA Transfer. 1=Data Packet Read from Memory Start Address followed by Data Packet Write to Device Address 0=Data Packet Read from Device Address followed by Data Packet Write.." "0: Data Packet Read from Device Address followed by..,1: Data Packet Read from Memory Start Address.." bitfld.long 0xC 5. "BUSY,This is a status signal. 1=The DMA Channel is busy (FSM is not IDLE) 0=The DMA Channel is not busy (FSM is IDLE)" "0: The DMA Channel is not busy,1: The DMA Channel is busy" newline bitfld.long 0xC 3.--4. "STS,This is a status signal. The status decode is listed in priority order with the highest priority first. 3: Error detected by the DMA 2: The DMA Channel is externally done in that the Device has terminated the.." "0: DMA Channel Control:Run is Disabled,1: The DMA Channel is locally done,2: The DMA Channel is externally done,3: Error detected by the DMA" bitfld.long 0xC 2. "DONE,This is a status signal. It is only valid while DMA Channel Control: Run is Enabled. This is the inverse of the DMA Channel Control: Busy field except this is qualified with the DMA Channel Control:Run field." "0: Channel is not done or it is OFF,1: Channel is done" newline bitfld.long 0xC 1. "REQ,This is a status field. 1= There is a transfer request from the Master Device 0= There is no transfer request from the Master Device" "0: There is no transfer request from the Master..,1: There is a transfer request from the Master Device" bitfld.long 0xC 0. "RUN,This is a control field. Note: This bit only applies to Hardware Flow Control mode. 1= This channel is enabled and will service transfer requests 0=This channel is disabled. All transfer requests are ignored." "0: This channel is disabled,1: This channel is enabled and will service.." group.byte 0x14++0x0 line.byte 0x0 "ISTS,DMA Channel N Interrupt Status" bitfld.byte 0x0 2. "DONE,This is an interrupt source register. This flags when the DMA Channel has completed a transfer successfully on its side. A completed transfer is defined as when the DMA Channel reaches its limit; Memory Start Address equals Memory End Address." "0: Memory Start Address does not equal Memory End..,1: Memory Start Address equals Memory End Address" bitfld.byte 0x0 1. "FLOW_CTRL,This is an interrupt source register. This flags when the DMA Channel has encountered a Hardware Flow Control Request after the DMA Channel has completed the transfer. This means the Master Device is attempting to overflow the DMA." "0: No Hardware Flow Control event,1: Hardware Flow Control is requesting after the.." newline bitfld.byte 0x0 0. "BUS_ERR,This is an interrupt source register. This flags when there is an Error detected over the internal 32-bit Bus. 1: Error detected. (R/WC)" "?,1: Error detected" group.byte 0x18++0x0 line.byte 0x0 "IEN,DMA CHANNEL N INTERRUPT ENABLE" bitfld.byte 0x0 2. "STS_EN_DONE,This is an interrupt enable for DMA Channel Interrupt:Status Done. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" bitfld.byte 0x0 1. "STS_EN_FLOW_CTRL,This is an interrupt enable for DMA Channel Interrupt:Status Flow Control Error. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" newline bitfld.byte 0x0 0. "STS_EN_BUS_ERR,This is an interrupt enable for DMA Channel Interrupt:Status Bus Error. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" tree.end tree "DMA_CHAN11" base ad:0x40002700 group.byte 0x0++0x0 line.byte 0x0 "ACTIVATE,Enable this channel for operation. The DMA Main Control: Activate must also be enabled for this channel to be operational." bitfld.byte 0x0 0. "CHN,Enable this channel for operation. The DMA Main Control:Activate must also be enabled for this channel to be operational. 1=Enable channel(block). Each individual channel must be enabled separately. 0=Disable.." "0: Disable channel,1: Enable channel" group.long 0x4++0xF line.long 0x0 "MSTART,This is the starting address for the Memory device." line.long 0x4 "MEND,This is the ending address for the Memory device." line.long 0x8 "DSTART,This is the Master Device address." line.long 0xC "CTRL,DMA Channel N Control" bitfld.long 0xC 25. "TRANS_ABORT,This is used to abort the current transfer on this DMA Channel. The aborted transfer will be forced to terminate immediately." "0,1" bitfld.long 0xC 24. "TRANS_GO,This is used for the Firmware Flow Control DMA transfer." "0,1" newline bitfld.long 0xC 20.--22. "TRANS_SIZE,This is the transfer size in Bytes of each Data Packet transfer. Note: The transfer size must be a legal AMBA transfer size. Valid sizes are 1 2 and 4 Bytes." "0,1,2,3,4,5,6,7" bitfld.long 0xC 19. "DIS_HW_FLOW_CTRL,This will Disable the Hardware Flow Control. When disabled any DMA Master device attempting to communicate to the DMA over the DMA Flow Control Interface (Ports: dma_req dma_term and dma_done) will be ignored. This should be set.." "0,1" newline bitfld.long 0xC 18. "LOCK,This is used to lock the arbitration of the Channel Arbiter on this channel once this channel is granted. Once this is locked it will remain on the arbiter until it has completed it transfer (either the Transfer Aborted Transfer Done or Transfer.." "0,1" bitfld.long 0xC 17. "INC_DEV_ADDR,This will enable an auto-increment to the DMA Channel Device Address. 1: Increment the DMA Channel Device Address by DMA Channel Control:Transfer Size after every Data Packet transfer 0: Do nothing" "0: Do nothing,1: Increment the DMA Channel Device Address by DMA.." newline bitfld.long 0xC 16. "INC_MEM_ADDR,This will enable an auto-increment to the DMA Channel Memory Address. 1=Increment the DMA Channel Memory Address by DMA Channel Control:Transfer Size after every Data Packet transfer 0=Do nothing" "0: Do nothing,1: Increment the DMA Channel Memory Address by DMA.." hexmask.long.byte 0xC 9.--15. 1. "HW_FLOW_CTRL_DEV,This is the device that is connected to this channel as its Hardware Flow Control master. The Flow Control Interface is a bus with each master concatenated onto it. This selects which bus index of the.." newline bitfld.long 0xC 8. "TX_DIR,This determines the direction of the DMA Transfer. 1=Data Packet Read from Memory Start Address followed by Data Packet Write to Device Address 0=Data Packet Read from Device Address followed by Data Packet Write.." "0: Data Packet Read from Device Address followed by..,1: Data Packet Read from Memory Start Address.." bitfld.long 0xC 5. "BUSY,This is a status signal. 1=The DMA Channel is busy (FSM is not IDLE) 0=The DMA Channel is not busy (FSM is IDLE)" "0: The DMA Channel is not busy,1: The DMA Channel is busy" newline bitfld.long 0xC 3.--4. "STS,This is a status signal. The status decode is listed in priority order with the highest priority first. 3: Error detected by the DMA 2: The DMA Channel is externally done in that the Device has terminated the.." "0: DMA Channel Control:Run is Disabled,1: The DMA Channel is locally done,2: The DMA Channel is externally done,3: Error detected by the DMA" bitfld.long 0xC 2. "DONE,This is a status signal. It is only valid while DMA Channel Control: Run is Enabled. This is the inverse of the DMA Channel Control: Busy field except this is qualified with the DMA Channel Control:Run field." "0: Channel is not done or it is OFF,1: Channel is done" newline bitfld.long 0xC 1. "REQ,This is a status field. 1= There is a transfer request from the Master Device 0= There is no transfer request from the Master Device" "0: There is no transfer request from the Master..,1: There is a transfer request from the Master Device" bitfld.long 0xC 0. "RUN,This is a control field. Note: This bit only applies to Hardware Flow Control mode. 1= This channel is enabled and will service transfer requests 0=This channel is disabled. All transfer requests are ignored." "0: This channel is disabled,1: This channel is enabled and will service.." group.byte 0x14++0x0 line.byte 0x0 "ISTS,DMA Channel N Interrupt Status" bitfld.byte 0x0 2. "DONE,This is an interrupt source register. This flags when the DMA Channel has completed a transfer successfully on its side. A completed transfer is defined as when the DMA Channel reaches its limit; Memory Start Address equals Memory End Address." "0: Memory Start Address does not equal Memory End..,1: Memory Start Address equals Memory End Address" bitfld.byte 0x0 1. "FLOW_CTRL,This is an interrupt source register. This flags when the DMA Channel has encountered a Hardware Flow Control Request after the DMA Channel has completed the transfer. This means the Master Device is attempting to overflow the DMA." "0: No Hardware Flow Control event,1: Hardware Flow Control is requesting after the.." newline bitfld.byte 0x0 0. "BUS_ERR,This is an interrupt source register. This flags when there is an Error detected over the internal 32-bit Bus. 1: Error detected. (R/WC)" "?,1: Error detected" group.byte 0x18++0x0 line.byte 0x0 "IEN,DMA CHANNEL N INTERRUPT ENABLE" bitfld.byte 0x0 2. "STS_EN_DONE,This is an interrupt enable for DMA Channel Interrupt:Status Done. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" bitfld.byte 0x0 1. "STS_EN_FLOW_CTRL,This is an interrupt enable for DMA Channel Interrupt:Status Flow Control Error. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" newline bitfld.byte 0x0 0. "STS_EN_BUS_ERR,This is an interrupt enable for DMA Channel Interrupt:Status Bus Error. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" tree.end tree "DMA_CHAN12" base ad:0x40002740 group.byte 0x0++0x0 line.byte 0x0 "ACTIVATE,Enable this channel for operation. The DMA Main Control: Activate must also be enabled for this channel to be operational." bitfld.byte 0x0 0. "CHN,Enable this channel for operation. The DMA Main Control:Activate must also be enabled for this channel to be operational. 1=Enable channel(block). Each individual channel must be enabled separately. 0=Disable.." "0: Disable channel,1: Enable channel" group.long 0x4++0xF line.long 0x0 "MSTART,This is the starting address for the Memory device." line.long 0x4 "MEND,This is the ending address for the Memory device." line.long 0x8 "DSTART,This is the Master Device address." line.long 0xC "CTRL,DMA Channel N Control" bitfld.long 0xC 25. "TRANS_ABORT,This is used to abort the current transfer on this DMA Channel. The aborted transfer will be forced to terminate immediately." "0,1" bitfld.long 0xC 24. "TRANS_GO,This is used for the Firmware Flow Control DMA transfer." "0,1" newline bitfld.long 0xC 20.--22. "TRANS_SIZE,This is the transfer size in Bytes of each Data Packet transfer. Note: The transfer size must be a legal AMBA transfer size. Valid sizes are 1 2 and 4 Bytes." "0,1,2,3,4,5,6,7" bitfld.long 0xC 19. "DIS_HW_FLOW_CTRL,This will Disable the Hardware Flow Control. When disabled any DMA Master device attempting to communicate to the DMA over the DMA Flow Control Interface (Ports: dma_req dma_term and dma_done) will be ignored. This should be set.." "0,1" newline bitfld.long 0xC 18. "LOCK,This is used to lock the arbitration of the Channel Arbiter on this channel once this channel is granted. Once this is locked it will remain on the arbiter until it has completed it transfer (either the Transfer Aborted Transfer Done or Transfer.." "0,1" bitfld.long 0xC 17. "INC_DEV_ADDR,This will enable an auto-increment to the DMA Channel Device Address. 1: Increment the DMA Channel Device Address by DMA Channel Control:Transfer Size after every Data Packet transfer 0: Do nothing" "0: Do nothing,1: Increment the DMA Channel Device Address by DMA.." newline bitfld.long 0xC 16. "INC_MEM_ADDR,This will enable an auto-increment to the DMA Channel Memory Address. 1=Increment the DMA Channel Memory Address by DMA Channel Control:Transfer Size after every Data Packet transfer 0=Do nothing" "0: Do nothing,1: Increment the DMA Channel Memory Address by DMA.." hexmask.long.byte 0xC 9.--15. 1. "HW_FLOW_CTRL_DEV,This is the device that is connected to this channel as its Hardware Flow Control master. The Flow Control Interface is a bus with each master concatenated onto it. This selects which bus index of the.." newline bitfld.long 0xC 8. "TX_DIR,This determines the direction of the DMA Transfer. 1=Data Packet Read from Memory Start Address followed by Data Packet Write to Device Address 0=Data Packet Read from Device Address followed by Data Packet Write.." "0: Data Packet Read from Device Address followed by..,1: Data Packet Read from Memory Start Address.." bitfld.long 0xC 5. "BUSY,This is a status signal. 1=The DMA Channel is busy (FSM is not IDLE) 0=The DMA Channel is not busy (FSM is IDLE)" "0: The DMA Channel is not busy,1: The DMA Channel is busy" newline bitfld.long 0xC 3.--4. "STS,This is a status signal. The status decode is listed in priority order with the highest priority first. 3: Error detected by the DMA 2: The DMA Channel is externally done in that the Device has terminated the.." "0: DMA Channel Control:Run is Disabled,1: The DMA Channel is locally done,2: The DMA Channel is externally done,3: Error detected by the DMA" bitfld.long 0xC 2. "DONE,This is a status signal. It is only valid while DMA Channel Control: Run is Enabled. This is the inverse of the DMA Channel Control: Busy field except this is qualified with the DMA Channel Control:Run field." "0: Channel is not done or it is OFF,1: Channel is done" newline bitfld.long 0xC 1. "REQ,This is a status field. 1= There is a transfer request from the Master Device 0= There is no transfer request from the Master Device" "0: There is no transfer request from the Master..,1: There is a transfer request from the Master Device" bitfld.long 0xC 0. "RUN,This is a control field. Note: This bit only applies to Hardware Flow Control mode. 1= This channel is enabled and will service transfer requests 0=This channel is disabled. All transfer requests are ignored." "0: This channel is disabled,1: This channel is enabled and will service.." group.byte 0x14++0x0 line.byte 0x0 "ISTS,DMA Channel N Interrupt Status" bitfld.byte 0x0 2. "DONE,This is an interrupt source register. This flags when the DMA Channel has completed a transfer successfully on its side. A completed transfer is defined as when the DMA Channel reaches its limit; Memory Start Address equals Memory End Address." "0: Memory Start Address does not equal Memory End..,1: Memory Start Address equals Memory End Address" bitfld.byte 0x0 1. "FLOW_CTRL,This is an interrupt source register. This flags when the DMA Channel has encountered a Hardware Flow Control Request after the DMA Channel has completed the transfer. This means the Master Device is attempting to overflow the DMA." "0: No Hardware Flow Control event,1: Hardware Flow Control is requesting after the.." newline bitfld.byte 0x0 0. "BUS_ERR,This is an interrupt source register. This flags when there is an Error detected over the internal 32-bit Bus. 1: Error detected. (R/WC)" "?,1: Error detected" group.byte 0x18++0x0 line.byte 0x0 "IEN,DMA CHANNEL N INTERRUPT ENABLE" bitfld.byte 0x0 2. "STS_EN_DONE,This is an interrupt enable for DMA Channel Interrupt:Status Done. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" bitfld.byte 0x0 1. "STS_EN_FLOW_CTRL,This is an interrupt enable for DMA Channel Interrupt:Status Flow Control Error. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" newline bitfld.byte 0x0 0. "STS_EN_BUS_ERR,This is an interrupt enable for DMA Channel Interrupt:Status Bus Error. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" tree.end tree "DMA_CHAN13" base ad:0x40002780 group.byte 0x0++0x0 line.byte 0x0 "ACTIVATE,Enable this channel for operation. The DMA Main Control: Activate must also be enabled for this channel to be operational." bitfld.byte 0x0 0. "CHN,Enable this channel for operation. The DMA Main Control:Activate must also be enabled for this channel to be operational. 1=Enable channel(block). Each individual channel must be enabled separately. 0=Disable.." "0: Disable channel,1: Enable channel" group.long 0x4++0xF line.long 0x0 "MSTART,This is the starting address for the Memory device." line.long 0x4 "MEND,This is the ending address for the Memory device." line.long 0x8 "DSTART,This is the Master Device address." line.long 0xC "CTRL,DMA Channel N Control" bitfld.long 0xC 25. "TRANS_ABORT,This is used to abort the current transfer on this DMA Channel. The aborted transfer will be forced to terminate immediately." "0,1" bitfld.long 0xC 24. "TRANS_GO,This is used for the Firmware Flow Control DMA transfer." "0,1" newline bitfld.long 0xC 20.--22. "TRANS_SIZE,This is the transfer size in Bytes of each Data Packet transfer. Note: The transfer size must be a legal AMBA transfer size. Valid sizes are 1 2 and 4 Bytes." "0,1,2,3,4,5,6,7" bitfld.long 0xC 19. "DIS_HW_FLOW_CTRL,This will Disable the Hardware Flow Control. When disabled any DMA Master device attempting to communicate to the DMA over the DMA Flow Control Interface (Ports: dma_req dma_term and dma_done) will be ignored. This should be set.." "0,1" newline bitfld.long 0xC 18. "LOCK,This is used to lock the arbitration of the Channel Arbiter on this channel once this channel is granted. Once this is locked it will remain on the arbiter until it has completed it transfer (either the Transfer Aborted Transfer Done or Transfer.." "0,1" bitfld.long 0xC 17. "INC_DEV_ADDR,This will enable an auto-increment to the DMA Channel Device Address. 1: Increment the DMA Channel Device Address by DMA Channel Control:Transfer Size after every Data Packet transfer 0: Do nothing" "0: Do nothing,1: Increment the DMA Channel Device Address by DMA.." newline bitfld.long 0xC 16. "INC_MEM_ADDR,This will enable an auto-increment to the DMA Channel Memory Address. 1=Increment the DMA Channel Memory Address by DMA Channel Control:Transfer Size after every Data Packet transfer 0=Do nothing" "0: Do nothing,1: Increment the DMA Channel Memory Address by DMA.." hexmask.long.byte 0xC 9.--15. 1. "HW_FLOW_CTRL_DEV,This is the device that is connected to this channel as its Hardware Flow Control master. The Flow Control Interface is a bus with each master concatenated onto it. This selects which bus index of the.." newline bitfld.long 0xC 8. "TX_DIR,This determines the direction of the DMA Transfer. 1=Data Packet Read from Memory Start Address followed by Data Packet Write to Device Address 0=Data Packet Read from Device Address followed by Data Packet Write.." "0: Data Packet Read from Device Address followed by..,1: Data Packet Read from Memory Start Address.." bitfld.long 0xC 5. "BUSY,This is a status signal. 1=The DMA Channel is busy (FSM is not IDLE) 0=The DMA Channel is not busy (FSM is IDLE)" "0: The DMA Channel is not busy,1: The DMA Channel is busy" newline bitfld.long 0xC 3.--4. "STS,This is a status signal. The status decode is listed in priority order with the highest priority first. 3: Error detected by the DMA 2: The DMA Channel is externally done in that the Device has terminated the.." "0: DMA Channel Control:Run is Disabled,1: The DMA Channel is locally done,2: The DMA Channel is externally done,3: Error detected by the DMA" bitfld.long 0xC 2. "DONE,This is a status signal. It is only valid while DMA Channel Control: Run is Enabled. This is the inverse of the DMA Channel Control: Busy field except this is qualified with the DMA Channel Control:Run field." "0: Channel is not done or it is OFF,1: Channel is done" newline bitfld.long 0xC 1. "REQ,This is a status field. 1= There is a transfer request from the Master Device 0= There is no transfer request from the Master Device" "0: There is no transfer request from the Master..,1: There is a transfer request from the Master Device" bitfld.long 0xC 0. "RUN,This is a control field. Note: This bit only applies to Hardware Flow Control mode. 1= This channel is enabled and will service transfer requests 0=This channel is disabled. All transfer requests are ignored." "0: This channel is disabled,1: This channel is enabled and will service.." group.byte 0x14++0x0 line.byte 0x0 "ISTS,DMA Channel N Interrupt Status" bitfld.byte 0x0 2. "DONE,This is an interrupt source register. This flags when the DMA Channel has completed a transfer successfully on its side. A completed transfer is defined as when the DMA Channel reaches its limit; Memory Start Address equals Memory End Address." "0: Memory Start Address does not equal Memory End..,1: Memory Start Address equals Memory End Address" bitfld.byte 0x0 1. "FLOW_CTRL,This is an interrupt source register. This flags when the DMA Channel has encountered a Hardware Flow Control Request after the DMA Channel has completed the transfer. This means the Master Device is attempting to overflow the DMA." "0: No Hardware Flow Control event,1: Hardware Flow Control is requesting after the.." newline bitfld.byte 0x0 0. "BUS_ERR,This is an interrupt source register. This flags when there is an Error detected over the internal 32-bit Bus. 1: Error detected. (R/WC)" "?,1: Error detected" group.byte 0x18++0x0 line.byte 0x0 "IEN,DMA CHANNEL N INTERRUPT ENABLE" bitfld.byte 0x0 2. "STS_EN_DONE,This is an interrupt enable for DMA Channel Interrupt:Status Done. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" bitfld.byte 0x0 1. "STS_EN_FLOW_CTRL,This is an interrupt enable for DMA Channel Interrupt:Status Flow Control Error. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" newline bitfld.byte 0x0 0. "STS_EN_BUS_ERR,This is an interrupt enable for DMA Channel Interrupt:Status Bus Error. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" tree.end tree "DMA_CHAN14" base ad:0x400027C0 group.byte 0x0++0x0 line.byte 0x0 "ACTIVATE,Enable this channel for operation. The DMA Main Control: Activate must also be enabled for this channel to be operational." bitfld.byte 0x0 0. "CHN,Enable this channel for operation. The DMA Main Control:Activate must also be enabled for this channel to be operational. 1=Enable channel(block). Each individual channel must be enabled separately. 0=Disable.." "0: Disable channel,1: Enable channel" group.long 0x4++0xF line.long 0x0 "MSTART,This is the starting address for the Memory device." line.long 0x4 "MEND,This is the ending address for the Memory device." line.long 0x8 "DSTART,This is the Master Device address." line.long 0xC "CTRL,DMA Channel N Control" bitfld.long 0xC 25. "TRANS_ABORT,This is used to abort the current transfer on this DMA Channel. The aborted transfer will be forced to terminate immediately." "0,1" bitfld.long 0xC 24. "TRANS_GO,This is used for the Firmware Flow Control DMA transfer." "0,1" newline bitfld.long 0xC 20.--22. "TRANS_SIZE,This is the transfer size in Bytes of each Data Packet transfer. Note: The transfer size must be a legal AMBA transfer size. Valid sizes are 1 2 and 4 Bytes." "0,1,2,3,4,5,6,7" bitfld.long 0xC 19. "DIS_HW_FLOW_CTRL,This will Disable the Hardware Flow Control. When disabled any DMA Master device attempting to communicate to the DMA over the DMA Flow Control Interface (Ports: dma_req dma_term and dma_done) will be ignored. This should be set.." "0,1" newline bitfld.long 0xC 18. "LOCK,This is used to lock the arbitration of the Channel Arbiter on this channel once this channel is granted. Once this is locked it will remain on the arbiter until it has completed it transfer (either the Transfer Aborted Transfer Done or Transfer.." "0,1" bitfld.long 0xC 17. "INC_DEV_ADDR,This will enable an auto-increment to the DMA Channel Device Address. 1: Increment the DMA Channel Device Address by DMA Channel Control:Transfer Size after every Data Packet transfer 0: Do nothing" "0: Do nothing,1: Increment the DMA Channel Device Address by DMA.." newline bitfld.long 0xC 16. "INC_MEM_ADDR,This will enable an auto-increment to the DMA Channel Memory Address. 1=Increment the DMA Channel Memory Address by DMA Channel Control:Transfer Size after every Data Packet transfer 0=Do nothing" "0: Do nothing,1: Increment the DMA Channel Memory Address by DMA.." hexmask.long.byte 0xC 9.--15. 1. "HW_FLOW_CTRL_DEV,This is the device that is connected to this channel as its Hardware Flow Control master. The Flow Control Interface is a bus with each master concatenated onto it. This selects which bus index of the.." newline bitfld.long 0xC 8. "TX_DIR,This determines the direction of the DMA Transfer. 1=Data Packet Read from Memory Start Address followed by Data Packet Write to Device Address 0=Data Packet Read from Device Address followed by Data Packet Write.." "0: Data Packet Read from Device Address followed by..,1: Data Packet Read from Memory Start Address.." bitfld.long 0xC 5. "BUSY,This is a status signal. 1=The DMA Channel is busy (FSM is not IDLE) 0=The DMA Channel is not busy (FSM is IDLE)" "0: The DMA Channel is not busy,1: The DMA Channel is busy" newline bitfld.long 0xC 3.--4. "STS,This is a status signal. The status decode is listed in priority order with the highest priority first. 3: Error detected by the DMA 2: The DMA Channel is externally done in that the Device has terminated the.." "0: DMA Channel Control:Run is Disabled,1: The DMA Channel is locally done,2: The DMA Channel is externally done,3: Error detected by the DMA" bitfld.long 0xC 2. "DONE,This is a status signal. It is only valid while DMA Channel Control: Run is Enabled. This is the inverse of the DMA Channel Control: Busy field except this is qualified with the DMA Channel Control:Run field." "0: Channel is not done or it is OFF,1: Channel is done" newline bitfld.long 0xC 1. "REQ,This is a status field. 1= There is a transfer request from the Master Device 0= There is no transfer request from the Master Device" "0: There is no transfer request from the Master..,1: There is a transfer request from the Master Device" bitfld.long 0xC 0. "RUN,This is a control field. Note: This bit only applies to Hardware Flow Control mode. 1= This channel is enabled and will service transfer requests 0=This channel is disabled. All transfer requests are ignored." "0: This channel is disabled,1: This channel is enabled and will service.." group.byte 0x14++0x0 line.byte 0x0 "ISTS,DMA Channel N Interrupt Status" bitfld.byte 0x0 2. "DONE,This is an interrupt source register. This flags when the DMA Channel has completed a transfer successfully on its side. A completed transfer is defined as when the DMA Channel reaches its limit; Memory Start Address equals Memory End Address." "0: Memory Start Address does not equal Memory End..,1: Memory Start Address equals Memory End Address" bitfld.byte 0x0 1. "FLOW_CTRL,This is an interrupt source register. This flags when the DMA Channel has encountered a Hardware Flow Control Request after the DMA Channel has completed the transfer. This means the Master Device is attempting to overflow the DMA." "0: No Hardware Flow Control event,1: Hardware Flow Control is requesting after the.." newline bitfld.byte 0x0 0. "BUS_ERR,This is an interrupt source register. This flags when there is an Error detected over the internal 32-bit Bus. 1: Error detected. (R/WC)" "?,1: Error detected" group.byte 0x18++0x0 line.byte 0x0 "IEN,DMA CHANNEL N INTERRUPT ENABLE" bitfld.byte 0x0 2. "STS_EN_DONE,This is an interrupt enable for DMA Channel Interrupt:Status Done. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" bitfld.byte 0x0 1. "STS_EN_FLOW_CTRL,This is an interrupt enable for DMA Channel Interrupt:Status Flow Control Error. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" newline bitfld.byte 0x0 0. "STS_EN_BUS_ERR,This is an interrupt enable for DMA Channel Interrupt:Status Bus Error. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" tree.end tree "DMA_CHAN15" base ad:0x40002800 group.byte 0x0++0x0 line.byte 0x0 "ACTIVATE,Enable this channel for operation. The DMA Main Control: Activate must also be enabled for this channel to be operational." bitfld.byte 0x0 0. "CHN,Enable this channel for operation. The DMA Main Control:Activate must also be enabled for this channel to be operational. 1=Enable channel(block). Each individual channel must be enabled separately. 0=Disable.." "0: Disable channel,1: Enable channel" group.long 0x4++0xF line.long 0x0 "MSTART,This is the starting address for the Memory device." line.long 0x4 "MEND,This is the ending address for the Memory device." line.long 0x8 "DSTART,This is the Master Device address." line.long 0xC "CTRL,DMA Channel N Control" bitfld.long 0xC 25. "TRANS_ABORT,This is used to abort the current transfer on this DMA Channel. The aborted transfer will be forced to terminate immediately." "0,1" bitfld.long 0xC 24. "TRANS_GO,This is used for the Firmware Flow Control DMA transfer." "0,1" newline bitfld.long 0xC 20.--22. "TRANS_SIZE,This is the transfer size in Bytes of each Data Packet transfer. Note: The transfer size must be a legal AMBA transfer size. Valid sizes are 1 2 and 4 Bytes." "0,1,2,3,4,5,6,7" bitfld.long 0xC 19. "DIS_HW_FLOW_CTRL,This will Disable the Hardware Flow Control. When disabled any DMA Master device attempting to communicate to the DMA over the DMA Flow Control Interface (Ports: dma_req dma_term and dma_done) will be ignored. This should be set.." "0,1" newline bitfld.long 0xC 18. "LOCK,This is used to lock the arbitration of the Channel Arbiter on this channel once this channel is granted. Once this is locked it will remain on the arbiter until it has completed it transfer (either the Transfer Aborted Transfer Done or Transfer.." "0,1" bitfld.long 0xC 17. "INC_DEV_ADDR,This will enable an auto-increment to the DMA Channel Device Address. 1: Increment the DMA Channel Device Address by DMA Channel Control:Transfer Size after every Data Packet transfer 0: Do nothing" "0: Do nothing,1: Increment the DMA Channel Device Address by DMA.." newline bitfld.long 0xC 16. "INC_MEM_ADDR,This will enable an auto-increment to the DMA Channel Memory Address. 1=Increment the DMA Channel Memory Address by DMA Channel Control:Transfer Size after every Data Packet transfer 0=Do nothing" "0: Do nothing,1: Increment the DMA Channel Memory Address by DMA.." hexmask.long.byte 0xC 9.--15. 1. "HW_FLOW_CTRL_DEV,This is the device that is connected to this channel as its Hardware Flow Control master. The Flow Control Interface is a bus with each master concatenated onto it. This selects which bus index of the.." newline bitfld.long 0xC 8. "TX_DIR,This determines the direction of the DMA Transfer. 1=Data Packet Read from Memory Start Address followed by Data Packet Write to Device Address 0=Data Packet Read from Device Address followed by Data Packet Write.." "0: Data Packet Read from Device Address followed by..,1: Data Packet Read from Memory Start Address.." bitfld.long 0xC 5. "BUSY,This is a status signal. 1=The DMA Channel is busy (FSM is not IDLE) 0=The DMA Channel is not busy (FSM is IDLE)" "0: The DMA Channel is not busy,1: The DMA Channel is busy" newline bitfld.long 0xC 3.--4. "STS,This is a status signal. The status decode is listed in priority order with the highest priority first. 3: Error detected by the DMA 2: The DMA Channel is externally done in that the Device has terminated the.." "0: DMA Channel Control:Run is Disabled,1: The DMA Channel is locally done,2: The DMA Channel is externally done,3: Error detected by the DMA" bitfld.long 0xC 2. "DONE,This is a status signal. It is only valid while DMA Channel Control: Run is Enabled. This is the inverse of the DMA Channel Control: Busy field except this is qualified with the DMA Channel Control:Run field." "0: Channel is not done or it is OFF,1: Channel is done" newline bitfld.long 0xC 1. "REQ,This is a status field. 1= There is a transfer request from the Master Device 0= There is no transfer request from the Master Device" "0: There is no transfer request from the Master..,1: There is a transfer request from the Master Device" bitfld.long 0xC 0. "RUN,This is a control field. Note: This bit only applies to Hardware Flow Control mode. 1= This channel is enabled and will service transfer requests 0=This channel is disabled. All transfer requests are ignored." "0: This channel is disabled,1: This channel is enabled and will service.." group.byte 0x14++0x0 line.byte 0x0 "ISTS,DMA Channel N Interrupt Status" bitfld.byte 0x0 2. "DONE,This is an interrupt source register. This flags when the DMA Channel has completed a transfer successfully on its side. A completed transfer is defined as when the DMA Channel reaches its limit; Memory Start Address equals Memory End Address." "0: Memory Start Address does not equal Memory End..,1: Memory Start Address equals Memory End Address" bitfld.byte 0x0 1. "FLOW_CTRL,This is an interrupt source register. This flags when the DMA Channel has encountered a Hardware Flow Control Request after the DMA Channel has completed the transfer. This means the Master Device is attempting to overflow the DMA." "0: No Hardware Flow Control event,1: Hardware Flow Control is requesting after the.." newline bitfld.byte 0x0 0. "BUS_ERR,This is an interrupt source register. This flags when there is an Error detected over the internal 32-bit Bus. 1: Error detected. (R/WC)" "?,1: Error detected" group.byte 0x18++0x0 line.byte 0x0 "IEN,DMA CHANNEL N INTERRUPT ENABLE" bitfld.byte 0x0 2. "STS_EN_DONE,This is an interrupt enable for DMA Channel Interrupt:Status Done. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" bitfld.byte 0x0 1. "STS_EN_FLOW_CTRL,This is an interrupt enable for DMA Channel Interrupt:Status Flow Control Error. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" newline bitfld.byte 0x0 0. "STS_EN_BUS_ERR,This is an interrupt enable for DMA Channel Interrupt:Status Bus Error. 1=Enable Interrupt 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" tree.end tree.end tree "DMA_MAIN" base ad:0x40002400 group.byte 0x0++0x0 line.byte 0x0 "ACTRST,Soft reset the entire module. Enable the blocks operation." bitfld.byte 0x0 1. "SOFT_RST,Soft reset the entire module. This bit is self-clearing." "0,1" bitfld.byte 0x0 0. "ACT,Enable the blocks operation. (R/WS) 1=Enable block. Each individual channel must be enabled separately. 0=Disable all channels." "0: Disable all channels,1: Enable block" rgroup.long 0x4++0x3 line.long 0x0 "DATA_PKT,Debug register that has the data that is stored in the Data Packet. This data is read data from the currently active transfer source." tree.end tree "EC_REG_BANK" base ad:0x4000FC00 group.byte 0x0++0x0 line.byte 0x0 "SRAM_CNFG,SRAM Configuration Register" bitfld.byte 0x0 0.--1. "SRAM_SIZE,SRAM Configuration Register: 0: 384KB (352k Code 32k Data) 1: 320kB (288k Code 32k Data) 2: 256kB (224k Code 32k Data) 3: Illegal 256kB (224k Code 32k Data)" "0: 384KB,1: 320kB,2: 256kB,3: Illegal 256kB" group.long 0x4++0x3 line.long 0x0 "AHB_ERR_ADDR,AHB Error Address [0:0]" group.byte 0x14++0x0 line.byte 0x0 "AHB_ERR_CTRL,AHB Error Control [0:0] AHB_ERROR_DISABLE. 0: EC memory exceptions are enabled. 1: EC memory exceptions are disabled." group.long 0x18++0x17 line.long 0x0 "INTR_CTRL,Interrupt Control [0:0] NVIC_EN (NVIC_EN) This bit enables Alternate NVIC IRQ's Vectors. The Alternate NVIC Vectors provides each interrupt event with a dedicated (direct) NVIC vector. 0 = Alternate NVIC vectors disabled. 1=.." line.long 0x4 "ETM_CTRL,ETM TRACE Enable [0:0] TRACE_EN (TRACE_EN) This bit enables the ARM TRACE debug port (ETM/ITM). The Trace Debug Interface pins are forced to the TRACE functions. 0 = ARM TRACE port disabled. 1= ARM TRACE port enabled" line.long 0x8 "DEBUG_CTRL,Debug Enable Register" bitfld.long 0x8 4. "BSP_EN,This bit sets the boundary scan tap controller accessibility from JTAG port. 1= Boundary scan tap controller accessibile through JTAG Port. 0= Boundary scan tap controller not accessibile through JTAG Port." "0: Boundary scan tap controller not accessibile..,1: Boundary scan tap controller accessibile through.." newline bitfld.long 0x8 3. "PU_EN,If this bit is set to '1b' internal pull-up resistors are automatically enabled on the appropriate debugging port wires whenever the debug port is enabled (the DEBUG_EN bit in this register is '1b' and the JTAG_RST# pin is high). The setting.." "0,1" newline bitfld.long 0x8 1.--2. "PIN_CFG,This field determines which pins are affected by the TRST# debug enable pin. 3=Reserved 2=The pins associated with the JTAG TCK and TMS switch to the debug interface when TRST# is de-asserted high. The pins associated with TDI and.." "0: All four pins associated with JTAG,1: The pins associated with the JTAG TCK,2: The pins associated with the JTAG TCK and TMS..,3: Reserved" newline bitfld.long 0x8 0. "EN,DEBUG_EN (JTAG_EN) This bit enables the JTAG/SWD debug port. 0= JTAG/SWD port disabled. JTAG/SWD cannot be enabled (i.e. the TRST# pin is ignored and the JTAG signals remain in their non-JTAG state) 1= JTAG/SWD port.." "0: JTAG/SWD port disabled,1: JTAG/SWD port enabled" line.long 0xC "OTP_LOCK,Lock Register" bitfld.long 0xC 2. "VBAT_REG_LOCK,VBAT REG LOCK. 0 = Not Locked. 1 = Locked." "0: Not Locked,1: Locked" newline bitfld.long 0xC 1. "VBAT_RAM_LOCK,VBAT RAM LOCK bit. 0 = Not Locked. 1 = Locked." "0: Not Locked,1: Locked" newline bitfld.long 0xC 0. "TEST,Test" "0,1" line.long 0x10 "WDT_CNT,WDT Event Count [3:0] WDT_COUNT (WDT_COUNT) These EC R/W bits are cleared to 0 on VCC1 POR. but not on a WDT. Note: This field is written by Boot ROM firmware to indicate the number of times a WDT fired before loading a good EC code.." line.long 0x14 "AESH_BSWAP_CTRL,AES HASH Byte Swap Control Register." bitfld.long 0x14 5.--7. "OP_BLK_SWAP_EN,Used to enable word swap on a DWORD during AHB write from AES / HASH block 0=Disable." "0: Disable,1: 1=Swap doublewords in 8-byte blocks. Useful for..,2: 2=Swap doublewords in 16-byte blocks. Useful for..,3: 3=Swap doublewords in 64-byte blocks. Useful for..,4: 4=Swap 32-bit doublewords in 128-byte blocks,?,?,?" newline bitfld.long 0x14 2.--4. "IP_BLK_SWAP_EN,Used to enable word swap on a DWORD during AHB read from AES / HASH block 0=Disable." "0: Disable,1: 1=Swap doublewords in 8-byte blocks. Useful for..,2: 2=Swap doublewords in 16-byte blocks. Useful for..,3: 3=Swap doublewords in 64-byte blocks. Useful for..,4: 4=Swap 32-bit doublewords in 128-byte blocks,?,?,?" newline bitfld.long 0x14 1. "OP_BYTE_SWAP_EN,Used to enable byte swap on a DWORD during AHB write from AES / HASH block: 1=Enable; 0=Disable." "0: Disable,1: Enable" newline bitfld.long 0x14 0. "IP_BYTE_SWAP_EN,Used to enable byte swap on a DWORD during AHB read from AES / HASH block: 1=Enable; 0=Disable." "0: Disable,1: Enable" group.long 0x40++0x3 line.long 0x0 "PECI_DIS,PECI Disable" bitfld.long 0x0 0. "P_DIS,When this bit is asserted ('1') it disables the PECI pads to reduce leakage." "0,1" group.long 0x64++0x3 line.long 0x0 "GPIO_BANK_PWR,GPIO Bank Power Register" bitfld.long 0x0 7. "GPIO_BANK_PWR_LOCK,GPIO Bank Power Lock. 0: VTR_LEVEL bits[2:0] and GPIO Bank Power Lock bit are R/W 1 = VTR_LEVEL bits[2:0] and GPIO Bank Power Lock bit are Read Only." "0: VTR_LEVEL bits[2:0] and GPIO Bank Power Lock bit..,1: VTR_LEVEL bits[2:0] and GPIO Bank Power Lock bit.." newline bitfld.long 0x0 1. "VTR_LVL2,Voltage value on VTR2. This bit is set by Firmware after a VTR Power On Reset. It must be set by software if the VTR power rail is not active when RESET_SYS is de-asserted. Write access is determined by bit 7. 1=VTR2 is.." "0: VTR2 is powered by 3,1: VTR2 is powered by 1" newline bitfld.long 0x0 0. "TEST,This bit must be programmed to 0h for proper operation of the device." "0,1" group.long 0x70++0x3 line.long 0x0 "JTAG_MCFG,JTAG Master Configuration Register" bitfld.long 0x0 3. "MAS_SLV,This bit controls the direction of the JTAG port. 1=The JTAG Port is configured as a Master 0=The JTAG Port is configures as a Slave." "0: The JTAG Port is configures as a Slave,1: The JTAG Port is configured as a Master" newline bitfld.long 0x0 0.--2. "JTM_CLK,This field determines the JTAG Master clock rate derived from the 48MHz master clock. 7=375KHz; 6=750KHz; 5=1.5Mhz; 4=3Mhz; 3=6Mhz; 2=12Mhz; 1=24MHz; 0=Reserved." "0: Reserved,1: 24MHz,2: 12Mhz,3: 6Mhz,4: 3Mhz,5: 1,6: 750KHz,7: 375KHz" rgroup.long 0x74++0x3 line.long 0x0 "JTAG_MSTS,JTAG Master Status Register" bitfld.long 0x0 0. "JTM_DONE,This bit is set to '1b' when the JTAG Master Command Register is written. It becomes '0b' when shifting has completed. Software can poll this bit to determine when a command has completed and it is therefore safe to remove the data in the.." "0,1" group.long 0x78++0xF line.long 0x0 "JTAG_MTDO,JTAG Master TDO Register" hexmask.long 0x0 0.--31. 1. "JTM_TDO,When the JTAG Master Command Register is written from 1 to 32 bits are shifted into this register starting with bit 0 from the JTAG_TDO pin. Shifting is at the rate determined by the JTM_CLK field in the JTAG Master Configuration Register." line.long 0x4 "JTAG_MTDI,JTAG Master TDI Register" hexmask.long 0x4 0.--31. 1. "JTM_TDI,When the JTAG Master Command Register is written from 1 to 32 bits are shifted out of this register starting with bit 0 onto the JTAG_TDI pin. Shifting is at the rate determined by the JTM_CLK field in the JTAG Master Configuration.." line.long 0x8 "JTAG_MTMS,JTAG Master TMS Register" hexmask.long 0x8 0.--31. 1. "JTM_TMS,When the JTAG Master Command Register is written from 1 to 32 bits are shifted out of this register starting with bit 0 onto the JTAG_TMS pin. Shifting is at the rate determined by the JTM_CLK field in the JTAG Master Configuration.." line.long 0xC "JTAG_MCMD,JTAG Master Command Register" hexmask.long.byte 0xC 0.--4. 1. "JTM_COUNT,If the JTAG Port is configured as a Master writing this register starts clocking and shifting on the JTAG port. The JTAG Master port will shift JTM_COUNT+1 times so writing a '0h' will shift 1 bit and writing '31h' will shift 32 bits." group.long 0x90++0x3 line.long 0x0 "VW_SRC_CNGF,Virtual Wire Source Configuration Register" bitfld.long 0x0 0.--2. "VW_SRC,VWIRE_SOURCE [2] VWIRE_SOURCE [1] VWIRE_SOURCE [0]" "0,1,2,3,4,5,6,7" group.byte 0x94++0x0 line.byte 0x0 "ACOMP_CTRL,Comparator Enable" bitfld.byte 0x0 4. "CMP1EN,Comparator 1 Enable 0: Disable Comparator for operation 1: Enable Comparator operation." "0: Disable Comparator for operation,1: Enable Comparator operation" newline bitfld.byte 0x0 2. "CONF0LCK,Comparator 0 Configuration Locked 0: Configuration Not Locked. Bits[2 0] are Read-Write 1: Configuration Locked. Bits[2 0] are Read-Only Note: If the CMP_STRAP0 Pin = 1 the Boot ROM writes this bit. Once it is written.." "0: Configuration Not Locked,1: Configuration Locked" newline bitfld.byte 0x0 0. "CMP0EN,Comparator 0 Enable 0: Disable Comparator for operation 1: Enable Comparator operation." "0: Disable Comparator for operation,1: Enable Comparator operation" group.byte 0x98++0x0 line.byte 0x0 "ACOMP_SLP_CTRL,Analog Comparator Sleep Control Register" bitfld.byte 0x0 1. "CMP1SLP_EN,Comparator 1 Deep Sleep Enable. 0 = Comparator Deep Sleep Disable. 1 = Comparator Deep Sleep Enable." "0: Comparator Deep Sleep Disable,1: Comparator Deep Sleep Enable" newline bitfld.byte 0x0 0. "CMP0SLP_EN,Comparator 0 Deep Sleep Enable. 0 = Comparator Deep Sleep Disable. 1 = Comparator Deep Sleep Enable. Note: If the CMP_STRAP0 Pin = 1 the Boot ROM writes this bit. Once it is written this bit becomes a read-only.." "0: Comparator Deep Sleep Disable,1: Comparator Deep Sleep Enable" group.long 0xB0++0xF line.long 0x0 "EMDRST_EN,Embedded Reset Enable Register" bitfld.long 0x0 0. "EN,Embedded Reset Enable Register. 0 = Disable 1 = Enable." "0: Disable,1: Enable" line.long 0x4 "EMDRST_TOUT,Embedded Reset Timeout Register" bitfld.long 0x4 0.--2. "TOUT,Embedded Reset Timeout Register." "0,1,2,3,4,5,6,7" line.long 0x8 "EMDRST_STS,Embedded Reset Status Register" bitfld.long 0x8 0. "STS,Embedded Reset Status Register." "0,1" line.long 0xC "EMDRST_CNT,Embedded Reset Count Register" hexmask.long.tbyte 0xC 0.--18. 1. "CNT,Embedded Reset CNT Register." group.long 0x180++0xF line.long 0x0 "FW_SCR0,BOOT ROM Scratch 0 Register" hexmask.long 0x0 0.--31. 1. "SCR0,This field has no functionality other than storage. This register is aliased to ESPI Config Scratch Register." line.long 0x4 "FW_SCR1,BOOT ROM Scratch 1 Register" hexmask.long 0x4 2.--31. 1. "SCR1,This field has no functionality other than storage. This register is aliased to ESPI Config Scratch Register." newline bitfld.long 0x4 0.--1. "UDS_CRC_STS,UDS CRC status. 0 = UDS CRC checking disabled. Hardware POR state 1 = UDS CRC check passed 2 = UDS CRC check failed 3 = invalid. Can only get this result if UDS CRC feature not enabled and bits are set by application code." "0: UDS CRC checking disabled,1: UDS CRC check passed,2: UDS CRC check failed,3: invalid" line.long 0x8 "FW_SCR2,BOOT ROM Scratch 2 Register" hexmask.long 0x8 0.--31. 1. "SCR2,This field has no functionality other than storage. This register is aliased to ESPI Config Scratch Register." line.long 0xC "FW_SCR3,BOOT ROM Scratch 3 Register" hexmask.long 0xC 0.--31. 1. "SCR3,This field has no functionality other than storage. This register is aliased to ESPI Config Scratch Register." tree.end tree "ECIA (EC Interrupt Aggregator)" base ad:0x4000E000 group.long 0x0++0x7 line.long 0x0 "SRC8,GIRQ8 SOURCE" line.long 0x4 "EN_SET8,GIRQ8 ENABLE SET" rgroup.long 0x8++0x3 line.long 0x0 "RESULT8,GIRQ8 RESULT" group.long 0xC++0x3 line.long 0x0 "EN_CLR8,GIRQ8 ENABLE CLEAR" group.long 0x14++0x7 line.long 0x0 "SRC9,GIRQ9 SOURCE" line.long 0x4 "EN_SET9,GIRQ9 ENABLE SET" rgroup.long 0x1C++0x3 line.long 0x0 "RESULT9,GIRQ9 RESULT" group.long 0x20++0x3 line.long 0x0 "EN_CLR9,GIRQ9 ENABLE CLEAR" group.long 0x28++0x7 line.long 0x0 "SRC10,GIRQ10 SOURCE" line.long 0x4 "EN_SET10,GIRQ10 ENABLE SET" rgroup.long 0x30++0x3 line.long 0x0 "RESULT10,GIRQ10 RESULT" group.long 0x34++0x3 line.long 0x0 "EN_CLR10,GIRQ10 ENABLE CLEAR" group.long 0x3C++0x7 line.long 0x0 "SRC11,GIRQ11 SOURCE" line.long 0x4 "EN_SET11,GIRQ11 ENABLE SET" rgroup.long 0x44++0x3 line.long 0x0 "RESULT11,GIRQ11 RESULT" group.long 0x48++0x3 line.long 0x0 "EN_CLR11,GIRQ11 ENABLE CLEAR" group.long 0x50++0x7 line.long 0x0 "SRC12,GIRQ12 SOURCE" line.long 0x4 "EN_SET12,GIRQ12 ENABLE SET" rgroup.long 0x58++0x3 line.long 0x0 "RESULT12,GIRQ12 RESULT" group.long 0x5C++0x3 line.long 0x0 "EN_CLR12,GIRQ12 ENABLE CLEAR" group.long 0x64++0x7 line.long 0x0 "SRC13,GIRQ13 SOURCE" line.long 0x4 "EN_SET13,GIRQ13 ENABLE SET" rgroup.long 0x6C++0x3 line.long 0x0 "RESULT13,GIRQ13 RESULT" group.long 0x70++0x3 line.long 0x0 "EN_CLR13,GIRQ13 ENABLE CLEAR" group.long 0x78++0x7 line.long 0x0 "SRC14,GIRQ14 SOURCE" line.long 0x4 "EN_SET14,GIRQ14 ENABLE SET" rgroup.long 0x80++0x3 line.long 0x0 "RESULT14,GIRQ14 RESULT" group.long 0x84++0x3 line.long 0x0 "EN_CLR14,GIRQ14 ENABLE CLEAR" group.long 0x8C++0x7 line.long 0x0 "SRC15,GIRQ15 SOURCE" line.long 0x4 "EN_SET15,GIRQ15 ENABLE SET" rgroup.long 0x94++0x3 line.long 0x0 "RESULT15,GIRQ15 RESULT" group.long 0x98++0x3 line.long 0x0 "EN_CLR15,GIRQ15 ENABLE CLEAR" group.long 0xA0++0x7 line.long 0x0 "SRC16,GIRQ16 SOURCE" line.long 0x4 "EN_SET16,GIRQ16 ENABLE SET" rgroup.long 0xA8++0x3 line.long 0x0 "RESULT16,GIRQ16 RESULT" group.long 0xAC++0x3 line.long 0x0 "EN_CLR16,GIRQ16 ENABLE CLEAR" group.long 0xB4++0x7 line.long 0x0 "SRC17,GIRQ17 SOURCE" line.long 0x4 "EN_SET17,GIRQ17 ENABLE SET" rgroup.long 0xBC++0x3 line.long 0x0 "RESULT17,GIRQ17 RESULT" group.long 0xC0++0x3 line.long 0x0 "EN_CLR17,GIRQ17 ENABLE CLEAR" group.long 0xC8++0x7 line.long 0x0 "SRC18,GIRQ18 SOURCE" line.long 0x4 "EN_SET18,GIRQ18 ENABLE SET" rgroup.long 0xD0++0x3 line.long 0x0 "RESULT18,GIRQ18 RESULT" group.long 0xD4++0x3 line.long 0x0 "EN_CLR18,GIRQ18 ENABLE CLEAR" group.long 0xDC++0x7 line.long 0x0 "SRC19,GIRQ19 SOURCE" line.long 0x4 "EN_SET19,GIRQ19 ENABLE SET" rgroup.long 0xE4++0x3 line.long 0x0 "RESULT19,GIRQ19 RESULT" group.long 0xE8++0x3 line.long 0x0 "EN_CLR19,GIRQ19 ENABLE CLEAR" group.long 0xF0++0x7 line.long 0x0 "SRC20,GIRQ20 SOURCE" line.long 0x4 "EN_SET20,GIRQ20 ENABLE SET" rgroup.long 0xF8++0x3 line.long 0x0 "RESULT20,GIRQ20 RESULT" group.long 0xFC++0x3 line.long 0x0 "EN_CLR20,GIRQ20 ENABLE CLEAR" group.long 0x104++0x7 line.long 0x0 "SRC21,GIRQ21 SOURCE" line.long 0x4 "EN_SET21,GIRQ21 ENABLE SET" rgroup.long 0x10C++0x3 line.long 0x0 "RESULT21,GIRQ21 RESULT" group.long 0x110++0x3 line.long 0x0 "EN_CLR21,GIRQ21 ENABLE CLEAR" group.long 0x118++0x7 line.long 0x0 "SRC22,GIRQ22 SOURCE" line.long 0x4 "EN_SET22,GIRQ22 ENABLE SET" rgroup.long 0x120++0x3 line.long 0x0 "RESULT22,GIRQ22 RESULT" group.long 0x124++0x3 line.long 0x0 "EN_CLR22,GIRQ22 ENABLE CLEAR" group.long 0x12C++0x7 line.long 0x0 "SRC23,GIRQ23 SOURCE" line.long 0x4 "EN_SET23,GIRQ23 ENABLE SET" rgroup.long 0x134++0x3 line.long 0x0 "RESULT23,GIRQ23 RESULT" group.long 0x138++0x3 line.long 0x0 "EN_CLR23,GIRQ23 ENABLE CLEAR" group.long 0x140++0x7 line.long 0x0 "SRC24,GIRQ24 SOURCE" line.long 0x4 "EN_SET24,GIRQ24 ENABLE SET" rgroup.long 0x148++0x3 line.long 0x0 "RESULT24,GIRQ24 RESULT" group.long 0x14C++0x3 line.long 0x0 "EN_CLR24,GIRQ24 ENABLE CLEAR" group.long 0x154++0x7 line.long 0x0 "SRC25,GIRQ25 SOURCE" line.long 0x4 "EN_SET25,GIRQ25 ENABLE SET" rgroup.long 0x15C++0x3 line.long 0x0 "RESULT25,GIRQ25 RESULT" group.long 0x160++0x3 line.long 0x0 "EN_CLR25,GIRQ25 ENABLE CLEAR" group.long 0x168++0x7 line.long 0x0 "SRC26,GIRQ26 SOURCE" line.long 0x4 "EN_SET26,GIRQ26 ENABLE SET" rgroup.long 0x170++0x3 line.long 0x0 "RESULT26,GIRQ26 RESULT" group.long 0x174++0x3 line.long 0x0 "EN_CLR26,GIRQ26 ENABLE CLEAR" group.long 0x200++0x7 line.long 0x0 "BLK_EN_SET,Block Enable Set Register" hexmask.long 0x0 0.--30. 1. "VTOR_EN_SET,Each GIRQx bit can be individually enabled to assert an interrupt event. Reads always return the current value of the internal GIRQX_ENABLE bit. The state of the GIRQX_ENABLE bit is determined by the corresponding GIRQX_ENABLE_SET.." line.long 0x4 "BLK_EN_CLR,Block Enable Clear Register." hexmask.long 0x4 0.--30. 1. "VTOR_EN_CLR,Each GIRQx bit can be individually disabled to inhibit an interrupt event. Reads always return the current value of the internal GIRQX_ENABLE bit. The state of the GIRQX_ENABLE bit is determined by the corresponding GIRQX_ENABLE_SET.." rgroup.long 0x208++0x3 line.long 0x0 "BLK_IRQ_VTOR,Block IRQ Vector Register" hexmask.long 0x0 0.--24. 1. "VTOR,Each bit in this field reports the status of the group GIRQ interrupt assertion to the NVIC. If the GIRQx interrupt is disabled as a group by the Block Enable Clear Register then the corresponding bit will be '0'b and no interrupt will be.." tree.end sif (cpuis("MEC1723N*")||cpuis("MEC1724N*")) tree "EEPROM" base ad:0x40002C00 group.long 0x0++0x1B line.long 0x0 "MODE,EEPROM Mode Register" bitfld.long 0x0 1. "SOFT_RST,This write-only bit is used to reset the EEPROM" "0,1" bitfld.long 0x0 0. "ACT,This bit is used to enable and disable the EEPROM controller." "0,1" line.long 0x4 "EXE,EEPROM Execute Register" hexmask.long.byte 0x4 24.--28. 1. "TRANS_SIZE,The number of bytes to be transferred between the EEPROM fabric and the buffer. A count of 0 is means a transfer of 32 bytes. This field is only applicable for WRITE and READ commands." bitfld.long 0x4 16.--18. "CMD,A write to this register automatically starts an EEPROM transfer between the fabric and the buffer. 3=WRITE STATUS; 2=READ STATUS; 1=WRITE; 0=READ." "0: READ,1: WRITE,2: READ STATUS,3: WRITE STATUS,?,?,?,?" newline hexmask.long.word 0x4 0.--15. 1. "ADDR,This register represents a byte address in the EEPROM. Bits[15:11] should be 0 but there is error flagged if they are not. This field only applies to READ and WRITE commands. It does not apply to READ STATUS and WRITE STATUS commands." line.long 0x8 "STS,EEPROM Status Register" bitfld.long 0x8 8. "TRANS_ACT,A transfer between the EEPROM fabric and the EEPROM Buffer Register is in progress." "0,1" bitfld.long 0x8 1. "EXE_ERR,This bit is set to '1b' if an illegal command has been programmed into the block. (R/WC) A command is illegal if: The EEPROM Execute Register is written while a previous command has not yet completed (that is while TRANSFER_ACTIVE is.." "0,1" newline bitfld.long 0x8 0. "TRANS_COMPL,This bit indicated whether the transfer between the EEPROM fabric and the EEPROM Buffer Register has completed. (R/WC) 1=The transfer between the EEPROM fabric and the EEPROM Buffer Register has completed 0=The transfer between the.." "0: The transfer between the EEPROM fabric and the..,1: The transfer between the EEPROM fabric and the.." line.long 0xC "IEN,EEPROM Interrupt Enable Register" bitfld.long 0xC 1. "EXE_ERR,Assert an EEPROM interrupt when the EXECUTION_ERROR status is asserted. 1=Enable Interrupt; 0=Disable Interrupt." "0: Disable Interrupt,1: Enable Interrupt" bitfld.long 0xC 0. "TRANS_COMPL,Assert an EEPROM interrupt when the TRANSFER_COMPLETE status is asserted. 1=Enable Interrupt; 0=Disable Interrupt." "0: Disable Interrupt,1: Enable Interrupt" line.long 0x10 "PSWD,EEPROM Password Register" hexmask.long 0x10 0.--30. 1. "PSWD,If this 31-bit value matches the key in the EEPROM Unlock Register then the EEPROM array can be read or written. This register is write-once only. Once written it can be neither read nor written until the next system reset." line.long 0x14 "UNLOCK,EEPROM Unlock Register" hexmask.long 0x14 0.--30. 1. "UNLOCK,When this 31-bit register is written the least significant 31 bits of the write are compared to the EEPROM Password Register that stores the key. If all bits match the LOCK bit in the EEPROM Status Register cleared and the EEPROM array.." line.long 0x18 "LOCK,EEPROM Lock Register" bitfld.long 0x18 1. "LOCK,EEPROM Access Lock. When this bit is set to '1b' the EEPROM is locked from all accesses including reads writes and status queries. Once set to '1b' it can only be cleared to '0b' by a RESET_SYS or by writing the EEPROM Unlock Register.." "0: EEPROM is unlocked and may be accessed,1: EEPROM is locked and cannot be accessed" bitfld.long 0x18 0. "JTAG_LOCK,If this bit is set to '1b' the LOCK bit is set to '1b' whenever the JTAG/SWD test interface is activated. This has priority over the EEPROM Unlock Register register so that writing the EEPROM Unlock Register register with a value that.." "0: The JTAG/SWD test interface has no effect on the..,1: The LOCK bit is set to '1b' whenever the.." rgroup.long 0x1C++0x3 line.long 0x0 "RSVD,Reserved" repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x20)++0x3 line.long 0x0 "EEBUF[$1],One byte of EEPROM Buffer Register. The Data buffer of 32 bytes is used to transfer data to and from the EEPROM fabric. For WRITES. it must be written before the WRITE command is started. For READ STATUS and WRITE STATUS commands. only the.." repeat.end tree.end endif tree "EMI (Embedded Memory Interface)" base ad:0x0 tree "EMI0" base ad:0x400F4000 group.byte 0x0++0x3 line.byte 0x0 "RT_HOST2EC,Host-to-EC Mailbox Register" line.byte 0x1 "RT_EC2HOST,EC-to-Host Mailbox Register" line.byte 0x2 "RT_EC_ADDR_LSB,EC Address Access Control Register" hexmask.byte 0x2 2.--7. 1. "ADDR,This field defines bits[7:2] of EC_Address [15:0]. Bits[1:0] of the EC_Address are always forced to 00b. The EC_Address is aligned on a DWord boundary. It is the address of the memory being accessed by EC Data Byte 0 Register which is an.." bitfld.byte 0x2 0.--1. "ACCESS_TYPE,This field defines the type of access that occurs when the EC Data Register is read or written. 11b=Auto-increment 32-bit access. 10b=32-bit access. 01b=16-bit access. 00b=8-bit access." "0,1,2,3" line.byte 0x3 "RT_EC_ADDR_MSB,EC Address Access Control Register" bitfld.byte 0x3 7. "REGION,The field specifies which of two segments in the 32-bit internal address space is to be accessed by the EC_Address[14:2] to generate accesses to the memory. 1=The address defined by EC_Address[14:2] is relative to the base address.." "0: The address defined by EC_Address[14:2] is..,1: The address defined by EC_Address[14:2] is.." hexmask.byte 0x3 2.--6. 1. "ADDR,This field defines bits[14:8] of EC_Address. Bits[1:0] of the EC_Address are always forced to 00b. The EC_Address is aligned on a DWord boundary. It is the address of the memory being accessed by EC Data Byte 0 Register which is an offset.." group.long 0x4++0x3 line.long 0x0 "RT_DATA,EC Data Byte Register" group.byte 0x8++0x4 line.byte 0x0 "RT_INTR_SRC_LSB,Interrupt Source LSB Register" hexmask.byte 0x0 1.--7. 1. "EC_SWI_LSB,EC Software Interrupt Least Significant Bits. These bits are software interrupt bits that may be set by the EC to notify the host of an event. The meaning of these bits is dependent on the firmware implementation. Each bit in this field.." bitfld.byte 0x0 0. "EC_WR,EC Mailbox Write. This bit is set when the EC-to-HOST Mailbox Register has been written by the EC at offset 01h of the EC-Only registers. Note: there is no corresponding mask bit in the Interrupt Mask LSB Register." "0,1" line.byte 0x1 "RT_INTR_SRC_MSB,Interrupt Source MSB Register" hexmask.byte 0x1 0.--7. 1. "EC_SWI_MSB,EC Software Interrupt Most Significant Bits. These bits are software interrupt bits that may be set by the EC to notify the host of an event. The meaning of these bits is dependent on the firmware implementation. Each bit in this field is.." line.byte 0x2 "RT_INTR_MASK_LSB,Interrupt Mask LSB Register" hexmask.byte 0x2 1.--7. 1. "EC_SWI_EN_LSB,EC Software Interrupt Enable Least Significant Bits. Each bit that is set to '1b' in this field enables the generation of a Host Event interrupt by the corresponding bit in the EC_SWI field in the Interrupt Source LSB Register." bitfld.byte 0x2 0. "TEST,Test Bit." "0,1" line.byte 0x3 "RT_INTR_MASK_MSB,Interrupt Mask MSB Register" hexmask.byte 0x3 1.--7. 1. "EC_SWI_EN_MSB,EC Software Interrupt Enable Most Significant Bits. Each bit that is set to '1b' in this field enables the generation of a Host Event interrupt by the corresponding bit in the EC_SWI field in the Interrupt Source MSB Register." line.byte 0x4 "RT_APP_ID,Application ID Register. APPLICATION_ID When this field is 00h it can be written with any value. When set to a non-zero value. writing that value will clear this register to 00h. When set to a non-zero value. writing any value other than the.." group.byte 0x10++0x0 line.byte 0x0 "APP_ID_ASGN,Application ID Assignment Register." group.byte 0x100++0x1 line.byte 0x0 "HOST2EC,Host-to-EC Mailbox Register. 8-bit mailbox used communicate information from the system host to the embedded controller. Writing this register generates an event to notify the embedded controller. (R/WC)" line.byte 0x1 "EC2HOST,EC-to-Host Mailbox Register. 8-bit mailbox used communicate information from the embedded controller to the system host. Writing this register generates an event to notify the system host." group.long 0x104++0x3 line.long 0x0 "MEM0_BASE,Memory Base Address 0 Register [31:2] This memory base address defines the beginning of region 0 in the Embedded Controller's 32-bit internal address space. Memory allocated to region 0 is intended to be shared between the Host and the EC. The.." group.word 0x108++0x3 line.word 0x0 "MEM0_RD_LIMITS,Memory Read Limit 0 Register [14:2] Whenever a read of any byte in the EC Data Register is attempted. and bit 15 of EC_Address is 0. the field EC_Address[14:2] in the EC_Address_Register is compared to this field. As long as.." line.word 0x2 "MEM0_WR_LIMITS,Memory Write Limit 0 Register [14:2] Whenever a write of any byte in EC DATA Register is attempted and bit 15 of EC_Address is 0. the field EC_ADDRESS_MSB in the EC_Address Register is compared to this field. As long as EC_Address[14:2] is.." group.long 0x10C++0x3 line.long 0x0 "MEM1_BASE,Memory Base Address 1 Register. [31:2] This memory base address defines the beginning of region 1 in the Embedded Controller's 32-bit internal address space. Memory allocated to region 1 is intended to be shared between the Host and the EC. The.." group.word 0x110++0x7 line.word 0x0 "MEM1_RD_LIMITS,Memory Read Limit 1 Register. [14:2]: Whenever a read of any byte in the EC Data Register is attempted. and bit 15 of EC_ADDRESS is 1. the field EC_ADDRESS in the EC_Address_Register is compared to this field. As long as EC_ADDRESS is less.." line.word 0x2 "MEM1_WR_LIMITS,Memory Write Limit 1 Register. [14:2]: Whenever a write of any byte in EC DATA Register is attempted and bit 15 of EC_Address is 1. the field EC_Address[14:2] in the EC_Address Register is compared to this field. As long as.." line.word 0x4 "INTR_SET,[15:1] Interrupt Set Register. Writing a bit in this field with a '1b' sets the corresponding bit in the Interrupt Source Register to '1b'. Writing a bit in this field with a '0b' has no effect. Reading this field returns the current contents of.." line.word 0x6 "HOST_CLR_EN,[15:1] Host Clear Enable Register. When a bit in this field is '0b'. the corresponding bit in the Interrupt Source Register cannot be cleared by writes to the Interrupt Source Register. When a bit in this field is '1b'. the corresponding bit.." group.long 0x120++0x1F line.long 0x0 "APP_ID_STS0,Application ID Status register [31:0]" line.long 0x4 "APP_ID_STS1,Application ID Status register [63:32]" line.long 0x8 "APP_ID_STS2,Application ID Status register [95:64]" line.long 0xC "APP_ID_STS3,Application ID Status register [127:96]" line.long 0x10 "APP_ID_STS4,Application ID Status register [159:128]" line.long 0x14 "APP_ID_STS5,Application ID Status register [191:160]" line.long 0x18 "APP_ID_STS6,Application ID Status register [223:192]" line.long 0x1C "APP_ID_STS7,Application ID Status register [255:224]" tree.end tree "EMI1" base ad:0x400F4400 group.byte 0x0++0x3 line.byte 0x0 "RT_HOST2EC,Host-to-EC Mailbox Register" line.byte 0x1 "RT_EC2HOST,EC-to-Host Mailbox Register" line.byte 0x2 "RT_EC_ADDR_LSB,EC Address Access Control Register" hexmask.byte 0x2 2.--7. 1. "ADDR,This field defines bits[7:2] of EC_Address [15:0]. Bits[1:0] of the EC_Address are always forced to 00b. The EC_Address is aligned on a DWord boundary. It is the address of the memory being accessed by EC Data Byte 0 Register which is an.." bitfld.byte 0x2 0.--1. "ACCESS_TYPE,This field defines the type of access that occurs when the EC Data Register is read or written. 11b=Auto-increment 32-bit access. 10b=32-bit access. 01b=16-bit access. 00b=8-bit access." "0,1,2,3" line.byte 0x3 "RT_EC_ADDR_MSB,EC Address Access Control Register" bitfld.byte 0x3 7. "REGION,The field specifies which of two segments in the 32-bit internal address space is to be accessed by the EC_Address[14:2] to generate accesses to the memory. 1=The address defined by EC_Address[14:2] is relative to the base address.." "0: The address defined by EC_Address[14:2] is..,1: The address defined by EC_Address[14:2] is.." hexmask.byte 0x3 2.--6. 1. "ADDR,This field defines bits[14:8] of EC_Address. Bits[1:0] of the EC_Address are always forced to 00b. The EC_Address is aligned on a DWord boundary. It is the address of the memory being accessed by EC Data Byte 0 Register which is an offset.." group.long 0x4++0x3 line.long 0x0 "RT_DATA,EC Data Byte Register" group.byte 0x8++0x4 line.byte 0x0 "RT_INTR_SRC_LSB,Interrupt Source LSB Register" hexmask.byte 0x0 1.--7. 1. "EC_SWI_LSB,EC Software Interrupt Least Significant Bits. These bits are software interrupt bits that may be set by the EC to notify the host of an event. The meaning of these bits is dependent on the firmware implementation. Each bit in this field.." bitfld.byte 0x0 0. "EC_WR,EC Mailbox Write. This bit is set when the EC-to-HOST Mailbox Register has been written by the EC at offset 01h of the EC-Only registers. Note: there is no corresponding mask bit in the Interrupt Mask LSB Register." "0,1" line.byte 0x1 "RT_INTR_SRC_MSB,Interrupt Source MSB Register" hexmask.byte 0x1 0.--7. 1. "EC_SWI_MSB,EC Software Interrupt Most Significant Bits. These bits are software interrupt bits that may be set by the EC to notify the host of an event. The meaning of these bits is dependent on the firmware implementation. Each bit in this field is.." line.byte 0x2 "RT_INTR_MASK_LSB,Interrupt Mask LSB Register" hexmask.byte 0x2 1.--7. 1. "EC_SWI_EN_LSB,EC Software Interrupt Enable Least Significant Bits. Each bit that is set to '1b' in this field enables the generation of a Host Event interrupt by the corresponding bit in the EC_SWI field in the Interrupt Source LSB Register." bitfld.byte 0x2 0. "TEST,Test Bit." "0,1" line.byte 0x3 "RT_INTR_MASK_MSB,Interrupt Mask MSB Register" hexmask.byte 0x3 1.--7. 1. "EC_SWI_EN_MSB,EC Software Interrupt Enable Most Significant Bits. Each bit that is set to '1b' in this field enables the generation of a Host Event interrupt by the corresponding bit in the EC_SWI field in the Interrupt Source MSB Register." line.byte 0x4 "RT_APP_ID,Application ID Register. APPLICATION_ID When this field is 00h it can be written with any value. When set to a non-zero value. writing that value will clear this register to 00h. When set to a non-zero value. writing any value other than the.." group.byte 0x10++0x0 line.byte 0x0 "APP_ID_ASGN,Application ID Assignment Register." group.byte 0x100++0x1 line.byte 0x0 "HOST2EC,Host-to-EC Mailbox Register. 8-bit mailbox used communicate information from the system host to the embedded controller. Writing this register generates an event to notify the embedded controller. (R/WC)" line.byte 0x1 "EC2HOST,EC-to-Host Mailbox Register. 8-bit mailbox used communicate information from the embedded controller to the system host. Writing this register generates an event to notify the system host." group.long 0x104++0x3 line.long 0x0 "MEM0_BASE,Memory Base Address 0 Register [31:2] This memory base address defines the beginning of region 0 in the Embedded Controller's 32-bit internal address space. Memory allocated to region 0 is intended to be shared between the Host and the EC. The.." group.word 0x108++0x3 line.word 0x0 "MEM0_RD_LIMITS,Memory Read Limit 0 Register [14:2] Whenever a read of any byte in the EC Data Register is attempted. and bit 15 of EC_Address is 0. the field EC_Address[14:2] in the EC_Address_Register is compared to this field. As long as.." line.word 0x2 "MEM0_WR_LIMITS,Memory Write Limit 0 Register [14:2] Whenever a write of any byte in EC DATA Register is attempted and bit 15 of EC_Address is 0. the field EC_ADDRESS_MSB in the EC_Address Register is compared to this field. As long as EC_Address[14:2] is.." group.long 0x10C++0x3 line.long 0x0 "MEM1_BASE,Memory Base Address 1 Register. [31:2] This memory base address defines the beginning of region 1 in the Embedded Controller's 32-bit internal address space. Memory allocated to region 1 is intended to be shared between the Host and the EC. The.." group.word 0x110++0x7 line.word 0x0 "MEM1_RD_LIMITS,Memory Read Limit 1 Register. [14:2]: Whenever a read of any byte in the EC Data Register is attempted. and bit 15 of EC_ADDRESS is 1. the field EC_ADDRESS in the EC_Address_Register is compared to this field. As long as EC_ADDRESS is less.." line.word 0x2 "MEM1_WR_LIMITS,Memory Write Limit 1 Register. [14:2]: Whenever a write of any byte in EC DATA Register is attempted and bit 15 of EC_Address is 1. the field EC_Address[14:2] in the EC_Address Register is compared to this field. As long as.." line.word 0x4 "INTR_SET,[15:1] Interrupt Set Register. Writing a bit in this field with a '1b' sets the corresponding bit in the Interrupt Source Register to '1b'. Writing a bit in this field with a '0b' has no effect. Reading this field returns the current contents of.." line.word 0x6 "HOST_CLR_EN,[15:1] Host Clear Enable Register. When a bit in this field is '0b'. the corresponding bit in the Interrupt Source Register cannot be cleared by writes to the Interrupt Source Register. When a bit in this field is '1b'. the corresponding bit.." group.long 0x120++0x1F line.long 0x0 "APP_ID_STS0,Application ID Status register [31:0]" line.long 0x4 "APP_ID_STS1,Application ID Status register [63:32]" line.long 0x8 "APP_ID_STS2,Application ID Status register [95:64]" line.long 0xC "APP_ID_STS3,Application ID Status register [127:96]" line.long 0x10 "APP_ID_STS4,Application ID Status register [159:128]" line.long 0x14 "APP_ID_STS5,Application ID Status register [191:160]" line.long 0x18 "APP_ID_STS6,Application ID Status register [223:192]" line.long 0x1C "APP_ID_STS7,Application ID Status register [255:224]" tree.end tree "EMI2" base ad:0x400F4800 group.byte 0x0++0x3 line.byte 0x0 "RT_HOST2EC,Host-to-EC Mailbox Register" line.byte 0x1 "RT_EC2HOST,EC-to-Host Mailbox Register" line.byte 0x2 "RT_EC_ADDR_LSB,EC Address Access Control Register" hexmask.byte 0x2 2.--7. 1. "ADDR,This field defines bits[7:2] of EC_Address [15:0]. Bits[1:0] of the EC_Address are always forced to 00b. The EC_Address is aligned on a DWord boundary. It is the address of the memory being accessed by EC Data Byte 0 Register which is an.." bitfld.byte 0x2 0.--1. "ACCESS_TYPE,This field defines the type of access that occurs when the EC Data Register is read or written. 11b=Auto-increment 32-bit access. 10b=32-bit access. 01b=16-bit access. 00b=8-bit access." "0,1,2,3" line.byte 0x3 "RT_EC_ADDR_MSB,EC Address Access Control Register" bitfld.byte 0x3 7. "REGION,The field specifies which of two segments in the 32-bit internal address space is to be accessed by the EC_Address[14:2] to generate accesses to the memory. 1=The address defined by EC_Address[14:2] is relative to the base address.." "0: The address defined by EC_Address[14:2] is..,1: The address defined by EC_Address[14:2] is.." hexmask.byte 0x3 2.--6. 1. "ADDR,This field defines bits[14:8] of EC_Address. Bits[1:0] of the EC_Address are always forced to 00b. The EC_Address is aligned on a DWord boundary. It is the address of the memory being accessed by EC Data Byte 0 Register which is an offset.." group.long 0x4++0x3 line.long 0x0 "RT_DATA,EC Data Byte Register" group.byte 0x8++0x4 line.byte 0x0 "RT_INTR_SRC_LSB,Interrupt Source LSB Register" hexmask.byte 0x0 1.--7. 1. "EC_SWI_LSB,EC Software Interrupt Least Significant Bits. These bits are software interrupt bits that may be set by the EC to notify the host of an event. The meaning of these bits is dependent on the firmware implementation. Each bit in this field.." bitfld.byte 0x0 0. "EC_WR,EC Mailbox Write. This bit is set when the EC-to-HOST Mailbox Register has been written by the EC at offset 01h of the EC-Only registers. Note: there is no corresponding mask bit in the Interrupt Mask LSB Register." "0,1" line.byte 0x1 "RT_INTR_SRC_MSB,Interrupt Source MSB Register" hexmask.byte 0x1 0.--7. 1. "EC_SWI_MSB,EC Software Interrupt Most Significant Bits. These bits are software interrupt bits that may be set by the EC to notify the host of an event. The meaning of these bits is dependent on the firmware implementation. Each bit in this field is.." line.byte 0x2 "RT_INTR_MASK_LSB,Interrupt Mask LSB Register" hexmask.byte 0x2 1.--7. 1. "EC_SWI_EN_LSB,EC Software Interrupt Enable Least Significant Bits. Each bit that is set to '1b' in this field enables the generation of a Host Event interrupt by the corresponding bit in the EC_SWI field in the Interrupt Source LSB Register." bitfld.byte 0x2 0. "TEST,Test Bit." "0,1" line.byte 0x3 "RT_INTR_MASK_MSB,Interrupt Mask MSB Register" hexmask.byte 0x3 1.--7. 1. "EC_SWI_EN_MSB,EC Software Interrupt Enable Most Significant Bits. Each bit that is set to '1b' in this field enables the generation of a Host Event interrupt by the corresponding bit in the EC_SWI field in the Interrupt Source MSB Register." line.byte 0x4 "RT_APP_ID,Application ID Register. APPLICATION_ID When this field is 00h it can be written with any value. When set to a non-zero value. writing that value will clear this register to 00h. When set to a non-zero value. writing any value other than the.." group.byte 0x10++0x0 line.byte 0x0 "APP_ID_ASGN,Application ID Assignment Register." group.byte 0x100++0x1 line.byte 0x0 "HOST2EC,Host-to-EC Mailbox Register. 8-bit mailbox used communicate information from the system host to the embedded controller. Writing this register generates an event to notify the embedded controller. (R/WC)" line.byte 0x1 "EC2HOST,EC-to-Host Mailbox Register. 8-bit mailbox used communicate information from the embedded controller to the system host. Writing this register generates an event to notify the system host." group.long 0x104++0x3 line.long 0x0 "MEM0_BASE,Memory Base Address 0 Register [31:2] This memory base address defines the beginning of region 0 in the Embedded Controller's 32-bit internal address space. Memory allocated to region 0 is intended to be shared between the Host and the EC. The.." group.word 0x108++0x3 line.word 0x0 "MEM0_RD_LIMITS,Memory Read Limit 0 Register [14:2] Whenever a read of any byte in the EC Data Register is attempted. and bit 15 of EC_Address is 0. the field EC_Address[14:2] in the EC_Address_Register is compared to this field. As long as.." line.word 0x2 "MEM0_WR_LIMITS,Memory Write Limit 0 Register [14:2] Whenever a write of any byte in EC DATA Register is attempted and bit 15 of EC_Address is 0. the field EC_ADDRESS_MSB in the EC_Address Register is compared to this field. As long as EC_Address[14:2] is.." group.long 0x10C++0x3 line.long 0x0 "MEM1_BASE,Memory Base Address 1 Register. [31:2] This memory base address defines the beginning of region 1 in the Embedded Controller's 32-bit internal address space. Memory allocated to region 1 is intended to be shared between the Host and the EC. The.." group.word 0x110++0x7 line.word 0x0 "MEM1_RD_LIMITS,Memory Read Limit 1 Register. [14:2]: Whenever a read of any byte in the EC Data Register is attempted. and bit 15 of EC_ADDRESS is 1. the field EC_ADDRESS in the EC_Address_Register is compared to this field. As long as EC_ADDRESS is less.." line.word 0x2 "MEM1_WR_LIMITS,Memory Write Limit 1 Register. [14:2]: Whenever a write of any byte in EC DATA Register is attempted and bit 15 of EC_Address is 1. the field EC_Address[14:2] in the EC_Address Register is compared to this field. As long as.." line.word 0x4 "INTR_SET,[15:1] Interrupt Set Register. Writing a bit in this field with a '1b' sets the corresponding bit in the Interrupt Source Register to '1b'. Writing a bit in this field with a '0b' has no effect. Reading this field returns the current contents of.." line.word 0x6 "HOST_CLR_EN,[15:1] Host Clear Enable Register. When a bit in this field is '0b'. the corresponding bit in the Interrupt Source Register cannot be cleared by writes to the Interrupt Source Register. When a bit in this field is '1b'. the corresponding bit.." group.long 0x120++0x1F line.long 0x0 "APP_ID_STS0,Application ID Status register [31:0]" line.long 0x4 "APP_ID_STS1,Application ID Status register [63:32]" line.long 0x8 "APP_ID_STS2,Application ID Status register [95:64]" line.long 0xC "APP_ID_STS3,Application ID Status register [127:96]" line.long 0x10 "APP_ID_STS4,Application ID Status register [159:128]" line.long 0x14 "APP_ID_STS5,Application ID Status register [191:160]" line.long 0x18 "APP_ID_STS6,Application ID Status register [223:192]" line.long 0x1C "APP_ID_STS7,Application ID Status register [255:224]" tree.end tree.end tree "ESPI (Enhanced Serial Peripheral Interface)" base ad:0x0 tree "ESPI_IO" base ad:0x400F3400 group.byte 0x0++0x1 line.byte 0x0 "IND,The INDEX register. which is part of the Configuration Port. is used as a pointer to a Configuration Register Address." line.byte 0x1 "DAT_REG,The DATA register. which is part of the Configuration Port. is used to read or write data to the register currently being selected by the INDEX Register." rgroup.long 0x100++0x13 line.long 0x0 "PC_LC_ADDR_LSW,Peripheral Channel Last Cycle Register (DWord 0)" hexmask.long 0x0 0.--31. 1. "LADR,This field records bits[31:0] of the 64 bit address of the most recent eSPI transaction." line.long 0x4 "PC_LC_ADDR_MSW,Peripheral Channel Last Cycle Register (DWord 1)" hexmask.long 0x4 0.--31. 1. "MADR,This field records bits[63:32] of the 64 bit address of the most recent eSPI transaction." line.long 0x8 "PC_LC_LEN_TYPE_TAG,Peripheral Channel Last Cycle Register (DWord 2)" hexmask.long.byte 0x8 20.--23. 1. "PC_TAG,This field records the tag of the most recent eSPI transaction." newline hexmask.long.byte 0x8 12.--19. 1. "PC_CY_TYPE,This field records the cycle type of the most recent eSPI transaction." newline hexmask.long.word 0x8 0.--11. 1. "PC_LEN,This field records the length of the most recent eSPI transaction." line.long 0xC "PC_ERR_ADDR_LSW,Peripheral Channel Error Address Register (DWord 0)" hexmask.long 0xC 0.--31. 1. "LSDW,This field records bits[31:0] of the 64 bit address of the most recent eSPI transaction that incurred an error." line.long 0x10 "PC_ERR_ADDR_MSW,Peripheral Channel Error Address Register (DWord 1)" hexmask.long 0x10 0.--31. 1. "MSDW,This field records bits[63:32] of the 64 bit address of the most recent eSPI transaction that incurred an error." group.long 0x114++0x7 line.long 0x0 "PC_STATUS,Peripheral Channel Status Register" bitfld.long 0x0 28. "M_EN_CHNG,This bit is set to '1' whenever the field PC_MASTERING_ENABLE_STATUS in this register changes. Once set it remains set until cleared by being written with a 1 (R/WC)" "0,1" newline bitfld.long 0x0 27. "M_EN_STS,This bit is 1 if three bits in the Peripheral Channel Capabilities and Configurations register Peripheral Channel Mastering Enable Peripheral Channel Ready and Peripheral Channel Enable are all 1 and 0 otherwise." "0,1" newline bitfld.long 0x0 25. "EN_CHNG,This bit is set to '1' whenever the field PC_CHANNEL_ENABLE_STATUS in this register changes. Once set it remains set until cleared by being written with a 1. (R/WC)" "0,1" newline bitfld.long 0x0 24. "CHN_EN_STS,This bit reflects the Host writable configuration field." "0,1" newline bitfld.long 0x0 17. "BAR_CONFL,This bit is set to '1' whenever a BAR conflict occurs on an eSPI address. A BAR conflict occurs when more than one BAR matches the address of an eSPI transaction. Once set it remains set until cleared by being written with a 1. (R/WC)" "0,1" newline bitfld.long 0x0 16. "PC_BUS_ERROR,This bit is set to '1' whenever an eSPI access causes an internal bus error. Once set it remains set until cleared by being written with a 1. (R/WC)" "0,1" newline hexmask.long.byte 0x0 8.--13. 1. "VIR_BAR_LDN,This field returns the Logical Device Number of the device targeted by the most recent virtual transaction." newline bitfld.long 0x0 2. "VIR_TYP,This bit returns the type of Virtualized eSPI transaction that is 1=Peripheral Channel Memory Address access 0=Peripheral Channel I/O Address access." "0: Peripheral Channel I/O Address access,1: Peripheral Channel Memory Address access" newline bitfld.long 0x0 1. "VIR_WR,This bit is set whenever a eSPI write transaction targeting a Logical Device with an I/O BAR or a Memory BAR in which the VIRTUALIZED bit is set. (R/WC)" "0,1" newline bitfld.long 0x0 0. "VIR_RD,This bit is set whenever a eSPI read transaction targeting a Logical Device with an I/O BAR or a Memory BAR in which the VIRTUALIZED bit is set. (R/WC)" "0,1" line.long 0x4 "PC_IEN,Peripheral Channel Interrupt Enable Register" bitfld.long 0x4 28. "M_EN_CHNG_EN,When this bit is '1' an interrupt is generated when the bit PC_MASTERING_ENABLE_CHANGE in the Peripheral Channel Status Register is 1. When this bit is '0' the status bit will not generate an interrupt." "0,1" newline bitfld.long 0x4 25. "EN_CHNG_EN,When this bit is '1' an interrupt is generated when the bit PC_ENABLE_CHANGE in the Peripheral Channel Status Register is 1. When this bit is '0' the status bit will not generate an interrupt." "0,1" newline bitfld.long 0x4 17. "BAR_CONFL_EN,When this bit is '1' an interrupt is generated when the bit BAR_CONFLICT in the Peripheral Channel Status Register is 1. When this bit is '0' the status bit will not generate an interrupt." "0,1" newline bitfld.long 0x4 16. "BUS_ERR_EN,When this bit is '1' an interrupt is generated when the bit PC_BUS_ERROR in the Peripheral Channel Status Register is 1. When this bit is '0' the status bit will not generate an interrupt." "0,1" newline bitfld.long 0x4 1. "VIR_WR_EN,When this bit is '1' an interrupt is generated when the bit PC_VIRTUAL_WRITE in the Peripheral Channel Status Register is 1. When this bit is '0' the status bit will not generate an interrupt." "0,1" newline bitfld.long 0x4 0. "VIR_RD_EN,When this bit is '1' an interrupt is generated when the bit PC_VIRTUAL_READ in the Peripheral Channel Status Register is 1. When this bit is '0' the status bit will not generate an interrupt." "0,1" group.long 0x120++0xF line.long 0x0 "IOBAR_INH_LSW,BAR Inhibit Register (DWord 0)" hexmask.long 0x0 0.--31. 1. "LSDW,When bit Di of BAR_Inhibit is 1 the BAR for Logical Device i is disabled and its addresses will not be claimed on the eSPI bus independent of the value of the Valid bit in the BAR. The BAR Inhibit function applies to both I/O transactions and.." line.long 0x4 "IOBAR_INH_MSW,BAR Inhibit Register (DWord 1)" hexmask.long 0x4 0.--31. 1. "MSDW,When bit Di of BAR_Inhibit is 1 the BAR for Logical Device i is disabled and its addresses will not be claimed on the eSPI bus independent of the value of the Valid bit in the BAR. The BAR Inhibit function applies to both I/O transactions and.." line.long 0x8 "IOBAR_INIT,eSPI BAR Init Register" hexmask.long.word 0x8 0.--15. 1. "INIT,This field is loaded into the Base Address Register register for Logical Device Ch (eSPI I/O Configuration Port) on RESET_SIO." line.long 0xC "EC_CTRL_IRQ,EC IRQ Register" bitfld.long 0xC 0. "IRQ,This bit can be used as a firmware-controlled interrupt source for the EC. When the EC entry in the IRQ Assignment Table is set to a valid IRQ number changes in this bit will be transmitted to the Host over a Virtual Wire IRQ channel." "0,1" group.long 0x134++0x4B line.long 0x0 "BASE_ADDR,eSPI I/O Base Address Register" bitfld.long 0x0 16. "VIR,1=Peripheral Channel I/O for this device is virtualized and reads and writes are handled in firmware 0=All Peripheral Channel I/O Reads and Writes for this device are completed by hardware." "0: All Peripheral Channel I/O Reads and Writes for..,1: Peripheral Channel I/O for this device is.." newline hexmask.long.byte 0x0 8.--13. 1. "LDN,These 6 bits are used to specify a logical device number within a bus. This field is multiplied by 400h to provide the address within the peripheral bus address. Logical Device Numbers that do not corresponding to logical devices that are.." newline hexmask.long.byte 0x0 0.--7. 1. "MASK,These 8 bits are used to mask off address bits in the address match between an eSPI I/O address and the Host Address field of the BARs. A block of up to 256 8-bit registers can be assigned to one base address." line.long 0x4 "ESPI_MEM_BASE_ADDR,eSPI Memory Base Address Register" bitfld.long 0x4 16. "VIR,1=Peripheral Channel I/O for this device is virtualized and reads and writes are handled in firmware 0=All Peripheral Channel I/O Reads and Writes for this device are completed by hardware." "0: All Peripheral Channel I/O Reads and Writes for..,1: Peripheral Channel I/O for this device is.." newline hexmask.long.byte 0x4 8.--13. 1. "LDN,These 6 bits are used to specify a logical device number within a bus. This field is multiplied by 400h to provide the address within the peripheral bus address. Logical Device Numbers that do not corresponding to logical devices that are.." newline hexmask.long.byte 0x4 0.--7. 1. "MASK,These 8 bits are used to mask off address bits in the address match between an eSPI I/O address and the Host Address field of the BARs. A block of up to 256 8-bit registers can be assigned to one base address." line.long 0x8 "MBX_BASE_ADDR,Mailbox BAR Register" bitfld.long 0x8 16. "VIR,1=Peripheral Channel I/O for this device is virtualized and reads and writes are handled in firmware 0=All Peripheral Channel I/O Reads and Writes for this device are completed by hardware." "0: All Peripheral Channel I/O Reads and Writes for..,1: Peripheral Channel I/O for this device is.." newline hexmask.long.byte 0x8 8.--13. 1. "LDN,These 6 bits are used to specify a logical device number within a bus. This field is multiplied by 400h to provide the address within the peripheral bus address. Logical Device Numbers that do not corresponding to logical devices that are.." newline hexmask.long.byte 0x8 0.--7. 1. "MASK,These 8 bits are used to mask off address bits in the address match between an eSPI I/O address and the Host Address field of the BARs. A block of up to 256 8-bit registers can be assigned to one base address." line.long 0xC "EM8042_BASE_ADDR,8042 Emulated Keyboard Controller BAR Register" bitfld.long 0xC 16. "VIR,1=Peripheral Channel I/O for this device is virtualized and reads and writes are handled in firmware 0=All Peripheral Channel I/O Reads and Writes for this device are completed by hardware." "0: All Peripheral Channel I/O Reads and Writes for..,1: Peripheral Channel I/O for this device is.." newline hexmask.long.byte 0xC 8.--13. 1. "LDN,These 6 bits are used to specify a logical device number within a bus. This field is multiplied by 400h to provide the address within the peripheral bus address. Logical Device Numbers that do not corresponding to logical devices that are.." newline hexmask.long.byte 0xC 0.--7. 1. "MASK,These 8 bits are used to mask off address bits in the address match between an eSPI I/O address and the Host Address field of the BARs. A block of up to 256 8-bit registers can be assigned to one base address." line.long 0x10 "ACPI_EC_0_BASE_ADDR,ACPI EC Channel 0 Register" bitfld.long 0x10 16. "VIR,1=Peripheral Channel I/O for this device is virtualized and reads and writes are handled in firmware 0=All Peripheral Channel I/O Reads and Writes for this device are completed by hardware." "0: All Peripheral Channel I/O Reads and Writes for..,1: Peripheral Channel I/O for this device is.." newline hexmask.long.byte 0x10 8.--13. 1. "LDN,These 6 bits are used to specify a logical device number within a bus. This field is multiplied by 400h to provide the address within the peripheral bus address. Logical Device Numbers that do not corresponding to logical devices that are.." newline hexmask.long.byte 0x10 0.--7. 1. "MASK,These 8 bits are used to mask off address bits in the address match between an eSPI I/O address and the Host Address field of the BARs. A block of up to 256 8-bit registers can be assigned to one base address." line.long 0x14 "ACPI_EC_1_BASE_ADDR,ACPI EC Channel 1 BAR Register" bitfld.long 0x14 16. "VIR,1=Peripheral Channel I/O for this device is virtualized and reads and writes are handled in firmware 0=All Peripheral Channel I/O Reads and Writes for this device are completed by hardware." "0: All Peripheral Channel I/O Reads and Writes for..,1: Peripheral Channel I/O for this device is.." newline hexmask.long.byte 0x14 8.--13. 1. "LDN,These 6 bits are used to specify a logical device number within a bus. This field is multiplied by 400h to provide the address within the peripheral bus address. Logical Device Numbers that do not corresponding to logical devices that are.." newline hexmask.long.byte 0x14 0.--7. 1. "MASK,These 8 bits are used to mask off address bits in the address match between an eSPI I/O address and the Host Address field of the BARs. A block of up to 256 8-bit registers can be assigned to one base address." line.long 0x18 "ACPI_EC_2_BASE_ADDR,ACPI EC Channel 2 BAR Register" bitfld.long 0x18 16. "VIR,1=Peripheral Channel I/O for this device is virtualized and reads and writes are handled in firmware 0=All Peripheral Channel I/O Reads and Writes for this device are completed by hardware." "0: All Peripheral Channel I/O Reads and Writes for..,1: Peripheral Channel I/O for this device is.." newline hexmask.long.byte 0x18 8.--13. 1. "LDN,These 6 bits are used to specify a logical device number within a bus. This field is multiplied by 400h to provide the address within the peripheral bus address. Logical Device Numbers that do not corresponding to logical devices that are.." newline hexmask.long.byte 0x18 0.--7. 1. "MASK,These 8 bits are used to mask off address bits in the address match between an eSPI I/O address and the Host Address field of the BARs. A block of up to 256 8-bit registers can be assigned to one base address." line.long 0x1C "ACPI_EC_3_BASE_ADDR,ACPI EC Channel 3 BAR Register" bitfld.long 0x1C 16. "VIR,1=Peripheral Channel I/O for this device is virtualized and reads and writes are handled in firmware 0=All Peripheral Channel I/O Reads and Writes for this device are completed by hardware." "0: All Peripheral Channel I/O Reads and Writes for..,1: Peripheral Channel I/O for this device is.." newline hexmask.long.byte 0x1C 8.--13. 1. "LDN,These 6 bits are used to specify a logical device number within a bus. This field is multiplied by 400h to provide the address within the peripheral bus address. Logical Device Numbers that do not corresponding to logical devices that are.." newline hexmask.long.byte 0x1C 0.--7. 1. "MASK,These 8 bits are used to mask off address bits in the address match between an eSPI I/O address and the Host Address field of the BARs. A block of up to 256 8-bit registers can be assigned to one base address." line.long 0x20 "ACPI_EC_4_BASE_ADDR,ACPI EC Channel 4 BAR Register" bitfld.long 0x20 16. "VIR,1=Peripheral Channel I/O for this device is virtualized and reads and writes are handled in firmware 0=All Peripheral Channel I/O Reads and Writes for this device are completed by hardware." "0: All Peripheral Channel I/O Reads and Writes for..,1: Peripheral Channel I/O for this device is.." newline hexmask.long.byte 0x20 8.--13. 1. "LDN,These 6 bits are used to specify a logical device number within a bus. This field is multiplied by 400h to provide the address within the peripheral bus address. Logical Device Numbers that do not corresponding to logical devices that are.." newline hexmask.long.byte 0x20 0.--7. 1. "MASK,These 8 bits are used to mask off address bits in the address match between an eSPI I/O address and the Host Address field of the BARs. A block of up to 256 8-bit registers can be assigned to one base address." line.long 0x24 "ACPI_PM1_BASE_ADDR,I/O Base Address Register" bitfld.long 0x24 16. "VIR,1=Peripheral Channel I/O for this device is virtualized and reads and writes are handled in firmware 0=All Peripheral Channel I/O Reads and Writes for this device are completed by hardware." "0: All Peripheral Channel I/O Reads and Writes for..,1: Peripheral Channel I/O for this device is.." newline hexmask.long.byte 0x24 8.--13. 1. "LDN,These 6 bits are used to specify a logical device number within a bus. This field is multiplied by 400h to provide the address within the peripheral bus address. Logical Device Numbers that do not corresponding to logical devices that are.." newline hexmask.long.byte 0x24 0.--7. 1. "MASK,These 8 bits are used to mask off address bits in the address match between an eSPI I/O address and the Host Address field of the BARs. A block of up to 256 8-bit registers can be assigned to one base address." line.long 0x28 "FAST_KDB_BASE_ADDR,Legacy (Fast Keyboard) BAR Register" bitfld.long 0x28 16. "VIR,1=Peripheral Channel I/O for this device is virtualized and reads and writes are handled in firmware 0=All Peripheral Channel I/O Reads and Writes for this device are completed by hardware." "0: All Peripheral Channel I/O Reads and Writes for..,1: Peripheral Channel I/O for this device is.." newline hexmask.long.byte 0x28 8.--13. 1. "LDN,These 6 bits are used to specify a logical device number within a bus. This field is multiplied by 400h to provide the address within the peripheral bus address. Logical Device Numbers that do not corresponding to logical devices that are.." newline hexmask.long.byte 0x28 0.--7. 1. "MASK,These 8 bits are used to mask off address bits in the address match between an eSPI I/O address and the Host Address field of the BARs. A block of up to 256 8-bit registers can be assigned to one base address." line.long 0x2C "UART_0_BASE_ADDR,UART 0 BAR Register" bitfld.long 0x2C 16. "VIR,1=Peripheral Channel I/O for this device is virtualized and reads and writes are handled in firmware 0=All Peripheral Channel I/O Reads and Writes for this device are completed by hardware." "0: All Peripheral Channel I/O Reads and Writes for..,1: Peripheral Channel I/O for this device is.." newline hexmask.long.byte 0x2C 8.--13. 1. "LDN,These 6 bits are used to specify a logical device number within a bus. This field is multiplied by 400h to provide the address within the peripheral bus address. Logical Device Numbers that do not corresponding to logical devices that are.." newline hexmask.long.byte 0x2C 0.--7. 1. "MASK,These 8 bits are used to mask off address bits in the address match between an eSPI I/O address and the Host Address field of the BARs. A block of up to 256 8-bit registers can be assigned to one base address." line.long 0x30 "UART_1_BASE_ADDR,UART 1 BAR Register" bitfld.long 0x30 16. "VIR,1=Peripheral Channel I/O for this device is virtualized and reads and writes are handled in firmware 0=All Peripheral Channel I/O Reads and Writes for this device are completed by hardware." "0: All Peripheral Channel I/O Reads and Writes for..,1: Peripheral Channel I/O for this device is.." newline hexmask.long.byte 0x30 8.--13. 1. "LDN,These 6 bits are used to specify a logical device number within a bus. This field is multiplied by 400h to provide the address within the peripheral bus address. Logical Device Numbers that do not corresponding to logical devices that are.." newline hexmask.long.byte 0x30 0.--7. 1. "MASK,These 8 bits are used to mask off address bits in the address match between an eSPI I/O address and the Host Address field of the BARs. A block of up to 256 8-bit registers can be assigned to one base address." line.long 0x34 "EMI_0_BASE_ADDR,Embedded Memory Interface (EMI) 0 BAR Register" bitfld.long 0x34 16. "VIR,1=Peripheral Channel I/O for this device is virtualized and reads and writes are handled in firmware 0=All Peripheral Channel I/O Reads and Writes for this device are completed by hardware." "0: All Peripheral Channel I/O Reads and Writes for..,1: Peripheral Channel I/O for this device is.." newline hexmask.long.byte 0x34 8.--13. 1. "LDN,These 6 bits are used to specify a logical device number within a bus. This field is multiplied by 400h to provide the address within the peripheral bus address. Logical Device Numbers that do not corresponding to logical devices that are.." newline hexmask.long.byte 0x34 0.--7. 1. "MASK,These 8 bits are used to mask off address bits in the address match between an eSPI I/O address and the Host Address field of the BARs. A block of up to 256 8-bit registers can be assigned to one base address." line.long 0x38 "EMI_1_BASE_ADDR,Embedded Memory Interface (EMI) 1 BAR Register" bitfld.long 0x38 16. "VIR,1=Peripheral Channel I/O for this device is virtualized and reads and writes are handled in firmware 0=All Peripheral Channel I/O Reads and Writes for this device are completed by hardware." "0: All Peripheral Channel I/O Reads and Writes for..,1: Peripheral Channel I/O for this device is.." newline hexmask.long.byte 0x38 8.--13. 1. "LDN,These 6 bits are used to specify a logical device number within a bus. This field is multiplied by 400h to provide the address within the peripheral bus address. Logical Device Numbers that do not corresponding to logical devices that are.." newline hexmask.long.byte 0x38 0.--7. 1. "MASK,These 8 bits are used to mask off address bits in the address match between an eSPI I/O address and the Host Address field of the BARs. A block of up to 256 8-bit registers can be assigned to one base address." line.long 0x3C "EMI_2_BASE_ADDR,Embedded Memory Interface (EMI) 2 BAR Register" bitfld.long 0x3C 16. "VIR,1=Peripheral Channel I/O for this device is virtualized and reads and writes are handled in firmware 0=All Peripheral Channel I/O Reads and Writes for this device are completed by hardware." "0: All Peripheral Channel I/O Reads and Writes for..,1: Peripheral Channel I/O for this device is.." newline hexmask.long.byte 0x3C 8.--13. 1. "LDN,These 6 bits are used to specify a logical device number within a bus. This field is multiplied by 400h to provide the address within the peripheral bus address. Logical Device Numbers that do not corresponding to logical devices that are.." newline hexmask.long.byte 0x3C 0.--7. 1. "MASK,These 8 bits are used to mask off address bits in the address match between an eSPI I/O address and the Host Address field of the BARs. A block of up to 256 8-bit registers can be assigned to one base address." line.long 0x40 "PORT80_0_BASE_ADDR,BIOS Debug Port (Port 80) 0 BAR Register" bitfld.long 0x40 16. "VIR,1=Peripheral Channel I/O for this device is virtualized and reads and writes are handled in firmware 0=All Peripheral Channel I/O Reads and Writes for this device are completed by hardware." "0: All Peripheral Channel I/O Reads and Writes for..,1: Peripheral Channel I/O for this device is.." newline hexmask.long.byte 0x40 8.--13. 1. "LDN,These 6 bits are used to specify a logical device number within a bus. This field is multiplied by 400h to provide the address within the peripheral bus address. Logical Device Numbers that do not corresponding to logical devices that are.." newline hexmask.long.byte 0x40 0.--7. 1. "MASK,These 8 bits are used to mask off address bits in the address match between an eSPI I/O address and the Host Address field of the BARs. A block of up to 256 8-bit registers can be assigned to one base address." line.long 0x44 "PORT80_1_BASE_ADDR,BIOS Debug Port (Port 80) 1 BAR Register" bitfld.long 0x44 16. "VIR,1=Peripheral Channel I/O for this device is virtualized and reads and writes are handled in firmware 0=All Peripheral Channel I/O Reads and Writes for this device are completed by hardware." "0: All Peripheral Channel I/O Reads and Writes for..,1: Peripheral Channel I/O for this device is.." newline hexmask.long.byte 0x44 8.--13. 1. "LDN,These 6 bits are used to specify a logical device number within a bus. This field is multiplied by 400h to provide the address within the peripheral bus address. Logical Device Numbers that do not corresponding to logical devices that are.." newline hexmask.long.byte 0x44 0.--7. 1. "MASK,These 8 bits are used to mask off address bits in the address match between an eSPI I/O address and the Host Address field of the BARs. A block of up to 256 8-bit registers can be assigned to one base address." line.long 0x48 "RTC_BASE_ADDR,RTC Base Address Register" bitfld.long 0x48 16. "VIR,1=Peripheral Channel I/O for this device is virtualized and reads and writes are handled in firmware 0=All Peripheral Channel I/O Reads and Writes for this device are completed by hardware." "0: All Peripheral Channel I/O Reads and Writes for..,1: Peripheral Channel I/O for this device is.." newline hexmask.long.byte 0x48 8.--13. 1. "LDN,These 6 bits are used to specify a logical device number within a bus. This field is multiplied by 400h to provide the address within the peripheral bus address. Logical Device Numbers that do not corresponding to logical devices that are.." newline hexmask.long.byte 0x48 0.--7. 1. "MASK,These 8 bits are used to mask off address bits in the address match between an eSPI I/O address and the Host Address field of the BARs. A block of up to 256 8-bit registers can be assigned to one base address." group.long 0x18C++0x3 line.long 0x0 "GLUE_BASE_ADDR,GLUE Base Address Register" bitfld.long 0x0 16. "VIR,1=Peripheral Channel I/O for this device is virtualized and reads and writes are handled in firmware 0=All Peripheral Channel I/O Reads and Writes for this device are completed by hardware." "0: All Peripheral Channel I/O Reads and Writes for..,1: Peripheral Channel I/O for this device is.." newline hexmask.long.byte 0x0 8.--13. 1. "LDN,These 6 bits are used to specify a logical device number within a bus. This field is multiplied by 400h to provide the address within the peripheral bus address. Logical Device Numbers that do not corresponding to logical devices that are.." newline hexmask.long.byte 0x0 0.--7. 1. "MASK,These 8 bits are used to mask off address bits in the address match between an eSPI I/O address and the Host Address field of the BARs. A block of up to 256 8-bit registers can be assigned to one base address." group.long 0x220++0xF line.long 0x0 "LTR_STS,LTR Peripheral Status Register" bitfld.long 0x0 8. "TX_BUSY,This bit is set to '1' when firmware writes '1' to the LTR_START (ltr_initiate) bit in the LTR Peripheral Control Register. It is cleared by hardware when the transfer is sufficiently complete so that another packet can be transmitted. If.." "0,1" newline bitfld.long 0x0 4. "DIS_H_STS,A '1' in this bit indicates that the last requested Transmit operation was aborted because Bus Mastering has been disabled by the Host. Bus Mastering is disabled whenever the Peripheral Channel Mastering Enable bit in that register is '0' .." "0,1" newline bitfld.long 0x0 3. "STRT_OVRUN_STS,A Start was attempted while the TRANSMIT_BUSY bit in this register was '1'. Any Transmit in progress is immediately terminated. (R/WC)" "0,1" newline bitfld.long 0x0 0. "TX_DON_STS,This bit is set to '1' whenever a Transmit operation terminates (the TRANSMIT_DONE bit in this register goes from 1 to 0). (R/WC)" "0,1" line.long 0x4 "LTR_EN,LTR Peripheral Enable Register" bitfld.long 0x4 0. "TX_DONE_IEN,When this bit is '1' an interrupt is generated when the bit TRANSMIT_DONE_STATUS in the LTR Peripheral Status Register is 1. When this bit is '0' the status bit will not generate an interrupt." "0,1" line.long 0x8 "LTR_CTRL,LTR Peripheral Control Register" hexmask.long.byte 0x8 8.--11. 1. "OUTG_TAG,This 4-bit value will be inserted as the TAG number in the next transmitted LTR packet. According to current understanding of Intel specs this field should be kept zero by firmware." newline bitfld.long 0x8 0. "STRT,Writing '1' to this bit triggers the transmission of an LTR packet defined by the LTR Peripheral Message register. Writing '0' to this bit has no effect. The transmission will be inhibited if the Peripheral channel is not Ready as defined in.." "0,1" line.long 0xC "LTR_MESG,LTR Peripheral Message Register" bitfld.long 0xC 15. "REQ_BIT,1 = Maximum latency tolerated is defined by the Scale and Length fields of this register. 0 = No Requirement. Infinite latency tolerated. (Default)." "0: No Requirement,1: Maximum latency tolerated is defined by the.." newline bitfld.long 0xC 13.--14. "RES_TX_BITS,These bits are Read/Write but are undefined in the 16-bit LTR message format. These bits are transmitted but according to current specs they must always be kept as zeros when writing this register." "0,1,2,3" newline bitfld.long 0xC 10.--12. "SCAL,This field declares the time unit expressed by each count of the Value field of this register." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xC 0.--9. 1. "VAL,This field declares a time in units expressed by the Scale field. Zero in both this field and the Scale field (zero time) demands best possible effort (minimal latency) by the chipset." group.long 0x240++0x3 line.long 0x0 "OOB_RX_ADDR_LSW,OOB Channel Receive Address Register" hexmask.long 0x0 2.--31. 1. "RX_BUF,This field must be initialized to contain the Base Address for accepting the next OOB packet." group.long 0x248++0x3 line.long 0x0 "OOB_TX_ADDR_LSW,OOB Channel Transmit Address Register" hexmask.long 0x0 2.--31. 1. "TX_BUF,Before starting an OOB Transmit this field must be initialized to contain the Base Address of the buffer in SRAM. The contents of the transmit buffer should not be modified while TRANSMIT_BUSY is asserted." group.long 0x250++0x1F line.long 0x0 "OOB_RX_LEN,OOB Channel Receive Length Register" hexmask.long.word 0x0 16.--28. 1. "BUF,Before setting the Receive Enable bit to allow incoming traffic to the Receive Buffer area this 13-bit field must be initialized to contain the length in bytes of the receiving buffer in SRAM. This limits the number of bytes that can be.." newline hexmask.long.word 0x0 0.--12. 1. "MSG,This 13-bit read-only field reports how many bytes were received into SRAM in the last packet. This is necessary independent of any 'byte count' in the packet itself to distinguish between an SMBus packet with or without a PEC byte." line.long 0x4 "OOB_TX_LEN,OOB Channel Transmit Length Register" hexmask.long.word 0x4 0.--12. 1. "MSG,This 13-bit field declares how many bytes are to be transmitted from the Tramsit Buffer memory. A value of zero or a value greater than the defined Max Packet Size (73 decimal or 4Dh by default) is illegal and will trigger Bad Request.." line.long 0x8 "OOB_RX_CTRL,OOB Channel Receive Control Register" bitfld.long 0x8 16.--18. "MAX_PAYLD_SIZE_SEL,This allows firmware to read the correspondingly-named field in the eSPI Configuration register. The 001b default code selects 64-byte mode which is actually a 73-byte max payload size for eSPI (64 bytes plus MCTP wrapper bytes)." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9. "CHN_EN,This allows firmware to read the OOB Message Channel Enabled field in the eSPI Configuration register. The Master sets the bit to '1' to enable the OOB channel." "0,1" newline bitfld.long 0x8 0. "SET_RX_AVAIL,Firmware sets this bit to '1' to indicate that an SRAM buffer is available to receive the next Down OOB packet. This forces the bit RECEIVE_ENABLE bit in the OOB Channel Receive Status Register register to be set to '1'. The OOB Channel.." "0,1" line.long 0xC "OOB_RX_IEN,OOB Channel Receive Interrupt Enable Register" bitfld.long 0xC 0. "RX_IEN,When this bit is '1' an interrupt is generated when the bit RECEIVE_DONE_STATUS in the OOB Channel Receive Status Register is 1. When this bit is '0' the status bit will not generate an interrupt." "0,1" line.long 0x10 "OOB_RX_STS,OOB Channel Receive Status Register" hexmask.long.byte 0x10 8.--11. 1. "IN_TAG,This field holds the 4-bit TAG in the last message received from the Master." newline bitfld.long 0x10 3. "RX_EN,This bit is set to '1' when firmware sets the bit SET_RECEIVE_AVAILABLE in the OOB Channel Receive Control Register to '1' to indicate that an SRAM buffer is available to receive the next Down OOB packet. The OOB Channel Receive Address.." "0,1" newline bitfld.long 0x10 2. "OVRUN_STS,This bit is set to '1' whenever an incoming packet is truncated because it was longer than the RECEIVE_BUFFER_LENGTH field. Incoming extra bytes are discarded when this error is triggered but the buffer receives the data up to its limit .." "0,1" newline bitfld.long 0x10 1. "INT_BUS_ERR_STS,This bit is set to '1' whenever the channel tries to write an incoming byte into an invalid area of the internal addressing space. This could happen if the OOB Channel Receive Address Register was set to something invalid by.." "0,1" newline bitfld.long 0x10 0. "DONE,This bit is set to '1' whenever the RECEIVE_ENABLE bit in this register is cleared to '0' by hardware when an incoming packet is completely transferred to SRAM. This bit is also set whenever either OVERRUN_STATUS or INTERNAL_BUS_ERROR_STATUS in.." "0,1" line.long 0x14 "OOB_TX_CTRL,OOB Channel Transmit Control Register" hexmask.long.byte 0x14 8.--11. 1. "OUTG_TAG,This 4-bit value will be inserted as the TAG number in the next transmitted OOB packet. This field must be 0." newline bitfld.long 0x14 0. "TX_STRT,A write of '1' to this bit starts the transmission of an OOB packet defined by the OOB Channel Transmit Address Register and OOB Channel Transmit Length Register registers. A write of '0' has no effect. The transmission will be.." "0,1" line.long 0x18 "OOB_TX_IEN,OOB Channel Transmit Interrupt Enable Register" bitfld.long 0x18 1. "CHN_EN_CHNG,When this bit is '1' an interrupt is generated when the bit CHANNEL_ENABLE_CHANGE_STATUS in the OOB Channel Transmit Status Register is 1. When this bit is '0' the status bit will not generate an interrupt." "0,1" newline bitfld.long 0x18 0. "DONE,When this bit is '1' an interrupt is generated when the bit TRANSMIT_DONE_STATUS in the OOB Channel Transmit Status Register is 1. When this bit is '0' the status bit will not generate an interrupt." "0,1" line.long 0x1C "OOB_TX_STS,OOB Channel Transmit Status Register" bitfld.long 0x1C 9. "CHN_EN_IMG,This bit is an image of the OOB Channel Enabled bit in the OOB Channel Receive Control Register register. It is provided here so that it can be seen with the CHANNEL_ENABLE_CHANGE_STATUS Interrupt Status bit for efficiency." "0,1" newline bitfld.long 0x1C 8. "TX_BUSY,This bit is set to '1' when firmware writes '1' to the TRANSMIT_START bit. It is cleared by hardware when the transfer is complete. If the TRANSMIT_START bit is written '1' while this bit is also '1' then this will set the.." "0,1" newline bitfld.long 0x1C 5. "BAD_REQ,This bit is intended for any situation where a firmware request cannot be started because it expresses something impossible. This bit will be set for a request to Transmit 0 bytes or if a Transmit length is more than the selected Max.." "0,1" newline bitfld.long 0x1C 3. "STRT_OVRUN_STS,This error flag indicates a Start was attempted while the channel was Busy. Any Transmit in progress is immediately halted. (R/WC)" "0,1" newline bitfld.long 0x1C 2. "INT_BUS_ERR_STS,This error flag indicates an internal bus violation occurred in trying to transmit. (R/WC)" "0,1" newline bitfld.long 0x1C 1. "CHN_EN_CHNG_STS,This bit is set to '1' whenever the eSPI Master changes the state of the OOB Message Channel Enable bit in the OOB Channel Capabilities and Configurations Master register. (R/WC)." "0,1" newline bitfld.long 0x1C 0. "DONE,This bit is set to '1' whenever a Transmit operation terminates (TRANSMIT_BUSY in this register goes from '1' to '0'). (R/WC)" "0,1" group.long 0x280++0x3 line.long 0x0 "FC_FLASH_ADDR_LSW,Flash Access Channel Flash Address Register" hexmask.long 0x0 0.--31. 1. "FLSW,Before starting a Flash access this field must be initialized to contain the value used by eSPI for addressing the Flash contents." group.long 0x288++0x3 line.long 0x0 "FC_BUF_ADDR_LSW,Flash Access Channel Buffer Address Register" hexmask.long 0x0 0.--31. 1. "BLSW,Before starting a Flash access this field must be initialized with the address of the data buffer in the EC's memory space." group.long 0x290++0xB line.long 0x0 "FC_XFR_LEN,Flash Access Channel Transfer Length Register" hexmask.long 0x0 0.--31. 1. "TLEN,Before starting a Flash access this field must be initialized with the total number of bytes to be transferred in the requested transaction sequence. If the Master attempts to transfer more bytes than this in Read Completions the transfer is.." line.long 0x4 "FC_CTRL,Flash Access Channel Control Register" bitfld.long 0x4 16. "ABRT,By writing '1' to this bit while Busy==1 the transaction sequence last triggered by the Start bit is terminated and the Busy bit is cleared at the next protocol-compliant opportunity. The clearing of the Busy bit will set the DONE status bit.." "0,1" newline hexmask.long.byte 0x4 4.--7. 1. "TAG,This field should always be written to zero which is the only expected Tag value for Flash Access traffic. It provides the 4-bit TAG value in the eSPI Transaction Header sent by the EC. Completion traffic from the Master is required to match.." newline bitfld.long 0x4 2.--3. "FUNC,This bit selects the requested Flash function as follows: 11=Erase Flash Range=Larger of two ranges if a choice exists 10=Erase Flash Range=Smaller of two ranges if a choice exists 01=Write to Flash 00=Read from Flash." "0: Read from Flash,1: Write to Flash,?,?" newline bitfld.long 0x4 0. "FSTRT,A write of '1' to this bit starts the transmission and sets the Busy status bit. A write of '0' has no effect. The transmission will be inhibited if the OOB channel is not Ready as defined in the eSPI Flash Channel Ready Register." "0,1" line.long 0x8 "FC_IEN,Flash Access Channel Interrupt Enable Register" bitfld.long 0x8 1. "EN_STS_CHNG,When this bit is '1' an interrupt is generated when the bit CHANNEL_ENABLE_CHANGE_STATUS in the Flash Access Channel Status Register is 1. When this bit is '0' the status bit will not generate an interrupt." "0,1" newline bitfld.long 0x8 0. "DONE,When this bit is '1' an interrupt is generated when the bit DONE in the Flash Access Channel Status Register is 1. When this bit is '0' the status bit will not generate an interrupt." "0,1" rgroup.long 0x29C++0x3 line.long 0x0 "FC_CFG,Flash Access Channel Configuration Register" bitfld.long 0x0 12.--14. "MAX_RD_REQ,This comes read-only from the eSPI Configuration register set by the Master to declare the maximum number of bytes that can be requested by the EC in a single Flash Read request packet. 111b = 4K bytes 110b = 2K bytes 101b.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "MAX_PAYLD_SEL,This is a read-only image of the equivalent field of the eSPI Configuration register set by the Master to declare the maximum number of bytes that can be used in a single Flash payload in either direction. It will never be set.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--4. "ERAS_BLK_SIZE,This is a read-only image of the equivalent field of the eSPI Configuration register. This field is set by the Master to define what the Erase block size is for the Flash being used and whether there is a choice available to firmware." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "BUSY,This bit is set to '1' when a '1' is written to the FLASH_START bit and cleared either by hardware completion of the requested operation or by firmware writing '1' to the ABORT_ACCESS bit. 1=The Channel is busy. 0=The Channel is not busy." "0: The Channel is not busy,1: The Channel is busy" group.long 0x2A0++0x3 line.long 0x0 "FC_STS,Flash Access Channel Status Register" bitfld.long 0x0 11. "BAD_REQ,This bit is set to '1' when a firmware Flash Access request is invalid. For example this bit is set for a request to Read or Write 0 bytes. This bit is cleared by writing '1'. (R/WC)" "0,1" newline bitfld.long 0x0 9. "STRT_OVRFLW,This bit is set if a command (initiated by setting the Start bit) has been ignored because the Busy bit was already on. The transfer in progress is also brought to the Done state at the next opportunity allowed by the eSPI protocol as.." "0: No Start Overflow detected,1: Start Overflow" newline bitfld.long 0x0 8. "FAIL,This bit is set to '1' by an explicit UNSUCCESSFUL COMPLETION response from the eSPI Master which also terminates the transaction sequence. This may occur if an invalid or illegal section of Flash memory is accessed and only at Runtime.." "0: The eSPI Master indicated successful completion,1: The eSPI Master indicated unsuccessful completion" newline bitfld.long 0x0 7. "INCMPL,This bit is set to '1' by a SUCCESSFUL COMPLETION Read response from the eSPI Master indicating a Final Completion but with too few bytes provided for the Transaction step that was issued by the eSPI Slave. It is cleared by writing '1'." "0: The eSPI Master finished with at least enough data,1: The eSPI Master finished with too little data" newline bitfld.long 0x0 6. "DAT_OVRUN,This bit is set to '1' by a SUCCESSFUL COMPLETION response by the eSPI Master to a Read sequence but either without indicating Final Completion when the requested byte count is reached or with too many bytes provided while indicating.." "0: The eSPI Master finished without too much data,1: The eSPI Master finished with too much data" newline bitfld.long 0x0 5. "ABORT_SLAVE,This bit is set to '1' if the Abort bit is set to '1' by firmware while the Busy bit is '1' thereby clearing Busy status. It is cleared by writing '1'. (R/WC) 1=The command finished because of the Abort bit. 0=The command finished.." "0: The command finished without an Abort bit..,1: The command finished because of the Abort bit" newline bitfld.long 0x0 4. "INT_BUS_ERR,This bit is set to '1' if the internal bus master associated with the Flash Access Channel encounters a Bus Fault condition. It is cleared by writing '1'. (R/WC) 1=Bus Error detected. 0=The command finished without a Bus Error." "0: The command finished without a Bus Error,1: Bus Error detected" newline bitfld.long 0x0 3. "DIS_MAST,This bit is set to '1' if the Flash Channel is disabled by the Master while the Busy bit is '1'. It is cleared by writing '1'. (R/WC) 1=The command finished because the Enable bit became 0. 0=The command finished without a change in the.." "0: The command finished without a change in the..,1: The command finished because the Enable bit.." newline bitfld.long 0x0 2. "DONE,1=Channel is done=Busy bit has been cleared since this bit was last cleared. It is cleared by writing '1'. (R/WC) 0=Channel is not done=Busy bit has not been cleared since this bit was last cleared." "0: Channel is not done=Busy bit has not been..,1: Channel is done=Busy bit has been cleared since.." newline bitfld.long 0x0 1. "CHN_EN_CHNG,0=Flash Access Enable bit in eSPI Configuration space has not been changed since this bit was last cleared. 1=Flash Access Enable bit in eSPI Configuration space has been changed since this bit was last cleared. The current state of.." "0: Flash Access Enable bit in eSPI Configuration..,1: Flash Access Enable bit in eSPI Configuration.." newline bitfld.long 0x0 0. "CHN_EN,This bit is a Read-only image of the bit Flash Access Channel Enable in the eSPI Configuration space. Rising or falling edges of this bit will set the CHANNEL_ENABLE_CHANGE_STATUS bit to 1 and may be used to trigger interrupts. A falling.." "0: Flash Access Channel Enable bit = 0,1: Flash Access Channel Enable bit = 1" rgroup.byte 0x2B0++0x0 line.byte 0x0 "VW_EN_STS,Virtual Wire Status Register" bitfld.byte 0x0 0. "CHN_EN_STS,This bit is a Read-only image of the bit Virtual Wire Channel Enable in the eSPI Configuration space. 1=Virtual Wire Channel Enable bit = 1; 0=Virtual Wire Channel Enable bit = 0." "0: Virtual Wire Channel Enable bit = 0,1: Virtual Wire Channel Enable bit = 1" group.byte 0x2E0++0xD line.byte 0x0 "CAP_ID,eSPI Capabilities ID Register" hexmask.byte 0x0 0.--7. 1. "ESP_DEVID,The default value should not be changed." line.byte 0x1 "GLB_CAP0,eSPI Capabilities Global Capabilities 0 Register" bitfld.byte 0x1 3. "FC_CHN,1=Flash Access Channel is supported by the slave; 0=Flash Access Channel not supported by the slave." "0: Flash Access Channel not supported by the slave,1: Flash Access Channel is supported by the slave" newline bitfld.byte 0x1 2. "OOB_MSG_CHN,1=OOB Message Channel is supported by the slave; 0=OOB Message Channel not supported by the slave." "0: OOB Message Channel not supported by the slave,1: OOB Message Channel is supported by the slave" newline bitfld.byte 0x1 1. "VW_CHN,1=Virtual Wire Channel is supported by the slave; 0=Virtual Wire Channel Channel not supported by the slave." "0: Virtual Wire Channel Channel not supported by..,1: Virtual Wire Channel is supported by the slave" newline bitfld.byte 0x1 0. "PHL_CHN,1=Peripheral Channel is supported by the slave; 0=Peripheral Channel not supported by the slave." "0: Peripheral Channel not supported by the slave,1: Peripheral Channel is supported by the slave" line.byte 0x2 "GLB_CAP1,eSPI Capabilities Global Capabilities 1 Register" bitfld.byte 0x2 4.--5. "IO_MODE,This field identifies the I/O modes supported by the slave. It corresponds to the field I/O Mode Support bits [25:24] of the eSPI General Capabilities and Configurations register. 11b=Single Dual and Quad I/O 10b=Single and Quad.." "0,1,2,3" newline bitfld.byte 0x2 3. "ALERT,This field is a read-only copy of the ALERT Mode field bit 28 of the Config Offset 8h=General Capabilities and Configurations Register." "0,1" newline bitfld.byte 0x2 0.--2. "MAX_FREQ,This field identifies the maximum frequency of operation supported by the slave. It corresponds to the field Maximum Frequency Supported bits [18:16] of the eSPI General Capabilities and Configurations register. 111b - 101b=Reserved.." "0,1,2,3,4,5,6,7" line.byte 0x3 "PC_CAP,eSPI Peripheral Channel Capabilities Register" bitfld.byte 0x3 0.--2. "MAX_PAYLD_SIZE,This field identifies the maximum payload size supported by the slave. It corresponds to the field Peripheral Channel Maximum Payload Size Supported bits [6:4] of the Peripheral Channel Capabilities and Configurations Register." "0,1,2,3,4,5,6,7" line.byte 0x4 "VW_CAP,eSPI Virtual Wire Channel Capabilities Register" hexmask.byte 0x4 0.--5. 1. "MAX_CNT,This field identifies the maximum Virtual Wire Count supported by the slave. It corresponds to the field Maximum Virtual Wire Count Supported bits [13:8] of the Virtual Wire Channel Capabilities and Configurations Register. This field.." line.byte 0x5 "OOB_CAP,eSPI OOB Channel Capabilities Register" bitfld.byte 0x5 0.--2. "MAX_PAYLD_SIZ,This field identifies the maximum payload size supported by the slave. It corresponds to the field OOB Message Channel Maximum Payload Size Supported bits [6:4] of the OOB Channel Capabilities and Configurations Register. 111b -.." "0,1,2,3,4,5,6,7" line.byte 0x6 "FC_CAP,eSPI Flash Channel Capabilities Register" bitfld.byte 0x6 4. "SHAR_MODE,This field identifies the flash sharing scheme supported by the slave. It corresponds to the field Flash Sharing Mode bit [11] of the Flash Channel Capabilities and Configurations Register. 1=Slave attached flash sharing.." "0: Master attached flash sharing,1: Slave attached flash sharing" newline bitfld.byte 0x6 0.--2. "MAX_PAY_LD,This field identifies the maximum payload size supported by the slave. It corresponds to the field Flash Access Channel Maximum Payload Size Supported bits [7:0] of the Flash Channel Capabilities and Configurations Register. 111b -.." "0,1,2,3,4,5,6,7" line.byte 0x7 "PC_READY,eSPI Peripheral Channel Ready Register" bitfld.byte 0x7 0. "PHL_CHN_RDY,Firmware sets this bit to '1' to inform the Master than the Peripheral channel is ready for transactions. It corresponds to the field Peripheral Channel Ready bit 1 of the Config Offset 10h=Peripheral Channel Capabilities and.." "0,1" line.byte 0x8 "OOB_READY,eSPI OOB Channel Ready Register" bitfld.byte 0x8 0. "CHN,Firmware sets this bit to '1' to inform the Master that the OOB channel is ready for transactions. It corresponds to the field OOB Message Channel Ready bit 1 of Config Offset 30h=OOB ChannelCapabilities and Configurations Register. It is.." "0,1" line.byte 0x9 "FC_READY,eSPI Flash Channel Ready Register" bitfld.byte 0x9 0. "CHN,Firmware sets this bit to '1' to inform the Master that the Flash channel is ready for transactions. It corresponds to the field Flash Channel Ready bit 1 of Config Offset 40h=Flash Channel Capabilities and Configurations Register. It is.." "0,1" line.byte 0xA "RESET_STS,eSPI Reset Interrupt Status Register" bitfld.byte 0xA 1. "ESPI_RST_PIN_STATE,This field reflects the current state of the eSPI_RESET# pin." "0,1" newline bitfld.byte 0xA 0. "ESP_INTR,This bit is set to '1' whenever the ESPI_RESET_PIN_STATE bit in this register changes state. It is cleared to '0' whenever it is written with a '1'. Writes of a '0' have no effect. (R/WC) This bit is the source for the eSPI_RESET Interrupt." "0,1" line.byte 0xB "RESET_IEN,eSPI Reset Interrupt Enable Register" bitfld.byte 0xB 0. "ESP_RIEN,1=The RESET_ESPI Interrupt will be asserted when the ESPI_RESET_INTERRUPT_STATUS bit in the eSPI Reset Interrupt Status Register register is '1' 0=The RESET_ESPI Interrupt will not be asserted." "0: The RESET_ESPI Interrupt will not be asserted,1: The RESET_ESPI Interrupt will be asserted when.." line.byte 0xC "PLTRST_SRC,PLTRST Source Register" bitfld.byte 0xC 0. "SRC,1=The PLTRST reset signal is determined a signal external to the eSPI block. The PLTRST# virtual wire is ignored 0=The PLTRST reset signal is determined by the PLTRST# virtual wire." "0: The PLTRST reset signal is determined by the..,1: The PLTRST reset signal is determined a signal.." line.byte 0xD "VW_READY,eSPI Virtual Wire Channel Ready Register" bitfld.byte 0xD 0. "CHN,Firmware sets this bit to '1' to inform the Master than the Virtual Wire channel is ready for transactions. It corresponds to the field Virtual Wire Channel Ready bit 1 of the Config Offset 20h=Channel 1 Capabilities and Configurations.." "0,1" group.long 0x300++0x7 line.long 0x0 "RPMC_OP_DISP_RW,RPMC OP1 Opcode Display Configuration Register" hexmask.long.byte 0x0 4.--9. 1. "TOTAL,RPMC Total" newline bitfld.long 0x0 3. "CS1_DISP848,RPMC CS1 display 848 Sel" "0,1" newline bitfld.long 0x0 2. "CS1_DISP048,RPMC CS1 display 048 Sel" "0,1" newline bitfld.long 0x0 1. "CS0_DISP848,RPMC CS0 display 848 Sel" "0,1" newline bitfld.long 0x0 0. "CS0_DISP048,RPMC CS0 display 048 Sel" "0,1" line.long 0x4 "RPMC_NUM_DISP_RW,RPMC OP1 Opcode Num Counter Register" hexmask.long.byte 0x4 24.--28. 1. "CS1_CNT,RPMC CS1 Count" newline hexmask.long.byte 0x4 16.--23. 1. "CS1_OP1,RPMC CS1 OP1" newline hexmask.long.byte 0x4 8.--12. 1. "CS0_CNT,RPMC CS0 Count" newline hexmask.long.byte 0x4 0.--7. 1. "CS0_OP1,RPMC CS0 OP1" group.byte 0x330++0x0 line.byte 0x0 "ACTIVATE,eSPI Activate Register" bitfld.byte 0x0 0. "ACT,1=Activate. When this bit is '1' the eSPI Logical Device is powered and functional. 0=Deactivate. When this bit is 0 the logical device is powered down and inactive. Except for the eSPI Activate Register itself clocks to the block are.." "0: Deactivate,1: Activate" group.long 0x334++0x4B line.long 0x0 "ADDR,eSPI I/O Base Address Configuration Register" hexmask.long.word 0x0 16.--31. 1. "ESP_H_ADDR,These 16 bits are used to match eSPI I/O addresses." newline bitfld.long 0x0 0. "VALID,1=The BAR is valid and will participate in eSPI matches. 0=The BAR is ignored." "0: The BAR is ignored,1: The BAR is valid and will participate in eSPI.." line.long 0x4 "ESPI_MEM_ADDR,eSPI Memory Base Address Configuration Register" hexmask.long.word 0x4 16.--31. 1. "ESP_H_ADDR,These 16 bits are used to match eSPI I/O addresses." newline bitfld.long 0x4 0. "VALID,1=The BAR is valid and will participate in eSPI matches. 0=The BAR is ignored." "0: The BAR is ignored,1: The BAR is valid and will participate in eSPI.." line.long 0x8 "MBX_ADDR,Mailbox Base Address Configuration Register" hexmask.long.word 0x8 16.--31. 1. "ESP_H_ADDR,These 16 bits are used to match eSPI I/O addresses." newline bitfld.long 0x8 0. "VALID,1=The BAR is valid and will participate in eSPI matches. 0=The BAR is ignored." "0: The BAR is ignored,1: The BAR is valid and will participate in eSPI.." line.long 0xC "EM8042_ADDR,8042 Emulated Keyboard Controller Base Address Configuration Register" hexmask.long.word 0xC 16.--31. 1. "ESP_H_ADDR,These 16 bits are used to match eSPI I/O addresses." newline bitfld.long 0xC 0. "VALID,1=The BAR is valid and will participate in eSPI matches. 0=The BAR is ignored." "0: The BAR is ignored,1: The BAR is valid and will participate in eSPI.." line.long 0x10 "ACPI_EC0_ADDR,ACPI EC 0 Base Address Configuration Register" hexmask.long.word 0x10 16.--31. 1. "ESP_H_ADDR,These 16 bits are used to match eSPI I/O addresses." newline bitfld.long 0x10 0. "VALID,1=The BAR is valid and will participate in eSPI matches. 0=The BAR is ignored." "0: The BAR is ignored,1: The BAR is valid and will participate in eSPI.." line.long 0x14 "ACPI_EC1_ADDR,ACPI EC 1 Base Address Configuration Register" hexmask.long.word 0x14 16.--31. 1. "ESP_H_ADDR,These 16 bits are used to match eSPI I/O addresses." newline bitfld.long 0x14 0. "VALID,1=The BAR is valid and will participate in eSPI matches. 0=The BAR is ignored." "0: The BAR is ignored,1: The BAR is valid and will participate in eSPI.." line.long 0x18 "ACPI_EC2_ADDR,ACPI EC 2 Base Address Configuration Register" hexmask.long.word 0x18 16.--31. 1. "ESP_H_ADDR,These 16 bits are used to match eSPI I/O addresses." newline bitfld.long 0x18 0. "VALID,1=The BAR is valid and will participate in eSPI matches. 0=The BAR is ignored." "0: The BAR is ignored,1: The BAR is valid and will participate in eSPI.." line.long 0x1C "ACPI_EC3_ADDR,ACPI EC 3 Base Address Configuration Register" hexmask.long.word 0x1C 16.--31. 1. "ESP_H_ADDR,These 16 bits are used to match eSPI I/O addresses." newline bitfld.long 0x1C 0. "VALID,1=The BAR is valid and will participate in eSPI matches. 0=The BAR is ignored." "0: The BAR is ignored,1: The BAR is valid and will participate in eSPI.." line.long 0x20 "ACPI_EC4_ADDR,ACPI EC 4 Base Address Configuration Register" hexmask.long.word 0x20 16.--31. 1. "ESP_H_ADDR,These 16 bits are used to match eSPI I/O addresses." newline bitfld.long 0x20 0. "VALID,1=The BAR is valid and will participate in eSPI matches. 0=The BAR is ignored." "0: The BAR is ignored,1: The BAR is valid and will participate in eSPI.." line.long 0x24 "ACPI_PM1_ADDR,ACPI PM1 Base Address Configuration Register" hexmask.long.word 0x24 16.--31. 1. "ESP_H_ADDR,These 16 bits are used to match eSPI I/O addresses." newline bitfld.long 0x24 0. "VALID,1=The BAR is valid and will participate in eSPI matches. 0=The BAR is ignored." "0: The BAR is ignored,1: The BAR is valid and will participate in eSPI.." line.long 0x28 "FAST_KBD_ADDR,I/O Base Address Configuration Register" hexmask.long.word 0x28 16.--31. 1. "ESP_H_ADDR,These 16 bits are used to match eSPI I/O addresses." newline bitfld.long 0x28 0. "VALID,1=The BAR is valid and will participate in eSPI matches. 0=The BAR is ignored." "0: The BAR is ignored,1: The BAR is valid and will participate in eSPI.." line.long 0x2C "UART0_ADDR,UART 0 Base Address Configuration Register" hexmask.long.word 0x2C 16.--31. 1. "ESP_H_ADDR,These 16 bits are used to match eSPI I/O addresses." newline bitfld.long 0x2C 0. "VALID,1=The BAR is valid and will participate in eSPI matches. 0=The BAR is ignored." "0: The BAR is ignored,1: The BAR is valid and will participate in eSPI.." line.long 0x30 "UART1_ADDR,UART 1 Base Address Configuration Register" hexmask.long.word 0x30 16.--31. 1. "UART1_ADDR,These 16 bits are used to match eSPI I/O addresses." newline bitfld.long 0x30 0. "VALID,1=The BAR is valid and will participate in eSPI matches. 0=The BAR is ignored." "0: The BAR is ignored,1: The BAR is valid and will participate in eSPI.." line.long 0x34 "EMI0_ADDR,Embedded Memory Interface (EMI) 0 BAR Config Register" hexmask.long.word 0x34 16.--31. 1. "ESP_H_ADDR,These 16 bits are used to match eSPI I/O addresses." newline bitfld.long 0x34 0. "VALID,1=The BAR is valid and will participate in eSPI matches. 0=The BAR is ignored." "0: The BAR is ignored,1: The BAR is valid and will participate in eSPI.." line.long 0x38 "EMI1_ADDR,Embedded Memory Interface (EMI) 1 BAR Config Register" hexmask.long.word 0x38 16.--31. 1. "ESP_H_ADDR,These 16 bits are used to match eSPI I/O addresses." newline bitfld.long 0x38 0. "VALID,1=The BAR is valid and will participate in eSPI matches. 0=The BAR is ignored." "0: The BAR is ignored,1: The BAR is valid and will participate in eSPI.." line.long 0x3C "EMI2_ADDR,Embedded Memory Interface (EMI) 2 BAR Config Register" hexmask.long.word 0x3C 16.--31. 1. "ESP_H_ADDR,These 16 bits are used to match eSPI I/O addresses." newline bitfld.long 0x3C 0. "VALID,1=The BAR is valid and will participate in eSPI matches. 0=The BAR is ignored." "0: The BAR is ignored,1: The BAR is valid and will participate in eSPI.." line.long 0x40 "PORT80_0_ADDR,BIOS Debug Port (Port 80) 0 BAR Config Register" hexmask.long.word 0x40 16.--31. 1. "ESP_H_ADDR,These 16 bits are used to match eSPI I/O addresses." newline bitfld.long 0x40 0. "VALID,1=The BAR is valid and will participate in eSPI matches. 0=The BAR is ignored." "0: The BAR is ignored,1: The BAR is valid and will participate in eSPI.." line.long 0x44 "PORT80_1_ADDR,BIOS Debug Port (Port 80) 1 BAR Config Register" hexmask.long.word 0x44 16.--31. 1. "ESP_H_ADDR,These 16 bits are used to match eSPI I/O addresses." newline bitfld.long 0x44 0. "VALID,1=The BAR is valid and will participate in eSPI matches. 0=The BAR is ignored." "0: The BAR is ignored,1: The BAR is valid and will participate in eSPI.." line.long 0x48 "RTC_ADDR,RTC BAR Config Register" hexmask.long.word 0x48 16.--31. 1. "ESPI_HOST_ADDRESS,These 16 bits are used to match eSPI I/O addresses." newline bitfld.long 0x48 0. "VALID,1=The BAR is valid and will participate in eSPI matches. 0=The BAR is ignored." "0: The BAR is ignored,1: The BAR is valid and will participate in eSPI.." group.long 0x38C++0x3 line.long 0x0 "GLUE_ADDR,GLUE Base Address Configuration Register" hexmask.long.word 0x0 16.--31. 1. "ESPI_HOST_ADDRESS,These 16 bits are used to match eSPI I/O addresses." newline bitfld.long 0x0 0. "VALID,1=The BAR is valid and will participate in eSPI matches. 0=The BAR is ignored." "0: The BAR is ignored,1: The BAR is valid and will participate in eSPI.." group.byte 0x3AC++0x12 line.byte 0x0 "MBX_HOST_SIRQ_IRQ,Mailbox (MBX_Host_SIRQ Interrupt) Selection Register" hexmask.byte 0x0 0.--7. 1. "IRQ,FFh= IRQ generation from this device is disabled. FEh-0=Changes in the value of the signal associated with this register are sent as a Virtual Wire transaction to the Master. The Virtual Wire index is 0 for IRQ values 7Fh to 0h and the.." line.byte 0x1 "MBX_HOST_SMI_IRQ,Mailbox (MBX_Host_SMI Interrupt) Selection Register" hexmask.byte 0x1 0.--7. 1. "IRQ,FFh= IRQ generation from this device is disabled. FEh-0=Changes in the value of the signal associated with this register are sent as a Virtual Wire transaction to the Master. The Virtual Wire index is 0 for IRQ values 7Fh to 0h and the.." line.byte 0x2 "KIRQ_8042_IRQ,8042 (KIRQ Interrupt) Selection Register" hexmask.byte 0x2 0.--7. 1. "IRQ,FFh= IRQ generation from this device is disabled. FEh-0=Changes in the value of the signal associated with this register are sent as a Virtual Wire transaction to the Master. The Virtual Wire index is 0 for IRQ values 7Fh to 0h and the.." line.byte 0x3 "MIRQ_8042_IRQ,8042 (MIRQ Interrupt) Selection Register" hexmask.byte 0x3 0.--7. 1. "IRQ,FFh= IRQ generation from this device is disabled. FEh-0=Changes in the value of the signal associated with this register are sent as a Virtual Wire transaction to the Master. The Virtual Wire index is 0 for IRQ values 7Fh to 0h and the.." line.byte 0x4 "ACPI_EC0_OBF_IRQ,ACPI EC 0 (EC_OBF Interrupt) Selection Register" hexmask.byte 0x4 0.--7. 1. "IRQ,FFh= IRQ generation from this device is disabled. FEh-0=Changes in the value of the signal associated with this register are sent as a Virtual Wire transaction to the Master. The Virtual Wire index is 0 for IRQ values 7Fh to 0h and the.." line.byte 0x5 "ACPI_EC1_OBF_IRQ,ACPI EC 1 (EC_OBF Interrupt) Selection Register" hexmask.byte 0x5 0.--7. 1. "IRQ,FFh= IRQ generation from this device is disabled. FEh-0=Changes in the value of the signal associated with this register are sent as a Virtual Wire transaction to the Master. The Virtual Wire index is 0 for IRQ values 7Fh to 0h and the.." line.byte 0x6 "ACPI_EC2_OBF_IRQ,ACPI EC 2 (EC_OBF Interrupt) Selection Register" hexmask.byte 0x6 0.--7. 1. "IRQ,FFh= IRQ generation from this device is disabled. FEh-0=Changes in the value of the signal associated with this register are sent as a Virtual Wire transaction to the Master. The Virtual Wire index is 0 for IRQ values 7Fh to 0h and the.." line.byte 0x7 "ACPI_EC3_OBF_IRQ,ACPI EC 3 (EC_OBF Interrupt) Selection Register" hexmask.byte 0x7 0.--7. 1. "IRQ,FFh= IRQ generation from this device is disabled. FEh-0=Changes in the value of the signal associated with this register are sent as a Virtual Wire transaction to the Master. The Virtual Wire index is 0 for IRQ values 7Fh to 0h and the.." line.byte 0x8 "ACPI_EC4_OBF_IRQ,ACPI EC 4 (EC_OBF Interrupt) Selection Register" hexmask.byte 0x8 0.--7. 1. "IRQ,FFh= IRQ generation from this device is disabled. FEh-0=Changes in the value of the signal associated with this register are sent as a Virtual Wire transaction to the Master. The Virtual Wire index is 0 for IRQ values 7Fh to 0h and the.." line.byte 0x9 "UART0_IRQ,UART 0 (UART Interrupt) Selection Register" hexmask.byte 0x9 0.--7. 1. "IRQ,FFh= IRQ generation from this device is disabled. FEh-0=Changes in the value of the signal associated with this register are sent as a Virtual Wire transaction to the Master. The Virtual Wire index is 0 for IRQ values 7Fh to 0h and the.." line.byte 0xA "UART1_IRQ,UART 1 (UART Interrupt) Selection Register" hexmask.byte 0xA 0.--7. 1. "IRQ,FFh= IRQ generation from this device is disabled. FEh-0=Changes in the value of the signal associated with this register are sent as a Virtual Wire transaction to the Master. The Virtual Wire index is 0 for IRQ values 7Fh to 0h and the.." line.byte 0xB "EMI0_HOST_IRQ,EMI 0 (Host Event Interrupt) Selection Register" hexmask.byte 0xB 0.--7. 1. "IRQ,FFh= IRQ generation from this device is disabled. FEh-0=Changes in the value of the signal associated with this register are sent as a Virtual Wire transaction to the Master. The Virtual Wire index is 0 for IRQ values 7Fh to 0h and the.." line.byte 0xC "EMI0_EC_HOST_IRQ,EMI 0 (EC-to-Host Interrupt) Selection Register" hexmask.byte 0xC 0.--7. 1. "IRQ,FFh= IRQ generation from this device is disabled. FEh-0=Changes in the value of the signal associated with this register are sent as a Virtual Wire transaction to the Master. The Virtual Wire index is 0 for IRQ values 7Fh to 0h and the.." line.byte 0xD "EMI1_HOST_IRQ,EMI 1 (Host Event Interrupt) Selection Register" hexmask.byte 0xD 0.--7. 1. "IRQ,FFh= IRQ generation from this device is disabled. FEh-0=Changes in the value of the signal associated with this register are sent as a Virtual Wire transaction to the Master. The Virtual Wire index is 0 for IRQ values 7Fh to 0h and the.." line.byte 0xE "EMI1_EC_HOST_IRQ,EMI 1 (EC-to-Host Interrupt) Selection Register" hexmask.byte 0xE 0.--7. 1. "IRQ,FFh= IRQ generation from this device is disabled. FEh-0=Changes in the value of the signal associated with this register are sent as a Virtual Wire transaction to the Master. The Virtual Wire index is 0 for IRQ values 7Fh to 0h and the.." line.byte 0xF "EMI2_HOST_IRQ,EMI 2 (Host Event Interrupt) Selection Register" hexmask.byte 0xF 0.--7. 1. "IRQ,FFh= IRQ generation from this device is disabled. FEh-0=Changes in the value of the signal associated with this register are sent as a Virtual Wire transaction to the Master. The Virtual Wire index is 0 for IRQ values 7Fh to 0h and the.." line.byte 0x10 "EMI2_EC_HOST_IRQ,EMI 2 (EC-to-Host Interrupt) Selection Register" hexmask.byte 0x10 0.--7. 1. "IRQ,FFh= IRQ generation from this device is disabled. FEh-0=Changes in the value of the signal associated with this register are sent as a Virtual Wire transaction to the Master. The Virtual Wire index is 0 for IRQ values 7Fh to 0h and the.." line.byte 0x11 "RTC_IRQ,RTC (RTC Interrupt) Selection Register" hexmask.byte 0x11 0.--7. 1. "IRQ,FFh= IRQ generation from this device is disabled. FEh-0=Changes in the value of the signal associated with this register are sent as a Virtual Wire transaction to the Master. The Virtual Wire index is 0 for IRQ values 7Fh to 0h and the.." line.byte 0x12 "EC_IRQ,EC (EC_IRQ Interrupt) Selection Register" hexmask.byte 0x12 0.--7. 1. "IRQ,FFh= IRQ generation from this device is disabled. FEh-0=Changes in the value of the signal associated with this register are sent as a Virtual Wire transaction to the Master. The Virtual Wire index is 0 for IRQ values 7Fh to 0h and the.." rgroup.long 0x3E4++0x3 line.long 0x0 "RPMC_NUM_DISP_R,RPMC OP1 Opcode Num Counter Register" hexmask.long.byte 0x0 24.--28. 1. "CS1_CNT,RPMC CS1 Count" newline hexmask.long.byte 0x0 16.--23. 1. "CS1_OP1,RPMC CS1 OP1" newline hexmask.long.byte 0x0 8.--12. 1. "CS0_CNT,RPMC CS0 Count" newline hexmask.long.byte 0x0 0.--7. 1. "CS0_OP1,RPMC CS0 OP1" group.byte 0x3F0++0x0 line.byte 0x0 "ESPI_VW_ERR,eSPI Virtual Wire Errors Register" bitfld.byte 0x0 5. "CLR_NFTL_STS,When this field is written with a 1 the Virtual Wire ERROR_NON_- FATAL (bit 2 in Slave-to-Master Virtual Wire Index 5h) is cleared to 0. Because clearing the status bit changes its state a Virtual Wire packet reporting the new state.." "0,1" newline bitfld.byte 0x0 4. "NFTL_STS,This bit is a Master-readable copy of the Virtual Wire ERROR_NON_FATAL (bit 2 in Slave-to-Master Virtual Wire Index 5h)." "0,1" newline bitfld.byte 0x0 1. "CLR_FTL_STATUS,When this field is written with a 1 the Virtual Wire ERROR_FATAL (bit 1 in Slave-to-Master Virtual Wire Index 5h) is cleared to 0. Because clearing the status bit changes its state a Virtual Wire packet reporting the new state will.." "0,1" newline bitfld.byte 0x0 0. "FTL_STS,This bit is a Master-readable copy of the Virtual Wire ERROR_FATAL (bit 1 in Slave-to-Master Virtual Wire Index 5h)." "0,1" tree.end tree "ESPI_MEMORY" base ad:0x400F3800 group.long 0x130++0x3 line.long 0x0 "BAR_LDI_MBX_H0,Mailbox Memory Base Address" bitfld.long 0x0 16. "VIR,1=Peripheral Channel I/O for this device is virtualized and reads and writes are handled in firmware 0=All Peripheral Channel I/O Reads and Writes for this device are completed by hardware." "0: All Peripheral Channel I/O Reads and Writes for..,1: Peripheral Channel I/O for this device is.." newline hexmask.long.byte 0x0 8.--13. 1. "LDN,These 6 bits are used to specify a logical device number within a bus. This field is multiplied by 400h to provide the address within the peripheral bus address. Logical Device Numbers that do not corresponding to logical devices that are.." newline hexmask.long.byte 0x0 0.--7. 1. "MASK,These 8 bits are used to mask off address bits in the address match between an eSPI I/O address and the Host Address field of the BARs. A block of up to 256 8-bit registers can be assigned to one base address." group.word 0x13A++0x3 line.word 0x0 "BAR_LDI_ACPI_EC0_H0,ACPI EC Channel 0 Memory BAR (LSB)" hexmask.word.byte 0x0 8.--13. 1. "LDN,These 6 bits are used to specify a logical device number within a bus. This field is multiplied by 400h to provide the address within the peripheral bus address. Logical Device Numbers that do not corresponding to logical devices that are.." newline hexmask.word.byte 0x0 0.--7. 1. "MASK,These 8 bits are used to mask off address bits in the address match between an eSPI I/O address and the Host Address field of the BARs. A block of up to 256 8-bit registers can be assigned to one base address." line.word 0x2 "BAR_LDI_ACPI_EC0_H1,ACPI EC Channel 0 Memory BAR (MSB)" bitfld.word 0x2 0. "VIR,1=Peripheral Channel I/O for this device is virtualized and reads and writes are handled in firmware 0=All Peripheral Channel I/O Reads and Writes for this device are completed by hardware." "0: All Peripheral Channel I/O Reads and Writes for..,1: Peripheral Channel I/O for this device is.." group.long 0x144++0x3 line.long 0x0 "BAR_LDI_ACPI_EC1_H0,ACPI EC Channel 1 Memory BAR" bitfld.long 0x0 16. "VIR,1=Peripheral Channel I/O for this device is virtualized and reads and writes are handled in firmware 0=All Peripheral Channel I/O Reads and Writes for this device are completed by hardware." "0: All Peripheral Channel I/O Reads and Writes for..,1: Peripheral Channel I/O for this device is.." newline hexmask.long.byte 0x0 8.--13. 1. "LDN,These 6 bits are used to specify a logical device number within a bus. This field is multiplied by 400h to provide the address within the peripheral bus address. Logical Device Numbers that do not corresponding to logical devices that are.." newline hexmask.long.byte 0x0 0.--7. 1. "MASK,These 8 bits are used to mask off address bits in the address match between an eSPI I/O address and the Host Address field of the BARs. A block of up to 256 8-bit registers can be assigned to one base address." group.word 0x14E++0x3 line.word 0x0 "BAR_LDI_ACPI_EC2_H0,ACPI EC Channel 2 Memory BAR (LSB)" hexmask.word.byte 0x0 8.--13. 1. "LDN,These 6 bits are used to specify a logical device number within a bus. This field is multiplied by 400h to provide the address within the peripheral bus address. Logical Device Numbers that do not corresponding to logical devices that are.." newline hexmask.word.byte 0x0 0.--7. 1. "MASK,These 8 bits are used to mask off address bits in the address match between an eSPI I/O address and the Host Address field of the BARs. A block of up to 256 8-bit registers can be assigned to one base address." line.word 0x2 "BAR_LDI_ACPI_EC2_H1,ACPI EC Channel 2 Memory BAR (MSB)" bitfld.word 0x2 0. "VIR,1=Peripheral Channel I/O for this device is virtualized and reads and writes are handled in firmware 0=All Peripheral Channel I/O Reads and Writes for this device are completed by hardware." "0: All Peripheral Channel I/O Reads and Writes for..,1: Peripheral Channel I/O for this device is.." group.long 0x158++0x7 line.long 0x0 "BAR_LDI_ACPI_EC3_H0,ACPI EC Channel 3 Memory BAR" bitfld.long 0x0 16. "VIR,1=Peripheral Channel I/O for this device is virtualized and reads and writes are handled in firmware 0=All Peripheral Channel I/O Reads and Writes for this device are completed by hardware." "0: All Peripheral Channel I/O Reads and Writes for..,1: Peripheral Channel I/O for this device is.." newline hexmask.long.byte 0x0 8.--13. 1. "LDN,These 6 bits are used to specify a logical device number within a bus. This field is multiplied by 400h to provide the address within the peripheral bus address. Logical Device Numbers that do not corresponding to logical devices that are.." newline hexmask.long.byte 0x0 0.--7. 1. "MASK,These 8 bits are used to mask off address bits in the address match between an eSPI I/O address and the Host Address field of the BARs. A block of up to 256 8-bit registers can be assigned to one base address." line.long 0x4 "BAR_LDI_ACPI_EC4_H0,ACPI EC Channel 4 Memory BAR" bitfld.long 0x4 16. "VIR,1=Peripheral Channel I/O for this device is virtualized and reads and writes are handled in firmware 0=All Peripheral Channel I/O Reads and Writes for this device are completed by hardware." "0: All Peripheral Channel I/O Reads and Writes for..,1: Peripheral Channel I/O for this device is.." newline hexmask.long.byte 0x4 8.--13. 1. "LDN,These 6 bits are used to specify a logical device number within a bus. This field is multiplied by 400h to provide the address within the peripheral bus address. Logical Device Numbers that do not corresponding to logical devices that are.." newline hexmask.long.byte 0x4 0.--7. 1. "MASK,These 8 bits are used to mask off address bits in the address match between an eSPI I/O address and the Host Address field of the BARs. A block of up to 256 8-bit registers can be assigned to one base address." group.word 0x160++0x1 line.word 0x0 "BAR_LDI_ACPI_EC4_H1,ACPI EC Channel 4 Memory BAR (MSB)" bitfld.word 0x0 0. "VIR,1=Peripheral Channel I/O for this device is virtualized and reads and writes are handled in firmware 0=All Peripheral Channel I/O Reads and Writes for this device are completed by hardware." "0: All Peripheral Channel I/O Reads and Writes for..,1: Peripheral Channel I/O for this device is.." group.long 0x16C++0x3 line.long 0x0 "BAR_LDI_EM0_H0,Embedded Memory Interface (EMI) 0 Memory Base Address" bitfld.long 0x0 16. "VIR,1=Peripheral Channel I/O for this device is virtualized and reads and writes are handled in firmware 0=All Peripheral Channel I/O Reads and Writes for this device are completed by hardware." "0: All Peripheral Channel I/O Reads and Writes for..,1: Peripheral Channel I/O for this device is.." newline hexmask.long.byte 0x0 8.--13. 1. "LDN,These 6 bits are used to specify a logical device number within a bus. This field is multiplied by 400h to provide the address within the peripheral bus address. Logical Device Numbers that do not corresponding to logical devices that are.." newline hexmask.long.byte 0x0 0.--7. 1. "MASK,These 8 bits are used to mask off address bits in the address match between an eSPI I/O address and the Host Address field of the BARs. A block of up to 256 8-bit registers can be assigned to one base address." group.word 0x176++0x3 line.word 0x0 "BAR_LDI_EM1_H0,Embedded Memory Interface (EMI) 1 Memory Base Address (LSB)" hexmask.word.byte 0x0 8.--13. 1. "LDN,These 6 bits are used to specify a logical device number within a bus. This field is multiplied by 400h to provide the address within the peripheral bus address. Logical Device Numbers that do not corresponding to logical devices that are.." newline hexmask.word.byte 0x0 0.--7. 1. "MASK,These 8 bits are used to mask off address bits in the address match between an eSPI I/O address and the Host Address field of the BARs. A block of up to 256 8-bit registers can be assigned to one base address." line.word 0x2 "BAR_LDI_EM1_H1,Embedded Memory Interface (EMI) 1 Memory Base Address (MSB)" bitfld.word 0x2 0. "VIR,1=Peripheral Channel I/O for this device is virtualized and reads and writes are handled in firmware 0=All Peripheral Channel I/O Reads and Writes for this device are completed by hardware." "0: All Peripheral Channel I/O Reads and Writes for..,1: Peripheral Channel I/O for this device is.." group.long 0x180++0x3 line.long 0x0 "BAR_LDI_EM2_H0,Embedded Memory Interface (EMI) 2 Memory Base Address" bitfld.long 0x0 16. "VIR,1=Peripheral Channel I/O for this device is virtualized and reads and writes are handled in firmware 0=All Peripheral Channel I/O Reads and Writes for this device are completed by hardware." "0: All Peripheral Channel I/O Reads and Writes for..,1: Peripheral Channel I/O for this device is.." newline hexmask.long.byte 0x0 8.--13. 1. "LDN,These 6 bits are used to specify a logical device number within a bus. This field is multiplied by 400h to provide the address within the peripheral bus address. Logical Device Numbers that do not corresponding to logical devices that are.." newline hexmask.long.byte 0x0 0.--7. 1. "MASK,These 8 bits are used to mask off address bits in the address match between an eSPI I/O address and the Host Address field of the BARs. A block of up to 256 8-bit registers can be assigned to one base address." group.word 0x1AC++0x3 line.word 0x0 "BAR_SRAM0_H0,SRAM 0 Memory Base Address Config" hexmask.word.byte 0x0 4.--7. 1. "SIZE,This field defines the size of the region mapped from Host Memory address space into the internal address space in powers of 2. 15=The region is 64KB in extent 14=The region is 32KB in extent ... 1=The region is 2B in extent.." newline bitfld.word 0x0 1.--2. "ACCESS,These 2 bits define the access type of access to this SRAM region. 3=Host has Read/write access to the region 2=Host has Write-only access to the region 1=Host has Read-only access to the region 0=Host has no access to this.." "0: Host has no access to this region,1: Host has Read-only access to the region,2: Host has Write-only access to the region,3: Host has Read/write access to the region" newline bitfld.word 0x0 0. "VALID,1=The BAR is valid and will participate in eSPI matches. 0=The BAR is ignored." "0: The BAR is ignored,1: The BAR is valid and will participate in eSPI.." line.word 0x2 "BAR_SRAM0_H1,SRAM 0 Memory Base Address LSB" hexmask.word 0x2 0.--15. 1. "ADDR,This is the LSB of the 32-bit field that defines the base address of the internal memory region to which Host accesses to the region starting at RAM eSPI Host Address are mapped. The least significant 2**RAM SIZE bits are ignored." group.long 0x1B0++0x3 line.long 0x0 "BAR_SRAM0_H2,SRAM 0 Memory Base Address MSB" hexmask.long.word 0x0 0.--15. 1. "ADDR,This is the MSB of the 32-bit field that defines the base address of the internal memory region to which Host accesses to the region starting at RAM eSPI Host Address are mapped. The least significant 2**RAM SIZE bits are ignored." group.word 0x1B6++0x5 line.word 0x0 "BAR_SRAM1_H0,SRAM 1 Memory Base Address Config" hexmask.word.byte 0x0 4.--7. 1. "SIZE,This field defines the size of the region mapped from Host Memory address space into the internal address space in powers of 2. 15=The region is 64KB in extent 14=The region is 32KB in extent ... 1=The region is 2B in extent.." newline bitfld.word 0x0 1.--2. "ACCESS,These 2 bits define the access type of access to this SRAM region. 3=Host has Read/write access to the region 2=Host has Write-only access to the region 1=Host has Read-only access to the region 0=Host has no access to this.." "0: Host has no access to this region,1: Host has Read-only access to the region,2: Host has Write-only access to the region,3: Host has Read/write access to the region" newline bitfld.word 0x0 0. "VALID,1=The BAR is valid and will participate in eSPI matches. 0=The BAR is ignored." "0: The BAR is ignored,1: The BAR is valid and will participate in eSPI.." line.word 0x2 "BAR_SRAM1_H1,SRAM 1 Memory Base Address LSB" hexmask.word 0x2 0.--15. 1. "ADDR,This is the LSB of the 32-bit field that defines the base address of the internal memory region to which Host accesses to the region starting at RAM eSPI Host Address are mapped. The least significant 2**RAM SIZE bits are ignored." line.word 0x4 "BAR_SRAM1_H2,SRAM 1 Memory Base Address MSB" hexmask.word 0x4 0.--15. 1. "ADDR,This the MSB of the 32-bit field that defines the base address of the internal memory region to which Host accesses to the region starting at RAM eSPI Host Address are mapped. The least significant 2**RAM SIZE bits are ignored." group.long 0x200++0xB line.long 0x0 "BM_STS,Bus Master Status Register" bitfld.long 0x0 27. "BAD2_REQ,This bit is set and the START request is terminated immediately (BM2_TRANSFER_DONE=1) without triggering traffic if register contents are invalid at the time the BM2_START bit is written to '1' by firmware. (R/WC) Examples of a Bad.." "0,1" newline bitfld.long 0x0 25. "INTR2_BUS_ERR,This bit is set if a transfer on Bus Master Channel 2 is terminated due to a bus error internal to the EC. This can happen if an invalid address is provided in the Bus Master 2 internal Address register. (R/WC)" "0,1" newline bitfld.long 0x0 24. "FAIL2,This bit is set if a Layer 3 transaction from Bus Master Channel 2 completes with an Unsuccessful Completion packet from the eSPI Host. For example this will happen if the START request attempts to read from a forbidden or unmapped address in.." "0,1" newline bitfld.long 0x0 23. "INCMPL2,This bit is set if the transfer on Bus Master Channel 2 completed but an insufficient number of bytes were transferred. Some of the data will not be delivered on the internal bus. (R/WC)" "0,1" newline bitfld.long 0x0 22. "DAT2_OVRUN,This bit is set if the transfer on Bus Master Channel 2 completed but too many bytes were delivered by the eSPI Host. Some of the data will not be delivered on the internal bus. (R/WC)" "0,1" newline bitfld.long 0x0 21. "STRT2_OVRFLW,This bit is set if the bit BM2_START in the Bus Master 2 Control Register is written with a 1 while the bit BM2_BUSY is 1. This condition immediately halts the transfer in progress also (BM2_TRANSFER_DONE=1). (R/WC)" "0,1" newline bitfld.long 0x0 20. "ABORT_CH1_ERR,This bit is set if an error occurs on Bus Master Channel 1 while a Channel 2 transfer is in progress if the two channels are linked. Linkage occurs when bit BM2_WAIT_BM1_NOT_BUSY in register Bus Master 2 Control Register is set to.." "0,1" newline bitfld.long 0x0 19. "ABORT2_H,A '1' in this bit indicates that the last requested Mastering operation was aborted because Bus Mastering has been disabled by the Host. Bus Mastering is disabled whenever the Peripheral Channel Mastering Enable bit in that register is '0' .." "0,1" newline bitfld.long 0x0 18. "ABORT2_EC,This bit is set when the control bit BM2_ABORT in the Bus Master 2 Control Register is written with a 1 during an active transfer. (R/WC)" "0,1" newline bitfld.long 0x0 17. "BUSY2,Hardware sets this bit to 1 when the control bit BM2_START in the Bus Master 2 Control Register is written with a 1. This bit is cleared when the transfer completes. This may happen normally but it is guaranteed to happen also if any of the.." "0,1" newline bitfld.long 0x0 16. "TX_DONE2,This bit is set to '1' when a START transfer on Bus Master Channel 2 has completed and occurs simultaneously with the clearing of the BM2_BUSY bit. This may happen normally but it is guaranteed to happen also if any of the Error bits in.." "0,1" newline bitfld.long 0x0 11. "BAD1_REQ,This bit is set and the START request is terminated immediately (BM1_TRANSFER_DONE=1) without triggering traffic if register contents are invalid at the time the BM1_START bit is written to '1' by firmware. (R/WC) Examples of a Bad.." "0,1" newline bitfld.long 0x0 9. "INTR1_BUS_ERR,This bit is set if a transfer on Bus Master Channel 1 is terminated due to a bus error internal to the EC. This can happen if an invalid address is provided in the Bus Master 1 internal Address register. (R/WC)" "0,1" newline bitfld.long 0x0 8. "FAIL1,This bit is set if a Layer 3 transaction from Bus Master Channel 1 completes with an Unsuccessful Completion packet from the eSPI Host. For example this will happen if the START request attempts to read from a forbidden or unmapped address in.." "0,1" newline bitfld.long 0x0 7. "INCMPL1,This bit is set if the transfer on Bus Master Channel 1 completed but an insufficient number of bytes were transferred. Some of the data will not be delivered on the internal bus. (R/WC)" "0,1" newline bitfld.long 0x0 6. "DAT1_OVRUN,This bit is set if the transfer on Bus Master Channel 1 completed but too many bytes were delivered by the eSPI Host. Some of the data will not be delivered on the internal bus. (R/WC)" "0,1" newline bitfld.long 0x0 5. "STRT1_OVRFLW,This bit is set if the bit BM1_START in the Bus Master 1 Control Register is written with a 1 while the bit BM1_BUSY is 1. This condition immediately halts the transfer in progress also (BM1_TRANSFER_DONE=1). (R/WC)" "0,1" newline bitfld.long 0x0 4. "ABORT_CH2_ERR,This bit is set if an error occurs on Bus Master Channel 2 while a Channel 1 transfer is in progress if the two channels are linked. Linkage occurs when bit BM1_WAIT_BM2_NOT_BUSY in register Bus Master 1 Control Register is set to.." "0,1" newline bitfld.long 0x0 3. "ABORT1_H,A '1' in this bit indicates that the last requested Mastering operation was aborted because Bus Mastering has been disabled by the Host. Bus Mastering is disabled whenever the Peripheral Channel Mastering Enable bit in that register is '0' .." "0,1" newline bitfld.long 0x0 2. "ABORT1_EC,This bit is set when the control bit BM1_ABORT in the Bus Master 1 Control Register is written with a 1 during an active transfer. (R/WC)" "0,1" newline bitfld.long 0x0 1. "BUSY1,Hardware sets this bit to 1 when the control bit BM1_START in the Bus Master 1 Control Register is written with a 1. This bit is cleared when the transfer completes. This may happen normally but it is guaranteed to happen also if any of the.." "0,1" newline bitfld.long 0x0 0. "TX_DONE1,This bit is set to '1' when a START transfer on Bus Master Channel 1 has completed and occurs simultaneously with the clearing of the BM1_BUSY bit. This may happen normally but it is also guaranteed to happen if any of the Error bits in.." "0,1" line.long 0x4 "BM_IEN,Bus Master Interrupt Enable Register" bitfld.long 0x4 1. "TX2_DONE_EN,When this bit is '1' an interrupt is generated when the bit BM2_TRANSFER_DONE in the Bus Master Status Register is 1. When this bit is '0' the status bit will not generate an interrupt." "0,1" newline bitfld.long 0x4 0. "TX1_DONE_EN,When this bit is '1' an interrupt is generated when the bit BM1_TRANSFER_DONE in the Bus Master Status Register is 1. When this bit is '0' the status bit will not generate an interrupt." "0,1" line.long 0x8 "BM_CFG,Bus Master Configuration Register" hexmask.long.byte 0x8 16.--19. 1. "TAG2,This 4-bit Tag value is included in all eSPI traffic originating from the BM2 Bus Master instance. This bit should not be modified while the bit BM2_BUSY in the Bus Master Status Register is '1'." newline hexmask.long.byte 0x8 0.--3. 1. "TAG1,This 4-bit Tag value is included in all eSPI traffic originating from the BM1 Bus Master instance. This bit should not be modified while the bit BM1_BUSY in the Bus Master Status Register is '1'." group.long 0x210++0xF line.long 0x0 "BM1_CTRL,Bus Master 1 Control Register" hexmask.long.word 0x0 16.--28. 1. "LEN,This field sets the length in bytes of a transfer on Bus Master Channel 1. A value of zero or a value greater than exactly 4K (0x1000) is illegal. Any length which in combination with the Bus Master 1 Host Address register will cause the.." newline bitfld.long 0x0 8.--9. "CYC_TYPE,This field provides the cycle type to use inside the eSPI transaction header: 11b=Memory Write 64-bit addressing 10b=Memory Read 64-bit addressing 01b=Memory Write 32-bit addressing 00b=Memory Read 32-bit addressing." "0,1,2,3" newline bitfld.long 0x0 3. "BM1WAIT_BM2NOTBUSY,1=The transfer on Bus Master Channel 1 will be held until a transfer in progress on Bus Master Channel 2 has completed. If that transfer completes unsuccessfully then this transfer will also terminate before generating any.." "0: The transfer on Bus Master Channel 1 will..,1: The transfer on Bus Master Channel 1 will be.." newline bitfld.long 0x0 2. "EN_INTER_INCR,1=The internal address will be incremented after each transfer to eSPI 0=The internal address will remain fixed for the entire Bus Master transfer. This may be used to transfer data to or from an on-chip FIFO instead of a region.." "0: The internal address will remain fixed for the..,1: The internal address will be incremented after.." newline bitfld.long 0x0 1. "ABORT,A write of '1' to this bit will cause an active transfer on Bus Master Channel 1 to terminate at the next point allowed by the eSPI protocol. A write of 0 has no effect. Reads of this bit return 0. If this bit is written to 1 by firmware .." "0,1" newline bitfld.long 0x0 0. "START,A write of '1' to this bit starts a Bus Master transfer on Bus Master Channel 1. A write of 0 has no effect. Reads of this bit return 0. The transmission will be inhibited if the Peripheral channel is not Ready as defined in the eSPI.." "0,1" line.long 0x4 "BM1_HOST_ADDR_LSW,Bus Master 1 Host Address Register (DWord 0)" hexmask.long 0x4 0.--31. 1. "LSDW,This register sets bits [31:0] of the Host address used for a transfer on Bus Master Channel 1. This address combined with the Length must not cross a 4K boundary or else the START request will terminate without traffic posting the Bad.." line.long 0x8 "BM1_HOST_ADDR_MSW,Bus Master 1 Host Address Register (DWord 1)" hexmask.long 0x8 0.--31. 1. "MSDW,This register sets bits [63:32] of the Host address used for a transfer on Bus Master Channel 1. This address combined with the Length must not cross a 4K boundary or else the START request will terminate without traffic posting the Bad.." line.long 0xC "BM1_EC_ADDR_LSW,Bus Master 1 Internal Address Register" hexmask.long 0xC 2.--31. 1. "IN_ADDR,This register sets the internal address to be used for a transfer on Bus Master Channel 1." group.long 0x224++0xF line.long 0x0 "BM2_CTRL,Bus Master 2 Control Register" hexmask.long.word 0x0 16.--28. 1. "LEN,This field sets the length in bytes of a transfer on Bus Master Channel 2. A value of zero or a value greater than exactly 4K (0x1000) is illegal. Any length which in combination with the Bus Master 2 Host Address register will cause the.." newline bitfld.long 0x0 8.--9. "CYC_TYPE,This field provides the cycle type to use inside the eSPI transaction header: 11b=Memory Write 64-bit addressing 10b=Memory Read 64-bit addressing 01b=Memory Write 32-bit addressing 00b=Memory Read 32-bit addressing." "0,1,2,3" newline bitfld.long 0x0 3. "BM2WAIT_BM1NOTBUSY,1=The transfer on Bus Master Channel 2 will be held until a transfer in progress on Bus Master Channel 1 has completed. If that transfer completes unsuccessfully then this transfer will also terminate before generating any.." "0: The transfer on Bus Master Channel 2 will..,1: The transfer on Bus Master Channel 2 will be.." newline bitfld.long 0x0 2. "EN_INTER_INCR,1=The internal address will be incremented after each transfer to eSPI 0=The internal address will remain fixed for the entire Bus Master transfer. This may be used to transfer data to or from an on-chip FIFO instead of a region.." "0: The internal address will remain fixed for the..,1: The internal address will be incremented after.." newline bitfld.long 0x0 1. "ABORT,A write of '1' to this bit will cause an active transfer on Bus Master Channel 2 to terminate at the next point allowed by the eSPI protocol. A write of 0 has no effect. Reads of this bit return 0. If this bit is written to 1 by firmware .." "0,1" newline bitfld.long 0x0 0. "START,A write of '1' to this bit starts a Bus Master transfer on Bus Master Channel 2. A write of 0 has no effect. Reads of this bit return 0. The transmission will be inhibited if the Peripheral channel is not Ready as defined in the eSPI.." "0,1" line.long 0x4 "BM2_HOST_ADDR_LSW,Bus Master 2 Host Address Register (DWord 0)" hexmask.long 0x4 0.--31. 1. "LSDW,This register sets bits [31:0] of the Host address used for a transfer on Bus Master Channel 2. This address combined with the Length must not cross a 4K boundary or else the START request will terminate without traffic posting the Bad.." line.long 0x8 "BM2_HOST_ADDR_MSW,Bus Master 2 Host Address Register (DWord 1)" hexmask.long 0x8 0.--31. 1. "MSDW,This register sets bits [63:32] of the Host address used for a transfer on Bus Master Channel 2. This address combined with the Length must not cross a 4K boundary or else the START request will terminate without traffic posting the Bad.." line.long 0xC "BM2_EC_ADDR_LSW,Bus Master 2 Internal Address Register" hexmask.long 0xC 2.--31. 1. "IN_ADDR,This register sets the internal address to be used for a transfer on Bus Master Channel 2." group.word 0x330++0x59 line.word 0x0 "BAR_LDH_MBX_H0,Mailbox Memory BAR Configuration Register (Word 0)" bitfld.word 0x0 0. "VALID,1=The BAR is valid and will participate in eSPI matches. 0=The BAR is ignored." "0: The BAR is ignored,1: The BAR is valid and will participate in eSPI.." line.word 0x2 "BAR_LDH_MBX_H1,Mailbox Memory BAR Configuration Register (Word 1)" hexmask.word 0x2 0.--15. 1. "ESP_H_ADDR_W0,Bits[15:0] of the 64 bits that are used to match eSPI memory addresses." line.word 0x4 "BAR_LDH_MBX_H2,Mailbox Memory BAR Configuration Register (Word 2)" hexmask.word 0x4 0.--15. 1. "ESP_H_ADDR_W1,Bits[31:16] of the 64 bits that are used to match eSPI memory addresses." line.word 0x6 "BAR_LDH_MBX_H3,Mailbox Memory BAR Configuration Register (Word 3)" hexmask.word 0x6 0.--15. 1. "ESP_H_ADDR_W2,Bits[47:32] of the 64 bits that are used to match eSPI memory addresses." line.word 0x8 "BAR_LDH_MBX_H4,Mailbox Memory BAR Configuration Register (Word 4)" hexmask.word 0x8 0.--15. 1. "ESP_H_ADDR_W3,Bits[63:48] of the 64 bits that are used to match eSPI memory addresses." line.word 0xA "BAR_LDH_ACPI_EC0_H0,ACPI EC Channel 0 Memory BAR Configuration Register (Word 0)" bitfld.word 0xA 0. "VALID,1=The BAR is valid and will participate in eSPI matches. 0=The BAR is ignored." "0: The BAR is ignored,1: The BAR is valid and will participate in eSPI.." line.word 0xC "BAR_LDH_ACPI_EC0_H1,ACPI EC Channel 0 Memory BAR Configuration Register (Word 1)" hexmask.word 0xC 0.--15. 1. "ESP_H_ADDR_W0,Bits[15:0] of the 64 bits that are used to match eSPI memory addresses." line.word 0xE "BAR_LDH_ACPI_EC0_H2,ACPI EC Channel 0 Memory BAR Configuration Register (Word 2)" hexmask.word 0xE 0.--15. 1. "ESP_H_ADDR_W1,Bits[31:16] of the 64 bits that are used to match eSPI memory addresses." line.word 0x10 "BAR_LDH_ACPI_EC0_H3,ACPI EC Channel 0 Memory BAR Configuration Register (Word 3)" hexmask.word 0x10 0.--15. 1. "ESP_H_ADDR_W2,Bits[47:32] of the 64 bits that are used to match eSPI memory addresses." line.word 0x12 "BAR_LDH_ACPI_EC0_H4,ACPI EC Channel 0 Memory BAR Configuration Register (Word 4)" hexmask.word 0x12 0.--15. 1. "ESP_H_ADDR_W3,Bits[63:48] of the 64 bits that are used to match eSPI memory addresses." line.word 0x14 "BAR_LDH_ACPI_EC1_H0,ACPI EC Channel 1 Memory BAR Configuration Register (Word 0)" bitfld.word 0x14 0. "VALID,1=The BAR is valid and will participate in eSPI matches. 0=The BAR is ignored." "0: The BAR is ignored,1: The BAR is valid and will participate in eSPI.." line.word 0x16 "BAR_LDH_ACPI_EC1_H1,ACPI EC Channel 1 Memory BAR Configuration Register (Word 1)" hexmask.word 0x16 0.--15. 1. "ESP_H_ADDR_W0,Bits[15:0] of the 64 bits that are used to match eSPI memory addresses." line.word 0x18 "BAR_LDH_ACPI_EC1_H2,ACPI EC Channel 1 Memory BAR Configuration Register (Word 2)" hexmask.word 0x18 0.--15. 1. "ESP_H_ADDR_W1,Bits[31:16] of the 64 bits that are used to match eSPI memory addresses." line.word 0x1A "BAR_LDH_ACPI_EC1_H3,ACPI EC Channel 1 Memory BAR Configuration Register (Word 3)" hexmask.word 0x1A 0.--15. 1. "ESP_H_ADDR_W2,Bits[47:32] of the 64 bits that are used to match eSPI memory addresses." line.word 0x1C "BAR_LDH_ACPI_EC1_H4,ACPI EC Channel 1 Memory BAR Configuration Register (Word 4)" hexmask.word 0x1C 0.--15. 1. "ESP_H_ADDR_W3,Bits[63:48] of the 64 bits that are used to match eSPI memory addresses." line.word 0x1E "BAR_LDH_ACPI_EC2_H0,ACPI EC Channel 2 Memory BAR Configuration Register (Word 0)" bitfld.word 0x1E 0. "VALID,1=The BAR is valid and will participate in eSPI matches. 0=The BAR is ignored." "0: The BAR is ignored,1: The BAR is valid and will participate in eSPI.." line.word 0x20 "BAR_LDH_ACPI_EC2_H1,ACPI EC Channel 2 Memory BAR Configuration Register (Word 1)" hexmask.word 0x20 0.--15. 1. "ESP_H_ADDR_W0,Bits[15:0] of the 64 bits that are used to match eSPI memory addresses." line.word 0x22 "BAR_LDH_ACPI_EC2_H2,ACPI EC Channel 2 Memory BAR Configuration Register (Word 2)" hexmask.word 0x22 0.--15. 1. "ESP_H_ADDR_W1,Bits[31:16] of the 64 bits that are used to match eSPI memory addresses." line.word 0x24 "BAR_LDH_ACPI_EC2_H3,ACPI EC Channel 2 Memory BAR Configuration Register (Word 3)" hexmask.word 0x24 0.--15. 1. "ESP_H_ADDR_W2,Bits[47:32] of the 64 bits that are used to match eSPI memory addresses." line.word 0x26 "BAR_LDH_ACPI_EC2_H4,ACPI EC Channel 2 Memory BAR Configuration Register (Word 4)" hexmask.word 0x26 0.--15. 1. "ESP_H_ADDR_W3,Bits[63:48] of the 64 bits that are used to match eSPI memory addresses." line.word 0x28 "BAR_LDH_ACPI_EC3_H0,ACPI EC Channel 3 Memory BAR Configuration Register (Word 0)" bitfld.word 0x28 0. "VALID,1=The BAR is valid and will participate in eSPI matches. 0=The BAR is ignored." "0: The BAR is ignored,1: The BAR is valid and will participate in eSPI.." line.word 0x2A "BAR_LDH_ACPI_EC3_H1,ACPI EC Channel 3 Memory BAR Configuration Register (Word 1)" hexmask.word 0x2A 0.--15. 1. "ESP_H_ADDR_W0,Bits[15:0] of the 64 bits that are used to match eSPI memory addresses." line.word 0x2C "BAR_LDH_ACPI_EC3_H2,ACPI EC Channel 3 Memory BAR Configuration Register (Word 2)" hexmask.word 0x2C 0.--15. 1. "ESP_H_ADDR_W1,Bits[31:16] of the 64 bits that are used to match eSPI memory addresses." line.word 0x2E "BAR_LDH_ACPI_EC3_H3,ACPI EC Channel 3 Memory BAR Configuration Register (Word 3)" hexmask.word 0x2E 0.--15. 1. "ESP_H_ADDR_W2,Bits[47:32] of the 64 bits that are used to match eSPI memory addresses." line.word 0x30 "BAR_LDH_ACPI_EC3_H4,ACPI EC Channel 3 Memory BAR Configuration Register (Word 4)" hexmask.word 0x30 0.--15. 1. "ESP_H_ADDR_W3,Bits[63:48] of the 64 bits that are used to match eSPI memory addresses." line.word 0x32 "BAR_LDH_ACPI_EC4_H0,ACPI EC Channel 4 Memory BAR Configuration Register (Word 0)" bitfld.word 0x32 0. "VALID,1=The BAR is valid and will participate in eSPI matches. 0=The BAR is ignored." "0: The BAR is ignored,1: The BAR is valid and will participate in eSPI.." line.word 0x34 "BAR_LDH_ACPI_EC4_H1,ACPI EC Channel 4 Memory BAR Configuration Register (Word 1)" hexmask.word 0x34 0.--15. 1. "ESP_H_ADDR_W0,Bits[15:0] of the 64 bits that are used to match eSPI memory addresses." line.word 0x36 "BAR_LDH_ACPI_EC4_H2,ACPI EC Channel 4 Memory BAR Configuration Register (Word 2)" hexmask.word 0x36 0.--15. 1. "ESP_H_ADDR_W1,Bits[31:16] of the 64 bits that are used to match eSPI memory addresses." line.word 0x38 "BAR_LDH_ACPI_EC4_H3,ACPI EC Channel 4 Memory BAR Configuration Register (Word 3)" hexmask.word 0x38 0.--15. 1. "ESP_H_ADDR_W2,Bits[47:32] of the 64 bits that are used to match eSPI memory addresses." line.word 0x3A "BAR_LDH_ACPI_EC4_H4,ACPI EC Channel 4 Memory BAR Configuration Register (Word 4)" hexmask.word 0x3A 0.--15. 1. "ESP_H_ADDR_W3,Bits[63:48] of the 64 bits that are used to match eSPI memory addresses." line.word 0x3C "BAR_LDH_EM0_H0,EMI 0 Memory BAR Configuration Register (Word 0)" bitfld.word 0x3C 0. "VALID,1=The BAR is valid and will participate in eSPI matches. 0=The BAR is ignored." "0: The BAR is ignored,1: The BAR is valid and will participate in eSPI.." line.word 0x3E "BAR_LDH_EM0_H1,EMI 0 Memory BAR Configuration Address Register (Word 1)" hexmask.word 0x3E 0.--15. 1. "ESP_H_ADDR_W0,Bits[15:0] of the 64 bits that are used to match eSPI memory addresses." line.word 0x40 "BAR_LDH_EM0_H2,EMI 0 Memory BAR Configuration Address Register (Word 2)" hexmask.word 0x40 0.--15. 1. "ESP_H_ADDR_W1,Bits[31:16] of the 64 bits that are used to match eSPI memory addresses." line.word 0x42 "EMI_0_MEM_BAR_CFG_W3,EMI 0 Memory BAR Configuration Address Register (Word 3)" hexmask.word 0x42 0.--15. 1. "ESPI_HOST_ADDRESS_W2,Bits[47:32] of the 64 bits that are used to match eSPI memory addresses." line.word 0x44 "EMI_0_MEM_BAR_CFG_W4,EMI 0 Memory BAR Configuration Address Register (Word 4)" hexmask.word 0x44 0.--15. 1. "ESPI_HOST_ADDRESS_W3,Bits[63:48] of the 64 bits that are used to match eSPI memory addresses." line.word 0x46 "EMI_1_MEM_BAR_CFG_W0,EMI 1 Memory BAR Configuration Register (Word 0) )" bitfld.word 0x46 0. "VALID,1=The BAR is valid and will participate in eSPI matches. 0=The BAR is ignored." "0: The BAR is ignored,1: The BAR is valid and will participate in eSPI.." line.word 0x48 "EMI_1_MEM_BAR_CFG_W1,EMI 1 Memory BAR Configuration Register (Word 1) )" hexmask.word 0x48 0.--15. 1. "ESPI_HOST_ADDRESS_W0,Bits[15:0] of the 64 bits that are used to match eSPI memory addresses." line.word 0x4A "EMI_1_MEM_BAR_CFG_W2,EMI 1 Memory BAR Configuration Register (Word 2) )" hexmask.word 0x4A 0.--15. 1. "ESPI_HOST_ADDRESS_W1,Bits[31:16] of the 64 bits that are used to match eSPI memory addresses." line.word 0x4C "EMI_1_MEM_BAR_CFG_W3,EMI 1 Memory BAR Configuration Register (Word 3) )" hexmask.word 0x4C 0.--15. 1. "ESPI_HOST_ADDRESS_W2,Bits[47:32] of the 64 bits that are used to match eSPI memory addresses." line.word 0x4E "EMI_1_MEM_BAR_CFG_W4,EMI 1 Memory BAR Configuration Register (Word 4) )" hexmask.word 0x4E 0.--15. 1. "ESPI_HOST_ADDRESS_W3,Bits[63:48] of the 64 bits that are used to match eSPI memory addresses." line.word 0x50 "EMI_2_MEM_BAR_CFG_W0,EMI 2 Memory BAR Configuration Register (Word 0) )" bitfld.word 0x50 0. "VALID,1=The BAR is valid and will participate in eSPI matches. 0=The BAR is ignored." "0: The BAR is ignored,1: The BAR is valid and will participate in eSPI.." line.word 0x52 "EMI_2_MEM_BAR_CFG_W1,EMI 2 Memory BAR Configuration Register (Word 1) )" hexmask.word 0x52 0.--15. 1. "ESPI_HOST_ADDRESS_W0,Bits[15:0] of the 64 bits that are used to match eSPI memory addresses." line.word 0x54 "EMI_2_MEM_BAR_CFG_W2,EMI 2 Memory BAR Configuration Register (Word 2) )" hexmask.word 0x54 0.--15. 1. "ESPI_HOST_ADDRESS_W1,Bits[31:16] of the 64 bits that are used to match eSPI memory addresses." line.word 0x56 "EMI_2_MEM_BAR_CFG_W3,EMI 2 Memory BAR Configuration Register (Word 3) )" hexmask.word 0x56 0.--15. 1. "ESPI_HOST_ADDRESS_W2,Bits[47:32] of the 64 bits that are used to match eSPI memory addresses." line.word 0x58 "EMI_2_MEM_BAR_CFG_W4,EMI 2 Memory BAR Configuration Register (Word 4) )" hexmask.word 0x58 0.--15. 1. "ESPI_HOST_ADDRESS_W3,Bits[63:48] of the 64 bits that are used to match eSPI memory addresses." group.word 0x3AC++0x13 line.word 0x0 "SRAM_0_MEM_BAR_CFG_W0,SRAM BAR 0 Configuration Register (Word 0) )" bitfld.word 0x0 0. "VALID,1=The BAR is valid and will participate in eSPI matches. 0=The BAR is ignored." "0: The BAR is ignored,1: The BAR is valid and will participate in eSPI.." line.word 0x2 "SRAM_0_MEM_BAR_CFG_W1,SRAM BAR 0 Configuration Register (Word 1) )" hexmask.word 0x2 0.--15. 1. "ESPI_HOST_ADDRESS_W0,Bits[15:0] of the 64 bits that are used to match eSPI memory addresses." line.word 0x4 "SRAM_0_MEM_BAR_CFG_W2,SRAM BAR 0 Configuration Register (Word 2) )" hexmask.word 0x4 0.--15. 1. "ESPI_HOST_ADDRESS_W1,Bits[31:16] of the 64 bits that are used to match eSPI memory addresses." line.word 0x6 "SRAM_0_MEM_BAR_CFG_W3,SRAM BAR 0 Configuration Register (Word 3) )" hexmask.word 0x6 0.--15. 1. "ESPI_HOST_ADDRESS_W2,Bits[47:32] of the 64 bits that are used to match eSPI memory addresses." line.word 0x8 "SRAM_0_MEM_BAR_CFG_W4,SRAM BAR 0 Configuration Register (Word 4) )" hexmask.word 0x8 0.--15. 1. "ESPI_HOST_ADDRESS_W3,Bits[63:48] of the 64 bits that are used to match eSPI memory addresses." line.word 0xA "SRAM_1_MEM_BAR_CFG_W0,SRAM BAR 1 Configuration Register (Word 0) )" bitfld.word 0xA 0. "VALID,1=The BAR is valid and will participate in eSPI matches. 0=The BAR is ignored." "0: The BAR is ignored,1: The BAR is valid and will participate in eSPI.." line.word 0xC "SRAM_1_MEM_BAR_CFG_W1,SRAM BAR 1 Configuration Register (Word 1) )" hexmask.word 0xC 0.--15. 1. "ESPI_HOST_ADDRESS_W0,Bits[15:0] of the 64 bits that are used to match eSPI memory addresses." line.word 0xE "SRAM_1_MEM_BAR_CFG_W2,SRAM BAR 1 Configuration Register (Word 2) )" hexmask.word 0xE 0.--15. 1. "ESPI_HOST_ADDRESS_W1,Bits[31:16] of the 64 bits that are used to match eSPI memory addresses." line.word 0x10 "SRAM_1_MEM_BAR_CFG_W3,SRAM BAR 1 Configuration Register (Word 3) )" hexmask.word 0x10 0.--15. 1. "ESPI_HOST_ADDRESS_W2,Bits[47:32] of the 64 bits that are used to match eSPI memory addresses." line.word 0x12 "SRAM_1_MEM_BAR_CFG_W4,SRAM BAR 1 Configuration Register (Word 4) )" hexmask.word 0x12 0.--15. 1. "ESPI_HOST_ADDRESS_W3,Bits[63:48] of the 64 bits that are used to match eSPI memory addresses." tree.end tree "ESPI_MSVW00_06" base ad:0x400F9C00 group.long 0x0++0x53 line.long 0x0 "MSVW00_DW0,Master-to-Slave Virtual Wire 0 Register (DW 0)" hexmask.long.byte 0x0 12.--15. 1. "MTOS_R_STATE,The four bits in this field are loaded into SRC0 SRC1 SRC2 and SRC3 when the reset signal selected by M2S RESET SRC is asserted. If MTOS_SRC is set for RESET_SYS the SRC bits are set to the default value of this field rather than.." bitfld.long 0x0 8.--9. "MTOS_SRC,This field determines which reset signal in addition to RESET_SYS resets SRC[3:0] in this register: 3=PLTRST 2=RESET_SIO 1=RESET_SYS. This is the only reset signal that will reset the SRC fields. 0=RESET_ESPI." "0: RESET_ESPI,1: RESET_SYS,2: RESET_SIO,3: PLTRST" hexmask.long.byte 0x0 4.--7. 1. "INDEX,The Index for SRC0 SRC1 SRC2 and SRC3. When the Index field of an incoming Master-to-Slave Virtual Wire transaction matches this value the fields SRC0 SRC1 SRC2 and SRC3 are updated by the data contained in the respective bit positions in.." hexmask.long.byte 0x0 0.--3. 1. "M2S_2H_BACKUP,The Boot ROM firmware will copy this field into the SRC3 to SRC0 bits of the Master-to-Slave Virtual Wire Register that corresponds to Virtual Wire Index 2h on a RESET_SYS. If software always saves the state of the Index 2h SRC bits on.." line.long 0x4 "MSVW00_DW1,Master-to-Slave Virtual Wire 0 Register (DW 1)" hexmask.long.byte 0x4 24.--27. 1. "SRC3IRQ_SEL,A change in the value of SRC3 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." hexmask.long.byte 0x4 16.--19. 1. "SRC2IRQ_SEL,A change in the value of SRC2 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." hexmask.long.byte 0x4 8.--11. 1. "SRC1IRQ_SEL,A change in the value of SRC1 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." hexmask.long.byte 0x4 0.--3. 1. "SRC0IRQ_SEL,A change in the value of SRC0 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." line.long 0x8 "MSVW00_DW2,Master-to-Slave Virtual Wire 0 Register (DW 2)" bitfld.long 0x8 24. "SRC3,Master-to-Slave data for Bit Position 3 for the virtual wire associated with the index defined by INDEX." "0,1" bitfld.long 0x8 16. "SRC2,Master-to-Slave data for Bit Position 2 for the virtual wire associated with the index defined by INDEX." "0,1" bitfld.long 0x8 8. "SRC1,Master-to-Slave data for Bit Position 1 for the virtual wire associated with the index defined by INDEX." "0,1" bitfld.long 0x8 0. "SRC0,Master-to-Slave data for Bit Position 0 for the virtual wire associated with the index defined by INDEX." "0,1" line.long 0xC "MSVW01_DW0,Master-to-Slave Virtual Wire 1 Register (DW 0)" hexmask.long.byte 0xC 12.--15. 1. "MTOS_R_STATE,The four bits in this field are loaded into SRC0 SRC1 SRC2 and SRC3 when the reset signal selected by M2S RESET SRC is asserted. If MTOS_SRC is set for RESET_SYS the SRC bits are set to the default value of this field rather than.." bitfld.long 0xC 8.--9. "MTOS_SRC,This field determines which reset signal in addition to RESET_SYS resets SRC[3:0] in this register: 3=PLTRST 2=RESET_SIO 1=RESET_SYS. This is the only reset signal that will reset the SRC fields. 0=RESET_ESPI." "0: RESET_ESPI,1: RESET_SYS,2: RESET_SIO,3: PLTRST" hexmask.long.byte 0xC 0.--7. 1. "IND,The Index for SRC0 SRC1 SRC2 and SRC3. When the Index field of an incoming Master-to-Slave Virtual Wire transaction matches this value the fields SRC0 SRC1 SRC2 and SRC3 are updated by the data contained in the respective bit positions in.." line.long 0x10 "MSVW01_DW1,Master-to-Slave Virtual Wire 1 Register (DW 1)" hexmask.long.byte 0x10 24.--27. 1. "SRC3IRQ_SEL,A change in the value of SRC3 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." hexmask.long.byte 0x10 16.--19. 1. "SRC2IRQ_SEL,A change in the value of SRC2 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." hexmask.long.byte 0x10 8.--11. 1. "SRC1IRQ_SEL,A change in the value of SRC1 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." hexmask.long.byte 0x10 0.--3. 1. "SRC0IRQ_SEL,A change in the value of SRC0 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." line.long 0x14 "MSVW01_DW2,Master-to-Slave Virtual Wire 1 Register (DW 2)" bitfld.long 0x14 24. "SRC3,Master-to-Slave data for Bit Position 3 for the virtual wire associated with the index defined by INDEX." "0,1" bitfld.long 0x14 16. "SRC2,Master-to-Slave data for Bit Position 2 for the virtual wire associated with the index defined by INDEX." "0,1" bitfld.long 0x14 8. "SRC1,Master-to-Slave data for Bit Position 1 for the virtual wire associated with the index defined by INDEX." "0,1" bitfld.long 0x14 0. "SRC0,Master-to-Slave data for Bit Position 0 for the virtual wire associated with the index defined by INDEX." "0,1" line.long 0x18 "MSVW02_DW0,Master-to-Slave Virtual Wire 2 Register (DW 0)" hexmask.long.byte 0x18 12.--15. 1. "MTOS_R_STATE,The four bits in this field are loaded into SRC0 SRC1 SRC2 and SRC3 when the reset signal selected by M2S RESET SRC is asserted. If MTOS_SRC is set for RESET_SYS the SRC bits are set to the default value of this field rather than.." bitfld.long 0x18 8.--9. "MTOS_SRC,This field determines which reset signal in addition to RESET_SYS resets SRC[3:0] in this register: 3=PLTRST 2=RESET_SIO 1=RESET_SYS. This is the only reset signal that will reset the SRC fields. 0=RESET_ESPI." "0: RESET_ESPI,1: RESET_SYS,2: RESET_SIO,3: PLTRST" hexmask.long.byte 0x18 0.--7. 1. "IND,The Index for SRC0 SRC1 SRC2 and SRC3. When the Index field of an incoming Master-to-Slave Virtual Wire transaction matches this value the fields SRC0 SRC1 SRC2 and SRC3 are updated by the data contained in the respective bit positions in.." line.long 0x1C "MSVW02_DW1,Master-to-Slave Virtual Wire 2 Register (DW 1)" hexmask.long.byte 0x1C 24.--27. 1. "SRC3IRQ_SEL,A change in the value of SRC3 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." hexmask.long.byte 0x1C 16.--19. 1. "SRC2IRQ_SEL,A change in the value of SRC2 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." hexmask.long.byte 0x1C 8.--11. 1. "SRC1IRQ_SEL,A change in the value of SRC1 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." hexmask.long.byte 0x1C 0.--3. 1. "SRC0IRQ_SEL,A change in the value of SRC0 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." line.long 0x20 "MSVW02_DW2,Master-to-Slave Virtual Wire 2 Register (DW 2)" bitfld.long 0x20 24. "SRC3,Master-to-Slave data for Bit Position 3 for the virtual wire associated with the index defined by INDEX." "0,1" bitfld.long 0x20 16. "SRC2,Master-to-Slave data for Bit Position 2 for the virtual wire associated with the index defined by INDEX." "0,1" bitfld.long 0x20 8. "SRC1,Master-to-Slave data for Bit Position 1 for the virtual wire associated with the index defined by INDEX." "0,1" bitfld.long 0x20 0. "SRC0,Master-to-Slave data for Bit Position 0 for the virtual wire associated with the index defined by INDEX." "0,1" line.long 0x24 "MSVW03_DW0,Master-to-Slave Virtual Wire 3 Register (DW 0)" hexmask.long.byte 0x24 12.--15. 1. "MTOS_R_STATE,The four bits in this field are loaded into SRC0 SRC1 SRC2 and SRC3 when the reset signal selected by M2S RESET SRC is asserted. If MTOS_SRC is set for RESET_SYS the SRC bits are set to the default value of this field rather than.." bitfld.long 0x24 8.--9. "MTOS_SRC,This field determines which reset signal in addition to RESET_SYS resets SRC[3:0] in this register: 3=PLTRST 2=RESET_SIO 1=RESET_SYS. This is the only reset signal that will reset the SRC fields. 0=RESET_ESPI." "0: RESET_ESPI,1: RESET_SYS,2: RESET_SIO,3: PLTRST" hexmask.long.byte 0x24 0.--7. 1. "IND,The Index for SRC0 SRC1 SRC2 and SRC3. When the Index field of an incoming Master-to-Slave Virtual Wire transaction matches this value the fields SRC0 SRC1 SRC2 and SRC3 are updated by the data contained in the respective bit positions in.." line.long 0x28 "MSVW03_DW1,Master-to-Slave Virtual Wire 3 Register (DW 1)" hexmask.long.byte 0x28 24.--27. 1. "SRC3IRQ_SEL,A change in the value of SRC3 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." hexmask.long.byte 0x28 16.--19. 1. "SRC2IRQ_SEL,A change in the value of SRC2 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." hexmask.long.byte 0x28 8.--11. 1. "SRC1IRQ_SEL,A change in the value of SRC1 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." hexmask.long.byte 0x28 0.--3. 1. "SRC0IRQ_SEL,A change in the value of SRC0 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." line.long 0x2C "MSVW03_DW2,Master-to-Slave Virtual Wire 3 Register (DW 2)" bitfld.long 0x2C 24. "SRC3,Master-to-Slave data for Bit Position 3 for the virtual wire associated with the index defined by INDEX." "0,1" bitfld.long 0x2C 16. "SRC2,Master-to-Slave data for Bit Position 2 for the virtual wire associated with the index defined by INDEX." "0,1" bitfld.long 0x2C 8. "SRC1,Master-to-Slave data for Bit Position 1 for the virtual wire associated with the index defined by INDEX." "0,1" bitfld.long 0x2C 0. "SRC0,Master-to-Slave data for Bit Position 0 for the virtual wire associated with the index defined by INDEX." "0,1" line.long 0x30 "MSVW04_DW0,Master-to-Slave Virtual Wire 4 Register (DW 0)" hexmask.long.byte 0x30 12.--15. 1. "MTOS_R_STATE,The four bits in this field are loaded into SRC0 SRC1 SRC2 and SRC3 when the reset signal selected by M2S RESET SRC is asserted. If MTOS_SRC is set for RESET_SYS the SRC bits are set to the default value of this field rather than.." bitfld.long 0x30 8.--9. "MTOS_SRC,This field determines which reset signal in addition to RESET_SYS resets SRC[3:0] in this register: 3=PLTRST 2=RESET_SIO 1=RESET_SYS. This is the only reset signal that will reset the SRC fields. 0=RESET_ESPI." "0: RESET_ESPI,1: RESET_SYS,2: RESET_SIO,3: PLTRST" hexmask.long.byte 0x30 0.--7. 1. "IND,The Index for SRC0 SRC1 SRC2 and SRC3. When the Index field of an incoming Master-to-Slave Virtual Wire transaction matches this value the fields SRC0 SRC1 SRC2 and SRC3 are updated by the data contained in the respective bit positions in.." line.long 0x34 "MSVW04_DW1,Master-to-Slave Virtual Wire 4 Register (DW 1)" hexmask.long.byte 0x34 24.--27. 1. "SRC3IRQ_SEL,A change in the value of SRC3 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." hexmask.long.byte 0x34 16.--19. 1. "SRC2IRQ_SEL,A change in the value of SRC2 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." hexmask.long.byte 0x34 8.--11. 1. "SRC1IRQ_SEL,A change in the value of SRC1 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." hexmask.long.byte 0x34 0.--3. 1. "SRC0IRQ_SEL,A change in the value of SRC0 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." line.long 0x38 "MSVW04_DW2,Master-to-Slave Virtual Wire 4 Register (DW 2)" bitfld.long 0x38 24. "SRC3,Master-to-Slave data for Bit Position 3 for the virtual wire associated with the index defined by INDEX." "0,1" bitfld.long 0x38 16. "SRC2,Master-to-Slave data for Bit Position 2 for the virtual wire associated with the index defined by INDEX." "0,1" bitfld.long 0x38 8. "SRC1,Master-to-Slave data for Bit Position 1 for the virtual wire associated with the index defined by INDEX." "0,1" bitfld.long 0x38 0. "SRC0,Master-to-Slave data for Bit Position 0 for the virtual wire associated with the index defined by INDEX." "0,1" line.long 0x3C "MSVW05_DW0,Master-to-Slave Virtual Wire 5 Register (DW 0)" hexmask.long.byte 0x3C 12.--15. 1. "MTOS_R_STATE,The four bits in this field are loaded into SRC0 SRC1 SRC2 and SRC3 when the reset signal selected by M2S RESET SRC is asserted. If MTOS_SRC is set for RESET_SYS the SRC bits are set to the default value of this field rather than.." bitfld.long 0x3C 8.--9. "MTOS_SRC,This field determines which reset signal in addition to RESET_SYS resets SRC[3:0] in this register: 3=PLTRST 2=RESET_SIO 1=RESET_SYS. This is the only reset signal that will reset the SRC fields. 0=RESET_ESPI." "0: RESET_ESPI,1: RESET_SYS,2: RESET_SIO,3: PLTRST" hexmask.long.byte 0x3C 0.--7. 1. "IND,The Index for SRC0 SRC1 SRC2 and SRC3. When the Index field of an incoming Master-to-Slave Virtual Wire transaction matches this value the fields SRC0 SRC1 SRC2 and SRC3 are updated by the data contained in the respective bit positions in.." line.long 0x40 "MSVW05_DW1,Master-to-Slave Virtual Wire 5 Register (DW 1)" hexmask.long.byte 0x40 24.--27. 1. "SRC3IRQ_SEL,A change in the value of SRC3 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." hexmask.long.byte 0x40 16.--19. 1. "SRC2IRQ_SEL,A change in the value of SRC2 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." hexmask.long.byte 0x40 8.--11. 1. "SRC1IRQ_SEL,A change in the value of SRC1 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." hexmask.long.byte 0x40 0.--3. 1. "SRC0IRQ_SEL,A change in the value of SRC0 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." line.long 0x44 "MSVW05_DW2,Master-to-Slave Virtual Wire 5 Register (DW 2)" bitfld.long 0x44 24. "SRC3,Master-to-Slave data for Bit Position 3 for the virtual wire associated with the index defined by INDEX." "0,1" bitfld.long 0x44 16. "SRC2,Master-to-Slave data for Bit Position 2 for the virtual wire associated with the index defined by INDEX." "0,1" bitfld.long 0x44 8. "SRC1,Master-to-Slave data for Bit Position 1 for the virtual wire associated with the index defined by INDEX." "0,1" bitfld.long 0x44 0. "SRC0,Master-to-Slave data for Bit Position 0 for the virtual wire associated with the index defined by INDEX." "0,1" line.long 0x48 "MSVW06_DW0,Master-to-Slave Virtual Wire 6 Register (DW 0)" hexmask.long.byte 0x48 12.--15. 1. "MTOS_R_STATE,The four bits in this field are loaded into SRC0 SRC1 SRC2 and SRC3 when the reset signal selected by M2S RESET SRC is asserted. If MTOS_SRC is set for RESET_SYS the SRC bits are set to the default value of this field rather than.." bitfld.long 0x48 8.--9. "MTOS_SRC,This field determines which reset signal in addition to RESET_SYS resets SRC[3:0] in this register: 3=PLTRST 2=RESET_SIO 1=RESET_SYS. This is the only reset signal that will reset the SRC fields. 0=RESET_ESPI." "0: RESET_ESPI,1: RESET_SYS,2: RESET_SIO,3: PLTRST" hexmask.long.byte 0x48 0.--7. 1. "IND,The Index for SRC0 SRC1 SRC2 and SRC3. When the Index field of an incoming Master-to-Slave Virtual Wire transaction matches this value the fields SRC0 SRC1 SRC2 and SRC3 are updated by the data contained in the respective bit positions in.." line.long 0x4C "MSVW06_DW1,Master-to-Slave Virtual Wire 6 Register (DW 1)" hexmask.long.byte 0x4C 24.--27. 1. "SRC3IRQ_SEL,A change in the value of SRC3 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." hexmask.long.byte 0x4C 16.--19. 1. "SRC2IRQ_SEL,A change in the value of SRC2 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." hexmask.long.byte 0x4C 8.--11. 1. "SRC1IRQ_SEL,A change in the value of SRC1 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." hexmask.long.byte 0x4C 0.--3. 1. "SRC0IRQ_SEL,A change in the value of SRC0 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." line.long 0x50 "MSVW06_DW2,Master-to-Slave Virtual Wire 6 Register (DW 2)" bitfld.long 0x50 24. "SRC3,Master-to-Slave data for Bit Position 3 for the virtual wire associated with the index defined by INDEX." "0,1" bitfld.long 0x50 16. "SRC2,Master-to-Slave data for Bit Position 2 for the virtual wire associated with the index defined by INDEX." "0,1" bitfld.long 0x50 8. "SRC1,Master-to-Slave data for Bit Position 1 for the virtual wire associated with the index defined by INDEX." "0,1" bitfld.long 0x50 0. "SRC0,Master-to-Slave data for Bit Position 0 for the virtual wire associated with the index defined by INDEX." "0,1" tree.end tree "ESPI_MSVW07_10" base ad:0x400F9C54 group.long 0x0++0x2F line.long 0x0 "MSVW07_DW0,Master-to-Slave Virtual Wire 7 Register (DW 0)" hexmask.long.byte 0x0 12.--15. 1. "MTOS_R_STATE,The four bits in this field are loaded into SRC0 SRC1 SRC2 and SRC3 when the reset signal selected by M2S RESET SRC is asserted. If MTOS_SRC is set for RESET_SYS the SRC bits are set to the default value of this field rather than.." bitfld.long 0x0 8.--9. "MTOS_SRC,This field determines which reset signal in addition to RESET_SYS resets SRC[3:0] in this register: 3=PLTRST 2=RESET_SIO 1=RESET_SYS. This is the only reset signal that will reset the SRC fields. 0=RESET_ESPI." "0: RESET_ESPI,1: RESET_SYS,2: RESET_SIO,3: PLTRST" hexmask.long.byte 0x0 0.--7. 1. "IND,The Index for SRC0 SRC1 SRC2 and SRC3. When the Index field of an incoming Master-to-Slave Virtual Wire transaction matches this value the fields SRC0 SRC1 SRC2 and SRC3 are updated by the data contained in the respective bit positions in.." line.long 0x4 "MSVW07_DW1,Master-to-Slave Virtual Wire 7 Register (DW 1)" hexmask.long.byte 0x4 24.--27. 1. "SRC3IRQ_SEL,A change in the value of SRC3 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." hexmask.long.byte 0x4 16.--19. 1. "SRC2IRQ_SEL,A change in the value of SRC2 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." hexmask.long.byte 0x4 8.--11. 1. "SRC1IRQ_SEL,A change in the value of SRC1 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." hexmask.long.byte 0x4 0.--3. 1. "SRC0IRQ_SEL,A change in the value of SRC0 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." line.long 0x8 "MSVW07_DW2,Master-to-Slave Virtual Wire 7 Register (DW 2)" bitfld.long 0x8 24. "SRC3,Master-to-Slave data for Bit Position 3 for the virtual wire associated with the index defined by INDEX." "0,1" bitfld.long 0x8 16. "SRC2,Master-to-Slave data for Bit Position 2 for the virtual wire associated with the index defined by INDEX." "0,1" bitfld.long 0x8 8. "SRC1,Master-to-Slave data for Bit Position 1 for the virtual wire associated with the index defined by INDEX." "0,1" bitfld.long 0x8 0. "SRC0,Master-to-Slave data for Bit Position 0 for the virtual wire associated with the index defined by INDEX." "0,1" line.long 0xC "MSVW08_DW0,Master-to-Slave Virtual Wire 8 Register (DW 0)" hexmask.long.byte 0xC 12.--15. 1. "MTOS_R_STATE,The four bits in this field are loaded into SRC0 SRC1 SRC2 and SRC3 when the reset signal selected by M2S RESET SRC is asserted. If MTOS_SRC is set for RESET_SYS the SRC bits are set to the default value of this field rather than.." bitfld.long 0xC 8.--9. "MTOS_SRC,This field determines which reset signal in addition to RESET_SYS resets SRC[3:0] in this register: 3=PLTRST 2=RESET_SIO 1=RESET_SYS. This is the only reset signal that will reset the SRC fields. 0=RESET_ESPI." "0: RESET_ESPI,1: RESET_SYS,2: RESET_SIO,3: PLTRST" hexmask.long.byte 0xC 0.--7. 1. "IND,The Index for SRC0 SRC1 SRC2 and SRC3. When the Index field of an incoming Master-to-Slave Virtual Wire transaction matches this value the fields SRC0 SRC1 SRC2 and SRC3 are updated by the data contained in the respective bit positions in.." line.long 0x10 "MSVW08_DW1,Master-to-Slave Virtual Wire 8 Register (DW 1)" hexmask.long.byte 0x10 24.--27. 1. "SRC3IRQ_SEL,A change in the value of SRC3 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." hexmask.long.byte 0x10 16.--19. 1. "SRC2IRQ_SEL,A change in the value of SRC2 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." hexmask.long.byte 0x10 8.--11. 1. "SRC1IRQ_SEL,A change in the value of SRC1 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." hexmask.long.byte 0x10 0.--3. 1. "SRC0IRQ_SEL,A change in the value of SRC0 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." line.long 0x14 "MSVW08_DW2,Master-to-Slave Virtual Wire 8 Register (DW 2)" bitfld.long 0x14 24. "SRC3,Master-to-Slave data for Bit Position 3 for the virtual wire associated with the index defined by INDEX." "0,1" bitfld.long 0x14 16. "SRC2,Master-to-Slave data for Bit Position 2 for the virtual wire associated with the index defined by INDEX." "0,1" bitfld.long 0x14 8. "SRC1,Master-to-Slave data for Bit Position 1 for the virtual wire associated with the index defined by INDEX." "0,1" bitfld.long 0x14 0. "SRC0,Master-to-Slave data for Bit Position 0 for the virtual wire associated with the index defined by INDEX." "0,1" line.long 0x18 "MSVW09_DW0,Master-to-Slave Virtual Wire 9 Register (DW 0)" hexmask.long.byte 0x18 12.--15. 1. "MTOS_R_STATE,The four bits in this field are loaded into SRC0 SRC1 SRC2 and SRC3 when the reset signal selected by M2S RESET SRC is asserted. If MTOS_SRC is set for RESET_SYS the SRC bits are set to the default value of this field rather than.." bitfld.long 0x18 8.--9. "MTOS_SRC,This field determines which reset signal in addition to RESET_SYS resets SRC[3:0] in this register: 3=PLTRST 2=RESET_SIO 1=RESET_SYS. This is the only reset signal that will reset the SRC fields. 0=RESET_ESPI." "0: RESET_ESPI,1: RESET_SYS,2: RESET_SIO,3: PLTRST" hexmask.long.byte 0x18 0.--7. 1. "IND,The Index for SRC0 SRC1 SRC2 and SRC3. When the Index field of an incoming Master-to-Slave Virtual Wire transaction matches this value the fields SRC0 SRC1 SRC2 and SRC3 are updated by the data contained in the respective bit positions in.." line.long 0x1C "MSVW09_DW1,Master-to-Slave Virtual Wire 9 Register (DW 1)" hexmask.long.byte 0x1C 24.--27. 1. "SRC3IRQ_SEL,A change in the value of SRC3 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." hexmask.long.byte 0x1C 16.--19. 1. "SRC2IRQ_SEL,A change in the value of SRC2 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." hexmask.long.byte 0x1C 8.--11. 1. "SRC1IRQ_SEL,A change in the value of SRC1 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." hexmask.long.byte 0x1C 0.--3. 1. "SRC0IRQ_SEL,A change in the value of SRC0 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." line.long 0x20 "MSVW09_DW2,Master-to-Slave Virtual Wire 9 Register (DW 2)" bitfld.long 0x20 24. "SRC3,Master-to-Slave data for Bit Position 3 for the virtual wire associated with the index defined by INDEX." "0,1" bitfld.long 0x20 16. "SRC2,Master-to-Slave data for Bit Position 2 for the virtual wire associated with the index defined by INDEX." "0,1" bitfld.long 0x20 8. "SRC1,Master-to-Slave data for Bit Position 1 for the virtual wire associated with the index defined by INDEX." "0,1" bitfld.long 0x20 0. "SRC0,Master-to-Slave data for Bit Position 0 for the virtual wire associated with the index defined by INDEX." "0,1" line.long 0x24 "MSVW10_DW0,Master-to-Slave Virtual Wire 10 Register (DW 0)" hexmask.long.byte 0x24 12.--15. 1. "MTOS_R_STATE,The four bits in this field are loaded into SRC0 SRC1 SRC2 and SRC3 when the reset signal selected by M2S RESET SRC is asserted. If MTOS_SRC is set for RESET_SYS the SRC bits are set to the default value of this field rather than.." bitfld.long 0x24 8.--9. "MTOS_SRC,This field determines which reset signal in addition to RESET_SYS resets SRC[3:0] in this register: 3=PLTRST 2=RESET_SIO 1=RESET_SYS. This is the only reset signal that will reset the SRC fields. 0=RESET_ESPI." "0: RESET_ESPI,1: RESET_SYS,2: RESET_SIO,3: PLTRST" hexmask.long.byte 0x24 0.--7. 1. "IND,The Index for SRC0 SRC1 SRC2 and SRC3. When the Index field of an incoming Master-to-Slave Virtual Wire transaction matches this value the fields SRC0 SRC1 SRC2 and SRC3 are updated by the data contained in the respective bit positions in.." line.long 0x28 "MSVW10_DW1,Master-to-Slave Virtual Wire 10 Register (DW 1)" hexmask.long.byte 0x28 24.--27. 1. "SRC3IRQ_SEL,A change in the value of SRC3 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." hexmask.long.byte 0x28 16.--19. 1. "SRC2IRQ_SEL,A change in the value of SRC2 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." hexmask.long.byte 0x28 8.--11. 1. "SRC1IRQ_SEL,A change in the value of SRC1 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." hexmask.long.byte 0x28 0.--3. 1. "SRC0IRQ_SEL,A change in the value of SRC0 will generate an interrupt to the EC. Changes in the SRC register value caused by a Reset Event do not generate an interrupt." line.long 0x2C "MSVW10_DW2,Master-to-Slave Virtual Wire 10 Register (DW 2)" bitfld.long 0x2C 24. "SRC3,Master-to-Slave data for Bit Position 3 for the virtual wire associated with the index defined by INDEX." "0,1" bitfld.long 0x2C 16. "SRC2,Master-to-Slave data for Bit Position 2 for the virtual wire associated with the index defined by INDEX." "0,1" bitfld.long 0x2C 8. "SRC1,Master-to-Slave data for Bit Position 1 for the virtual wire associated with the index defined by INDEX." "0,1" bitfld.long 0x2C 0. "SRC0,Master-to-Slave data for Bit Position 0 for the virtual wire associated with the index defined by INDEX." "0,1" tree.end tree "ESPI_SCRATCH" base ad:0x400FBC00 group.long 0x0++0x1F line.long 0x0 "SCRATCH0,Scratch 0 Register" hexmask.long 0x0 0.--31. 1. "SCR0,This field has no functionality other than storage. This register is aliased to ESPI Config Scratch Register." line.long 0x4 "SCRATCH1,Scratch 1 Register" hexmask.long 0x4 0.--31. 1. "SCR1,This field has no functionality other than storage. This register is aliased to ESPI Config Scratch Register." line.long 0x8 "SCRATCH2,Scratch 2 Register" hexmask.long 0x8 0.--31. 1. "SCR2,This field has no functionality other than storage. This register is aliased to ESPI Config Scratch Register." line.long 0xC "SCRATCH3,Scratch 3 Register" hexmask.long 0xC 0.--31. 1. "SCR3,This field has no functionality other than storage. This register is aliased to ESPI Config Scratch Register." line.long 0x10 "SCRATCH4,Scratch 4 Register" hexmask.long 0x10 0.--31. 1. "SCR4,This field has no functionality other than storage. This register is aliased to ESPI Config Scratch Register." line.long 0x14 "SCRATCH5,Scratch 5 Register" hexmask.long 0x14 0.--31. 1. "SCR5,This field has no functionality other than storage. This register is aliased to ESPI Config Scratch Register." line.long 0x18 "SCRATCH6,Scratch 6 Register" hexmask.long 0x18 0.--31. 1. "SCR6,This field has no functionality other than storage. This register is aliased to ESPI Config Scratch Register." line.long 0x1C "SCRATCH7,Scratch 7 Register" hexmask.long 0x1C 0.--31. 1. "SCR7,This field has no functionality other than storage. This register is aliased to ESPI Config Scratch Register." tree.end tree "ESPI_SMVW00_10" base ad:0x400F9E00 group.long 0x0++0x57 line.long 0x0 "SMVW00_DW0,Slave-to-Master Virtual Wire 0 Register (DWord 0)" bitfld.long 0x0 19. "CHNG3,This bit is set to 1 whenever the value in Bit3 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" bitfld.long 0x0 18. "CHNG2,This bit is set to 1 whenever the value in Bit2 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" bitfld.long 0x0 17. "CHNG1,This bit is set to 1 whenever the value in Bit1 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" bitfld.long 0x0 16. "CHNG0,This bit is set to 1 whenever the value in Bit0 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" hexmask.long.byte 0x0 12.--15. 1. "STOM_R_STATE,The four bits in this field are loaded into SRC0 SRC1 SRC2 and SRC3 when the reset signal selected by S2M RESET SRC is asserted. If STOM_SRC is set for RESET_SYS the SRC bits are set to the default value of this field rather than.." bitfld.long 0x0 8.--9. "STOM_SRC,This field determines which reset signal in addition to RESET_SYS resets SRC[3:0] in this register: 3=PLTRST 2=RESET_SIO 1=RESET_SYS. This is the only reset signal that will reset the SRC fields. 0=RESET_ESPI." "0: RESET_ESPI,1: RESET_SYS,2: RESET_SIO,3: PLTRST" hexmask.long.byte 0x0 0.--7. 1. "IND,The Index for SRC0 SRC1 SRC2 and SRC3. A write to this register that changes the value of any one or more of SRC0 SRC1 SRC2 or SRC3 will generate a Slave-to-Master Virtual Wire transaction with this index. Setting the INDEX field to 0.." line.long 0x4 "SMVW00_DW1,Slave-to-Master Virtual Wire 0 Register (DWord 1)" bitfld.long 0x4 24. "SRC3,Slave-to-Master data for Bit Position 3 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" bitfld.long 0x4 16. "SRC2,Slave-to-Master data for Bit Position 2 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" bitfld.long 0x4 8. "SRC1,Slave-to-Master data for Bit Position 1 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" bitfld.long 0x4 0. "SRC0,Slave-to-Master data for Bit Position 0 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" line.long 0x8 "SMVW01_DW0,Slave-to-Master Virtual Wire 1 Register (DWord 0)" bitfld.long 0x8 19. "CHNG3,This bit is set to 1 whenever the value in Bit3 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" bitfld.long 0x8 18. "CHNG2,This bit is set to 1 whenever the value in Bit2 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" bitfld.long 0x8 17. "CHNG1,This bit is set to 1 whenever the value in Bit1 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" bitfld.long 0x8 16. "CHNG0,This bit is set to 1 whenever the value in Bit0 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" hexmask.long.byte 0x8 12.--15. 1. "STOM_R_STATE,The four bits in this field are loaded into SRC0 SRC1 SRC2 and SRC3 when the reset signal selected by S2M RESET SRC is asserted. If STOM_SRC is set for RESET_SYS the SRC bits are set to the default value of this field rather than.." bitfld.long 0x8 8.--9. "STOM_SRC,This field determines which reset signal in addition to RESET_SYS resets SRC[3:0] in this register: 3=PLTRST 2=RESET_SIO 1=RESET_SYS. This is the only reset signal that will reset the SRC fields. 0=RESET_ESPI." "0: RESET_ESPI,1: RESET_SYS,2: RESET_SIO,3: PLTRST" hexmask.long.byte 0x8 0.--7. 1. "IND,The Index for SRC0 SRC1 SRC2 and SRC3. A write to this register that changes the value of any one or more of SRC0 SRC1 SRC2 or SRC3 will generate a Slave-to-Master Virtual Wire transaction with this index. Setting the INDEX field to 0.." line.long 0xC "SMVW01_DW1,Slave-to-Master Virtual Wire 1 Register (DWord 1)" bitfld.long 0xC 24. "SRC3,Slave-to-Master data for Bit Position 3 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" bitfld.long 0xC 16. "SRC2,Slave-to-Master data for Bit Position 2 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" bitfld.long 0xC 8. "SRC1,Slave-to-Master data for Bit Position 1 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" bitfld.long 0xC 0. "SRC0,Slave-to-Master data for Bit Position 0 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" line.long 0x10 "SMVW02_DW0,Slave-to-Master Virtual Wire 2 Register (DWord 0)" bitfld.long 0x10 19. "CHNG3,This bit is set to 1 whenever the value in Bit3 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" bitfld.long 0x10 18. "CHNG2,This bit is set to 1 whenever the value in Bit2 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" bitfld.long 0x10 17. "CHNG1,This bit is set to 1 whenever the value in Bit1 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" bitfld.long 0x10 16. "CHNG0,This bit is set to 1 whenever the value in Bit0 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" hexmask.long.byte 0x10 12.--15. 1. "STOM_R_STATE,The four bits in this field are loaded into SRC0 SRC1 SRC2 and SRC3 when the reset signal selected by S2M RESET SRC is asserted. If STOM_SRC is set for RESET_SYS the SRC bits are set to the default value of this field rather than.." bitfld.long 0x10 8.--9. "STOM_SRC,This field determines which reset signal in addition to RESET_SYS resets SRC[3:0] in this register: 3=PLTRST 2=RESET_SIO 1=RESET_SYS. This is the only reset signal that will reset the SRC fields. 0=RESET_ESPI." "0: RESET_ESPI,1: RESET_SYS,2: RESET_SIO,3: PLTRST" hexmask.long.byte 0x10 0.--7. 1. "IND,The Index for SRC0 SRC1 SRC2 and SRC3. A write to this register that changes the value of any one or more of SRC0 SRC1 SRC2 or SRC3 will generate a Slave-to-Master Virtual Wire transaction with this index. Setting the INDEX field to 0.." line.long 0x14 "SMVW02_DW1,Slave-to-Master Virtual Wire 2 Register (DWord 1)" bitfld.long 0x14 24. "SRC3,Slave-to-Master data for Bit Position 3 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" bitfld.long 0x14 16. "SRC2,Slave-to-Master data for Bit Position 2 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" bitfld.long 0x14 8. "SRC1,Slave-to-Master data for Bit Position 1 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" bitfld.long 0x14 0. "SRC0,Slave-to-Master data for Bit Position 0 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" line.long 0x18 "SMVW03_DW0,Slave-to-Master Virtual Wire 3 Register (DWord 0)" bitfld.long 0x18 19. "CHNG3,This bit is set to 1 whenever the value in Bit3 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" bitfld.long 0x18 18. "CHNG2,This bit is set to 1 whenever the value in Bit2 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" bitfld.long 0x18 17. "CHNG1,This bit is set to 1 whenever the value in Bit1 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" bitfld.long 0x18 16. "CHNG0,This bit is set to 1 whenever the value in Bit0 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" hexmask.long.byte 0x18 12.--15. 1. "STOM_R_STATE,The four bits in this field are loaded into SRC0 SRC1 SRC2 and SRC3 when the reset signal selected by S2M RESET SRC is asserted. If STOM_SRC is set for RESET_SYS the SRC bits are set to the default value of this field rather than.." bitfld.long 0x18 8.--9. "STOM_SRC,This field determines which reset signal in addition to RESET_SYS resets SRC[3:0] in this register: 3=PLTRST 2=RESET_SIO 1=RESET_SYS. This is the only reset signal that will reset the SRC fields. 0=RESET_ESPI." "0: RESET_ESPI,1: RESET_SYS,2: RESET_SIO,3: PLTRST" hexmask.long.byte 0x18 0.--7. 1. "IND,The Index for SRC0 SRC1 SRC2 and SRC3. A write to this register that changes the value of any one or more of SRC0 SRC1 SRC2 or SRC3 will generate a Slave-to-Master Virtual Wire transaction with this index. Setting the INDEX field to 0.." line.long 0x1C "SMVW03_DW1,Slave-to-Master Virtual Wire 3 Register (DWord 1)" bitfld.long 0x1C 24. "SRC3,Slave-to-Master data for Bit Position 3 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" bitfld.long 0x1C 16. "SRC2,Slave-to-Master data for Bit Position 2 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" bitfld.long 0x1C 8. "SRC1,Slave-to-Master data for Bit Position 1 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" bitfld.long 0x1C 0. "SRC0,Slave-to-Master data for Bit Position 0 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" line.long 0x20 "SMVW04_DW0,Slave-to-Master Virtual Wire 4 Register (DWord 0)" bitfld.long 0x20 19. "CHNG3,This bit is set to 1 whenever the value in Bit3 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" bitfld.long 0x20 18. "CHNG2,This bit is set to 1 whenever the value in Bit2 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" bitfld.long 0x20 17. "CHNG1,This bit is set to 1 whenever the value in Bit1 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" bitfld.long 0x20 16. "CHNG0,This bit is set to 1 whenever the value in Bit0 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" hexmask.long.byte 0x20 12.--15. 1. "STOM_R_STATE,The four bits in this field are loaded into SRC0 SRC1 SRC2 and SRC3 when the reset signal selected by S2M RESET SRC is asserted. If STOM_SRC is set for RESET_SYS the SRC bits are set to the default value of this field rather than.." bitfld.long 0x20 8.--9. "STOM_SRC,This field determines which reset signal in addition to RESET_SYS resets SRC[3:0] in this register: 3=PLTRST 2=RESET_SIO 1=RESET_SYS. This is the only reset signal that will reset the SRC fields. 0=RESET_ESPI." "0: RESET_ESPI,1: RESET_SYS,2: RESET_SIO,3: PLTRST" hexmask.long.byte 0x20 0.--7. 1. "IND,The Index for SRC0 SRC1 SRC2 and SRC3. A write to this register that changes the value of any one or more of SRC0 SRC1 SRC2 or SRC3 will generate a Slave-to-Master Virtual Wire transaction with this index. Setting the INDEX field to 0.." line.long 0x24 "SMVW04_DW1,Slave-to-Master Virtual Wire 4 Register (DWord 1)" bitfld.long 0x24 24. "SRC3,Slave-to-Master data for Bit Position 3 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" bitfld.long 0x24 16. "SRC2,Slave-to-Master data for Bit Position 2 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" bitfld.long 0x24 8. "SRC1,Slave-to-Master data for Bit Position 1 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" bitfld.long 0x24 0. "SRC0,Slave-to-Master data for Bit Position 0 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" line.long 0x28 "SMVW05_DW0,Slave-to-Master Virtual Wire 5 Register (DWord 0)" bitfld.long 0x28 19. "CHNG3,This bit is set to 1 whenever the value in Bit3 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" bitfld.long 0x28 18. "CHNG2,This bit is set to 1 whenever the value in Bit2 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" bitfld.long 0x28 17. "CHNG1,This bit is set to 1 whenever the value in Bit1 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" bitfld.long 0x28 16. "CHNG0,This bit is set to 1 whenever the value in Bit0 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" hexmask.long.byte 0x28 12.--15. 1. "STOM_R_STATE,The four bits in this field are loaded into SRC0 SRC1 SRC2 and SRC3 when the reset signal selected by S2M RESET SRC is asserted. If STOM_SRC is set for RESET_SYS the SRC bits are set to the default value of this field rather than.." bitfld.long 0x28 8.--9. "STOM_SRC,This field determines which reset signal in addition to RESET_SYS resets SRC[3:0] in this register: 3=PLTRST 2=RESET_SIO 1=RESET_SYS. This is the only reset signal that will reset the SRC fields. 0=RESET_ESPI." "0: RESET_ESPI,1: RESET_SYS,2: RESET_SIO,3: PLTRST" hexmask.long.byte 0x28 0.--7. 1. "IND,The Index for SRC0 SRC1 SRC2 and SRC3. A write to this register that changes the value of any one or more of SRC0 SRC1 SRC2 or SRC3 will generate a Slave-to-Master Virtual Wire transaction with this index. Setting the INDEX field to 0.." line.long 0x2C "SMVW05_DW1,Slave-to-Master Virtual Wire 5 Register (DWord 1)" bitfld.long 0x2C 24. "SRC3,Slave-to-Master data for Bit Position 3 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" bitfld.long 0x2C 16. "SRC2,Slave-to-Master data for Bit Position 2 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" bitfld.long 0x2C 8. "SRC1,Slave-to-Master data for Bit Position 1 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" bitfld.long 0x2C 0. "SRC0,Slave-to-Master data for Bit Position 0 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" line.long 0x30 "SMVW06_DW0,Slave-to-Master Virtual Wire 6 Register (DWord 0)" bitfld.long 0x30 19. "CHNG3,This bit is set to 1 whenever the value in Bit3 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" bitfld.long 0x30 18. "CHNG2,This bit is set to 1 whenever the value in Bit2 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" bitfld.long 0x30 17. "CHNG1,This bit is set to 1 whenever the value in Bit1 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" bitfld.long 0x30 16. "CHNG0,This bit is set to 1 whenever the value in Bit0 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" hexmask.long.byte 0x30 12.--15. 1. "STOM_R_STATE,The four bits in this field are loaded into SRC0 SRC1 SRC2 and SRC3 when the reset signal selected by S2M RESET SRC is asserted. If STOM_SRC is set for RESET_SYS the SRC bits are set to the default value of this field rather than.." bitfld.long 0x30 8.--9. "STOM_SRC,This field determines which reset signal in addition to RESET_SYS resets SRC[3:0] in this register: 3=PLTRST 2=RESET_SIO 1=RESET_SYS. This is the only reset signal that will reset the SRC fields. 0=RESET_ESPI." "0: RESET_ESPI,1: RESET_SYS,2: RESET_SIO,3: PLTRST" hexmask.long.byte 0x30 0.--7. 1. "IND,The Index for SRC0 SRC1 SRC2 and SRC3. A write to this register that changes the value of any one or more of SRC0 SRC1 SRC2 or SRC3 will generate a Slave-to-Master Virtual Wire transaction with this index. Setting the INDEX field to 0.." line.long 0x34 "SMVW06_DW1,Slave-to-Master Virtual Wire 6 Register (DWord 1)" bitfld.long 0x34 24. "SRC3,Slave-to-Master data for Bit Position 3 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" bitfld.long 0x34 16. "SRC2,Slave-to-Master data for Bit Position 2 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" bitfld.long 0x34 8. "SRC1,Slave-to-Master data for Bit Position 1 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" bitfld.long 0x34 0. "SRC0,Slave-to-Master data for Bit Position 0 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" line.long 0x38 "SMVW07_DW0,Slave-to-Master Virtual Wire 7 Register (DWord 0)" bitfld.long 0x38 19. "CHNG3,This bit is set to 1 whenever the value in Bit3 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" bitfld.long 0x38 18. "CHNG2,This bit is set to 1 whenever the value in Bit2 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" bitfld.long 0x38 17. "CHNG1,This bit is set to 1 whenever the value in Bit1 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" bitfld.long 0x38 16. "CHNG0,This bit is set to 1 whenever the value in Bit0 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" hexmask.long.byte 0x38 12.--15. 1. "STOM_R_STATE,The four bits in this field are loaded into SRC0 SRC1 SRC2 and SRC3 when the reset signal selected by S2M RESET SRC is asserted. If STOM_SRC is set for RESET_SYS the SRC bits are set to the default value of this field rather than.." bitfld.long 0x38 8.--9. "STOM_SRC,This field determines which reset signal in addition to RESET_SYS resets SRC[3:0] in this register: 3=PLTRST 2=RESET_SIO 1=RESET_SYS. This is the only reset signal that will reset the SRC fields. 0=RESET_ESPI." "0: RESET_ESPI,1: RESET_SYS,2: RESET_SIO,3: PLTRST" hexmask.long.byte 0x38 0.--7. 1. "IND,The Index for SRC0 SRC1 SRC2 and SRC3. A write to this register that changes the value of any one or more of SRC0 SRC1 SRC2 or SRC3 will generate a Slave-to-Master Virtual Wire transaction with this index. Setting the INDEX field to 0.." line.long 0x3C "SMVW07_DW1,Slave-to-Master Virtual Wire 7 Register (DWord 1)" bitfld.long 0x3C 24. "SRC3,Slave-to-Master data for Bit Position 3 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" bitfld.long 0x3C 16. "SRC2,Slave-to-Master data for Bit Position 2 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" bitfld.long 0x3C 8. "SRC1,Slave-to-Master data for Bit Position 1 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" bitfld.long 0x3C 0. "SRC0,Slave-to-Master data for Bit Position 0 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" line.long 0x40 "SMVW08_DW0,Slave-to-Master Virtual Wire 8 Register (DWord 0)" bitfld.long 0x40 19. "CHNG3,This bit is set to 1 whenever the value in Bit3 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" bitfld.long 0x40 18. "CHNG2,This bit is set to 1 whenever the value in Bit2 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" bitfld.long 0x40 17. "CHNG1,This bit is set to 1 whenever the value in Bit1 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" bitfld.long 0x40 16. "CHNG0,This bit is set to 1 whenever the value in Bit0 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" hexmask.long.byte 0x40 12.--15. 1. "STOM_R_STATE,The four bits in this field are loaded into SRC0 SRC1 SRC2 and SRC3 when the reset signal selected by S2M RESET SRC is asserted. If STOM_SRC is set for RESET_SYS the SRC bits are set to the default value of this field rather than.." bitfld.long 0x40 8.--9. "STOM_SRC,This field determines which reset signal in addition to RESET_SYS resets SRC[3:0] in this register: 3=PLTRST 2=RESET_SIO 1=RESET_SYS. This is the only reset signal that will reset the SRC fields. 0=RESET_ESPI." "0: RESET_ESPI,1: RESET_SYS,2: RESET_SIO,3: PLTRST" hexmask.long.byte 0x40 0.--7. 1. "IND,The Index for SRC0 SRC1 SRC2 and SRC3. A write to this register that changes the value of any one or more of SRC0 SRC1 SRC2 or SRC3 will generate a Slave-to-Master Virtual Wire transaction with this index. Setting the INDEX field to 0.." line.long 0x44 "SMVW08_DW1,Slave-to-Master Virtual Wire 8 Register (DWord 1)" bitfld.long 0x44 24. "SRC3,Slave-to-Master data for Bit Position 3 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" bitfld.long 0x44 16. "SRC2,Slave-to-Master data for Bit Position 2 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" bitfld.long 0x44 8. "SRC1,Slave-to-Master data for Bit Position 1 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" bitfld.long 0x44 0. "SRC0,Slave-to-Master data for Bit Position 0 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" line.long 0x48 "SMVW09_DW0,Slave-to-Master Virtual Wire 9 Register (DWord 0)" bitfld.long 0x48 19. "CHNG3,This bit is set to 1 whenever the value in Bit3 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" bitfld.long 0x48 18. "CHNG2,This bit is set to 1 whenever the value in Bit2 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" bitfld.long 0x48 17. "CHNG1,This bit is set to 1 whenever the value in Bit1 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" bitfld.long 0x48 16. "CHNG0,This bit is set to 1 whenever the value in Bit0 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" hexmask.long.byte 0x48 12.--15. 1. "STOM_R_STATE,The four bits in this field are loaded into SRC0 SRC1 SRC2 and SRC3 when the reset signal selected by S2M RESET SRC is asserted. If STOM_SRC is set for RESET_SYS the SRC bits are set to the default value of this field rather than.." bitfld.long 0x48 8.--9. "STOM_SRC,This field determines which reset signal in addition to RESET_SYS resets SRC[3:0] in this register: 3=PLTRST 2=RESET_SIO 1=RESET_SYS. This is the only reset signal that will reset the SRC fields. 0=RESET_ESPI." "0: RESET_ESPI,1: RESET_SYS,2: RESET_SIO,3: PLTRST" hexmask.long.byte 0x48 0.--7. 1. "IND,The Index for SRC0 SRC1 SRC2 and SRC3. A write to this register that changes the value of any one or more of SRC0 SRC1 SRC2 or SRC3 will generate a Slave-to-Master Virtual Wire transaction with this index. Setting the INDEX field to 0.." line.long 0x4C "SMVW09_DW1,Slave-to-Master Virtual Wire 9 Register (DWord 1)" bitfld.long 0x4C 24. "SRC3,Slave-to-Master data for Bit Position 3 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" bitfld.long 0x4C 16. "SRC2,Slave-to-Master data for Bit Position 2 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" bitfld.long 0x4C 8. "SRC1,Slave-to-Master data for Bit Position 1 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" bitfld.long 0x4C 0. "SRC0,Slave-to-Master data for Bit Position 0 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" line.long 0x50 "SMVW10_DW0,Slave-to-Master Virtual Wire 10 Register (DWord 0)" bitfld.long 0x50 19. "CHNG3,This bit is set to 1 whenever the value in Bit3 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" bitfld.long 0x50 18. "CHNG2,This bit is set to 1 whenever the value in Bit2 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" bitfld.long 0x50 17. "CHNG1,This bit is set to 1 whenever the value in Bit1 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" bitfld.long 0x50 16. "CHNG0,This bit is set to 1 whenever the value in Bit0 in this register changes. This bit is set to 0 whenever the 4 data bits in this register are transmitted to the Host by a Slave-to-Master Virtual Wire transaction. It is also set to 0 when this.." "0,1" hexmask.long.byte 0x50 12.--15. 1. "STOM_R_STATE,The four bits in this field are loaded into SRC0 SRC1 SRC2 and SRC3 when the reset signal selected by S2M RESET SRC is asserted. If STOM_SRC is set for RESET_SYS the SRC bits are set to the default value of this field rather than.." bitfld.long 0x50 8.--9. "STOM_SRC,This field determines which reset signal in addition to RESET_SYS resets SRC[3:0] in this register: 3=PLTRST 2=RESET_SIO 1=RESET_SYS. This is the only reset signal that will reset the SRC fields. 0=RESET_ESPI." "0: RESET_ESPI,1: RESET_SYS,2: RESET_SIO,3: PLTRST" hexmask.long.byte 0x50 0.--7. 1. "IND,The Index for SRC0 SRC1 SRC2 and SRC3. A write to this register that changes the value of any one or more of SRC0 SRC1 SRC2 or SRC3 will generate a Slave-to-Master Virtual Wire transaction with this index. Setting the INDEX field to 0.." line.long 0x54 "SMVW10_DW1,Slave-to-Master Virtual Wire 10 Register (DWord 1)" bitfld.long 0x54 24. "SRC3,Slave-to-Master data for Bit Position 3 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" bitfld.long 0x54 16. "SRC2,Slave-to-Master data for Bit Position 2 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" bitfld.long 0x54 8. "SRC1,Slave-to-Master data for Bit Position 1 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" bitfld.long 0x54 0. "SRC0,Slave-to-Master data for Bit Position 0 for the virtual wire associated with the index defined by INDEX. The most recent value of this bit is transmitted to the Master even if the bit changes multiple times before the Master issues the Virtual.." "0,1" tree.end tree.end tree "FAN" base ad:0x0 tree "FAN0" base ad:0x4000A000 group.word 0x0++0x3 line.word 0x0 "SETNG,The Fan Driver Setting used to control the output of the Fan Driver." hexmask.word 0x0 6.--15. 1. "FAN_SETNG,The Fan Driver Setting used to control the output of the Fan Driver." line.word 0x2 "CNFG,The Fan Configuration Register controls the general operation of the RPM based Fan Control Algorithm used by the fan driver." bitfld.word 0x2 15. "EN_RRC,Enables the ramp rate control circuitry during the Manual Mode of operation. 1=The ramp rate control circuitry for the Manual Mode of operation is enabled. The PWM setting will follow the ramp rate controls as determined by the Fan.." "0: The ramp rate control circuitry for the Manual..,1: The ramp rate control circuitry for the Manual.." newline bitfld.word 0x2 14. "DIS_GLITCH,Disables the low pass glitch filter that removes high frequency noise injected on the TACH pin. 1 - The glitch filter is disabled. 0 - The glitch filter is enabled." "0,1" newline bitfld.word 0x2 12.--13. "DER_OPT,Control some of the advanced options that affect the derivative portion of the RPM based fan control algorithm. These bits only apply if the Fan Speed Control Algorithm is used." "0,1,2,3" newline bitfld.word 0x2 10.--11. "ERR_RNG,Control some of the advanced options that affect the error window. When the measured fan speed is within the programmed error window around the target speed the fan drive setting is not updated. These bits only apply if the Fan Speed.." "0: 0 RPM,1: 50 RPM,2: 100 RPM,3: 200 RPM" newline bitfld.word 0x2 9. "POLARITY,Determines the polarity of the PWM driver. This does NOT affect the drive setting registers. A setting of 0% drive will still correspond to 0% drive independent of the polarity. 1 - The Polarity of the PWM driver is inverted. A drive.." "0,1" newline bitfld.word 0x2 7. "EN_ALGO,Enables the RPM based Fan Control Algorithm. 1=The control circuitry is enabled and the Fan Driver output will be automatically updated to maintain the programmed fan speed as indicated by the TACH Target Register." "0: The control circuitry is disabled and the fan..,1: The control circuitry is enabled and the Fan.." newline bitfld.word 0x2 5.--6. "RANGE,Adjusts the range of reported and programmed tachometer reading values. The RANGE bits determine the weighting of all TACH values (including the Valid TACH Count TACH Target and TACH reading). 3=Reported Minimum RPM: 4000. Tach Count.." "0: Reported Minimum RPM: 500,1: Reported Minimum RPM: 1000,2: Reported Minimum RPM: 2000,3: Reported Minimum RPM: 4000" newline bitfld.word 0x2 3.--4. "EDGES,Determines the minimum number of edges that must be detected on the TACH signal to determine a single rotation. A typical fan measured 5 edges (for a 2-pole fan). Increasing the number of edges measured with respect to the number of poles of.." "0,1,2,3" newline bitfld.word 0x2 0.--2. "UPDATE,Determines the base time between fan driver updates. The Update Time along with the Fan Step Register is used to control the ramp rate of the drive response to provide a cleaner transition of the actual fan operation as the desired fan.." "0: 100ms Note: This ramp rate control applies for..,1: 200ms,2: 300ms,3: 400ms,4: 500ms,5: 800ms,6: 1200ms,7: 1600ms" group.byte 0x4++0x5 line.byte 0x0 "PWM_DIVIDE,PWM Divide" hexmask.byte 0x0 0.--7. 1. "PWM_DIVIDE,The PWM Divide value determines the final frequency of the PWM driver. The driver base frequency is divided by the PWM Divide value to determine the final frequency." line.byte 0x1 "GAIN,Gain Register stores the gain terms used by the proportional and integral portions of the RPM based Fan Control Algorithm." bitfld.byte 0x1 4.--5. "GAIND,The derivative gain term. Gain Factor: 3=8x 2=4x 1=2x 0=1x" "0: 1x,1: 2x,2: 4x,3: 8x" newline bitfld.byte 0x1 2.--3. "GAINI,The integral gain term. Gain Factor: 3=8x 2=4x 1=2x 0=1x" "0: 1x,1: 2x,2: 4x,3: 8x" newline bitfld.byte 0x1 0.--1. "GAINP,The proportional gain term. Gain Factor: 3=8x 2=4x 1=2x 0=1x" "0: 1x,1: 2x,2: 4x,3: 8x" line.byte 0x2 "SPN_UP_CNFG,The Fan Spin Up Configuration Register controls the settings of Spin Up Routine." bitfld.byte 0x2 6.--7. "DRV_FAIL_CNT,Determines how many update cycles are used for the Drive Fail detection function. This circuitry determines whether the fan can be driven to the desired Tach target. These settings only apply if the Fan Speed Control Algorithm is.." "0: Drive Fail detection circuitry is disabled,1: Drive Fail detection circuitry will count for 16..,2: Drive Fail detection circuitry will count for 32..,3: Drive Fail detection circuitry will count for 64.." newline bitfld.byte 0x2 5. "NOKICK,Determines if the Spin Up Routine will drive the fan to 100% duty cycle for 1/4 of the programmed spin up time before driving it at the programmed level. 1=The Spin Up Routine will not drive the PWM to 100%. It will set the.." "0: The Spin Up Routine will drive the PWM to 100%..,1: The Spin Up Routine will not drive the PWM to 100%" newline bitfld.byte 0x2 2.--4. "SPIN_LVL,Determines the final drive level that is used by the Spin Up Routine. 7=65% 6=60% 5=55% 4=50% 3=45% 2=40% 1=35% 0=30%" "0: 30%,1: 35%,2: 40%,3: 45%,4: 50%,5: 55%,6: 60%,7: 65%" newline bitfld.byte 0x2 0.--1. "SPINUP_TIME,Determines the maximum Spin Time that the Spin Up Routine will run for. If a valid tachometer measurement is not detected before the Spin Time has elapsed an interrupt will be generated. When the RPM based Fan Control Algorithm is.." "0: 250 ms,1: 500 ms,2: 1 second,3: 2 seconds" line.byte 0x3 "STEP,FAN_STEP The Fan Step value represents the maximum step size the fan driver will take between update times" hexmask.byte 0x3 0.--7. 1. "FAN_STEP,The Fan Step value represents the maximum step size the fan driver will take between update times. When the PWM_BASE frequency range field in the PWM Driver Base Frequency Register is set to the value 1 2 or 3 this 8-bit field is.." line.byte 0x4 "MIN_DRV,the minimum drive setting for the RPM based Fan Control Algorithm." hexmask.byte 0x4 0.--7. 1. "MIN_DRIVE,The minimum drive setting." line.byte 0x5 "VALID_TCH_CNT,The maximum TACH Reading Register value to indicate that the fan is spinning properly." hexmask.byte 0x5 0.--7. 1. "VALID_TACH_CNT,The maximum TACH Reading Register value to indicate that the fan is spinning properly." group.word 0xA++0x5 line.word 0x0 "DRV_FAL_BND,The number of Tach counts used by the Fan Drive Fail detection circuitry" hexmask.word 0x0 3.--15. 1. "FAN_DRIVE_FAIL_BAND,The number of Tach counts used by the Fan Drive Fail detection circuitry." line.word 0x2 "TACH_TRGT,The target tachometer value." hexmask.word 0x2 3.--15. 1. "TACH_TARGET,The target tachometer value." line.word 0x4 "TACH_RDNG,[15:3] The current tachometer reading value." hexmask.word 0x4 3.--15. 1. "TACH_READING,The current tachometer reading value." group.byte 0x10++0x1 line.byte 0x0 "DRV_BS_FREQ,[1:0] Determines the frequency range of the PWM fan driver" bitfld.byte 0x0 0.--1. "PWM_BASE,Determines the frequency range of the PWM fan driver (when enabled). PWM resolution is 10-bit except when this field is set to '0b' when it is 8-bit. 3=2.34KHz 2=4.67KHz 1=23.4KHz.." "0: 26,1: 23,2: 4,3: 2" line.byte 0x1 "STS,The bits in this register are routed to interrupts." bitfld.byte 0x1 5. "DRIVE_FAIL,The bit Indicates that the RPM-based Fan Speed Control Algorithm cannot drive the Fan to the desired target setting at maximum drive. (R/WC) 1- The RPM-based Fan Speed Control Algorithm cannot drive Fan to the desired target.." "0,1" newline bitfld.byte 0x1 1. "FAN_SPIN,The bit Indicates that the Spin up Routine for the Fan could not detect a valid tachometer reading within its maximum time window. (R/WC) 1 - The Spin up Routine for the Fan could not detect a valid tachometer reading within.." "0,1" newline bitfld.byte 0x1 0. "FAN_STALL,The bit Indicates that the tachometer measurement on the Fan detects a stalled fan. (R/WC) 0 - Stalled fan not detected. 1 - Stalled fan detected." "0,1" tree.end tree "FAN1" base ad:0x4000A080 group.word 0x0++0x3 line.word 0x0 "SETNG,The Fan Driver Setting used to control the output of the Fan Driver." hexmask.word 0x0 6.--15. 1. "FAN_SETNG,The Fan Driver Setting used to control the output of the Fan Driver." line.word 0x2 "CNFG,The Fan Configuration Register controls the general operation of the RPM based Fan Control Algorithm used by the fan driver." bitfld.word 0x2 15. "EN_RRC,Enables the ramp rate control circuitry during the Manual Mode of operation. 1=The ramp rate control circuitry for the Manual Mode of operation is enabled. The PWM setting will follow the ramp rate controls as determined by the Fan.." "0: The ramp rate control circuitry for the Manual..,1: The ramp rate control circuitry for the Manual.." newline bitfld.word 0x2 14. "DIS_GLITCH,Disables the low pass glitch filter that removes high frequency noise injected on the TACH pin. 1 - The glitch filter is disabled. 0 - The glitch filter is enabled." "0,1" newline bitfld.word 0x2 12.--13. "DER_OPT,Control some of the advanced options that affect the derivative portion of the RPM based fan control algorithm. These bits only apply if the Fan Speed Control Algorithm is used." "0,1,2,3" newline bitfld.word 0x2 10.--11. "ERR_RNG,Control some of the advanced options that affect the error window. When the measured fan speed is within the programmed error window around the target speed the fan drive setting is not updated. These bits only apply if the Fan Speed.." "0: 0 RPM,1: 50 RPM,2: 100 RPM,3: 200 RPM" newline bitfld.word 0x2 9. "POLARITY,Determines the polarity of the PWM driver. This does NOT affect the drive setting registers. A setting of 0% drive will still correspond to 0% drive independent of the polarity. 1 - The Polarity of the PWM driver is inverted. A drive.." "0,1" newline bitfld.word 0x2 7. "EN_ALGO,Enables the RPM based Fan Control Algorithm. 1=The control circuitry is enabled and the Fan Driver output will be automatically updated to maintain the programmed fan speed as indicated by the TACH Target Register." "0: The control circuitry is disabled and the fan..,1: The control circuitry is enabled and the Fan.." newline bitfld.word 0x2 5.--6. "RANGE,Adjusts the range of reported and programmed tachometer reading values. The RANGE bits determine the weighting of all TACH values (including the Valid TACH Count TACH Target and TACH reading). 3=Reported Minimum RPM: 4000. Tach Count.." "0: Reported Minimum RPM: 500,1: Reported Minimum RPM: 1000,2: Reported Minimum RPM: 2000,3: Reported Minimum RPM: 4000" newline bitfld.word 0x2 3.--4. "EDGES,Determines the minimum number of edges that must be detected on the TACH signal to determine a single rotation. A typical fan measured 5 edges (for a 2-pole fan). Increasing the number of edges measured with respect to the number of poles of.." "0,1,2,3" newline bitfld.word 0x2 0.--2. "UPDATE,Determines the base time between fan driver updates. The Update Time along with the Fan Step Register is used to control the ramp rate of the drive response to provide a cleaner transition of the actual fan operation as the desired fan.." "0: 100ms Note: This ramp rate control applies for..,1: 200ms,2: 300ms,3: 400ms,4: 500ms,5: 800ms,6: 1200ms,7: 1600ms" group.byte 0x4++0x5 line.byte 0x0 "PWM_DIVIDE,PWM Divide" hexmask.byte 0x0 0.--7. 1. "PWM_DIVIDE,The PWM Divide value determines the final frequency of the PWM driver. The driver base frequency is divided by the PWM Divide value to determine the final frequency." line.byte 0x1 "GAIN,Gain Register stores the gain terms used by the proportional and integral portions of the RPM based Fan Control Algorithm." bitfld.byte 0x1 4.--5. "GAIND,The derivative gain term. Gain Factor: 3=8x 2=4x 1=2x 0=1x" "0: 1x,1: 2x,2: 4x,3: 8x" newline bitfld.byte 0x1 2.--3. "GAINI,The integral gain term. Gain Factor: 3=8x 2=4x 1=2x 0=1x" "0: 1x,1: 2x,2: 4x,3: 8x" newline bitfld.byte 0x1 0.--1. "GAINP,The proportional gain term. Gain Factor: 3=8x 2=4x 1=2x 0=1x" "0: 1x,1: 2x,2: 4x,3: 8x" line.byte 0x2 "SPN_UP_CNFG,The Fan Spin Up Configuration Register controls the settings of Spin Up Routine." bitfld.byte 0x2 6.--7. "DRV_FAIL_CNT,Determines how many update cycles are used for the Drive Fail detection function. This circuitry determines whether the fan can be driven to the desired Tach target. These settings only apply if the Fan Speed Control Algorithm is.." "0: Drive Fail detection circuitry is disabled,1: Drive Fail detection circuitry will count for 16..,2: Drive Fail detection circuitry will count for 32..,3: Drive Fail detection circuitry will count for 64.." newline bitfld.byte 0x2 5. "NOKICK,Determines if the Spin Up Routine will drive the fan to 100% duty cycle for 1/4 of the programmed spin up time before driving it at the programmed level. 1=The Spin Up Routine will not drive the PWM to 100%. It will set the.." "0: The Spin Up Routine will drive the PWM to 100%..,1: The Spin Up Routine will not drive the PWM to 100%" newline bitfld.byte 0x2 2.--4. "SPIN_LVL,Determines the final drive level that is used by the Spin Up Routine. 7=65% 6=60% 5=55% 4=50% 3=45% 2=40% 1=35% 0=30%" "0: 30%,1: 35%,2: 40%,3: 45%,4: 50%,5: 55%,6: 60%,7: 65%" newline bitfld.byte 0x2 0.--1. "SPINUP_TIME,Determines the maximum Spin Time that the Spin Up Routine will run for. If a valid tachometer measurement is not detected before the Spin Time has elapsed an interrupt will be generated. When the RPM based Fan Control Algorithm is.." "0: 250 ms,1: 500 ms,2: 1 second,3: 2 seconds" line.byte 0x3 "STEP,FAN_STEP The Fan Step value represents the maximum step size the fan driver will take between update times" hexmask.byte 0x3 0.--7. 1. "FAN_STEP,The Fan Step value represents the maximum step size the fan driver will take between update times. When the PWM_BASE frequency range field in the PWM Driver Base Frequency Register is set to the value 1 2 or 3 this 8-bit field is.." line.byte 0x4 "MIN_DRV,the minimum drive setting for the RPM based Fan Control Algorithm." hexmask.byte 0x4 0.--7. 1. "MIN_DRIVE,The minimum drive setting." line.byte 0x5 "VALID_TCH_CNT,The maximum TACH Reading Register value to indicate that the fan is spinning properly." hexmask.byte 0x5 0.--7. 1. "VALID_TACH_CNT,The maximum TACH Reading Register value to indicate that the fan is spinning properly." group.word 0xA++0x5 line.word 0x0 "DRV_FAL_BND,The number of Tach counts used by the Fan Drive Fail detection circuitry" hexmask.word 0x0 3.--15. 1. "FAN_DRIVE_FAIL_BAND,The number of Tach counts used by the Fan Drive Fail detection circuitry." line.word 0x2 "TACH_TRGT,The target tachometer value." hexmask.word 0x2 3.--15. 1. "TACH_TARGET,The target tachometer value." line.word 0x4 "TACH_RDNG,[15:3] The current tachometer reading value." hexmask.word 0x4 3.--15. 1. "TACH_READING,The current tachometer reading value." group.byte 0x10++0x1 line.byte 0x0 "DRV_BS_FREQ,[1:0] Determines the frequency range of the PWM fan driver" bitfld.byte 0x0 0.--1. "PWM_BASE,Determines the frequency range of the PWM fan driver (when enabled). PWM resolution is 10-bit except when this field is set to '0b' when it is 8-bit. 3=2.34KHz 2=4.67KHz 1=23.4KHz.." "0: 26,1: 23,2: 4,3: 2" line.byte 0x1 "STS,The bits in this register are routed to interrupts." bitfld.byte 0x1 5. "DRIVE_FAIL,The bit Indicates that the RPM-based Fan Speed Control Algorithm cannot drive the Fan to the desired target setting at maximum drive. (R/WC) 1- The RPM-based Fan Speed Control Algorithm cannot drive Fan to the desired target.." "0,1" newline bitfld.byte 0x1 1. "FAN_SPIN,The bit Indicates that the Spin up Routine for the Fan could not detect a valid tachometer reading within its maximum time window. (R/WC) 1 - The Spin up Routine for the Fan could not detect a valid tachometer reading within.." "0,1" newline bitfld.byte 0x1 0. "FAN_STALL,The bit Indicates that the tachometer measurement on the Fan detects a stalled fan. (R/WC) 0 - Stalled fan not detected. 1 - Stalled fan detected." "0,1" tree.end tree.end tree "GCR (Logical Device Configuration)" base ad:0x400FFF00 group.byte 0x7++0x0 line.byte 0x0 "LDN,A write to this register selects the current logical device. This allows access to the control and configuration registers for each logical device. Note: The Activate command operates only on the selected logical device." rgroup.byte 0x1C++0x1 line.byte 0x0 "DEV_REV,A read-only register which provides device revision information." line.byte 0x1 "DEV_SUBID,A read-only register which provides device sub ID information." rgroup.word 0x1E++0x1 line.word 0x0 "DEV_ID,A read-only register which provides device identification LSB." rgroup.byte 0x20++0x1 line.byte 0x0 "LEG_DEV_ID,A read-only register which provides legacy device identification." line.byte 0x1 "LEG_DEV_REV,A read-only register which provides legacy device revision information." rgroup.byte 0x24++0x2 line.byte 0x0 "OTP_ID,A read-only register which provides OTP ID information." line.byte 0x1 "VLD_ID,A read-only register which provides Validation ID information." line.byte 0x2 "BR_REV_ID,A read-only register which provides Boot ROM Revision ID information." tree.end tree "GP_SPI" base ad:0x0 tree "GP_SPI0" base ad:0x40009400 group.long 0x0++0x7 line.long 0x0 "ENABLE,[0:0] 1=Enabled. The device is fully operational 0=Disabled. Clocks are gated to conserve power and the SPDOUT and SPI_CLK signals are set to their inactive state" line.long 0x4 "CTRL,SPI Control" bitfld.long 0x4 6. "CE,SPI Chip Select Enable. 1= SPI_CS# output signal is asserted i.e. driven to logic '0' 0= SPI_CS# output signal is deasserted i.e. driven to logic '1'" "0: SPI_CS# output signal is deasserted,1: SPI_CS# output signal is asserted" bitfld.long 0x4 5. "AUTO_READ,Auto Read Enable. 1=A read of the SPI RX_DATA Register will clear both the RXBF status bit and the TXBE status bit 0=A read of the SPI RX_DATA Register will clear the RXBF status bit. The TXBE status bit will not be modified" "0: A read of the SPI RX_DATA Register will clear..,1: A read of the SPI RX_DATA Register will clear.." newline bitfld.long 0x4 4. "SOFT_RESET,Soft Reset is a self-clearing bit. Writing zero to this bit has no effect. Writing a one to this bit resets the entire SPI Interface including all counters and registers back to their initial state." "0,1" bitfld.long 0x4 2.--3. "SPDIN_SELECT,[3:2] 1xb=SPDIN1 and SPDIN2. Select this option for Dual Mode [3:2] 01b=SPDIN2 only. Select this option for Half Duplex [3:2] 00b=SPDIN1 only. Select this option for Full Duplex" "0,1,2,3" newline bitfld.long 0x4 1. "BIOEN,Bidirectional Output Enable control. 1=The SPDOUT_Direction signal configures the SPDOUT signal as an output. 0=The SPDOUT_Direction signal configures the SPDOUT signal as an input." "0: The SPDOUT_Direction signal configures the..,1: The SPDOUT_Direction signal configures the.." bitfld.long 0x4 0. "LSBF,Least Significant Bit First 1= The data is transferred in LSB-first order. 0= The data is transferred in MSB-first order. (default)" "0: The data is transferred in MSB-first order,1: The data is transferred in LSB-first order" rgroup.long 0x8++0x3 line.long 0x0 "STS,SPI Status" bitfld.long 0x0 2. "ACTIVE,ACTIVE status" "0,1" bitfld.long 0x0 1. "RXBF,1=RX_Data buffer is full 0=RX_Data buffer is not full" "0: RX_Data buffer is not full,1: RX_Data buffer is full" newline bitfld.long 0x0 0. "TXBE,1=TX_Data buffer is empty 0=TX_Data buffer is not empty" "0: TX_Data buffer is not empty,1: TX_Data buffer is empty" group.long 0xC++0xF line.long 0x0 "TX_DATA,[7:0] A write to this register when the Tx_Data buffer is empty (TXBE in the SPI Status Register is '1') initiates a SPI transaction." line.long 0x4 "RX_DATA,[7:0] This register is used to read the value returned by the external SPI device." line.long 0x8 "CLK_CTRL,SPI Clock Control. This register should not be changed during an active SPI transaction." bitfld.long 0x8 4. "CLKSRC,1=2MHz 0=48 MHz Ring Oscillator" "0: 48 MHz Ring Oscillator,1: 2MHz" bitfld.long 0x8 2. "CLKPOL,1=The SPI_CLK signal is high when the interface is idle and the first clock edge is a falling edge 0=The SPI_CLK is low when the interface is idle and the first clock edge is a rising edge" "0: The SPI_CLK is low when the interface is idle..,1: The SPI_CLK signal is high when the interface is.." newline bitfld.long 0x8 1. "RCLKPH,1=Valid data on SPDIN signal is expected after the first SPI_CLK edge. This data is sampled on the second and following even SPI_CLK edges (i.e. sample data on falling edge) 0=Valid data is expected on the SPDIN signal on the first SPI_CLK.." "0: Valid data is expected on the SPDIN signal on..,1: Valid data on SPDIN signal is expected after the.." bitfld.long 0x8 0. "TCLKPH,1=Valid data is clocked out on the first SPI_CLK edge on SPDOUT signal. The slave device should sample this data on the second and following even SPI_CLK edges (i.e. sample data on falling edge) 0=Valid data is clocked out on the SPDOUT.." "0: Valid data is clocked out on the SPDOUT signal..,1: Valid data is clocked out on the first SPI_CLK.." line.long 0xC "CLK_GEN,[5:0] PRELOAD SPI Clock Generator Preload value." hexmask.long.byte 0xC 0.--5. 1. "PRELOAD,SPI Clock Generator Preload Value" tree.end tree "GP_SPI1" base ad:0x40009480 group.long 0x0++0x7 line.long 0x0 "ENABLE,[0:0] 1=Enabled. The device is fully operational 0=Disabled. Clocks are gated to conserve power and the SPDOUT and SPI_CLK signals are set to their inactive state" line.long 0x4 "CTRL,SPI Control" bitfld.long 0x4 6. "CE,SPI Chip Select Enable. 1= SPI_CS# output signal is asserted i.e. driven to logic '0' 0= SPI_CS# output signal is deasserted i.e. driven to logic '1'" "0: SPI_CS# output signal is deasserted,1: SPI_CS# output signal is asserted" bitfld.long 0x4 5. "AUTO_READ,Auto Read Enable. 1=A read of the SPI RX_DATA Register will clear both the RXBF status bit and the TXBE status bit 0=A read of the SPI RX_DATA Register will clear the RXBF status bit. The TXBE status bit will not be modified" "0: A read of the SPI RX_DATA Register will clear..,1: A read of the SPI RX_DATA Register will clear.." newline bitfld.long 0x4 4. "SOFT_RESET,Soft Reset is a self-clearing bit. Writing zero to this bit has no effect. Writing a one to this bit resets the entire SPI Interface including all counters and registers back to their initial state." "0,1" bitfld.long 0x4 2.--3. "SPDIN_SELECT,[3:2] 1xb=SPDIN1 and SPDIN2. Select this option for Dual Mode [3:2] 01b=SPDIN2 only. Select this option for Half Duplex [3:2] 00b=SPDIN1 only. Select this option for Full Duplex" "0,1,2,3" newline bitfld.long 0x4 1. "BIOEN,Bidirectional Output Enable control. 1=The SPDOUT_Direction signal configures the SPDOUT signal as an output. 0=The SPDOUT_Direction signal configures the SPDOUT signal as an input." "0: The SPDOUT_Direction signal configures the..,1: The SPDOUT_Direction signal configures the.." bitfld.long 0x4 0. "LSBF,Least Significant Bit First 1= The data is transferred in LSB-first order. 0= The data is transferred in MSB-first order. (default)" "0: The data is transferred in MSB-first order,1: The data is transferred in LSB-first order" rgroup.long 0x8++0x3 line.long 0x0 "STS,SPI Status" bitfld.long 0x0 2. "ACTIVE,ACTIVE status" "0,1" bitfld.long 0x0 1. "RXBF,1=RX_Data buffer is full 0=RX_Data buffer is not full" "0: RX_Data buffer is not full,1: RX_Data buffer is full" newline bitfld.long 0x0 0. "TXBE,1=TX_Data buffer is empty 0=TX_Data buffer is not empty" "0: TX_Data buffer is not empty,1: TX_Data buffer is empty" group.long 0xC++0xF line.long 0x0 "TX_DATA,[7:0] A write to this register when the Tx_Data buffer is empty (TXBE in the SPI Status Register is '1') initiates a SPI transaction." line.long 0x4 "RX_DATA,[7:0] This register is used to read the value returned by the external SPI device." line.long 0x8 "CLK_CTRL,SPI Clock Control. This register should not be changed during an active SPI transaction." bitfld.long 0x8 4. "CLKSRC,1=2MHz 0=48 MHz Ring Oscillator" "0: 48 MHz Ring Oscillator,1: 2MHz" bitfld.long 0x8 2. "CLKPOL,1=The SPI_CLK signal is high when the interface is idle and the first clock edge is a falling edge 0=The SPI_CLK is low when the interface is idle and the first clock edge is a rising edge" "0: The SPI_CLK is low when the interface is idle..,1: The SPI_CLK signal is high when the interface is.." newline bitfld.long 0x8 1. "RCLKPH,1=Valid data on SPDIN signal is expected after the first SPI_CLK edge. This data is sampled on the second and following even SPI_CLK edges (i.e. sample data on falling edge) 0=Valid data is expected on the SPDIN signal on the first SPI_CLK.." "0: Valid data is expected on the SPDIN signal on..,1: Valid data on SPDIN signal is expected after the.." bitfld.long 0x8 0. "TCLKPH,1=Valid data is clocked out on the first SPI_CLK edge on SPDOUT signal. The slave device should sample this data on the second and following even SPI_CLK edges (i.e. sample data on falling edge) 0=Valid data is clocked out on the SPDOUT.." "0: Valid data is clocked out on the SPDOUT signal..,1: Valid data is clocked out on the first SPI_CLK.." line.long 0xC "CLK_GEN,[5:0] PRELOAD SPI Clock Generator Preload value." hexmask.long.byte 0xC 0.--5. 1. "PRELOAD,SPI Clock Generator Preload Value" tree.end tree.end tree "GPIO" base ad:0x40081000 repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "CTRL0[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x20)++0x3 line.long 0x0 "CTRL1[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x40)++0x3 line.long 0x0 "CTRL2[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x60)++0x3 line.long 0x0 "CTRL3[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "CTRL4[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xA0)++0x3 line.long 0x0 "CTRL5[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xC0)++0x3 line.long 0x0 "CTRL6[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xE0)++0x3 line.long 0x0 "CTRL7[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x100)++0x3 line.long 0x0 "CTRL10[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x120)++0x3 line.long 0x0 "CTRL11[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x140)++0x3 line.long 0x0 "CTRL12[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x160)++0x3 line.long 0x0 "CTRL13[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x180)++0x3 line.long 0x0 "CTRL14[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1A0)++0x3 line.long 0x0 "CTRL15[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1C0)++0x3 line.long 0x0 "CTRL16[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1E0)++0x3 line.long 0x0 "CTRL17[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x200)++0x3 line.long 0x0 "CTRL20[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x220)++0x3 line.long 0x0 "CTRL21[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x240)++0x3 line.long 0x0 "CTRL22[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x260)++0x3 line.long 0x0 "CTRL23[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x280)++0x3 line.long 0x0 "CTRL24[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x2A0)++0x3 line.long 0x0 "CTRL25[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end group.long 0x2C0++0x3 line.long 0x0 "CTRL26[0],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x300)++0x3 line.long 0x0 "PARIN[$1],The GPIO Input Registers." repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x380)++0x3 line.long 0x0 "PAROUT[$1],The GPIO Output Registers." repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x500)++0x3 line.long 0x0 "CTRL2P0[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x520)++0x3 line.long 0x0 "CTRL2P1[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x540)++0x3 line.long 0x0 "CTRL2P2[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x560)++0x3 line.long 0x0 "CTRL2P3[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x580)++0x3 line.long 0x0 "CTRL2P4[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x5A0)++0x3 line.long 0x0 "CTRL2P5[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x5C0)++0x3 line.long 0x0 "CTRL2P6[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x5E0)++0x3 line.long 0x0 "CTRL2P7[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x600)++0x3 line.long 0x0 "CTRL2P10[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x620)++0x3 line.long 0x0 "CTRL2P11[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x640)++0x3 line.long 0x0 "CTRL2P12[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x660)++0x3 line.long 0x0 "CTRL2P13[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x680)++0x3 line.long 0x0 "CTRL2P14[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x6A0)++0x3 line.long 0x0 "CTRL2P15[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x6C0)++0x3 line.long 0x0 "CTRL2P16[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x6E0)++0x3 line.long 0x0 "CTRL2P17[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x700)++0x3 line.long 0x0 "CTRL2P20[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x720)++0x3 line.long 0x0 "CTRL2P21[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x740)++0x3 line.long 0x0 "CTRL2P22[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x760)++0x3 line.long 0x0 "CTRL2P23[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x780)++0x3 line.long 0x0 "CTRL2P24[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x7A0)++0x3 line.long 0x0 "CTRL2P25[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end group.long 0x7C0++0x3 line.long 0x0 "CTRL2P26[0],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" tree.end tree "HTM (Hibernation Timer)" base ad:0x0 tree "HTM0" base ad:0x40009800 group.word 0x0++0x1 line.word 0x0 "PRLD,[15:0] This register is used to set the Hibernation Timer Preload value." group.word 0x4++0x1 line.word 0x0 "CTRL,HTimer Control Register" bitfld.word 0x0 0. "CTRL,1= The Hibernation Timer has a resolution of 0.125s per LSB which yields a maximum time in excess of 2 hours. 0= The Hibernation Timer has a resolution of 30.5us per LSB which yields a maximum time of ~2seconds." "0: The Hibernation Timer has a resolution of 30,1: The Hibernation Timer has a resolution of 0" rgroup.word 0x8++0x1 line.word 0x0 "CNT,The current state of the Hibernation Timer." tree.end tree "HTM1" base ad:0x40009820 group.word 0x0++0x1 line.word 0x0 "PRLD,[15:0] This register is used to set the Hibernation Timer Preload value." group.word 0x4++0x1 line.word 0x0 "CTRL,HTimer Control Register" bitfld.word 0x0 0. "CTRL,1= The Hibernation Timer has a resolution of 0.125s per LSB which yields a maximum time in excess of 2 hours. 0= The Hibernation Timer has a resolution of 30.5us per LSB which yields a maximum time of ~2seconds." "0: The Hibernation Timer has a resolution of 30,1: The Hibernation Timer has a resolution of 0" rgroup.word 0x8++0x1 line.word 0x0 "CNT,The current state of the Hibernation Timer." tree.end tree.end tree "IMSPI (Internal Master SPI)" base ad:0x40220000 group.long 0x0++0xF line.long 0x0 "MODE,IMSPI Mode Register" bitfld.long 0x0 24.--25. "IF_MODE,This field sets the interface mode for the SPI controller. 3=Reserved; 2=Quad Mode; 1=Dual Mode; 0=Single Mode." "0: Single Mode,1: Dual Mode,2: Quad Mode,3: Reserved" newline hexmask.long.byte 0x0 16.--23. 1. "CLOCK_DIVIDE,This SPI clock divide in terms of the number of system clocks. 255:1=The SPI clock period is equal to this number of system clocks. 0=The SPI clock period is equal to 256 system clocks." newline bitfld.long 0x0 10. "CPHA_MISO,This field is the CPHA field of the underlying SPI controller which affects only the MISO Data. This field changes determines the clock edge on which data are captured in combination with the CPOL field. For standard SPI Modes this must.." "0: If CPOL=0,1: If CPOL=0" newline bitfld.long 0x0 9. "CPHA_MOSI,This field is the CPHA field of the underlying SPI controller which affects only the MOSI Data. This field changes determines the clock edge on which data are sent in combination with the CPOL field. 1=If CPOL=0 data sent on Rising Edge;.." "0: If CPOL=0,1: If CPOL=0" newline bitfld.long 0x0 8. "CPOL,This bit corresponds to the Polarity control for the underlying SPI controller. It describes the default state of the SPI Clock signal. 1=The clock starts in a high state; 0=The clock starts in a low state." "0: The clock starts in a low state,1: The clock starts in a high state" newline bitfld.long 0x0 2. "DLY2_SUSB,This bit is routed to the DLY2_SUSB# pin function." "0,1" newline bitfld.long 0x0 1. "SOFT_RESET,A write of '1b' to this bit resets the controller. This bit is self-clearing." "0,1" newline bitfld.long 0x0 0. "ACTIVATE,This bit enables the controller. 1=The controller is enabled; 0=The controller is disabled and placed in its lowest power state." "0: The controller is disabled and placed in its..,1: The controller is enabled" line.long 0x4 "STATUS,IMSPI Status Register" bitfld.long 0x4 1. "INVALID_RESPONSE,The IMSPI has detected an invalid response field and therefore is aborting the transfer in failure. 1=A transfer error occurred due to an invalid response; 0=No error occurred. (R/WC)" "0: No error occurred,1: A transfer error occurred due to an invalid.." newline bitfld.long 0x4 0. "TIMEOUT,This flags when a transfer has terminated due to timeout on the response phase. 1=A transfer error occurred due to an invalid response; 0=No error occurred. (R/WC)" "0: No error occurred,1: A transfer error occurred due to an invalid.." line.long 0x8 "INT_ENABLE,IMSPI Interrupt Enable Register" bitfld.long 0x8 1. "INVALID_RESPONSE_LE,Assert an EEPROM interrupt when the INVALID_RESPONSE status is asserted. 1=Enable Interrupt; 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" newline bitfld.long 0x8 0. "TIMEOUT_LE,Assert an IMSPI interrupt when the TIMEOUT status is asserted. 1=Enable Interrupt; 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" line.long 0xC "TIMEOUT_CONTROL,IMSPI Timeout Control Register" hexmask.long.byte 0xC 0.--4. 1. "RESPONSE_TIMEOUT,This field is the maximum number of response cycles the IMSPI will wait until flagging a timeout. A setting of 0 will disable the timeout feature." tree.end tree "KBC (Keyboard Controller)" base ad:0x400F0400 rgroup.byte 0x0++0x0 line.byte 0x0 "HOST_DATA,READ_DATA. This 8-bit register is read-only. When read by the Host. the PCOBF and/or AUXOBF interrupts are cleared and the OBF flag in the status register is cleared." wgroup.byte 0x0++0x0 line.byte 0x0 "HOST_EC_DATA,WRITE_DATA. This 8-bit register is write-only. When written. the C/D bit in the Keyboard Status Read Register is cleared to '0'. signifying data. and the IBF in the same register is set to '1'. When the Runtime Register at offset 0h is.." wgroup.byte 0x4++0x0 line.byte 0x0 "HOST_WC,WRITE_CMD. This 8-bit register is write-only and is an alias of the register at offset 0h. When written. the C/D bit in the Keyboard Status Read Register is set to '1'. signifying a command. and the IBF in the same register is set to '1'." rgroup.byte 0x4++0x0 line.byte 0x0 "HOST_RS,Keyboard Status Read Register. This register is a read-only alias of the EC Keyboard Status Register." bitfld.byte 0x0 6.--7. "UD2,User-defined data." "0,1,2,3" bitfld.byte 0x0 5. "AUXOBF,Auxiliary Output Buffer Full." "0,1" newline bitfld.byte 0x0 4. "UD1,User-defined data." "0,1" bitfld.byte 0x0 3. "CMD_DAT,Command Data. This bit specifies whether the input data register contains data or a command ('0' = data '1' = command)." "0: data,1: command" newline bitfld.byte 0x0 2. "UD0,User-defined data." "0,1" bitfld.byte 0x0 1. "IBF,Input Buffer Full." "0,1" newline bitfld.byte 0x0 0. "OBF,Output Buffer Full." "0,1" rgroup.byte 0x100++0x0 line.byte 0x0 "H2EC_DATA,Host_EC Data/Cmd Register This register is an alias of the HOST_EC Data / CMD Register. When read at the EC-Only offset of 0h. it returns the data written by the Host to either Runtime Register offset 0h or Runtime Register offset 04h." wgroup.byte 0x100++0x0 line.byte 0x0 "EC_DATA,EC_Host Data Register" group.byte 0x104++0x0 line.byte 0x0 "EC_KBD_STS,Keyboard Status Register" bitfld.byte 0x0 6.--7. "UD2,User-defined data." "0,1,2,3" bitfld.byte 0x0 5. "AUXOBF,Auxiliary Output Buffer Full." "0,1" newline bitfld.byte 0x0 4. "UD1,User-defined data." "0,1" bitfld.byte 0x0 3. "CMD_DAT,Command Data. This bit specifies whether the input data register contains data or a command ('0' = data '1' = command)." "0: data,1: command" newline bitfld.byte 0x0 2. "UD0,User-defined data." "0,1" bitfld.byte 0x0 1. "IBF,Input Buffer Full." "0,1" newline bitfld.byte 0x0 0. "OBF,Output Buffer Full." "0,1" group.byte 0x108++0x0 line.byte 0x0 "KBCTRL,Keyboard Control Register" bitfld.byte 0x0 7. "AUXH,AUX in Hardware. 1=AUXOBF of the Keyboard Status Read Register is set in hardware by a write to the EC AUX Data Register 0=AUXOBF is not modified in hardware but can be read and written by the EC using the EC-Only alias of the EC.." "0: AUXOBF is not modified in hardware,1: AUXOBF of the Keyboard Status Read Register is.." bitfld.byte 0x0 6. "UD5,User-defined data." "0,1" newline bitfld.byte 0x0 5. "OBFEN,When this bit is '1' the system interrupt signal KIRQ is driven by the bit PCOBF and MIRQ is driven by AUXOBF. When this bit is '0' KIRQ and MIRQ are driven low. This bit must not be changed when OBF of the status register is equal to '1'." "0,1" bitfld.byte 0x0 3.--4. "UD4,User-defined data." "0,1,2,3" newline bitfld.byte 0x0 2. "PCOBFEN,1= reflects the value written to the PCOBF Register 0=PCOBF reflects the status of writes to the EC Data Register" "0: PCOBF reflects the status of writes to the EC..,1: reflects the value written to the PCOBF Register" bitfld.byte 0x0 1. "SAEN,Software-assist enable. 1=This bit allows control of the GATEA20 signal via firmware 0=GATEA20 corresponds to either the last Host-initiated control of GATEA20 or the firmware write to the Keyboard Control Register or the EC AUX Data Register." "0: GATEA20 corresponds to either the last..,1: This bit allows control of the GATEA20 signal.." newline bitfld.byte 0x0 0. "UD3,User-defined data." "0,1" wgroup.byte 0x10C++0x0 line.byte 0x0 "EC_AUX_DATA,EC_Host Aux Register. This 8-bit register is write-only. When written. the C/D in the Keyboard Status Read Register is cleared to '0'. signifying data. and the IBF in the same register is set to '1'. When the Runtime Register at offset 0h.." group.byte 0x114++0x0 line.byte 0x0 "PCOBF,8042 Emulated Keyboard Controller PCOBF Register" bitfld.byte 0x0 0. "PCOBF,PCOBF Register: If enabled by the bit OBFEN the bit PCOBF is gated onto KIRQ. The KIRQ signal is a system interrupt which signifies that the EC has written to the HOST2EC Data Register (EC-Only offset 0h)." "0,1" group.byte 0x330++0x0 line.byte 0x0 "ACTIVATE,Activate Register" bitfld.byte 0x0 0. "ACT,1=The 8042 Interface is powered and functional. 0=The 8042 Interface is powered down and inactive." "0: The 8042 Interface is powered down and inactive,1: The 8042 Interface is powered and functional" tree.end tree "KSI (Keyboard Scan Interface)" base ad:0x40009C00 group.long 0x4++0x3 line.long 0x0 "KSO_SEL,KSO Select and control" bitfld.long 0x0 7. "INV,0= KSO[x] driven low when selected 1= KSO[x] driven high when selected." "0: KSO[x] driven low when selected,1: KSO[x] driven high when selected" bitfld.long 0x0 6. "KSEN,0= Keyboard scan enabled 1= Keyboard scan disabled. All KSO output buffers disabled." "0: Keyboard scan enabled,1: Keyboard scan disabled" bitfld.long 0x0 5. "ALL,0=When key scan is enabled KSO output controlled by the KSO_SELECT field. 1=KSO[x] driven high when selected." "0: When key scan is enabled,1: KSO[x] driven high when selected" hexmask.long.byte 0x0 0.--4. 1. "SEL,This field selects a KSO line (00000b = KSO[0] etc.) for output according to the value off KSO_INVERT in this register." rgroup.long 0x8++0x3 line.long 0x0 "KSI,[7:0] This field returns the current state of the KSI pins." group.long 0xC++0xB line.long 0x0 "KSI_STS,[7:0] Each bit in this field is set on the falling edge of the corresponding KSI input pin. A KSI interrupt is generated when its corresponding status bit and interrupt enable bit are both set. KSI interrupts are logically ORed.." line.long 0x4 "KSI_IEN,[7:0] Each bit in KSI_INT_EN enables interrupt generation due to highto-low transition on a KSI input. An interrupt is generated when the corresponding bits in KSI_STATUS and KSI_INT_EN are both set." line.long 0x8 "EXT_CTRL,[0:0] PREDRIVE_ENABLE enables the PREDRIVE mode to actively drive the KSO pins high for approximately 100ns before switching to open-drain operation. 0=Disable predrive on KSO pins 1=Enable predrive on KSO pins." tree.end tree "LED (Blinking/Breathing LED)" base ad:0x0 tree "LED0" base ad:0x4000B800 group.long 0x0++0x17 line.long 0x0 "CFG,LED Configuration" bitfld.long 0x0 16. "SYMMETRY,SYMMETRY 1=The rising and falling ramp times are in Asymmetric mode. 0=The rising and falling ramp times are in Symmetric mode." "0: The rising and falling ramp times are in..,1: The rising and falling ramp times are in.." hexmask.long.byte 0x0 8.--15. 1. "WDT_RELOAD,WDT_RELOAD The PWM Watchdog Timer counter reload value. On system reset it defaults to 14h which corresponds to a 4 second Watchdog timeout value." newline bitfld.long 0x0 7. "RST,RESET Writes of '1' to this bit resets the PWM registers to their default values. This bit is self clearing. Writes of '0' to this bit have no effect." "0,1" bitfld.long 0x0 6. "EN_UPDATE,ENABLE_UPDATE This bit is set to 1 when written with a '1'. Writes of '0' have no effect. Hardware clears this bit to 0 when the breathing configuration registers are updated at the end of a PWM period. The current state of the bit is readable.." "0,1" newline bitfld.long 0x0 4.--5. "PWM_SIZE,PWM_SIZE This bit controls the behavior of PWM: 3=Reserved 2=PWM is configured as a 6-bit PWM 1=PWM is configured as a 7-bit PWM 0=PWM is configured as an 8-bit PWM" "0: PWM is configured as an 8-bit PWM,1: PWM is configured as a 7-bit PWM,2: PWM is configured as a 6-bit PWM,3: Reserved" bitfld.long 0x0 3. "SYNCH,SYNCHRONIZE When this bit is '1' all counters for all LEDs are reset to their initial values. When this bit is '0' in the LED Configuration Register for all LEDs then all counters for LEDs that are configured to blink or breathe will increment.." "0,1" newline bitfld.long 0x0 2. "CLK_SRC,1=Clock source is the 48 MHz clock 0=Clock source is the 32.768 KHz clock" "0: Clock source is the 32,1: Clock source is the 48 MHz clock" bitfld.long 0x0 0.--1. "CTRL,CONTROL 3=PWM is always on 2=LED blinking (standard PWM) 1=LED breathing configuration 0=PWM is always off. All internal registers and counters are reset to 0. Clocks are gated" "0: PWM is always off,1: LED breathing configuration,2: LED blinking,3: PWM is always on" line.long 0x4 "LIMIT,LED Limits This register may be written at any time. Values written into the register are held in an holding register. which is transferred into the actual register at the end of a PWM period. The two byte fields may be written independently. Reads.." hexmask.long.byte 0x4 8.--15. 1. "MAX,In breathing mode when the current duty cycle is greater than or equal to this value the breathing apparatus holds the current duty cycle for the period specified by the field HD in register LED_DELAY then starts decrementing the current duty cycle" hexmask.long.byte 0x4 0.--7. 1. "MIN,In breathing mode when the current duty cycle is less than or equal to this value the breathing apparatus holds the current duty cycle for the period specified by the field LD in register LED_DELAY then starts incrementing the current duty cycle In.." line.long 0x8 "DLY,LED Delay" hexmask.long.word 0x8 12.--23. 1. "HIGH_PULSE,In breathing mode the number of PWM periods to wait before updating the current duty cycle when the current duty cycle is greater than or equal to the value MAX in register LED_LIMIT." hexmask.long.word 0x8 0.--11. 1. "LOW_PULSE,The number of PWM periods to wait before updating the current duty cycle when the current duty cycle is greater than or equal to the value MIN in register LED_LIMIT." line.long 0xC "STEP,This register has eight segment fields which provide the amount the current duty cycle is adjusted at the end of every PWM period. Segment field selection is decoded based on the segment index. The segment index equation utilized depends on the.." hexmask.long.byte 0xC 28.--31. 1. "S7,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 111." hexmask.long.byte 0xC 24.--27. 1. "S6,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 110." newline hexmask.long.byte 0xC 20.--23. 1. "S5,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 101" hexmask.long.byte 0xC 16.--19. 1. "S4,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 100." newline hexmask.long.byte 0xC 12.--15. 1. "S3,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 011." hexmask.long.byte 0xC 8.--11. 1. "S2,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 010." newline hexmask.long.byte 0xC 4.--7. 1. "S1,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 001." hexmask.long.byte 0xC 0.--3. 1. "S0,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 000." line.long 0x10 "INTRVL,LED Update Interval" hexmask.long.byte 0x10 28.--31. 1. "I7,The number of PWM periods between updates to current duty cycle when the segment index is equal to 111b." hexmask.long.byte 0x10 24.--27. 1. "I6,The number of PWM periods between updates to current duty cycle when the segment index is equal to 110b." newline hexmask.long.byte 0x10 20.--23. 1. "I5,The number of PWM periods between updates to current duty cycle when the segment index is equal to 101b." hexmask.long.byte 0x10 16.--19. 1. "I4,The number of PWM periods between updates to current duty cycle when the segment index is equal to 100b." newline hexmask.long.byte 0x10 12.--15. 1. "I3,The number of PWM periods between updates to current duty cycle when the segment index is equal to 011b." hexmask.long.byte 0x10 8.--11. 1. "I2,The number of PWM periods between updates to current duty cycle when the segment index is equal to 010b." newline hexmask.long.byte 0x10 4.--7. 1. "I1,The number of PWM periods between updates to current duty cycle when the segment index is equal to 001b." hexmask.long.byte 0x10 0.--3. 1. "I0,The number of PWM periods between updates to current duty cycle when the segment index is equal to 000b." line.long 0x14 "OUTDLY,LED Output Delay" hexmask.long.byte 0x14 0.--7. 1. "DELAY,The delay in counts of the clock defined in Clock Source (CLKSRC) in which output transitions are delayed. When this field is 0 there is no added transition delay. When the LED is programmed to be Always On or Always Off the Output.." tree.end tree "LED1" base ad:0x4000B900 group.long 0x0++0x17 line.long 0x0 "CFG,LED Configuration" bitfld.long 0x0 16. "SYMMETRY,SYMMETRY 1=The rising and falling ramp times are in Asymmetric mode. 0=The rising and falling ramp times are in Symmetric mode." "0: The rising and falling ramp times are in..,1: The rising and falling ramp times are in.." hexmask.long.byte 0x0 8.--15. 1. "WDT_RELOAD,WDT_RELOAD The PWM Watchdog Timer counter reload value. On system reset it defaults to 14h which corresponds to a 4 second Watchdog timeout value." newline bitfld.long 0x0 7. "RST,RESET Writes of '1' to this bit resets the PWM registers to their default values. This bit is self clearing. Writes of '0' to this bit have no effect." "0,1" bitfld.long 0x0 6. "EN_UPDATE,ENABLE_UPDATE This bit is set to 1 when written with a '1'. Writes of '0' have no effect. Hardware clears this bit to 0 when the breathing configuration registers are updated at the end of a PWM period. The current state of the bit is readable.." "0,1" newline bitfld.long 0x0 4.--5. "PWM_SIZE,PWM_SIZE This bit controls the behavior of PWM: 3=Reserved 2=PWM is configured as a 6-bit PWM 1=PWM is configured as a 7-bit PWM 0=PWM is configured as an 8-bit PWM" "0: PWM is configured as an 8-bit PWM,1: PWM is configured as a 7-bit PWM,2: PWM is configured as a 6-bit PWM,3: Reserved" bitfld.long 0x0 3. "SYNCH,SYNCHRONIZE When this bit is '1' all counters for all LEDs are reset to their initial values. When this bit is '0' in the LED Configuration Register for all LEDs then all counters for LEDs that are configured to blink or breathe will increment.." "0,1" newline bitfld.long 0x0 2. "CLK_SRC,1=Clock source is the 48 MHz clock 0=Clock source is the 32.768 KHz clock" "0: Clock source is the 32,1: Clock source is the 48 MHz clock" bitfld.long 0x0 0.--1. "CTRL,CONTROL 3=PWM is always on 2=LED blinking (standard PWM) 1=LED breathing configuration 0=PWM is always off. All internal registers and counters are reset to 0. Clocks are gated" "0: PWM is always off,1: LED breathing configuration,2: LED blinking,3: PWM is always on" line.long 0x4 "LIMIT,LED Limits This register may be written at any time. Values written into the register are held in an holding register. which is transferred into the actual register at the end of a PWM period. The two byte fields may be written independently. Reads.." hexmask.long.byte 0x4 8.--15. 1. "MAX,In breathing mode when the current duty cycle is greater than or equal to this value the breathing apparatus holds the current duty cycle for the period specified by the field HD in register LED_DELAY then starts decrementing the current duty cycle" hexmask.long.byte 0x4 0.--7. 1. "MIN,In breathing mode when the current duty cycle is less than or equal to this value the breathing apparatus holds the current duty cycle for the period specified by the field LD in register LED_DELAY then starts incrementing the current duty cycle In.." line.long 0x8 "DLY,LED Delay" hexmask.long.word 0x8 12.--23. 1. "HIGH_PULSE,In breathing mode the number of PWM periods to wait before updating the current duty cycle when the current duty cycle is greater than or equal to the value MAX in register LED_LIMIT." hexmask.long.word 0x8 0.--11. 1. "LOW_PULSE,The number of PWM periods to wait before updating the current duty cycle when the current duty cycle is greater than or equal to the value MIN in register LED_LIMIT." line.long 0xC "STEP,This register has eight segment fields which provide the amount the current duty cycle is adjusted at the end of every PWM period. Segment field selection is decoded based on the segment index. The segment index equation utilized depends on the.." hexmask.long.byte 0xC 28.--31. 1. "S7,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 111." hexmask.long.byte 0xC 24.--27. 1. "S6,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 110." newline hexmask.long.byte 0xC 20.--23. 1. "S5,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 101" hexmask.long.byte 0xC 16.--19. 1. "S4,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 100." newline hexmask.long.byte 0xC 12.--15. 1. "S3,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 011." hexmask.long.byte 0xC 8.--11. 1. "S2,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 010." newline hexmask.long.byte 0xC 4.--7. 1. "S1,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 001." hexmask.long.byte 0xC 0.--3. 1. "S0,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 000." line.long 0x10 "INTRVL,LED Update Interval" hexmask.long.byte 0x10 28.--31. 1. "I7,The number of PWM periods between updates to current duty cycle when the segment index is equal to 111b." hexmask.long.byte 0x10 24.--27. 1. "I6,The number of PWM periods between updates to current duty cycle when the segment index is equal to 110b." newline hexmask.long.byte 0x10 20.--23. 1. "I5,The number of PWM periods between updates to current duty cycle when the segment index is equal to 101b." hexmask.long.byte 0x10 16.--19. 1. "I4,The number of PWM periods between updates to current duty cycle when the segment index is equal to 100b." newline hexmask.long.byte 0x10 12.--15. 1. "I3,The number of PWM periods between updates to current duty cycle when the segment index is equal to 011b." hexmask.long.byte 0x10 8.--11. 1. "I2,The number of PWM periods between updates to current duty cycle when the segment index is equal to 010b." newline hexmask.long.byte 0x10 4.--7. 1. "I1,The number of PWM periods between updates to current duty cycle when the segment index is equal to 001b." hexmask.long.byte 0x10 0.--3. 1. "I0,The number of PWM periods between updates to current duty cycle when the segment index is equal to 000b." line.long 0x14 "OUTDLY,LED Output Delay" hexmask.long.byte 0x14 0.--7. 1. "DELAY,The delay in counts of the clock defined in Clock Source (CLKSRC) in which output transitions are delayed. When this field is 0 there is no added transition delay. When the LED is programmed to be Always On or Always Off the Output.." tree.end tree "LED2" base ad:0x4000BA00 group.long 0x0++0x17 line.long 0x0 "CFG,LED Configuration" bitfld.long 0x0 16. "SYMMETRY,SYMMETRY 1=The rising and falling ramp times are in Asymmetric mode. 0=The rising and falling ramp times are in Symmetric mode." "0: The rising and falling ramp times are in..,1: The rising and falling ramp times are in.." hexmask.long.byte 0x0 8.--15. 1. "WDT_RELOAD,WDT_RELOAD The PWM Watchdog Timer counter reload value. On system reset it defaults to 14h which corresponds to a 4 second Watchdog timeout value." newline bitfld.long 0x0 7. "RST,RESET Writes of '1' to this bit resets the PWM registers to their default values. This bit is self clearing. Writes of '0' to this bit have no effect." "0,1" bitfld.long 0x0 6. "EN_UPDATE,ENABLE_UPDATE This bit is set to 1 when written with a '1'. Writes of '0' have no effect. Hardware clears this bit to 0 when the breathing configuration registers are updated at the end of a PWM period. The current state of the bit is readable.." "0,1" newline bitfld.long 0x0 4.--5. "PWM_SIZE,PWM_SIZE This bit controls the behavior of PWM: 3=Reserved 2=PWM is configured as a 6-bit PWM 1=PWM is configured as a 7-bit PWM 0=PWM is configured as an 8-bit PWM" "0: PWM is configured as an 8-bit PWM,1: PWM is configured as a 7-bit PWM,2: PWM is configured as a 6-bit PWM,3: Reserved" bitfld.long 0x0 3. "SYNCH,SYNCHRONIZE When this bit is '1' all counters for all LEDs are reset to their initial values. When this bit is '0' in the LED Configuration Register for all LEDs then all counters for LEDs that are configured to blink or breathe will increment.." "0,1" newline bitfld.long 0x0 2. "CLK_SRC,1=Clock source is the 48 MHz clock 0=Clock source is the 32.768 KHz clock" "0: Clock source is the 32,1: Clock source is the 48 MHz clock" bitfld.long 0x0 0.--1. "CTRL,CONTROL 3=PWM is always on 2=LED blinking (standard PWM) 1=LED breathing configuration 0=PWM is always off. All internal registers and counters are reset to 0. Clocks are gated" "0: PWM is always off,1: LED breathing configuration,2: LED blinking,3: PWM is always on" line.long 0x4 "LIMIT,LED Limits This register may be written at any time. Values written into the register are held in an holding register. which is transferred into the actual register at the end of a PWM period. The two byte fields may be written independently. Reads.." hexmask.long.byte 0x4 8.--15. 1. "MAX,In breathing mode when the current duty cycle is greater than or equal to this value the breathing apparatus holds the current duty cycle for the period specified by the field HD in register LED_DELAY then starts decrementing the current duty cycle" hexmask.long.byte 0x4 0.--7. 1. "MIN,In breathing mode when the current duty cycle is less than or equal to this value the breathing apparatus holds the current duty cycle for the period specified by the field LD in register LED_DELAY then starts incrementing the current duty cycle In.." line.long 0x8 "DLY,LED Delay" hexmask.long.word 0x8 12.--23. 1. "HIGH_PULSE,In breathing mode the number of PWM periods to wait before updating the current duty cycle when the current duty cycle is greater than or equal to the value MAX in register LED_LIMIT." hexmask.long.word 0x8 0.--11. 1. "LOW_PULSE,The number of PWM periods to wait before updating the current duty cycle when the current duty cycle is greater than or equal to the value MIN in register LED_LIMIT." line.long 0xC "STEP,This register has eight segment fields which provide the amount the current duty cycle is adjusted at the end of every PWM period. Segment field selection is decoded based on the segment index. The segment index equation utilized depends on the.." hexmask.long.byte 0xC 28.--31. 1. "S7,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 111." hexmask.long.byte 0xC 24.--27. 1. "S6,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 110." newline hexmask.long.byte 0xC 20.--23. 1. "S5,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 101" hexmask.long.byte 0xC 16.--19. 1. "S4,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 100." newline hexmask.long.byte 0xC 12.--15. 1. "S3,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 011." hexmask.long.byte 0xC 8.--11. 1. "S2,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 010." newline hexmask.long.byte 0xC 4.--7. 1. "S1,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 001." hexmask.long.byte 0xC 0.--3. 1. "S0,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 000." line.long 0x10 "INTRVL,LED Update Interval" hexmask.long.byte 0x10 28.--31. 1. "I7,The number of PWM periods between updates to current duty cycle when the segment index is equal to 111b." hexmask.long.byte 0x10 24.--27. 1. "I6,The number of PWM periods between updates to current duty cycle when the segment index is equal to 110b." newline hexmask.long.byte 0x10 20.--23. 1. "I5,The number of PWM periods between updates to current duty cycle when the segment index is equal to 101b." hexmask.long.byte 0x10 16.--19. 1. "I4,The number of PWM periods between updates to current duty cycle when the segment index is equal to 100b." newline hexmask.long.byte 0x10 12.--15. 1. "I3,The number of PWM periods between updates to current duty cycle when the segment index is equal to 011b." hexmask.long.byte 0x10 8.--11. 1. "I2,The number of PWM periods between updates to current duty cycle when the segment index is equal to 010b." newline hexmask.long.byte 0x10 4.--7. 1. "I1,The number of PWM periods between updates to current duty cycle when the segment index is equal to 001b." hexmask.long.byte 0x10 0.--3. 1. "I0,The number of PWM periods between updates to current duty cycle when the segment index is equal to 000b." line.long 0x14 "OUTDLY,LED Output Delay" hexmask.long.byte 0x14 0.--7. 1. "DELAY,The delay in counts of the clock defined in Clock Source (CLKSRC) in which output transitions are delayed. When this field is 0 there is no added transition delay. When the LED is programmed to be Always On or Always Off the Output.." tree.end tree "LED3" base ad:0x4000BB00 group.long 0x0++0x17 line.long 0x0 "CFG,LED Configuration" bitfld.long 0x0 16. "SYMMETRY,SYMMETRY 1=The rising and falling ramp times are in Asymmetric mode. 0=The rising and falling ramp times are in Symmetric mode." "0: The rising and falling ramp times are in..,1: The rising and falling ramp times are in.." hexmask.long.byte 0x0 8.--15. 1. "WDT_RELOAD,WDT_RELOAD The PWM Watchdog Timer counter reload value. On system reset it defaults to 14h which corresponds to a 4 second Watchdog timeout value." newline bitfld.long 0x0 7. "RST,RESET Writes of '1' to this bit resets the PWM registers to their default values. This bit is self clearing. Writes of '0' to this bit have no effect." "0,1" bitfld.long 0x0 6. "EN_UPDATE,ENABLE_UPDATE This bit is set to 1 when written with a '1'. Writes of '0' have no effect. Hardware clears this bit to 0 when the breathing configuration registers are updated at the end of a PWM period. The current state of the bit is readable.." "0,1" newline bitfld.long 0x0 4.--5. "PWM_SIZE,PWM_SIZE This bit controls the behavior of PWM: 3=Reserved 2=PWM is configured as a 6-bit PWM 1=PWM is configured as a 7-bit PWM 0=PWM is configured as an 8-bit PWM" "0: PWM is configured as an 8-bit PWM,1: PWM is configured as a 7-bit PWM,2: PWM is configured as a 6-bit PWM,3: Reserved" bitfld.long 0x0 3. "SYNCH,SYNCHRONIZE When this bit is '1' all counters for all LEDs are reset to their initial values. When this bit is '0' in the LED Configuration Register for all LEDs then all counters for LEDs that are configured to blink or breathe will increment.." "0,1" newline bitfld.long 0x0 2. "CLK_SRC,1=Clock source is the 48 MHz clock 0=Clock source is the 32.768 KHz clock" "0: Clock source is the 32,1: Clock source is the 48 MHz clock" bitfld.long 0x0 0.--1. "CTRL,CONTROL 3=PWM is always on 2=LED blinking (standard PWM) 1=LED breathing configuration 0=PWM is always off. All internal registers and counters are reset to 0. Clocks are gated" "0: PWM is always off,1: LED breathing configuration,2: LED blinking,3: PWM is always on" line.long 0x4 "LIMIT,LED Limits This register may be written at any time. Values written into the register are held in an holding register. which is transferred into the actual register at the end of a PWM period. The two byte fields may be written independently. Reads.." hexmask.long.byte 0x4 8.--15. 1. "MAX,In breathing mode when the current duty cycle is greater than or equal to this value the breathing apparatus holds the current duty cycle for the period specified by the field HD in register LED_DELAY then starts decrementing the current duty cycle" hexmask.long.byte 0x4 0.--7. 1. "MIN,In breathing mode when the current duty cycle is less than or equal to this value the breathing apparatus holds the current duty cycle for the period specified by the field LD in register LED_DELAY then starts incrementing the current duty cycle In.." line.long 0x8 "DLY,LED Delay" hexmask.long.word 0x8 12.--23. 1. "HIGH_PULSE,In breathing mode the number of PWM periods to wait before updating the current duty cycle when the current duty cycle is greater than or equal to the value MAX in register LED_LIMIT." hexmask.long.word 0x8 0.--11. 1. "LOW_PULSE,The number of PWM periods to wait before updating the current duty cycle when the current duty cycle is greater than or equal to the value MIN in register LED_LIMIT." line.long 0xC "STEP,This register has eight segment fields which provide the amount the current duty cycle is adjusted at the end of every PWM period. Segment field selection is decoded based on the segment index. The segment index equation utilized depends on the.." hexmask.long.byte 0xC 28.--31. 1. "S7,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 111." hexmask.long.byte 0xC 24.--27. 1. "S6,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 110." newline hexmask.long.byte 0xC 20.--23. 1. "S5,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 101" hexmask.long.byte 0xC 16.--19. 1. "S4,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 100." newline hexmask.long.byte 0xC 12.--15. 1. "S3,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 011." hexmask.long.byte 0xC 8.--11. 1. "S2,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 010." newline hexmask.long.byte 0xC 4.--7. 1. "S1,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 001." hexmask.long.byte 0xC 0.--3. 1. "S0,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 000." line.long 0x10 "INTRVL,LED Update Interval" hexmask.long.byte 0x10 28.--31. 1. "I7,The number of PWM periods between updates to current duty cycle when the segment index is equal to 111b." hexmask.long.byte 0x10 24.--27. 1. "I6,The number of PWM periods between updates to current duty cycle when the segment index is equal to 110b." newline hexmask.long.byte 0x10 20.--23. 1. "I5,The number of PWM periods between updates to current duty cycle when the segment index is equal to 101b." hexmask.long.byte 0x10 16.--19. 1. "I4,The number of PWM periods between updates to current duty cycle when the segment index is equal to 100b." newline hexmask.long.byte 0x10 12.--15. 1. "I3,The number of PWM periods between updates to current duty cycle when the segment index is equal to 011b." hexmask.long.byte 0x10 8.--11. 1. "I2,The number of PWM periods between updates to current duty cycle when the segment index is equal to 010b." newline hexmask.long.byte 0x10 4.--7. 1. "I1,The number of PWM periods between updates to current duty cycle when the segment index is equal to 001b." hexmask.long.byte 0x10 0.--3. 1. "I0,The number of PWM periods between updates to current duty cycle when the segment index is equal to 000b." line.long 0x14 "OUTDLY,LED Output Delay" hexmask.long.byte 0x14 0.--7. 1. "DELAY,The delay in counts of the clock defined in Clock Source (CLKSRC) in which output transitions are delayed. When this field is 0 there is no added transition delay. When the LED is programmed to be Always On or Always Off the Output.." tree.end tree.end tree "MBX (Mailbox Interface)" base ad:0x400F0000 group.byte 0x0++0x1 line.byte 0x0 "RT_IDX,MBX_Index Register" line.byte 0x1 "RT_DATA,MBX_Data_Register" group.long 0x100++0x3 line.long 0x0 "H2EC,If enabled. an interrupt to the EC marked by the MBX_DATA bit in the Interrupt Aggregator will be generated whenever the Host writes this register. This register is cleared when written with FFh." group.byte 0x104++0x0 line.byte 0x0 "EC2H,An EC write to this register will set bit EC_WR in the SMI Interrupt Source Register to '1b'. If enabled. this will generate a Host SMI. This register is cleared when written with FFh." group.long 0x108++0x7 line.long 0x0 "SMI_SRC,SMI Interrupt Source Register" hexmask.long.byte 0x0 1.--7. 1. "EC_SWI,EC Software Interrupt. An SIRQ to the Host is generated when any bit in this register when this bit is set to '1b' and the corresponding bit in the SMI Interrupt Mask Register register is '1b'." bitfld.long 0x0 0. "EC_WR,EC Mailbox Write. This bit is set automatically when the EC-to-Host Mailbox Register has been written. An SMI or SIRQ to the Host is generated when n this bit is '1b' and the corresponding bit in the SMI Interrupt Mask Register register is.." "0,1" line.long 0x4 "SMI_MASK,SMI Interrupt Mask Register" hexmask.long.byte 0x4 1.--7. 1. "ECSWI_EN,EC Software Interrupt Enable. If this bit is '1b' the bit EC_WR in the SMI Interrupt Source Register is enabled for the generation of SIRQ or nSMI events." bitfld.long 0x4 0. "ECWR_EN,EC Mailbox Write.Interrupt Enable. Each bit in this field that is '1b' enables the generation of SIRQ interrupts when the corresponding bit in the EC_SWI field in the SMI Interrupt Source Register is '1b'." "0,1" repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0x400F0110 ad:0x400F0114 ad:0x400F0118 ad:0x400F011C ad:0x400F0120 ad:0x400F0124 ad:0x400F0128 ad:0x400F012C) tree "MBX_REG[$1]" base $2 group.long ($2)++0x3 line.long 0x0 "u32,SOURCE" repeat 2. (increment 0x0 0x1)(increment 0x0 0x2) group.word ($2)++0x1 line.word 0x0 "u16[$1],ENABLE SET" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "u08[$1],RESULT" repeat.end tree.end repeat.end tree.end tree "OTP (One Time Programmable Memory)" base ad:0x40082000 group.byte 0x44++0x7 line.byte 0x0 "WR_LOCK0,This is the Write Lock Register." hexmask.byte 0x0 0.--7. 1. "WL0,When any of the bits are set the corresponding 32byte range in the OTP is not writable." line.byte 0x1 "WR_LOCK1,This is the Write Lock Register." hexmask.byte 0x1 0.--7. 1. "WL1,When any of the bits are set the corresponding 32byte range in the OTP is not writable." line.byte 0x2 "WR_LOCK2,This is the Write Lock Register." hexmask.byte 0x2 0.--7. 1. "WL2,When any of the bits are set the corresponding 32byte range in the OTP is not writable." line.byte 0x3 "WR_LOCK3,This is the Write Lock Register." hexmask.byte 0x3 0.--7. 1. "WL3,When any of the bits are set the corresponding 32byte range in the OTP is not writable." line.byte 0x4 "RD_LOCK0,This is the Read Lock Register." hexmask.byte 0x4 0.--7. 1. "RL0,When any of the bits are set the corresponding 32byte range in the OTP is not readable." line.byte 0x5 "RD_LOCK1,This is the Read Lock Register." hexmask.byte 0x5 0.--7. 1. "RL1,When any of the bits are set the corresponding 32byte range in the OTP is not readable." line.byte 0x6 "RD_LOCK2,This is the Read Lock Register." hexmask.byte 0x6 0.--7. 1. "RL2,When any of the bits are set the corresponding 32byte range in the OTP is not readable." line.byte 0x7 "RD_LOCK3,This is the Read Lock Register." hexmask.byte 0x7 0.--7. 1. "RL3,When any of the bits are set the corresponding 32byte range in the OTP is not readable." group.long 0x4C++0x7 line.long 0x0 "WR_FINE_LCK,This is the Write Fine Lock Register." hexmask.long 0x0 0.--31. 1. "WR_FINE_LCK,Each bit locks write to a byte in the OTP range starting byte 320 to 351 0=Not Locked 1=Locked." line.long 0x4 "RD_FINE_LCK,This is the Read Fine Lock Register." hexmask.long 0x4 0.--31. 1. "RD_FINE_LCK,Each bit locks read to a byte in the OTP range starting byte 320 to 351 0=Not Locked 1=Locked." tree.end tree "PCR (Power Clocks and Resets)" base ad:0x40080100 group.long 0x0++0x1B line.long 0x0 "SYS_SLP_CTRL,System Sleep Control" bitfld.long 0x0 3. "SLP_ALL,Initiates the System Sleep mode" "0,1" newline bitfld.long 0x0 2. "REG_STNDBY_EN,Regulator Standby Enable" "0,1" newline bitfld.long 0x0 0. "SL_MOD,Selects the System Sleep mode" "0,1" line.long 0x4 "PROC_CLK_CTRL,Processor Clock Control Register [7:0] Processor Clock Divide Value (PROC_DIV)" hexmask.long.byte 0x4 0.--7. 1. "DIV,Selects the EC clock rate" line.long 0x8 "SLOW_CLK_CTRL,Configures the EC_CLK clock domain" hexmask.long.word 0x8 0.--9. 1. "DIV,SLOW_CLOCK_DIVIDE. n=Divide by n; 0=Clock off" line.long 0xC "OSC_ID,Oscillator ID Register" bitfld.long 0xC 8. "PLL_LOCK,PLL Lock Status" "0,1" newline hexmask.long.byte 0xC 0.--7. 1. "TEST,Test bits" line.long 0x10 "PWR_RST_STS,PCR Power Reset Status Register" bitfld.long 0x10 12. "ESPI_CLK_ACTIVE,ESPI_CLK_ACTIVE" "0,1" newline bitfld.long 0x10 11. "PCICLK_ACTIVE,PCICLK_ACTIVE (PCICLK_ACTIVE)" "0,1" newline bitfld.long 0x10 10. "ACTIVE_32K,32K ACTIVE (ACTIVE_32K)" "0,1" newline bitfld.long 0x10 8. "WDT_EVENT,Indicates that a WDT_EVENT happened. (R/W1C) 0 = Not active. 1 = A WDT_EVENT occured." "0: Not active,1: A WDT_EVENT occured" newline bitfld.long 0x10 7. "JTAG_RST_STS,Indicates status of JTAG_TRST# pin. 0 = No JTAG reset occurred since the last time this bit was cleared. 1 = A reset occurred because of a JTAG command." "0: No JTAG reset occurred since the last time this..,1: A reset occurred because of a JTAG command" newline bitfld.long 0x10 6. "RST_SYS_STS,Indicates the status of RESET_SYS.(R/W1C) 0 = No reset occurred since the last time this bit was cleared. 1 = A reset occurred." "0: No reset occurred since the last time this bit..,1: A reset occurred" newline bitfld.long 0x10 5. "VBAT_RST_STS,VBAT reset status 0 = No reset occurred while VTR was off or since the last time this bit was cleared. 1 = A reset occurred.(R/WC)" "0: No reset occurred while VTR was off or since the..,1: A reset occurred" newline bitfld.long 0x10 4. "RST_VTR_STS,Indicates the status of RESET_VTR. 0 = reset active. 1 = reset not active.(R/W1C)" "0: reset active,1: reset not active" newline bitfld.long 0x10 3. "RST_H_STS,Indicates the status of RESET_VCC. 0 = reset active. 1 = reset not active." "0: reset active,1: reset not active" newline bitfld.long 0x10 2. "VCC_PWRGD_STS,Indicates the status of VCC_PWRGD. 0 = PWRGD not asserted. 1 = PWRGD asserte." "0: PWRGD not asserted,1: PWRGD asserte" line.long 0x14 "PWR_RST_CTRL,Power Reset Control Register" bitfld.long 0x14 8. "H_RST_SEL,Determines what generates the internal platform reset signal. 1=LRESET# pin; 0=eSPI PLTRST# VWire" "0: eSPI PLTRST# VWire,1: LRESET# pin" newline bitfld.long 0x14 0. "PWR_INV,Used by FW to control internal RESET_VCC signal function and external PWROK pin. This bit is read-only when VCC_PWRGD is de-asserted low." "0,1" line.long 0x18 "SYS_RST,System Reset Register" bitfld.long 0x18 8. "SOFT_SYS_RST,A write of a 1 forces an assertion of the RESET_SYS reset signal resetting the device. A write of 0 has no effect." "0,1" group.long 0x30++0x13 line.long 0x0 "SLP_EN_0,Sleep Enable 0 Register" bitfld.long 0x0 2. "IMSPI_SLP_EN,IMSPI Sleep Enable" "0,1" newline bitfld.long 0x0 1. "OTP_SLP_EN,OTP Enable" "0,1" line.long 0x4 "SLP_EN_1,Sleep Enable 1 Register" bitfld.long 0x4 31. "TMR16_1_SLP_EN,TIMER16_1 Sleep Enable (TIMER16_1_SLP_EN)" "0,1" newline bitfld.long 0x4 30. "TMR16_0_SLP_EN,TIMER16_0 Sleep Enable (TIMER16_0_SLP_EN)" "0,1" newline bitfld.long 0x4 29. "EC_REG_BANK_SLP_EN,EC_REG_BANK Sleep Enable (EC_REG_BANK_SLP_EN)" "0,1" newline bitfld.long 0x4 27. "PWM8_SLP_EN,PWM8 Sleep Enable (PWM8_SLP_EN)" "0,1" newline bitfld.long 0x4 26. "PWM7_SLP_EN,PWM7 Sleep Enable (PWM7_SLP_EN)" "0,1" newline bitfld.long 0x4 25. "PWM6_SLP_EN,PWM6 Sleep Enable (PWM6_SLP_EN)" "0,1" newline bitfld.long 0x4 24. "PWM5_SLP_EN,PWM5 Sleep Enable (PWM5_SLP_EN)" "0,1" newline bitfld.long 0x4 23. "PWM4_SLP_EN,PWM4 Sleep Enable (PWM4_SLP_EN)" "0,1" newline bitfld.long 0x4 22. "PWM3_SLP_EN,PWM3 Sleep Enable (PWM3_SLP_EN)" "0,1" newline bitfld.long 0x4 21. "PWM2_SLP_EN,PWM2 Sleep Enable (PWM2_SLP_EN)" "0,1" newline bitfld.long 0x4 20. "PWM1_SLP_EN,PWM1 Sleep Enable (PWM1_SLP_EN)" "0,1" newline bitfld.long 0x4 13. "TACH3_SLP_EN,TACH3 Sleep Enable (TACH3_SLP_EN)" "0,1" newline bitfld.long 0x4 12. "TACH2_SLP_EN,TACH2 Sleep Enable (TACH2_SLP_EN)" "0,1" newline bitfld.long 0x4 11. "TACH1_SLP_EN,TACH1 Sleep Enable (TACH1_SLP_EN)" "0,1" newline bitfld.long 0x4 10. "SMB0_SLP_EN,SMB0 Sleep Enable (SMB0_SLP_EN)" "0,1" newline bitfld.long 0x4 8. "PROC_SLP_EN,PROCESSOR Sleep Enable (PROCESSOR_SLP_EN)" "0,1" newline bitfld.long 0x4 7. "TFDP_SLP_EN,TFDP Sleep Enable (TFDP_SLP_EN)" "0,1" newline bitfld.long 0x4 6. "DMA_SLP_EN,DMA Sleep Enable (DMA_SLP_EN)" "0,1" newline bitfld.long 0x4 5. "PMC_SLP_EN,PMC Sleep Enable (PMC_SLP_EN)" "0,1" newline bitfld.long 0x4 4. "PWM0_SLP_EN,PWM0 Sleep Enable (PWM0_SLP_EN)" "0,1" newline bitfld.long 0x4 2. "TACH0_SLP_EN,TACH0 Sleep Enable (TACH0_SLP_EN)" "0,1" newline bitfld.long 0x4 1. "PECI_SLP_EN,PECI Sleep Enable" "0,1" newline bitfld.long 0x4 0. "INT_SLP_EN,Interrupt Sleep Enable" "0,1" line.long 0x8 "SLP_EN_2,Sleep Enable 2 Register" bitfld.long 0x8 29. "GLUE_SLP_EN,GLUE Sleep Enable" "0,1" newline bitfld.long 0x8 27. "SAF_BRDG_SLP_EN,SAF BRIDGE Sleep Enable" "0,1" newline bitfld.long 0x8 19. "ESPI_SLP_EN,eSPI Sleep Enable" "0,1" newline bitfld.long 0x8 2. "UART1_SLP_EN,UART 1 Sleep Enable" "0,1" newline bitfld.long 0x8 1. "UART0_SLP_EN,UART 0 Sleep Enable" "0,1" line.long 0xC "SLP_EN_3,Sleep Enable 3 Register" bitfld.long 0xC 31. "PWM9_SLP_EN,PWM9 Sleep Enable (PWM9_SLP_EN)" "0,1" newline bitfld.long 0xC 30. "CCT_SLP_EN,Capture Compare Timer Sleep Enable (CCTIMER_SLP_EN)" "0,1" newline bitfld.long 0xC 29. "HTM_1_SLP_EN,Hibernation TIMER 1 Sleep Enable (HTM_1_SLP_EN)" "0,1" newline bitfld.long 0xC 28. "AES_HASH_SLP_EN,AES_HASH Sleep Enable" "0,1" newline bitfld.long 0xC 27. "RNG_SLP_EN,RNG Sleep Enable" "0,1" newline bitfld.long 0xC 26. "PKE_SLP_EN,PKE Sleep Enable" "0,1" newline bitfld.long 0xC 25. "LED3_SLP_EN,LED3 Sleep Enable (LED3_SLP_EN)" "0,1" newline bitfld.long 0xC 24. "TMR32_1_SLP_EN,TIMER32_1 Sleep Enable (TIMER32_1_SLP_EN)" "0,1" newline bitfld.long 0xC 23. "TMR32_0_SLP_EN,TIMER32_0 Sleep Enable (TIMER32_0_SLP_EN)" "0,1" newline bitfld.long 0xC 22. "TMR16_3_SLP_EN,TIMER16_3 Sleep Enable (TIMER16_3_SLP_EN)" "0,1" newline bitfld.long 0xC 21. "TMR16_2_SLP_EN,TIMER16_2 Sleep Enable (TIMER16_2_SLP_EN)" "0,1" newline bitfld.long 0xC 20. "SMB4_SLP_EN,SMB4 Sleep Enable (SMB4_SLP_EN)" "0,1" newline bitfld.long 0xC 19. "BC_LINK0_SLP_EN,BC_LINK0 Sleep Enable (BC_LINK0_SLP_EN)" "0,1" newline bitfld.long 0xC 18. "LED2_SLP_EN,LED2 Sleep Enable (LED2_SLP_EN)" "0,1" newline bitfld.long 0xC 17. "LED1_SLP_EN,LED1 Sleep Enable (LED1_SLP_EN)" "0,1" newline bitfld.long 0xC 16. "LED0_SLP_EN,LED0 Sleep Enable (LED0_SLP_EN)" "0,1" newline bitfld.long 0xC 15. "SMB3_SLP_EN,SMB3 Sleep Enable (SMB3_SLP_EN)" "0,1" newline bitfld.long 0xC 14. "SMB2_SLP_EN,SMB2 Sleep Enable (SMB2_SLP_EN)" "0,1" newline bitfld.long 0xC 13. "SMB1_SLP_EN,SMB1 Sleep Enable (SMB1_SLP_EN)" "0,1" newline bitfld.long 0xC 10. "HTM_0_SLP_EN,Hibernation Timer 0 Sleep Enable (HTM_0_SLP_EN)" "0,1" newline bitfld.long 0xC 9. "GPSPI_0_SLP_EN,GPSPI 0 Sleep Enable (GPSPI_0_SLP_EN)" "0,1" newline bitfld.long 0xC 5. "PS2_0_SLP_EN,PS2_0 Sleep Enable (PS2_0_SLP_EN)" "0,1" newline bitfld.long 0xC 3. "ADC_SLP_EN,ADC Sleep Enable (ADC_SLP_EN)" "0,1" line.long 0x10 "SLP_EN_4,Sleep Enable 4 Register" bitfld.long 0x10 22. "GPSPI_1_SLP_EN,GPSPI 1 Sleep Enable (GPSPI_1_SLP_EN)" "0,1" newline sif (cpuis("MEC1723N*")) bitfld.long 0x10 14. "EEPROM_SLP_EN,EEPROM Sleep Enable (EEPROM_SLP_EN)" "0,1" newline endif sif (cpuis("MEC1724N*")) bitfld.long 0x10 14. "EEPROM_SLP_EN,EEPROM Sleep Enable (EEPROM_SLP_EN)" "0,1" newline endif bitfld.long 0x10 12. "RC_ID2_SLP_EN,RC_ID2 Sleep Enable (RC_ID2_SLP_EN)" "0,1" newline bitfld.long 0x10 11. "RC_ID1_SLP_EN,RC_ID1 Sleep Enable (RC_ID1_SLP_EN)" "0,1" newline bitfld.long 0x10 10. "RC_ID0_SLP_EN,RC_ID0 Sleep Enable (RC_ID0_SLP_EN)" "0,1" newline bitfld.long 0x10 8. "QMSPI_SLP_EN,Quad Master SPI Sleep Enable" "0,1" newline bitfld.long 0x10 1. "PWM11_SLP_EN,PWM11 Sleep Enable (PWM11_SLP_EN)" "0,1" newline bitfld.long 0x10 0. "PWM10_SLP_EN,PWM10 Sleep Enable (PWM10_SLP_EN)" "0,1" group.long 0x50++0x13 line.long 0x0 "CLK_REQ_0,Clock Required 0 Register" bitfld.long 0x0 2. "IMSPI_CLK_REQ,IMSPI Sleep clock Required" "0,1" newline bitfld.long 0x0 1. "OTP_CLK_REQ,OTP Enable" "0,1" newline bitfld.long 0x0 0. "JTAG_STAP_CLK_REQ,JTAG STAP Enable" "0,1" line.long 0x4 "CLK_REQ_1,Clock Required 1 Register" bitfld.long 0x4 31. "TMR16_1_CLK_REQ,TIMER16_1 Clock Required (TIMER16_1_CLK_REQ)" "0,1" newline bitfld.long 0x4 30. "TMR16_0_CLK_REQ,TIMER16_0 Clock Required (TIMER16_0_CLK_REQ)" "0,1" newline bitfld.long 0x4 29. "EC_REG_BANK_CLK_REQ,EC_REG_BANK Clock Required (EC_REG_BANK_CLK_REQ)" "0,1" newline bitfld.long 0x4 27. "PWM8_CLK_REQ,PWM8 Clock Required (PWM8_CLK_REQ)" "0,1" newline bitfld.long 0x4 26. "PWM7_CLK_REQ,PWM7 Clock Required (PWM7_CLK_REQ)" "0,1" newline bitfld.long 0x4 25. "PWM6_CLK_REQ,PWM6 Clock Required (PWM6_CLK_REQ)" "0,1" newline bitfld.long 0x4 24. "PWM5_CLK_REQ,PWM5 Clock Required (PWM5_CLK_REQ)" "0,1" newline bitfld.long 0x4 23. "PWM4_CLK_REQ,PWM4 Clock Required (PWM4_CLK_REQ)" "0,1" newline bitfld.long 0x4 22. "PWM3_CLK_REQ,PWM3 Clock Required (PWM3_CLK_REQ)" "0,1" newline bitfld.long 0x4 21. "PWM2_CLK_REQ,PWM2 Clock Required (PWM2_CLK_REQ)" "0,1" newline bitfld.long 0x4 20. "PWM1_CLK_REQ,PWM1 Clock Required (PWM1_CLK_REQ)" "0,1" newline bitfld.long 0x4 13. "TACH3_CLK_REQ,TACH3 Clock Required (TACH3_CLK_REQ)" "0,1" newline bitfld.long 0x4 12. "TACH2_CLK_REQ,TACH2 Clock Required (TACH2_CLK_REQ)" "0,1" newline bitfld.long 0x4 11. "TACH1_CLK_REQ,TACH1 Clock Required (TACH1_CLK_REQ)" "0,1" newline bitfld.long 0x4 10. "SMB0_CLK_REQ,SMB0 Clock Required (SMB0_CLK_REQ)" "0,1" newline bitfld.long 0x4 9. "WDT_CLK_REQ,WDT Clock Required (WDT_CLK_REQ)" "0,1" newline bitfld.long 0x4 8. "PROC_CLK_REQ,PROCESSOR Clock Required (PROCESSOR_CLK_REQ)" "0,1" newline bitfld.long 0x4 7. "TFDP_CLK_REQ,TFDP Clock Required (TFDP_CLK_REQ)" "0,1" newline bitfld.long 0x4 6. "DMA_CLK_REQ,DMA Clock Required (DMA_CLK_REQ)" "0,1" newline bitfld.long 0x4 5. "PMC_CLK_REQ,PMC Clock Required (PMC_CLK_REQ)" "0,1" newline bitfld.long 0x4 4. "PWM0_CLK_REQ,PWM0 Clock Required (PWM0_CLK_REQ)" "0,1" newline bitfld.long 0x4 2. "TACH0_CLK_REQ,TACH0 Clock Required (TACH0_CLK_REQ)" "0,1" newline bitfld.long 0x4 1. "PECI_CLK_REQ,PECI Clock Required" "0,1" newline bitfld.long 0x4 0. "INT_CLK_REQ,Interrupt Clock Required" "0,1" line.long 0x8 "CLK_REQ_2,Clock Required 2 Register" bitfld.long 0x8 27. "SAF_BRDG_CLK_REQ,SAF BRIDGE Clock Required" "0,1" newline bitfld.long 0x8 24. "ASIF_CLK_REQ,ASIF Clock Required" "0,1" newline bitfld.long 0x8 19. "ESPI_CLK_REQ,eSPI Clock Required" "0,1" newline bitfld.long 0x8 18. "RTC_CLK_REQ,RTC Clock Required (RTC_CLK_REQ)" "0,1" newline bitfld.long 0x8 16. "KBCEM_CLK_REQ,8042EM Clock Required (8042EM_CLK_REQ)" "0,1" newline bitfld.long 0x8 12. "GLBL_CFG_CLK_REQ,GLBL_CFG (GLBL_CFG_CLK_REQ)" "0,1" newline bitfld.long 0x8 2. "UART1_CLK_REQ,UART 1 Clock Required" "0,1" newline bitfld.long 0x8 1. "UART0_CLK_REQ,UART 0 Clock Required" "0,1" newline bitfld.long 0x8 0. "IMAP_CLK_REQ,IMAP Clock Required (IMAP_CLK_REQ)" "0,1" line.long 0xC "CLK_REQ_3,Clock Required 3 Register" bitfld.long 0xC 31. "PWM9_CLK_REQ,PWM9 Clock Required (PWM9_CLK_REQ)" "0,1" newline bitfld.long 0xC 30. "CCTIMER_CLK_REQ,Capture Compare Timer Clock Required (CCTIMER_CLK_REQ)" "0,1" newline bitfld.long 0xC 29. "HTM_1_CLK_REQ,Hibernation TIMER 1 Clock Required (HTM_1_CLK_REQ)" "0,1" newline bitfld.long 0xC 28. "AES_HASH_CLK_REQ,AES_HASH Clock Required" "0,1" newline bitfld.long 0xC 27. "RNG_CLK_REQ,RNG Clock Required" "0,1" newline bitfld.long 0xC 26. "PKE_CLK_REQ,PKE Clock Required" "0,1" newline bitfld.long 0xC 25. "LED3_CLK_REQ,LED3 Clock Required (LED3_CLK_REQ)" "0,1" newline bitfld.long 0xC 24. "TMR32_1_CLK_REQ,TIMER32_1 Clock Required (TIMER32_1_CLK_REQ)" "0,1" newline bitfld.long 0xC 23. "TMR32_0_CLK_REQ,TIMER32_0 Clock Required (TIMER32_0_CLK_REQ)" "0,1" newline bitfld.long 0xC 22. "TMR16_3_CLK_REQ,TIMER16_3 Clock Required (TIMER16_3_CLK_REQ)" "0,1" newline bitfld.long 0xC 21. "TMR16_2_CLK_REQ,TIMER16_2 Clock Required (TIMER16_2_CLK_REQ)" "0,1" newline bitfld.long 0xC 20. "SMB_4_CLK_REQ,SMB 4 Clock Required (SMB_4_CLK_REQ)" "0,1" newline bitfld.long 0xC 19. "BC_LINK0_CLK_REQ,BC_LINK0 Clock Required (BC_LINK0_CLK_REQ)" "0,1" newline bitfld.long 0xC 18. "LED2_CLK_REQ,LED2 Clock Required (LED2_CLK_REQ)" "0,1" newline bitfld.long 0xC 17. "LED1_CLK_REQ,LED1 Clock Required (LED1_CLK_REQ)" "0,1" newline bitfld.long 0xC 16. "LED0_CLK_REQ,LED0 Clock Required (LED0_CLK_REQ)" "0,1" newline bitfld.long 0xC 15. "SMB3_CLK_REQ,SMB3 Clock Required (SMB3_CLK_REQ)" "0,1" newline bitfld.long 0xC 14. "SMB2_CLK_REQ,SMB2 Clock Required (SMB2_CLK_REQ)" "0,1" newline bitfld.long 0xC 13. "SMB1_CLK_REQ,SMB1 Clock Required (SMB1_CLK_REQ)" "0,1" newline bitfld.long 0xC 11. "KMS_CLK_REQ,KEYSCAN Clock Required (KMS_CLK_REQ)" "0,1" newline bitfld.long 0xC 10. "HTM0_CLK_REQ,Hibernation TIMER 0 Clock Required (HTM_0_CLK_REQ)" "0,1" newline bitfld.long 0xC 9. "GPSPI_0_CLK_REQ,GPSPI 0 Clock Required (GPSPI_0_CLK_REQ)" "0,1" newline bitfld.long 0xC 5. "PS2_0_CLK_REQ,PS2_0 Clock Required (PS2_0_CLK_REQ)" "0,1" newline bitfld.long 0xC 3. "ADC_CLK_REQ,ADC Clock Required (ADC_CLK_REQ)" "0,1" line.long 0x10 "CLK_REQ_4,Clock Required 4 Register" bitfld.long 0x10 22. "GPSPI_1_CLK_REQ,GPSPI 1 Clock Required (GPSPI_1_CLK_REQ)" "0,1" newline bitfld.long 0x10 16. "SPI_SLAVE_CLK_REQ,SPI SLAVE Clock Required (SPI_SLAVE_CLK_REQ)" "0,1" newline sif (cpuis("MEC1723N*")) bitfld.long 0x10 14. "EEPROM_CLK_REQ,EEPROM Clock Required (EEPROM_CLK_REQ)" "0,1" newline endif sif (cpuis("MEC1724N*")) bitfld.long 0x10 14. "EEPROM_CLK_REQ,EEPROM Clock Required (EEPROM_CLK_REQ)" "0,1" newline endif bitfld.long 0x10 12. "RC_ID2_CLK_REQ,RC_ID2 Clock Required (RC_ID2_CLK_REQ)" "0,1" newline bitfld.long 0x10 11. "RC_ID1_CLK_REQ,RC_ID1 Clock Required (RC_ID1_CLK_REQ)" "0,1" newline bitfld.long 0x10 10. "RC_ID0_CLK_REQ,RC_ID0 Clock Required (RC_ID0_CLK_REQ)" "0,1" newline bitfld.long 0x10 8. "QMSPI_CLK_REQ,Quad Master SPI Clock Required" "0,1" newline bitfld.long 0x10 6. "RTOS_CLK_REQ,RTOS Clock Required (RTOS_CLK_REQ)" "0,1" newline bitfld.long 0x10 1. "PWM11_CLK_REQ,PWM11 Clock Required (PWM11_CLK_REQ)" "0,1" newline bitfld.long 0x10 0. "PWM10_CLK_REQ,PWM10 Clock Required (PWM10_CLK_REQ)" "0,1" group.long 0x70++0x1F line.long 0x0 "RST_EN_0,Reset Enable 0 Register" bitfld.long 0x0 1. "OTP_RST_EN,OTP Reset Enable" "0,1" line.long 0x4 "RST_EN_1,Reset Enable 1 Register" bitfld.long 0x4 31. "TMR16_1_RST_EN,TIMER16_1 Reset Enable (TIMER16_1_RST_EN)" "0,1" newline bitfld.long 0x4 30. "TMR16_0_RST_EN,TIMER16_0 Reset Enable (TIMER16_0_RST_EN)" "0,1" newline bitfld.long 0x4 27. "PWM8_RST_EN,PWM8 Reset Enable (PWM8_RST_EN)" "0,1" newline bitfld.long 0x4 26. "PWM7_RST_EN,PWM7 Reset Enable (PWM7_RST_EN)" "0,1" newline bitfld.long 0x4 25. "PWM6_RST_EN,PWM6 Reset Enable (PWM6_RST_EN)" "0,1" newline bitfld.long 0x4 24. "PWM5_RST_EN,PWM5 Reset Enable (PWM5_RST_EN)" "0,1" newline bitfld.long 0x4 23. "PWM4_RST_EN,PWM4 Reset Enable (PWM4_RST_EN)" "0,1" newline bitfld.long 0x4 22. "PWM3_RST_EN,PWM3 Reset Enable (PWM3_RST_EN)" "0,1" newline bitfld.long 0x4 21. "PWM2_RST_EN,PWM2 Reset Enable (PWM2_RST_EN)" "0,1" newline bitfld.long 0x4 20. "PWM1_RST_EN,PWM1 Reset Enable (PWM1_RST_EN)" "0,1" newline bitfld.long 0x4 13. "TACH3_RST_EN,TACH3 Reset Enable (TACH3_RST_EN)" "0,1" newline bitfld.long 0x4 12. "TACH2_RST_EN,TACH2 Reset Enable (TACH2_RST_EN)" "0,1" newline bitfld.long 0x4 11. "TACH1_RST_EN,TACH1 Reset Enable (TACH1_RST_EN)" "0,1" newline bitfld.long 0x4 10. "SMB0_RST_EN,SMB0 Reset Enable (SMB0_RST_EN)" "0,1" newline bitfld.long 0x4 9. "WDT_RST_EN,WDT Reset Enable (WDT_RST_EN)" "0,1" newline bitfld.long 0x4 7. "TFDP_RST_EN,TFDP Reset Enable (TFDP_RST_EN)" "0,1" newline bitfld.long 0x4 6. "DMA_RST_EN,DMA Reset Enable (DMA_RST_EN)" "0,1" newline bitfld.long 0x4 4. "PWM0_RST_EN,PWM0 Reset Enable (PWM0_RST_EN)" "0,1" newline bitfld.long 0x4 2. "TACH0_RST_EN,TACH0 Reset Enable (TACH0_RST_EN)" "0,1" newline bitfld.long 0x4 1. "PECI_RST_EN,PECI Reset Enable" "0,1" newline bitfld.long 0x4 0. "INT_RST_EN,Interrupt Reset Enable" "0,1" line.long 0x8 "RST_EN_2,Reset Enable 2 Register" bitfld.long 0x8 25. "PORT_80_0_RST_EN,Port 80 0 Reset Enable" "0,1" newline bitfld.long 0x8 24. "ASIF_RST_EN,ASIF Reset Enable" "0,1" newline bitfld.long 0x8 22. "ACPI_EC_3_RST_EN,ACPI EC 3 Reset Enable (ACPI_EC_3_RST_EN)" "0,1" newline bitfld.long 0x8 21. "ACPI_EC_2_RST_EN,ACPI EC 2 Reset Enable (ACPI_EC_2_RST_EN)" "0,1" newline bitfld.long 0x8 20. "SCRATCH_32_RST_EN,SCRATCH 32 Reset Enable" "0,1" newline bitfld.long 0x8 18. "RTC_RST_EN,RTC Reset Enable (RTC_RST_EN)" "0,1" newline bitfld.long 0x8 17. "MBX_RST_EN,Mailbox Reset Enable (MBX_RST_EN)" "0,1" newline bitfld.long 0x8 16. "KBCEM_RST_EN,8042EM Reset Enable (8042EM_RST_EN)" "0,1" newline bitfld.long 0x8 15. "ACPI_PM1_RST_EN,ACPI PM1 Reset Enable (ACPI_PM1_RST_EN)" "0,1" newline bitfld.long 0x8 14. "ACPI_EC1_RST_EN,ACPI EC 1 Reset Enable (ACPI_EC_1_RST_EN)" "0,1" newline bitfld.long 0x8 13. "ACPI_EC0_RST_EN,ACPI EC 0 Reset Enable (ACPI_EC_0_RST_EN)" "0,1" newline bitfld.long 0x8 2. "UART1_RST_EN,UART 1 Reset Enable" "0,1" newline bitfld.long 0x8 1. "UART0_RST_EN,UART 0 Reset Enable" "0,1" newline bitfld.long 0x8 0. "IMAP_RST_EN,IMAP Reset Enable (IMAP_RST_EN)" "0,1" line.long 0xC "RST_EN_3,Reset Enable 3 Register" bitfld.long 0xC 31. "PWM9_RST_EN,PWM9 Reset Enable (PWM9_RST_EN)" "0,1" newline bitfld.long 0xC 30. "CCTIMER_RST_EN,Capture Compare Timer Reset Enable (CCTIMER_RST_EN)" "0,1" newline bitfld.long 0xC 29. "HTM_1_RST_EN,Hibernation TIMER 1 Reset Enable (HTM_1_RST_EN)" "0,1" newline bitfld.long 0xC 28. "AES_HASH_RST_EN,AES_HASH Reset Enable" "0,1" newline bitfld.long 0xC 27. "RNG_RST_EN,RNG Reset Enable" "0,1" newline bitfld.long 0xC 26. "PKE_RST_EN,PKE Reset Enable" "0,1" newline bitfld.long 0xC 25. "LED3_RST_EN,LED3 Reset Enable (LED3_RST_EN)" "0,1" newline bitfld.long 0xC 24. "TMR32_1_RST_EN,TIMER32_1 Reset Enable (TIMER32_1_RST_EN)" "0,1" newline bitfld.long 0xC 23. "TMR32_0_RST_EN,TIMER32_0 Reset Enable (TIMER32_0_RST_EN)" "0,1" newline bitfld.long 0xC 22. "TMR16_3_RST_EN,TIMER16_3 Reset Enable (TIMER16_3_RST_EN)" "0,1" newline bitfld.long 0xC 21. "TMR16_2_RST_EN,TIMER16_2 Reset Enable (TIMER16_2_RST_EN)" "0,1" newline bitfld.long 0xC 20. "SMB_4_RST_EN,SMB 4 Reset Enable (SMB_4_RST_EN)" "0,1" newline bitfld.long 0xC 19. "BC_LINK0_RST_EN,BC_LINK0 Reset Enable (BC_LINK0_RST_EN)" "0,1" newline bitfld.long 0xC 18. "LED2_RST_EN,LED2 Reset Enable (LED2_RST_EN)" "0,1" newline bitfld.long 0xC 17. "LED1_RST_EN,LED1 Reset Enable (LED1_RST_EN)" "0,1" newline bitfld.long 0xC 16. "LED0_RST_EN,LED0 Reset Enable (LED0_RST_EN)" "0,1" newline bitfld.long 0xC 15. "SMB3_RST_EN,SMB3 Reset Enable (SMB3_RST_EN)" "0,1" newline bitfld.long 0xC 14. "SMB2_RST_EN,SMB2 Reset Enable (SMB2_RST_EN)" "0,1" newline bitfld.long 0xC 13. "SMB1_RST_EN,SMB1 Reset Enable (SMB1_RST_EN)" "0,1" newline bitfld.long 0xC 11. "KMS_RST_EN,KEYSCAN Reset Enable (KMS_RST_EN)" "0,1" newline bitfld.long 0xC 10. "HTM_0_RST_EN,Hibernation TIMER 0 Reset Enable (HTM_0_RST_EN)" "0,1" newline bitfld.long 0xC 9. "GPSPI_0_RST_EN,GPSPI 0 Reset Enable (GPSPI_0_RST_EN)" "0,1" newline bitfld.long 0xC 5. "PS2_0_RST_EN,PS2_0 Reset Enable (PS2_0_RST_EN)" "0,1" newline bitfld.long 0xC 3. "ADC_RST_EN,ADC Reset Enable (ADC_RST_EN)" "0,1" line.long 0x10 "RST_EN_4,Reset Enable 4 Register" bitfld.long 0x10 22. "GPSPI_1_RST_EN,GPSPI 1 Reset Enable (GPSPI_1_RST_EN)" "0,1" newline bitfld.long 0x10 16. "SPI_SLAVE_RST_EN,SPI SLAVE Reset Enable (SPI_SLAVE_RST_EN)" "0,1" newline sif (cpuis("MEC1723N*")) bitfld.long 0x10 14. "EEPROM_RST_EN,EEPROM Reset Enable (EEPROM_RST_EN)" "0,1" newline endif sif (cpuis("MEC1724N*")) bitfld.long 0x10 14. "EEPROM_RST_EN,EEPROM Reset Enable (EEPROM_RST_EN)" "0,1" newline endif bitfld.long 0x10 12. "RC_ID2_RST_EN,RC_ID2 Reset Enable (RC_ID2_RST_EN)" "0,1" newline bitfld.long 0x10 11. "RC_ID1_RST_EN,RC_ID1 Reset Enable (RC_ID1_RST_EN)" "0,1" newline bitfld.long 0x10 10. "RC_ID0_RST_EN,RC_ID0 Reset Enable (RC_ID0_RST_EN)" "0,1" newline bitfld.long 0x10 8. "QMSPI_RST_EN,Quad Master SPI Reset Enable" "0,1" newline bitfld.long 0x10 6. "RTOS_RST_EN,RTOS Reset Enable (RTOS_RST_EN)" "0,1" newline bitfld.long 0x10 1. "PWM11_RST_EN,PWM11 Reset Enable (PWM11_RST_EN)" "0,1" newline bitfld.long 0x10 0. "PWM10_RST_EN,PWM10 Reset Enable (PWM10_RST_EN)" "0,1" line.long 0x14 "LOCK_REG,LOCK Register" hexmask.long 0x14 0.--31. 1. "PCR_RST_EN_LOCK,PCR Reset Enable Lock Register." line.long 0x18 "SFT_VBAT_POR,SOFT VBAT Register" bitfld.long 0x18 0. "SFT_VBAT_POR,SOFT VBAT POWER ON RESET." "0,1" line.long 0x1C "PLL_REF,PLL reference clock select." bitfld.long 0x1C 0.--1. "PLL_REF,Source 32kHz MUX Select for the PLL reference clock source. 0 = Internal Silicon Oscillator 1 = XTAL 2 = VTR PIN 32KHZ_IN 3 = NONE-OFF" "0: Internal Silicon Oscillator,1: XTAL,2: VTR PIN 32KHZ_IN,3: NONE-OFF" rgroup.long 0x94++0xB line.long 0x0 "REG_CTRL_RUN,Regulator Control Running Register" hexmask.long 0x0 0.--31. 1. "CTRL_RUN,Regulator Control Running Register." line.long 0x4 "REG_CTRL_SLP,Regulator Control Sleeping Register" hexmask.long 0x4 0.--31. 1. "CTRL_SLP,Regulator Control Running Register." line.long 0x8 "REG_TIM,Regulator Time Register" hexmask.long.word 0x8 16.--29. 1. "PWRDN_DLY,Regulator Power Down delay Register." newline hexmask.long.word 0x8 0.--13. 1. "PWRUP_DLY,Regulator Power Up delay Register." rgroup.long 0xA4++0x7 line.long 0x0 "BNDGP_CTRL_RUN,Bandgap Control Running Register" hexmask.long 0x0 0.--31. 1. "CTRL_RUN,Regulator Control Running Register." line.long 0x4 "BNDGP_CTRL_SLP,Bandgap Control Sleeping Register" hexmask.long 0x4 0.--31. 1. "CTRL_SLP,Regulator Control Running Register." rgroup.long 0xC0++0xB line.long 0x0 "CLK_PRD,32KHz Period Counter Register" hexmask.long 0x0 0.--31. 1. "CLK_PRD,Counter 32khz period Counts system clock cycles between 2 positive edges of an 32kHz clock." line.long 0x4 "CLK_HGHPLS,32KHz Clock High Pulse Register" hexmask.long 0x4 0.--31. 1. "CLK_HGHPLS,Counter 32khz High Counts how many system clock cycles the 32kHz clock remains HIGH for." line.long 0x8 "CLK_MINPRD,32KHz Clock Min Period Register" hexmask.long 0x8 0.--31. 1. "CLK_MINPRD,This is the minimum period count that is acceptable for the 32kHz counter to flag a PASS status." group.long 0xCC++0x3 line.long 0x0 "CLK_MAXPRD,32KHz Clock Max Period Register" hexmask.long 0x0 0.--31. 1. "CLK_MAXPRD,This is the maximum period count that is acceptable for the 32kHz counter to flag a PASS status." rgroup.long 0xD0++0x3 line.long 0x0 "CLK_DTYVRTN,32KHz Clock Duty Variation Register" hexmask.long 0x0 0.--31. 1. "CLK_DTYVRTN,This is the difference in system clocks between the 32kHz clocks High Pulse Width and its Low Pulse Width." group.long 0xD4++0x3 line.long 0x0 "CLK_MAXDTYVRTN,32KHz Maximum Clock Duty Variation Register" hexmask.long 0x0 0.--31. 1. "CLK_MAXDTYVRTN,This is the difference maximum variation allowed to generate a PASS condition for the 32kHz clock" rgroup.long 0xD8++0x3 line.long 0x0 "CLK_VLDCNT,32KHz Clock Valid Count Register" hexmask.long 0x0 0.--31. 1. "CLK_VLDCNT,This counts the number of valid 32kHz periods and pulse width variations measured in a row. This count increments on a PASS and will reset on a FAIL." group.long 0xDC++0xF line.long 0x0 "CLK_VLDMIN,32KHz Clock Valid Minimum Count Register" hexmask.long 0x0 0.--31. 1. "CLK_VLDMIN,This is the minimum value of Counter 32kHz Valid Count that will flag the status Counter Valid." line.long 0x4 "CLK_32KHZ_CTRL,32KHz Clock Control Register" bitfld.long 0x4 24. "CLR_CNT,Counter 32kHz Clear Clears the counters." "0,1" newline bitfld.long 0x4 4. "SRC_SEL,Counter 32kHz Source Selects the source 32kHz clock that is measured." "0,1" newline bitfld.long 0x4 2. "VLD_EN,Enables the Counter for Valid count." "0,1" newline bitfld.long 0x4 1. "DTY_EN,Enables the Duty cycle Counter." "0,1" newline bitfld.long 0x4 0. "PRD_EN,Enables the Period Counter." "0,1" line.long 0x8 "CLK_STS,32KHz Clock Monitor Status Register" bitfld.long 0x8 6. "NVL,Counter 32kHz Unwell Status." "0,1" newline bitfld.long 0x8 5. "VLD,Counter 32kHz Valid Status." "0,1" newline bitfld.long 0x8 4. "STALL,Counter 32kHz Stall Status." "0,1" newline bitfld.long 0x8 3. "FAIL,Counter 32kHz Fail Status." "0,1" newline bitfld.long 0x8 2. "PASS_DTY,Counter 32kHz Pass Duty Status." "0,1" newline bitfld.long 0x8 1. "PASS_PRD,Counter 32kHz Pass Period Status." "0,1" newline bitfld.long 0x8 0. "PULSE_RDY,Counter 32kHz Pulse Ready Status." "0,1" line.long 0xC "CLK_INT_EN,32KHz Clock Monitor Interrupt Enable Register" bitfld.long 0xC 6. "NVL_IE,Counter 32kHz Unwell Interrupt Enable." "0,1" newline bitfld.long 0xC 5. "VLD_IE,Counter 32kHz Valid Interrupt Enable." "0,1" newline bitfld.long 0xC 4. "STALL_IE,Counter 32kHz Stall Interrupt Enable." "0,1" newline bitfld.long 0xC 3. "FAIL_IE,Counter 32kHz Fail Interrupt Enable." "0,1" newline bitfld.long 0xC 2. "PASS_DTY_IE,Counter 32kHz Pass Duty Interrupt Enable." "0,1" newline bitfld.long 0xC 1. "PASS_PRD_IE,Counter 32kHz Pass Period Interrupt Enable." "0,1" newline bitfld.long 0xC 0. "PULSE_RDY_IE,Counter 32kHz Pulse Ready Interrupt Enable." "0,1" tree.end tree "PECI" base ad:0x40006400 group.byte 0x0++0x0 line.byte 0x0 "WDATA,The Write Data Register provides access to a 32-byte Transmit FIFO." group.byte 0x4++0x0 line.byte 0x0 "RDATA,The Read Data Register provides access to a 32-byte Receive FIFO." group.byte 0x8++0x0 line.byte 0x0 "CTRL,Control Register" bitfld.byte 0x0 7. "MIEN,MIEN is the Master Interrupt Enable" "0,1" bitfld.byte 0x0 6. "TXEN,TXEN is the Transmit Enable bit." "0,1" bitfld.byte 0x0 5. "FRST,FRST is the FIFO Reset bit." "0,1" bitfld.byte 0x0 3. "RST,RST indicates that the PECI Core should be reset." "0,1" bitfld.byte 0x0 0. "PD,PD (Power Down) along with RST controls the Power Management Interface" "0,1" group.byte 0xC++0x0 line.byte 0x0 "STS1,Status Register 1" bitfld.byte 0x0 7. "MINT,MINT is the Master Interrupt Status bit and is asserted when any interrupt status bit in the Interrupt Interface is asserted." "0,1" bitfld.byte 0x0 5. "RDYHI,RDYHI is asserted '1' on the rising edge of the READY signal function (R/WC)" "0,1" bitfld.byte 0x0 4. "RDYLO,RDYLO is asserted '1' on the falling edge of the READY signal function (R/WC)" "0,1" bitfld.byte 0x0 3. "RDY,RDY represents the state of the READY signal function" "0,1" bitfld.byte 0x0 2. "ERR,ERR Indicates that an error for the current transaction has been detected." "0,1" bitfld.byte 0x0 1. "EOF,EOF (End of Frame) is asserted following Message Stop (tSTOP). (R/WC)" "0,1" bitfld.byte 0x0 0. "BOF,BOF (Beginning of Frame) is asserted when the PECI Core begins Address Timing Negotiation. (R/WC)" "0,1" rgroup.byte 0x10++0x0 line.byte 0x0 "STS2,Status Register 2" bitfld.byte 0x0 7. "IDLE,The IDLE status bit indicates when the SST/PECI bus is idle and a new transaction may begin." "0,1" bitfld.byte 0x0 3. "RFE,RFE indicates that the Read Data Register FIFO is empty. RFE does not generate an interrupt." "0,1" bitfld.byte 0x0 2. "RFF,RFF indicates that the Read Data Register FIFO is full." "0,1" bitfld.byte 0x0 1. "WFE,WFE indicates that the Write Data Register FIFO is empty." "0,1" bitfld.byte 0x0 0. "WFF,WFF indicates that the Write Data Register FIFO is full. WFF does not generate an interrupt." "0,1" group.byte 0x14++0x0 line.byte 0x0 "ERROR,Error Register" bitfld.byte 0x0 7. "CLKERR,CLKERR indicates that the READY signal function in the Hardware Interface was de-asserted in the middle of a transaction (R/WC)" "0,1" bitfld.byte 0x0 6. "RDOV,RDOV (Read Overrun). RDOV indicates that the internal read buffer has overflowed (R/WC)" "0,1" bitfld.byte 0x0 5. "WRUN,WRUN (Write Underrun). (R/WC)" "0,1" bitfld.byte 0x0 4. "WROV,WROV (Write Overrun). (R/WC)" "0,1" bitfld.byte 0x0 3. "REQERR,REQERR is asserted if PEC_AVAILABLE (READY) input is not asserted when the counts down to zero as shown in. When asserted REQERR can generate interrupt. (R/WC)" "0,1" bitfld.byte 0x0 1. "BERR,BERR (Bus Error). Bus contention has been detected. BERR is asserted when the PECI Module reads a value that is different from what it has driven (R/WC)" "0,1" bitfld.byte 0x0 0. "FERR,FERR (Frame Check Sequence Error). (R/WC)" "0,1" group.byte 0x18++0x0 line.byte 0x0 "IEN1,Interrupt Enable 1 Register" bitfld.byte 0x0 5. "RHEN,When the RHEN bit is asserted '1' the RDYHI interrupt is enabled." "0,1" bitfld.byte 0x0 4. "RLEN,When the RLEN bit is asserted '1' the RDYLO interrupt is enabled." "0,1" bitfld.byte 0x0 2. "EREN,When the EREN bit is asserted '1' the ERR interrupt is enabled." "0,1" bitfld.byte 0x0 1. "EIEN,When the EIEN bit is asserted '1' the EOF interrupt is enabled." "0,1" bitfld.byte 0x0 0. "BIEN,When the BIEN bit is asserted '1' the BOF interrupt is enabled." "0,1" group.byte 0x1C++0x0 line.byte 0x0 "IEN2,Interrupt Enable 2 Register" bitfld.byte 0x0 2. "ENRFF,When the ENRFF bit is asserted '1' the RFF interrupt is enabled." "0,1" bitfld.byte 0x0 1. "ENWFE,When the ENWFE bit is asserted '1' the WFE interrupt is enabled." "0,1" group.byte 0x20++0x0 line.byte 0x0 "OPTBTLO,Optimal Bit Time Register (Low Byte)" group.byte 0x24++0x0 line.byte 0x0 "OPTBTHI,Optimal Bit Time Register (High Byte)" group.long 0x30++0x3 line.long 0x0 "BDCTRL,Baud Control Register. The baud div value divides down the sytem clock frequency to create the peci CORE_CLK frequency." group.long 0x40++0x7 line.long 0x0 "BLKID,Block ID Register" line.long 0x4 "BLKREV,Revision Register" tree.end tree "PHOT" base ad:0x40003400 group.long 0x0++0x17 line.long 0x0 "CUCNT,PROCHOT Cumulative Count Register" hexmask.long.tbyte 0x0 0.--23. 1. "ACTIVE,This register contains the current filtered PROCHOT Active Counter value." line.long 0x4 "DC_CNT,PROCHOT Duty Cycle Count Register" hexmask.long.tbyte 0x4 0.--23. 1. "CNT,The contents of the PROCHOT Cumulative Count Register is copied into this register when the PROCHOT Duty Cycle Period Register transitions from 1 to 0." line.long 0x8 "DC_PER,PROCHOT Duty Cycle Period Register" hexmask.long.tbyte 0x8 0.--23. 1. "PER,This register defines the number of 100KHz periods required for a duty cycle measurement." line.long 0xC "CTRL_STS,PROCHOT Status/Control Register" bitfld.long 0xC 11. "PER,This sticky status bit is set to '1b' when the PROCHOT Period Counter transitions from '1b' to '0b.' (R/WC)" "0,1" bitfld.long 0xC 10. "ASSERT,This bit is set when the PROCHOT Assertion Counter Register value is greater than or equal to the PROCHOT Assertion Counter Limit Register value. (R/WC)" "0,1" bitfld.long 0xC 5. "FILT_EN,This bit determines whether a digital filter eliminates pulses on the PROCHOT# signal before PROCHOT# is sampled by the Assertion counter or the Active counter." "0,1" bitfld.long 0xC 4. "RST,Writing this self-clearing bit to one resets all the registers and logic in the PROCHOT Monitor block to its defined initial state." "0,1" bitfld.long 0xC 3. "PER_EN,This bit determines whether or not an interrupt will be generated when the PHOT_PERIOD bit is set." "0,1" bitfld.long 0xC 2. "ASSERT_EN,This bit determines whether or not an interrupt will be generated when the PHOT_ASSERT bit is set." "0,1" bitfld.long 0xC 1. "PIN,When PHOT_ENABLE is 1b this bit reflects the state of the PROCHOT# Pin input." "0,1" bitfld.long 0xC 0. "EN,This bit enables the PROCHOT Monitor logic." "0,1" line.long 0x10 "ASCNT,PROCHOT Assertion Counter Register" hexmask.long.word 0x10 0.--15. 1. "CNT,The PROCHOT Assertion Counter is a 16-bit up-counter that is clocked by the 100KHz and is gated and reset by the PROCHOT# input signal. This counter is used to measure a single PROCHOT assertion." line.long 0x14 "ASCLIM,PROCHOT Assertion Counter Register" hexmask.long.word 0x14 0.--15. 1. "CLIM,The PROCHOT Assertion Counter Limit register is compared to the 16-bit PROCHOT Assertion Counter." tree.end tree "PM1" base ad:0x400F1C00 group.byte 0x1++0x0 line.byte 0x0 "H_PM1_STS2,PM1 Status 2" bitfld.byte 0x0 7. "WAK_STS,This bit can be set or cleared by the EC. The Host writing a one to this bit can also clear this bit. (R/WC)" "0,1" bitfld.byte 0x0 3. "PWRBTNOR_STS,This bit can be set or cleared by the EC to simulate a Power button override event status if the power is controlled by the EC. The Host writing a one to this bit can also clear this bit. The EC must generate the associated hardware.." "0,1" bitfld.byte 0x0 2. "RTC_STS,This bit can be set or cleared by the EC to simulate a RTC status. The Host writing a one to this bit can also clear this bit. The EC must generate the associated SCI interrupt under software control. (R/WC)" "0,1" bitfld.byte 0x0 1. "SLPBTN_STS,This bit can be set or cleared by the EC to simulate a Sleep button status if the sleep state is controlled by the EC. The Host writing a one to this bit can also clear this bit. The EC must generate the associated SCI interrupt under.." "0,1" bitfld.byte 0x0 0. "PWRBTN_STS,This bit can be set or cleared by the EC to simulate a Power button status if the power is controlled by the EC. The Host writing a one to this bit can also clear this bit. The EC must generate the associated SCI interrupt under software.." "0,1" group.byte 0x3++0x0 line.byte 0x0 "H_PM1_EN2,PM1 Enable 2" bitfld.byte 0x0 2. "RTC_EN,This bit can be read or written by the Host. It can be read by the EC." "0,1" bitfld.byte 0x0 1. "SLPBTN_EN,This bit can be read or written by the Host. It can be read by the EC." "0,1" bitfld.byte 0x0 0. "PWRBTN_EN,This bit can be read or written by the Host. It can be read by the EC." "0,1" group.byte 0x5++0x0 line.byte 0x0 "H_PM1_CTRL2,PM1 Control 2" bitfld.byte 0x0 5. "SLP_EN,SLP_EN" "0,1" bitfld.byte 0x0 2.--4. "SLP_TYP,These bits can be set or cleared by the Host read by the EC." "0,1,2,3,4,5,6,7" bitfld.byte 0x0 1. "PWRBTNOR_EN,This bit can be set or cleared by the Host read by the EC." "0,1" group.byte 0x101++0x0 line.byte 0x0 "EC_PM1_STS2,PM1 Status 2" bitfld.byte 0x0 7. "WAK_STS,This bit can be set or cleared by the EC. The Host writing a one to this bit can also clear this bit. (R/WC)" "0,1" bitfld.byte 0x0 3. "PWRBTNOR_STS,This bit can be set or cleared by the EC to simulate a Power button override event status if the power is controlled by the EC. The Host writing a one to this bit can also clear this bit. The EC must generate the associated hardware.." "0,1" bitfld.byte 0x0 2. "RTC_STS,This bit can be set or cleared by the EC to simulate a RTC status. The Host writing a one to this bit can also clear this bit. The EC must generate the associated SCI interrupt under software control. (R/WC)" "0,1" bitfld.byte 0x0 1. "SLPBTN_STS,This bit can be set or cleared by the EC to simulate a Sleep button status if the sleep state is controlled by the EC. The Host writing a one to this bit can also clear this bit. The EC must generate the associated SCI interrupt under.." "0,1" bitfld.byte 0x0 0. "PWRBTN_STS,This bit can be set or cleared by the EC to simulate a Power button status if the power is controlled by the EC. The Host writing a one to this bit can also clear this bit. The EC must generate the associated SCI interrupt under software.." "0,1" group.byte 0x103++0x0 line.byte 0x0 "EC_PM1_EN2,PM1 Enable 2" bitfld.byte 0x0 2. "RTC_EN,This bit can be read or written by the Host. It can be read by the EC." "0,1" bitfld.byte 0x0 1. "SLPBTN_EN,This bit can be read or written by the Host. It can be read by the EC." "0,1" bitfld.byte 0x0 0. "PWRBTN_EN,This bit can be read or written by the Host. It can be read by the EC." "0,1" group.byte 0x105++0x0 line.byte 0x0 "EC_PM1_CTRL2,PM1 Control 2" bitfld.byte 0x0 5. "SLP_EN,SLP_EN" "0,1" bitfld.byte 0x0 2.--4. "SLP_TYP,These bits can be set or cleared by the Host read by the EC." "0,1,2,3,4,5,6,7" bitfld.byte 0x0 1. "PWRBTNOR_EN,This bit can be set or cleared by the Host read by the EC." "0,1" group.byte 0x110++0x0 line.byte 0x0 "EC_PM_STS,PM1 EC PM Status" hexmask.byte 0x0 1.--7. 1. "UD,User Defined" bitfld.byte 0x0 0. "EC_SCI_STS,If the EC_SCI_STS bit is '1' an interrupt is generated on the EC_SCI# pin." "0,1" tree.end tree "PORT92" base ad:0x400F2000 group.byte 0x0++0x0 line.byte 0x0 "RT_PORT92,PORT92 Register: The registers listed in the Runtime Register Summary table are for a single instance of the Legacy Port92/GATEA20 logic." bitfld.byte 0x0 1. "ALT_GATE_A20,This bit provides an alternate means for system control of the GATEA20 pin. ALT_A20 low drives GATEA20 low if A20 from the keyboard controller is also low. When Port 92 is enabled writing a 1 to this bit forces ALT_A20 high. ALT_A20.." "0: ALT_A20 is driven low,1: ALT_A20 is driven high" bitfld.byte 0x0 0. "ALT_CPU_RST,This bit provides an alternate means to generate a CPU_RESET pulse." "0,1" group.byte 0x100++0x0 line.byte 0x0 "GATEA20,GATEA20 Control Register" bitfld.byte 0x0 0. "GATEA20,0=The GATEA20 output is driven low 1=The GATEA20 output is driven high." "0: The GATEA20 output is driven low,1: The GATEA20 output is driven high" wgroup.byte 0x108++0x0 line.byte 0x0 "SETGA20L,SETGA20L Register. A write to this register sets GATEA20 in the GATEA20 Control Register." group.byte 0x10C++0x0 line.byte 0x0 "RSTGA20L,RSTGA20L Register. A write to this register sets GATEA20 in the GATEA20 Control Register." group.byte 0x330++0x0 line.byte 0x0 "EN,PORT92 Enable Register" bitfld.byte 0x0 0. "EN,When this bit is '1' the Port92h Register is enabled. When this bit is '0' the Port92h Register is disabled and Host writes to Host address 92h are ignored." "0,1" tree.end tree "PORT_80_DEBUG" base ad:0x400F8000 wgroup.long 0x0++0x3 line.long 0x0 "HOST_DATA32,Host Data Register" hexmask.long 0x0 0.--31. 1. "H_DAT,This is the host data." rgroup.byte 0x100++0x1 line.byte 0x0 "EC_DATA,EC Data Register." hexmask.byte 0x0 0.--7. 1. "EC_DATA,This is the Oldest FIFO byte from the Host." line.byte 0x1 "EC_ATTR,EC Attribute Register." bitfld.byte 0x1 6. "THRES_STAT,Threshold Status" "0,1" bitfld.byte 0x1 5. "EC_OVR,FIFO Overflow 1 = One or more bytes have been lost from the FIFO before this byte. 0 = No loss of information has occurred immediately before this byte." "0: No loss of information has occurred immediately..,1: One or more bytes have been lost from the FIFO.." bitfld.byte 0x1 4. "FIFO_NEMPTY,FIFO Not Empty Status" "0,1" newline bitfld.byte 0x1 2.--3. "EC_LEN,Length 00 = One byte or a continuation of a multi-byte value. 01 = The first byte (LSB) of a two-byte value. 10 = The first byte (LSB) of a 4-byte value. 11 = Invalid" "0: One byte,1: The first byte,?,?" bitfld.byte 0x1 0.--1. "EC_LANE,The byte address to which this byte was written 00 = Byte Lane 0 01 = Byte Lane 1 10 = Byte Lane 2 11 = Byte Lane 3" "0: Byte Lane 0,1: Byte Lane 1,?,?" group.long 0x104++0x3 line.long 0x0 "CFG,Configuration Register." bitfld.long 0x0 31. "SOFT_RST,Soft Reset When a 1 is written to this bit a one clock wide pulse resets the entire block" "0,1" bitfld.long 0x0 4.--6. "FIFO_THRESHOLD,This field determines the threshold for the Port 80 32-Bit BIOS Debug Port Interrupts. 7=30 entry threshold 6=28 entry threshold 5=24 entry threshold 4=20 entry threshold 3=16 entry threshold 2=8 entry threshold 1=4 entry threshold.." "0: 1 entry threshold,1: 4 entry threshold,2: 8 entry threshold,3: 16 entry threshold,4: 20 entry threshold,5: 24 entry threshold,6: 28 entry threshold,7: 30 entry threshold" bitfld.long 0x0 1. "SNPSHT_CLR,Writing this bit clears the Snapshot Register as well as the Capture Register (Buffer)." "0,1" newline bitfld.long 0x0 0. "FLUSH,Flush FIFO (also clears the OVERRUN bit) Self Clearing bit. This bit does not affect the Snapshot Register." "0,1" rgroup.byte 0x108++0x0 line.byte 0x0 "STS,Status Register" bitfld.byte 0x0 2. "THRES_STAT,Threshold Status is set when the number of threshold entries are above the selected threshold" "0,1" bitfld.byte 0x0 1. "OVERRUN,The OVERRUN bit is 1 when the host writes the Host Data Register when the FIFO is full." "0,1" bitfld.byte 0x0 0. "NOT_EMPTY,The NOT EMPTY bit is 1 when there is data in the FIFO. The NOT EMPTY bit is 0 when the FIFO is empty." "0,1" group.byte 0x109++0x0 line.byte 0x0 "INT_EN,Interrupt Enable Register" bitfld.byte 0x0 0. "THRES_IEN,Enable Threshold interrupt. When set threshold interrupt is enabled" "0,1" rgroup.long 0x10C++0xB line.long 0x0 "SNAPSHOT,Snapshot Register" hexmask.long 0x0 0.--31. 1. "SNAPSHOT,Current image of the 4-byte Port 80 value captured immediately from the Host CPU." line.long 0x4 "CAPTURE,Capture Register" hexmask.long 0x4 0.--31. 1. "CAPTURE,Current image of the 4-byte Port 80 value capture register." line.long 0x8 "TEST_MODES,Test Mode Register" bitfld.long 0x8 1.--2. "SZ4M_OMASTR,Size from other master 00 = Byte 01 = Word 10 = Double Word 11 = Invalid" "0: Byte,1: Word,?,?" bitfld.long 0x8 0. "EN_OMASTR,Enable other masters (JTAG EC etc) to be able to write to Port80 FIFO with size selection." "0,1" group.long 0x330++0x3 line.long 0x0 "ACTIVATE32,Activate Register" bitfld.long 0x0 0. "ACT,When this bit is asserted 1 the block is enabled. When this bit is 0 writes by the Host interface to the Host Data Register are not claimed the FIFO is flushed." "0,1" wgroup.byte 0x400++0x0 line.byte 0x0 "HOST_DATA8,Host Data Register" hexmask.byte 0x0 0.--7. 1. "HOST_DATA,This is the host data." group.byte 0x730++0x0 line.byte 0x0 "ACTIVATE8,Activate Register" bitfld.byte 0x0 0. "ACTIVATE,When this bit is asserted 1 the block is enabled. When this bit is 0 writes by the Host interface to the Host Data Register are not claimed the FIFO is flushed." "0,1" group.byte 0x7F0++0x0 line.byte 0x0 "HST_ALIS_DATA,Host Alias Data Register" bitfld.byte 0x0 0.--1. "ALIS_BLANE,Byte from Alias LDN Port80 mapped location in Snapshot Register b00 = Byte 0 b01 = Byte 1 b10 = Byte 2 b11 = Byte 3" "0: Byte 0,1: Byte 1,2: Byte 2,3: Byte 3" tree.end tree "POWERGUARD (PowerGuard Voltage Monitor)" base ad:0x0 tree "POWERGUARD_0" base ad:0x40003000 group.long 0x0++0x23 line.long 0x0 "LPF1_FREQ_CUTOFF_RATE,LPF1 Frequency Cut-off Rate Register" bitfld.long 0x0 21. "LPF1_SAMPLE_EQ_ADC,FILTER_ENABLE This bit controls the LPF1 sampling rate." "0,1" bitfld.long 0x0 20. "WEIGHT,This bit controls the weight parameter W in the First Order Average Equation and the weight parameter W2 in the Second Order Average Equation for Linear Predictive Filter 1." "0,1" hexmask.long.tbyte 0x0 0.--19. 1. "LPF1_CUTOFF_FREQ,The cutoff frequency for the Linear Predictive Filter 1." line.long 0x4 "LPF2_FREQ_CUTOFF_RATE,LPF2 Frequency Cut-off Rate Register" bitfld.long 0x4 21. "LPF1_SAMPLE_EQ_ADC,FILTER_ENABLE This bit controls the LPF1 sampling rate." "0,1" bitfld.long 0x4 20. "WEIGHT,This bit controls the weight parameter W in the First Order Average Equation and the weight parameter W2 in the Second Order Average Equation for Linear Predictive Filter 1." "0,1" hexmask.long.tbyte 0x4 0.--19. 1. "LPF2_CUTOFF_FREQ,The cutoff frequency for the Linear Predictive Filter 2." line.long 0x8 "DATA_REG,Data Register" hexmask.long.byte 0x8 24.--31. 1. "TEST_WRITE_DATA,When the TEST_DATA_MUX_SELECT bit in the Control And Status Register is a 1 writes to this register are used as the ADC sample data." hexmask.long.byte 0x8 16.--23. 1. "LPF2_OUTPUT_DATA,Data output of 2nd Order LPF." hexmask.long.byte 0x8 8.--15. 1. "LPF1_OUTPUT_DAT,Data output of 1st Order LPF." newline hexmask.long.byte 0x8 0.--7. 1. "SELECTED_BYTE0,The contents of this read-only field is controlled by the value written into the DATA_MUX_SELECT field in the Control And Status Register." line.long 0xC "THRESHOLD_LIMIT,Threshold Limit Register." hexmask.long.byte 0xC 24.--31. 1. "THRESHOLD_HIGH,This field contains the base value for setting the comparison threshold for the high-side comparator." hexmask.long.byte 0xC 16.--23. 1. "THRESHOLD_LOW,This field contains the base value for setting the comparison threshold for the low-side comparator." hexmask.long.byte 0xC 11.--15. 1. "HYSTERESIS,The contents of this field is added or subtracted both comparator thresholds based on the hysteresis settings for the comparators." newline hexmask.long.byte 0xC 0.--7. 1. "BIAS,The contents of this field are added to both THRESHOLD_HIGH and THRESHOLD_LOW when generating the comparison thresholds for the high-side and low-side comparators respectively." line.long 0x10 "LOW_TIMER,Low Timer Register" bitfld.long 0x10 31. "LOW_TIMER_RECOVERY_OPTIONS,Recovery mode for the low-side timer." "0,1" bitfld.long 0x10 30. "TEST_BIT,All writes to this register should clear this test bit to 0." "0,1" hexmask.long.word 0x10 12.--23. 1. "LOW_TIMER_LOAD,The value written into this field is the Load Count value for the LOW_TIMER_COUNTER." newline hexmask.long.word 0x10 0.--11. 1. "LOW_TIMER_COUNTER,Reads of this field provides the current count of the low-side timer." line.long 0x14 "HIGH_TIMER,High Timer Register" bitfld.long 0x14 31. "HIGH_TIMER_RECOVERY_OPTIONS,Recovery mode for the high-side timer." "0,1" bitfld.long 0x14 30. "TEST_BIT,All writes to this register should clear this test bit to 0." "0,1" hexmask.long.word 0x14 12.--23. 1. "HIGH_TIMER_LOAD,The value written into this field is the Load Count value for the HIGH_TIMER_COUNTER." newline hexmask.long.word 0x14 0.--11. 1. "HIGH_TIMER_COUNTER,Reads of this field provides the current count of the high-side timer." line.long 0x18 "CTRL_STS,Control and Status Register." bitfld.long 0x18 30. "PROCHOT_OUT,Current output of the ORing Logic." "0,1" bitfld.long 0x18 29. "COUT_HI,Current output of the high-side comparator." "0,1" bitfld.long 0x18 28. "COUT_LO,Current output of the low-side comparator." "0,1" newline bitfld.long 0x18 27. "FORCE_PROCHOT,Inverted copy of the current state of the input signal FORCE_PROCHOT# from the PROCHOT PWM." "0,1" bitfld.long 0x18 26. "MAN_RECOVERY_OUT,If both the high-side timer and the low-side timer are configured for Manual Recovery Mode this bit reports the status of the timer contribution to the ORing Logic." "0,1" bitfld.long 0x18 25. "CTMR_OUT_HI,Status bit of the high-side timer." "0,1" newline bitfld.long 0x18 24. "CTMR_OUT_LO,Status bit of the low-side timer." "0,1" bitfld.long 0x18 23. "BLOCK_RESET,When this bit is set to '1b' the entire block is reset." "0,1" bitfld.long 0x18 22. "BLOCK_DISABLE,When this bit is set to '1b' the PowerGuard block is disabled and placed in a low power state." "0,1" newline bitfld.long 0x18 20.--21. "TEST4,All writes to this register should clear this test bit to 0." "0,1,2,3" bitfld.long 0x18 18.--19. "TEST3,All writes to this register should clear this test bit to 0." "0,1,2,3" bitfld.long 0x18 17. "TEST2,All writes to this register should clear this test bit to 0." "0,1" newline bitfld.long 0x18 16. "TEST1,All writes to this register should clear this test bit to 0." "0,1" bitfld.long 0x18 12. "HIGH_COMPARATOR_HYSTERESIS_MODE,This bit selects Hysteresis Mode for the high-side comparator." "0,1" bitfld.long 0x18 11. "LOW_COMPARATOR_HYSTERESIS_MODE,This bit selects Hysteresis Mode for the low-side comparator." "0,1" newline bitfld.long 0x18 9.--10. "PROCHOT_DATA_MUX_SELECT,This field controls the source of the Prochot Data Mux." "0,1,2,3" bitfld.long 0x18 8. "TEST_DATA_MUX_SELECT,This bit controls the source of the ADC sample data to the Second Order LPF." "0,1" bitfld.long 0x18 7. "PROCHOT_GATE,This bit controls the effect of the VCI_OVRD_IN pin on the PROCHOT_IO# Output." "0,1" newline bitfld.long 0x18 4.--6. "DATA_MUX_SELECT,The field controls the read data accessible of the SELECTED_- BYTE0 field of the Data Register." "0,1,2,3,4,5,6,7" bitfld.long 0x18 3. "MANUAL_RECOVERY,This bit is set to '1b' if either high-side timer or the low-side timer is configured for Manual Recovery Mode and the timer times out and asserts." "0,1" bitfld.long 0x18 2. "FORCE_PROCHOT_ENABLE,FORCE_PROCHOT Enable bit" "0,1" newline bitfld.long 0x18 1. "CTMER_OUT_LO_ENABLE,The low-side timer output enable bit." "0,1" bitfld.long 0x18 0. "CTMER_OUT_HI_ENABLE,The high-side timer output enable bit." "0,1" line.long 0x1C "INT_STATUS,PowerGuard Interrupt Status Register" bitfld.long 0x1C 4. "FORCE_PROCHOT,This bit is set to '1b' if the FORCE_PROCHOT# input from the PROCHOT PWM is low (asserted). (R/WC)" "0,1" bitfld.long 0x1C 3. "CT_LO_L2H,This bit is set to 1b when the CTMR_OUT_LO in the Control And Status Register transitions from '0b' to '1b'. (R/WC)" "0,1" bitfld.long 0x1C 2. "CT_HI_L2H,This bit is set to 1b when the CTMR_OUT_HI in the Control And Status Register transitions from '0b' to '1b'. (R/WC)" "0,1" newline bitfld.long 0x1C 1. "CT_LO_H2L,This bit is set to 1b when the CTMR_OUT_LO in the Control And Status Register transitions from '1b' to '0b'. (R/WC)" "0,1" bitfld.long 0x1C 0. "CT_HI_H2L,This bit is set to 1b when the CTMR_OUT_HI in the Control And Status Register transitions from '1b' to '0b'. (R/WC)" "0,1" line.long 0x20 "IEN,PowerGuard Interrupt Enable Register" bitfld.long 0x20 4. "FORCE_PROCHOT_ENABLE,This bit is used to enable/disable the FORCE_PROCHOT# interrupt." "0,1" bitfld.long 0x20 3. "CT_LO_L2H_ENABLE,This bit is used to enable/disable the CTMR_OUT_LO interrupt." "0,1" bitfld.long 0x20 2. "CT_HI_L2H_ENABLE,This bit is used to enable/disable the CTMR_OUT_HI interrupt." "0,1" newline bitfld.long 0x20 1. "CT_LO_H2L_ENABLE,This bit is used to enable/disable the CTMR_OUT_LO interrupt." "0,1" bitfld.long 0x20 0. "CT_HI_H2L_ENABLE,This bit is used to enable/disable the CTMR_OUT_HI interrupt." "0,1" tree.end tree "POWERGUARD_1" base ad:0x40003080 group.long 0x0++0x23 line.long 0x0 "LPF1_FREQ_CUTOFF_RATE,LPF1 Frequency Cut-off Rate Register" bitfld.long 0x0 21. "LPF1_SAMPLE_EQ_ADC,FILTER_ENABLE This bit controls the LPF1 sampling rate." "0,1" bitfld.long 0x0 20. "WEIGHT,This bit controls the weight parameter W in the First Order Average Equation and the weight parameter W2 in the Second Order Average Equation for Linear Predictive Filter 1." "0,1" hexmask.long.tbyte 0x0 0.--19. 1. "LPF1_CUTOFF_FREQ,The cutoff frequency for the Linear Predictive Filter 1." line.long 0x4 "LPF2_FREQ_CUTOFF_RATE,LPF2 Frequency Cut-off Rate Register" bitfld.long 0x4 21. "LPF1_SAMPLE_EQ_ADC,FILTER_ENABLE This bit controls the LPF1 sampling rate." "0,1" bitfld.long 0x4 20. "WEIGHT,This bit controls the weight parameter W in the First Order Average Equation and the weight parameter W2 in the Second Order Average Equation for Linear Predictive Filter 1." "0,1" hexmask.long.tbyte 0x4 0.--19. 1. "LPF2_CUTOFF_FREQ,The cutoff frequency for the Linear Predictive Filter 2." line.long 0x8 "DATA_REG,Data Register" hexmask.long.byte 0x8 24.--31. 1. "TEST_WRITE_DATA,When the TEST_DATA_MUX_SELECT bit in the Control And Status Register is a 1 writes to this register are used as the ADC sample data." hexmask.long.byte 0x8 16.--23. 1. "LPF2_OUTPUT_DATA,Data output of 2nd Order LPF." hexmask.long.byte 0x8 8.--15. 1. "LPF1_OUTPUT_DAT,Data output of 1st Order LPF." newline hexmask.long.byte 0x8 0.--7. 1. "SELECTED_BYTE0,The contents of this read-only field is controlled by the value written into the DATA_MUX_SELECT field in the Control And Status Register." line.long 0xC "THRESHOLD_LIMIT,Threshold Limit Register." hexmask.long.byte 0xC 24.--31. 1. "THRESHOLD_HIGH,This field contains the base value for setting the comparison threshold for the high-side comparator." hexmask.long.byte 0xC 16.--23. 1. "THRESHOLD_LOW,This field contains the base value for setting the comparison threshold for the low-side comparator." hexmask.long.byte 0xC 11.--15. 1. "HYSTERESIS,The contents of this field is added or subtracted both comparator thresholds based on the hysteresis settings for the comparators." newline hexmask.long.byte 0xC 0.--7. 1. "BIAS,The contents of this field are added to both THRESHOLD_HIGH and THRESHOLD_LOW when generating the comparison thresholds for the high-side and low-side comparators respectively." line.long 0x10 "LOW_TIMER,Low Timer Register" bitfld.long 0x10 31. "LOW_TIMER_RECOVERY_OPTIONS,Recovery mode for the low-side timer." "0,1" bitfld.long 0x10 30. "TEST_BIT,All writes to this register should clear this test bit to 0." "0,1" hexmask.long.word 0x10 12.--23. 1. "LOW_TIMER_LOAD,The value written into this field is the Load Count value for the LOW_TIMER_COUNTER." newline hexmask.long.word 0x10 0.--11. 1. "LOW_TIMER_COUNTER,Reads of this field provides the current count of the low-side timer." line.long 0x14 "HIGH_TIMER,High Timer Register" bitfld.long 0x14 31. "HIGH_TIMER_RECOVERY_OPTIONS,Recovery mode for the high-side timer." "0,1" bitfld.long 0x14 30. "TEST_BIT,All writes to this register should clear this test bit to 0." "0,1" hexmask.long.word 0x14 12.--23. 1. "HIGH_TIMER_LOAD,The value written into this field is the Load Count value for the HIGH_TIMER_COUNTER." newline hexmask.long.word 0x14 0.--11. 1. "HIGH_TIMER_COUNTER,Reads of this field provides the current count of the high-side timer." line.long 0x18 "CTRL_STS,Control and Status Register." bitfld.long 0x18 30. "PROCHOT_OUT,Current output of the ORing Logic." "0,1" bitfld.long 0x18 29. "COUT_HI,Current output of the high-side comparator." "0,1" bitfld.long 0x18 28. "COUT_LO,Current output of the low-side comparator." "0,1" newline bitfld.long 0x18 27. "FORCE_PROCHOT,Inverted copy of the current state of the input signal FORCE_PROCHOT# from the PROCHOT PWM." "0,1" bitfld.long 0x18 26. "MAN_RECOVERY_OUT,If both the high-side timer and the low-side timer are configured for Manual Recovery Mode this bit reports the status of the timer contribution to the ORing Logic." "0,1" bitfld.long 0x18 25. "CTMR_OUT_HI,Status bit of the high-side timer." "0,1" newline bitfld.long 0x18 24. "CTMR_OUT_LO,Status bit of the low-side timer." "0,1" bitfld.long 0x18 23. "BLOCK_RESET,When this bit is set to '1b' the entire block is reset." "0,1" bitfld.long 0x18 22. "BLOCK_DISABLE,When this bit is set to '1b' the PowerGuard block is disabled and placed in a low power state." "0,1" newline bitfld.long 0x18 20.--21. "TEST4,All writes to this register should clear this test bit to 0." "0,1,2,3" bitfld.long 0x18 18.--19. "TEST3,All writes to this register should clear this test bit to 0." "0,1,2,3" bitfld.long 0x18 17. "TEST2,All writes to this register should clear this test bit to 0." "0,1" newline bitfld.long 0x18 16. "TEST1,All writes to this register should clear this test bit to 0." "0,1" bitfld.long 0x18 12. "HIGH_COMPARATOR_HYSTERESIS_MODE,This bit selects Hysteresis Mode for the high-side comparator." "0,1" bitfld.long 0x18 11. "LOW_COMPARATOR_HYSTERESIS_MODE,This bit selects Hysteresis Mode for the low-side comparator." "0,1" newline bitfld.long 0x18 9.--10. "PROCHOT_DATA_MUX_SELECT,This field controls the source of the Prochot Data Mux." "0,1,2,3" bitfld.long 0x18 8. "TEST_DATA_MUX_SELECT,This bit controls the source of the ADC sample data to the Second Order LPF." "0,1" bitfld.long 0x18 7. "PROCHOT_GATE,This bit controls the effect of the VCI_OVRD_IN pin on the PROCHOT_IO# Output." "0,1" newline bitfld.long 0x18 4.--6. "DATA_MUX_SELECT,The field controls the read data accessible of the SELECTED_- BYTE0 field of the Data Register." "0,1,2,3,4,5,6,7" bitfld.long 0x18 3. "MANUAL_RECOVERY,This bit is set to '1b' if either high-side timer or the low-side timer is configured for Manual Recovery Mode and the timer times out and asserts." "0,1" bitfld.long 0x18 2. "FORCE_PROCHOT_ENABLE,FORCE_PROCHOT Enable bit" "0,1" newline bitfld.long 0x18 1. "CTMER_OUT_LO_ENABLE,The low-side timer output enable bit." "0,1" bitfld.long 0x18 0. "CTMER_OUT_HI_ENABLE,The high-side timer output enable bit." "0,1" line.long 0x1C "INT_STATUS,PowerGuard Interrupt Status Register" bitfld.long 0x1C 4. "FORCE_PROCHOT,This bit is set to '1b' if the FORCE_PROCHOT# input from the PROCHOT PWM is low (asserted). (R/WC)" "0,1" bitfld.long 0x1C 3. "CT_LO_L2H,This bit is set to 1b when the CTMR_OUT_LO in the Control And Status Register transitions from '0b' to '1b'. (R/WC)" "0,1" bitfld.long 0x1C 2. "CT_HI_L2H,This bit is set to 1b when the CTMR_OUT_HI in the Control And Status Register transitions from '0b' to '1b'. (R/WC)" "0,1" newline bitfld.long 0x1C 1. "CT_LO_H2L,This bit is set to 1b when the CTMR_OUT_LO in the Control And Status Register transitions from '1b' to '0b'. (R/WC)" "0,1" bitfld.long 0x1C 0. "CT_HI_H2L,This bit is set to 1b when the CTMR_OUT_HI in the Control And Status Register transitions from '1b' to '0b'. (R/WC)" "0,1" line.long 0x20 "IEN,PowerGuard Interrupt Enable Register" bitfld.long 0x20 4. "FORCE_PROCHOT_ENABLE,This bit is used to enable/disable the FORCE_PROCHOT# interrupt." "0,1" bitfld.long 0x20 3. "CT_LO_L2H_ENABLE,This bit is used to enable/disable the CTMR_OUT_LO interrupt." "0,1" bitfld.long 0x20 2. "CT_HI_L2H_ENABLE,This bit is used to enable/disable the CTMR_OUT_HI interrupt." "0,1" newline bitfld.long 0x20 1. "CT_LO_H2L_ENABLE,This bit is used to enable/disable the CTMR_OUT_LO interrupt." "0,1" bitfld.long 0x20 0. "CT_HI_H2L_ENABLE,This bit is used to enable/disable the CTMR_OUT_HI interrupt." "0,1" tree.end tree.end tree "PS2 (PS/2 Interface)" base ad:0x0 tree "PS2_0" base ad:0x40009000 wgroup.long 0x0++0x3 line.long 0x0 "TX_DATA,Writes to bits 7:0 of this register start a transmission of the data in this register to the peripheral" rgroup.long 0x0++0x3 line.long 0x0 "RX_DATA,Data received from a peripheral are recorded in this register in bits 7:0." group.long 0x4++0x7 line.long 0x0 "CONTROL,PS2 Control Register" bitfld.long 0x0 4.--5. "STOP,00b=Receiver expects an active high stop bit. 01b=Receiver expects an active low stop bit. 10b=Receiver ignores the level of the Stop bit (11th bit is not interpreted as a stop bit). 11b=Reserved." "0,1,2,3" bitfld.long 0x0 2.--3. "PARITY,00b=Receiver expects Odd Parity (default). 01b=Receiver expects Even Parity. 10b=Receiver ignores level of the parity bit (10th bit is not interpreted as a parity bit). 11b=Reserved" "0,1,2,3" newline bitfld.long 0x0 1. "EN,PS/2 Enable. 0=The PS/2 state machine is disabled. 1=The PS/2 state machine is enabled." "0: The PS/2 state machine is disabled,1: The PS/2 state machine is enabled" bitfld.long 0x0 0. "TR,PS/2 Transmit/Receive 0=The P2/2 channel is enabled to receive data. 1=The PS2 channel is enabled to transmit data." "0: The P2/2 channel is enabled to receive data,1: The PS2 channel is enabled to transmit data" line.long 0x4 "STATUS,PS2 Status Register" bitfld.long 0x4 7. "XMIT_START_TIMEOUT,Transmit Start Timeout. 0=No transmit start timeout detected 1=A start bit was not received within 25 ms following the transmit start event. The transmit start bit time-out condition is also indicated.." "0: No transmit start timeout detected,1: A start bit was not received within 25 ms.." bitfld.long 0x4 6. "RX_BUSY,Receive Channel Busy. 0=The channel is idle 1=The channel is actively receiving PS/2 data" "0: The channel is idle,1: The channel is actively receiving PS/2 data" newline bitfld.long 0x4 5. "XMIT_TIME_OUT,Transmitter Time-out. When the XMIT_TIMEOUT bit is set the PS2_T/R bit is held clear the PS/2 channel's CLK line is pulled low for a minimum of 300us until the PS/2 Status register is read." "0,1" bitfld.long 0x4 4. "XMIT_IDLE,Transmitter Idle. 0=The channel is actively transmitting PS/2 data. 1=The channel is not transmitting. A low to high transition on this bit generates a PS2 Activity interrupt." "0: The channel is actively transmitting PS/2 data,1: The channel is not transmitting" newline bitfld.long 0x4 3. "FE,Framing Error" "0,1" bitfld.long 0x4 2. "PE,Parity Error" "0,1" newline bitfld.long 0x4 1. "REC_TIMEOUT,Receive Timeout. The REC_TIMEOUT bit is cleared when the Status Register is read. A low to high transition on this bit generates a PS2 Activity interrupt. (R/WC)" "0,1" bitfld.long 0x4 0. "RDATA_RDY,Receive Data Ready. Reading the Receive Register clears this bit. A low to high transition on this bit generates a PS2 Activity interrupt." "0,1" tree.end tree.end tree "PWM (Pulse Width Modulator)" base ad:0x0 tree "PWM0" base ad:0x40005800 group.long 0x0++0xB line.long 0x0 "CNT_ON,This field determines both the frequency and duty cycle of the PWM signal. Setting this field to a value of n will cause the On time of the PWM to be n+1 cycles of the PWM Clock Source. When this field is set to zero and the.." line.long 0x4 "CNT_OFF,This field determine both the frequency and duty cycle of the PWM signal. Setting this field to a value of n will cause the Off time of the PWM to be n+1 cycles of the PWM Clock Source. When this field is set to zero. the PWM_OUTPUT is held.." line.long 0x8 "CFG,PWMx CONFIGURATION REGISTER" hexmask.long.byte 0x8 3.--6. 1. "CLK_PRE_DIV,The Clock source for the 16-bit down counter (see PWMx Counter ON Time Register and PWMx Counter OFF Time Register) is determined by bit D1 of this register. The Clock source is then divided by the value of Pre-Divider+1 and the resulting.." bitfld.long 0x8 2. "INV,1= PWM_OUTPUT ON State is active low; 0=PWM_OUTPUT ON State is active high." "0: PWM_OUTPUT ON State is active high,1: PWM_OUTPUT ON State is active low" bitfld.long 0x8 1. "CLK_SEL,This bit determines the clock source used by the PWM duty cycle and frequency control logic. 1=CLOCK_LOW 0=CLOCK_HIGH" "0: CLOCK_HIGH,1: CLOCK_LOW" bitfld.long 0x8 0. "PWM_EN,When the PWM_ENABLE is set to 0 the internal counters are reset and the internal state machine is set to the OFF state. In addition the PWM_OUTPUT signal is set to the inactive state as determined by the Invert bit. The PWMx Counter ON Time.." "0: Disabled,1: Enabled" tree.end tree "PWM1" base ad:0x40005810 group.long 0x0++0xB line.long 0x0 "CNT_ON,This field determines both the frequency and duty cycle of the PWM signal. Setting this field to a value of n will cause the On time of the PWM to be n+1 cycles of the PWM Clock Source. When this field is set to zero and the.." line.long 0x4 "CNT_OFF,This field determine both the frequency and duty cycle of the PWM signal. Setting this field to a value of n will cause the Off time of the PWM to be n+1 cycles of the PWM Clock Source. When this field is set to zero. the PWM_OUTPUT is held.." line.long 0x8 "CFG,PWMx CONFIGURATION REGISTER" hexmask.long.byte 0x8 3.--6. 1. "CLK_PRE_DIV,The Clock source for the 16-bit down counter (see PWMx Counter ON Time Register and PWMx Counter OFF Time Register) is determined by bit D1 of this register. The Clock source is then divided by the value of Pre-Divider+1 and the resulting.." bitfld.long 0x8 2. "INV,1= PWM_OUTPUT ON State is active low; 0=PWM_OUTPUT ON State is active high." "0: PWM_OUTPUT ON State is active high,1: PWM_OUTPUT ON State is active low" bitfld.long 0x8 1. "CLK_SEL,This bit determines the clock source used by the PWM duty cycle and frequency control logic. 1=CLOCK_LOW 0=CLOCK_HIGH" "0: CLOCK_HIGH,1: CLOCK_LOW" bitfld.long 0x8 0. "PWM_EN,When the PWM_ENABLE is set to 0 the internal counters are reset and the internal state machine is set to the OFF state. In addition the PWM_OUTPUT signal is set to the inactive state as determined by the Invert bit. The PWMx Counter ON Time.." "0: Disabled,1: Enabled" tree.end tree "PWM2" base ad:0x40005820 group.long 0x0++0xB line.long 0x0 "CNT_ON,This field determines both the frequency and duty cycle of the PWM signal. Setting this field to a value of n will cause the On time of the PWM to be n+1 cycles of the PWM Clock Source. When this field is set to zero and the.." line.long 0x4 "CNT_OFF,This field determine both the frequency and duty cycle of the PWM signal. Setting this field to a value of n will cause the Off time of the PWM to be n+1 cycles of the PWM Clock Source. When this field is set to zero. the PWM_OUTPUT is held.." line.long 0x8 "CFG,PWMx CONFIGURATION REGISTER" hexmask.long.byte 0x8 3.--6. 1. "CLK_PRE_DIV,The Clock source for the 16-bit down counter (see PWMx Counter ON Time Register and PWMx Counter OFF Time Register) is determined by bit D1 of this register. The Clock source is then divided by the value of Pre-Divider+1 and the resulting.." bitfld.long 0x8 2. "INV,1= PWM_OUTPUT ON State is active low; 0=PWM_OUTPUT ON State is active high." "0: PWM_OUTPUT ON State is active high,1: PWM_OUTPUT ON State is active low" bitfld.long 0x8 1. "CLK_SEL,This bit determines the clock source used by the PWM duty cycle and frequency control logic. 1=CLOCK_LOW 0=CLOCK_HIGH" "0: CLOCK_HIGH,1: CLOCK_LOW" bitfld.long 0x8 0. "PWM_EN,When the PWM_ENABLE is set to 0 the internal counters are reset and the internal state machine is set to the OFF state. In addition the PWM_OUTPUT signal is set to the inactive state as determined by the Invert bit. The PWMx Counter ON Time.." "0: Disabled,1: Enabled" tree.end tree "PWM3" base ad:0x40005830 group.long 0x0++0xB line.long 0x0 "CNT_ON,This field determines both the frequency and duty cycle of the PWM signal. Setting this field to a value of n will cause the On time of the PWM to be n+1 cycles of the PWM Clock Source. When this field is set to zero and the.." line.long 0x4 "CNT_OFF,This field determine both the frequency and duty cycle of the PWM signal. Setting this field to a value of n will cause the Off time of the PWM to be n+1 cycles of the PWM Clock Source. When this field is set to zero. the PWM_OUTPUT is held.." line.long 0x8 "CFG,PWMx CONFIGURATION REGISTER" hexmask.long.byte 0x8 3.--6. 1. "CLK_PRE_DIV,The Clock source for the 16-bit down counter (see PWMx Counter ON Time Register and PWMx Counter OFF Time Register) is determined by bit D1 of this register. The Clock source is then divided by the value of Pre-Divider+1 and the resulting.." bitfld.long 0x8 2. "INV,1= PWM_OUTPUT ON State is active low; 0=PWM_OUTPUT ON State is active high." "0: PWM_OUTPUT ON State is active high,1: PWM_OUTPUT ON State is active low" bitfld.long 0x8 1. "CLK_SEL,This bit determines the clock source used by the PWM duty cycle and frequency control logic. 1=CLOCK_LOW 0=CLOCK_HIGH" "0: CLOCK_HIGH,1: CLOCK_LOW" bitfld.long 0x8 0. "PWM_EN,When the PWM_ENABLE is set to 0 the internal counters are reset and the internal state machine is set to the OFF state. In addition the PWM_OUTPUT signal is set to the inactive state as determined by the Invert bit. The PWMx Counter ON Time.." "0: Disabled,1: Enabled" tree.end tree "PWM4" base ad:0x40005840 group.long 0x0++0xB line.long 0x0 "CNT_ON,This field determines both the frequency and duty cycle of the PWM signal. Setting this field to a value of n will cause the On time of the PWM to be n+1 cycles of the PWM Clock Source. When this field is set to zero and the.." line.long 0x4 "CNT_OFF,This field determine both the frequency and duty cycle of the PWM signal. Setting this field to a value of n will cause the Off time of the PWM to be n+1 cycles of the PWM Clock Source. When this field is set to zero. the PWM_OUTPUT is held.." line.long 0x8 "CFG,PWMx CONFIGURATION REGISTER" hexmask.long.byte 0x8 3.--6. 1. "CLK_PRE_DIV,The Clock source for the 16-bit down counter (see PWMx Counter ON Time Register and PWMx Counter OFF Time Register) is determined by bit D1 of this register. The Clock source is then divided by the value of Pre-Divider+1 and the resulting.." bitfld.long 0x8 2. "INV,1= PWM_OUTPUT ON State is active low; 0=PWM_OUTPUT ON State is active high." "0: PWM_OUTPUT ON State is active high,1: PWM_OUTPUT ON State is active low" bitfld.long 0x8 1. "CLK_SEL,This bit determines the clock source used by the PWM duty cycle and frequency control logic. 1=CLOCK_LOW 0=CLOCK_HIGH" "0: CLOCK_HIGH,1: CLOCK_LOW" bitfld.long 0x8 0. "PWM_EN,When the PWM_ENABLE is set to 0 the internal counters are reset and the internal state machine is set to the OFF state. In addition the PWM_OUTPUT signal is set to the inactive state as determined by the Invert bit. The PWMx Counter ON Time.." "0: Disabled,1: Enabled" tree.end tree "PWM5" base ad:0x40005850 group.long 0x0++0xB line.long 0x0 "CNT_ON,This field determines both the frequency and duty cycle of the PWM signal. Setting this field to a value of n will cause the On time of the PWM to be n+1 cycles of the PWM Clock Source. When this field is set to zero and the.." line.long 0x4 "CNT_OFF,This field determine both the frequency and duty cycle of the PWM signal. Setting this field to a value of n will cause the Off time of the PWM to be n+1 cycles of the PWM Clock Source. When this field is set to zero. the PWM_OUTPUT is held.." line.long 0x8 "CFG,PWMx CONFIGURATION REGISTER" hexmask.long.byte 0x8 3.--6. 1. "CLK_PRE_DIV,The Clock source for the 16-bit down counter (see PWMx Counter ON Time Register and PWMx Counter OFF Time Register) is determined by bit D1 of this register. The Clock source is then divided by the value of Pre-Divider+1 and the resulting.." bitfld.long 0x8 2. "INV,1= PWM_OUTPUT ON State is active low; 0=PWM_OUTPUT ON State is active high." "0: PWM_OUTPUT ON State is active high,1: PWM_OUTPUT ON State is active low" bitfld.long 0x8 1. "CLK_SEL,This bit determines the clock source used by the PWM duty cycle and frequency control logic. 1=CLOCK_LOW 0=CLOCK_HIGH" "0: CLOCK_HIGH,1: CLOCK_LOW" bitfld.long 0x8 0. "PWM_EN,When the PWM_ENABLE is set to 0 the internal counters are reset and the internal state machine is set to the OFF state. In addition the PWM_OUTPUT signal is set to the inactive state as determined by the Invert bit. The PWMx Counter ON Time.." "0: Disabled,1: Enabled" tree.end tree "PWM6" base ad:0x40005860 group.long 0x0++0xB line.long 0x0 "CNT_ON,This field determines both the frequency and duty cycle of the PWM signal. Setting this field to a value of n will cause the On time of the PWM to be n+1 cycles of the PWM Clock Source. When this field is set to zero and the.." line.long 0x4 "CNT_OFF,This field determine both the frequency and duty cycle of the PWM signal. Setting this field to a value of n will cause the Off time of the PWM to be n+1 cycles of the PWM Clock Source. When this field is set to zero. the PWM_OUTPUT is held.." line.long 0x8 "CFG,PWMx CONFIGURATION REGISTER" hexmask.long.byte 0x8 3.--6. 1. "CLK_PRE_DIV,The Clock source for the 16-bit down counter (see PWMx Counter ON Time Register and PWMx Counter OFF Time Register) is determined by bit D1 of this register. The Clock source is then divided by the value of Pre-Divider+1 and the resulting.." bitfld.long 0x8 2. "INV,1= PWM_OUTPUT ON State is active low; 0=PWM_OUTPUT ON State is active high." "0: PWM_OUTPUT ON State is active high,1: PWM_OUTPUT ON State is active low" bitfld.long 0x8 1. "CLK_SEL,This bit determines the clock source used by the PWM duty cycle and frequency control logic. 1=CLOCK_LOW 0=CLOCK_HIGH" "0: CLOCK_HIGH,1: CLOCK_LOW" bitfld.long 0x8 0. "PWM_EN,When the PWM_ENABLE is set to 0 the internal counters are reset and the internal state machine is set to the OFF state. In addition the PWM_OUTPUT signal is set to the inactive state as determined by the Invert bit. The PWMx Counter ON Time.." "0: Disabled,1: Enabled" tree.end tree "PWM7" base ad:0x40005870 group.long 0x0++0xB line.long 0x0 "CNT_ON,This field determines both the frequency and duty cycle of the PWM signal. Setting this field to a value of n will cause the On time of the PWM to be n+1 cycles of the PWM Clock Source. When this field is set to zero and the.." line.long 0x4 "CNT_OFF,This field determine both the frequency and duty cycle of the PWM signal. Setting this field to a value of n will cause the Off time of the PWM to be n+1 cycles of the PWM Clock Source. When this field is set to zero. the PWM_OUTPUT is held.." line.long 0x8 "CFG,PWMx CONFIGURATION REGISTER" hexmask.long.byte 0x8 3.--6. 1. "CLK_PRE_DIV,The Clock source for the 16-bit down counter (see PWMx Counter ON Time Register and PWMx Counter OFF Time Register) is determined by bit D1 of this register. The Clock source is then divided by the value of Pre-Divider+1 and the resulting.." bitfld.long 0x8 2. "INV,1= PWM_OUTPUT ON State is active low; 0=PWM_OUTPUT ON State is active high." "0: PWM_OUTPUT ON State is active high,1: PWM_OUTPUT ON State is active low" bitfld.long 0x8 1. "CLK_SEL,This bit determines the clock source used by the PWM duty cycle and frequency control logic. 1=CLOCK_LOW 0=CLOCK_HIGH" "0: CLOCK_HIGH,1: CLOCK_LOW" bitfld.long 0x8 0. "PWM_EN,When the PWM_ENABLE is set to 0 the internal counters are reset and the internal state machine is set to the OFF state. In addition the PWM_OUTPUT signal is set to the inactive state as determined by the Invert bit. The PWMx Counter ON Time.." "0: Disabled,1: Enabled" tree.end tree "PWM8" base ad:0x40005880 group.long 0x0++0xB line.long 0x0 "CNT_ON,This field determines both the frequency and duty cycle of the PWM signal. Setting this field to a value of n will cause the On time of the PWM to be n+1 cycles of the PWM Clock Source. When this field is set to zero and the.." line.long 0x4 "CNT_OFF,This field determine both the frequency and duty cycle of the PWM signal. Setting this field to a value of n will cause the Off time of the PWM to be n+1 cycles of the PWM Clock Source. When this field is set to zero. the PWM_OUTPUT is held.." line.long 0x8 "CFG,PWMx CONFIGURATION REGISTER" hexmask.long.byte 0x8 3.--6. 1. "CLK_PRE_DIV,The Clock source for the 16-bit down counter (see PWMx Counter ON Time Register and PWMx Counter OFF Time Register) is determined by bit D1 of this register. The Clock source is then divided by the value of Pre-Divider+1 and the resulting.." bitfld.long 0x8 2. "INV,1= PWM_OUTPUT ON State is active low; 0=PWM_OUTPUT ON State is active high." "0: PWM_OUTPUT ON State is active high,1: PWM_OUTPUT ON State is active low" bitfld.long 0x8 1. "CLK_SEL,This bit determines the clock source used by the PWM duty cycle and frequency control logic. 1=CLOCK_LOW 0=CLOCK_HIGH" "0: CLOCK_HIGH,1: CLOCK_LOW" bitfld.long 0x8 0. "PWM_EN,When the PWM_ENABLE is set to 0 the internal counters are reset and the internal state machine is set to the OFF state. In addition the PWM_OUTPUT signal is set to the inactive state as determined by the Invert bit. The PWMx Counter ON Time.." "0: Disabled,1: Enabled" tree.end tree "PWM9" base ad:0x40005890 group.long 0x0++0xB line.long 0x0 "CNT_ON,This field determines both the frequency and duty cycle of the PWM signal. Setting this field to a value of n will cause the On time of the PWM to be n+1 cycles of the PWM Clock Source. When this field is set to zero and the.." line.long 0x4 "CNT_OFF,This field determine both the frequency and duty cycle of the PWM signal. Setting this field to a value of n will cause the Off time of the PWM to be n+1 cycles of the PWM Clock Source. When this field is set to zero. the PWM_OUTPUT is held.." line.long 0x8 "CFG,PWMx CONFIGURATION REGISTER" hexmask.long.byte 0x8 3.--6. 1. "CLK_PRE_DIV,The Clock source for the 16-bit down counter (see PWMx Counter ON Time Register and PWMx Counter OFF Time Register) is determined by bit D1 of this register. The Clock source is then divided by the value of Pre-Divider+1 and the resulting.." bitfld.long 0x8 2. "INV,1= PWM_OUTPUT ON State is active low; 0=PWM_OUTPUT ON State is active high." "0: PWM_OUTPUT ON State is active high,1: PWM_OUTPUT ON State is active low" bitfld.long 0x8 1. "CLK_SEL,This bit determines the clock source used by the PWM duty cycle and frequency control logic. 1=CLOCK_LOW 0=CLOCK_HIGH" "0: CLOCK_HIGH,1: CLOCK_LOW" bitfld.long 0x8 0. "PWM_EN,When the PWM_ENABLE is set to 0 the internal counters are reset and the internal state machine is set to the OFF state. In addition the PWM_OUTPUT signal is set to the inactive state as determined by the Invert bit. The PWMx Counter ON Time.." "0: Disabled,1: Enabled" tree.end tree "PWM10" base ad:0x400058A0 group.long 0x0++0xB line.long 0x0 "CNT_ON,This field determines both the frequency and duty cycle of the PWM signal. Setting this field to a value of n will cause the On time of the PWM to be n+1 cycles of the PWM Clock Source. When this field is set to zero and the.." line.long 0x4 "CNT_OFF,This field determine both the frequency and duty cycle of the PWM signal. Setting this field to a value of n will cause the Off time of the PWM to be n+1 cycles of the PWM Clock Source. When this field is set to zero. the PWM_OUTPUT is held.." line.long 0x8 "CFG,PWMx CONFIGURATION REGISTER" hexmask.long.byte 0x8 3.--6. 1. "CLK_PRE_DIV,The Clock source for the 16-bit down counter (see PWMx Counter ON Time Register and PWMx Counter OFF Time Register) is determined by bit D1 of this register. The Clock source is then divided by the value of Pre-Divider+1 and the resulting.." bitfld.long 0x8 2. "INV,1= PWM_OUTPUT ON State is active low; 0=PWM_OUTPUT ON State is active high." "0: PWM_OUTPUT ON State is active high,1: PWM_OUTPUT ON State is active low" bitfld.long 0x8 1. "CLK_SEL,This bit determines the clock source used by the PWM duty cycle and frequency control logic. 1=CLOCK_LOW 0=CLOCK_HIGH" "0: CLOCK_HIGH,1: CLOCK_LOW" bitfld.long 0x8 0. "PWM_EN,When the PWM_ENABLE is set to 0 the internal counters are reset and the internal state machine is set to the OFF state. In addition the PWM_OUTPUT signal is set to the inactive state as determined by the Invert bit. The PWMx Counter ON Time.." "0: Disabled,1: Enabled" tree.end tree "PWM11" base ad:0x400058B0 group.long 0x0++0xB line.long 0x0 "CNT_ON,This field determines both the frequency and duty cycle of the PWM signal. Setting this field to a value of n will cause the On time of the PWM to be n+1 cycles of the PWM Clock Source. When this field is set to zero and the.." line.long 0x4 "CNT_OFF,This field determine both the frequency and duty cycle of the PWM signal. Setting this field to a value of n will cause the Off time of the PWM to be n+1 cycles of the PWM Clock Source. When this field is set to zero. the PWM_OUTPUT is held.." line.long 0x8 "CFG,PWMx CONFIGURATION REGISTER" hexmask.long.byte 0x8 3.--6. 1. "CLK_PRE_DIV,The Clock source for the 16-bit down counter (see PWMx Counter ON Time Register and PWMx Counter OFF Time Register) is determined by bit D1 of this register. The Clock source is then divided by the value of Pre-Divider+1 and the resulting.." bitfld.long 0x8 2. "INV,1= PWM_OUTPUT ON State is active low; 0=PWM_OUTPUT ON State is active high." "0: PWM_OUTPUT ON State is active high,1: PWM_OUTPUT ON State is active low" bitfld.long 0x8 1. "CLK_SEL,This bit determines the clock source used by the PWM duty cycle and frequency control logic. 1=CLOCK_LOW 0=CLOCK_HIGH" "0: CLOCK_HIGH,1: CLOCK_LOW" bitfld.long 0x8 0. "PWM_EN,When the PWM_ENABLE is set to 0 the internal counters are reset and the internal state machine is set to the OFF state. In addition the PWM_OUTPUT signal is set to the inactive state as determined by the Invert bit. The PWMx Counter ON Time.." "0: Disabled,1: Enabled" tree.end tree.end tree "QMSPI (Quad SPI Master Controller)" base ad:0x40070000 group.long 0x0++0x2B line.long 0x0 "MODE,QMSPI Mode Register" hexmask.long.word 0x0 16.--31. 1. "CLK_DIV,The SPI clock divide in number of system clocks. A value of 1 divides the master clock by 1 a value of 255 divides the master clock by 255. A value of 0 divides the master clock by 256." newline bitfld.long 0x0 12.--13. "CS,This defines which Chip Select will be used by the H/W when doing a transfer." "0,1,2,3" newline bitfld.long 0x0 10. "CHPA_MISO,Clock phase of the Master data in. Common SPI modes require this field to be programmed with the same value as CHPA_MOSI in this register. e.g. Mode 0: CPOL=0; CHPA_MISO=0; CHPA_MOSI=0; Mode 3: CPOL=1; CHPA_MISO=1; CHPA_MOSI=1. See.." "0: Data are captured on the rising edge of the SPI..,1: Data are captured on the falling edge of the SPI.." newline bitfld.long 0x0 9. "CHPA_MOSI,Clock phase of the Master data out. Common SPI modes require this field to be programmed with the same value as CHPA_MISO in this register. e.g. Mode 0: CPOL=0; CHPA_MISO=0; CHPA_MOSI=0; Mode 3: CPOL=1; CHPA_MISO=1; CHPA_MOSI=1. See.." "0: Data changes on the falling edge of the SPI clock,1: Data changes on the rising edge of the SPI clock" newline bitfld.long 0x0 8. "CPOL,Polarity of the SPI clock line when there are no transactions in process. 1=SPI Clock starts High; 0=SPI Clock starts Low." "0: SPI Clock starts Low,1: SPI Clock starts High" newline bitfld.long 0x0 4. "LDMA_TXEN,This enables the Local DMA TX usage (instead of the Central DMA) when the Control register enables the DMA." "0,1" newline bitfld.long 0x0 3. "LDMA_RXEN,This enables the Local DMA RX usage (instead of the Central DMA) when the Control register enables the DMA." "0,1" newline bitfld.long 0x0 2. "DMA_UNLGND_MOD,When enabled the DMA is allowed to operate w/ unaligned transfer lengths." "0,1" newline bitfld.long 0x0 1. "SOFT_RESET,Writing this bit with a 1 will reset the Quad SPI block. It is self-clearing." "0,1" newline bitfld.long 0x0 0. "ACT,This bit is used to activate the QMSPI block. 1=Enabled. The block is fully operational 0=Disabled. Clocks are gated to conserve power and the output signals are set to their inactive state." "0: Disabled,1: Enabled" line.long 0x4 "CTRL,QMSPI SPI Control" hexmask.long.word 0x4 17.--31. 1. "TRANS_LEN,The length of the SPI transfer. The count is in bytes or bits depending on the value of TRANSFER_LENGTH_BITS. A value of 0 means an infinite length transfer." newline bitfld.long 0x4 16. "DESCR_BUFF_EN,This enables the Description Buffers to be used. 1=Description Buffers in use. The first buffer is defined in DESCRIPTION_BUFFER_POINTER 0=Description Buffers disabled." "0: Description Buffers disabled,1: Description Buffers in use" newline hexmask.long.byte 0x4 12.--15. 1. "DESCR_BUFF_PTR,This field selects the first buffer used if Description Buffers are enabled." newline bitfld.long 0x4 10.--11. "TRANS_UNITS,3=TRANSFER_LENGTH defined in units of 16-byte segments 2=TRANSFER_LENGTH defined in units of 4-byte segments 1=TRANSFER_LENGTH defined in units of bytes 0=TRANSFER_LENGTH defined in units of bits." "0: TRANSFER_LENGTH defined in units of bits,1: TRANSFER_LENGTH defined in units of bytes,2: TRANSFER_LENGTH defined in units of 4-byte..,3: TRANSFER_LENGTH defined in units of 16-byte.." newline bitfld.long 0x4 9. "CLOSE_TRANS_EN,This selects what action is taken at the end of a transfer. When the transaction closes the Chip Select de-asserts the SPI interface returns to IDLE and the DMA interface terminates When Description Buffers are in use this bit must.." "0: The transaction is not terminated,1: The transaction is terminated" newline bitfld.long 0x4 7.--8. "RX_DMA_EN,This bit enables DMA support for Receive Transfer. If enabled DMA will be requested to empty the FIFO until either the interface reaches TRANSFER_LENGTH or the DMA sends a termination request. The size defined here must match.." "0: DMA is disabled,1: DMA is enabled,2: DMA is enabled and set to 2 Bytes,3: DMA is enabled and set to 4 Bytes" newline bitfld.long 0x4 6. "RX_TRANS_EN,This bit enables the receive function of the SPI interface. 1=Receive is enabled. Data received from the SPI Slave is stored in the Receive Buffer 0=Receive is disabled" "0: Receive is disabled,1: Receive is enabled" newline bitfld.long 0x4 4.--5. "TX_DMA_EN,This bit enables DMA support for Transmit Transfer. If enabled DMA will be requested to fill the FIFO until either the interface reaches TRANSFER_LENGTH or the DMA sends a termination request. The size defined here must match DMA.." "0: DMA is disabled,1: DMA is enabled,2: DMA is enabled and set to 2 Bytes,3: DMA is enabled and set to 4 Bytes" newline bitfld.long 0x4 2.--3. "TX_TRANS_EN,This field bit selects the transmit function of the SPI interface. 3=Transmit Enabled in 1 Mode. The MOSI or IO Bus will send out only 1's. The Transmit Buffer will not be used. 2=Transmit Enabled in 0 Mode." "0: Transmit is Disabled,1: Transmit Enabled,2: Transmit Enabled in 0 Mode,3: Transmit Enabled in 1 Mode" newline bitfld.long 0x4 0.--1. "TX_MODE,This field sets the transmission mode. If this field is set for Dual Mode or Quad Mode then either TX_TRANSFER_ENABLE or RX_TRANSFER_ENABLE must be 0. 3=Reserved; 2=Quad Mode; 1=Dual Mode; 0=Single/Duplex Mode." "0: Single/Duplex Mode,1: Dual Mode,2: Quad Mode,3: Reserved" line.long 0x8 "EXE,QMSPI Execute Register" bitfld.long 0x8 2. "CLR_DAT_BUFF,Writing a 1 to this bit will clear out the Transmit and Receive FIFOs. Any data stored in the FIFOs is discarded and all count fields are reset. Writing a 0 to this bit has no effect. This bit is self clearing." "0,1" newline bitfld.long 0x8 1. "STOP,Writing a 1 to this bit will stop any transfer in progress at the next byte boundary. Writing a 0 to this bit has no effect. This bit is self clearing. This bit must not be set to 1 if the field START in this register is set to 1." "0,1" newline bitfld.long 0x8 0. "START,Writing a 1 to this bit will start the SPI transfer. Writing a 0 to this bit has no effect. This bit is self-clearing. This bit must not be set to 1 if the field STOP in this register is set to 1." "0,1" line.long 0xC "IFCTRL,QMSPI Interface Control Register" bitfld.long 0xC 7. "PU_ON_NOTDRIVEN,1=Enable pull-up resistors on Transmit pins while the pins are not driven 0=No pull-up resistors enabled ion Transmit pins." "0: No pull-up resistors enabled ion Transmit pins,1: Enable pull-up resistors on Transmit pins while.." newline bitfld.long 0xC 6. "PD_ON_NOTDRIVEN,1=Enable pull-down resistors on Transmit pins while the pins are not driven 0=No pull-down resistors enabled ion Transmit pins." "0: No pull-down resistors enabled ion Transmit pins,1: Enable pull-down resistors on Transmit pins.." newline bitfld.long 0xC 5. "PU_ON_NOTSEL,1=Enable pull-up resistors on Receive pins while the SPI Chip Select signal is not asserted 0=No pull-up resistors enabled on Receive pins." "0: No pull-up resistors enabled on Receive pins,1: Enable pull-up resistors on Receive pins while.." newline bitfld.long 0xC 4. "PD_ON_NOT_SEL,1=Enable pull-down resistors on Receive pins while the SPI Chip Select signal is not asserted 0=No pull-down resistors enabled on Receive pins" "0: No pull-down resistors enabled on Receive pins,1: Enable pull-down resistors on Receive pins while.." newline bitfld.long 0xC 3. "HLD_OUT_EN,1=HOLD SPI Output Port is driven 0=HOLD SPI Output Port is not driven." "0: HOLD SPI Output Port is not driven,1: HOLD SPI Output Port is driven" newline bitfld.long 0xC 2. "HLD_OUT_VAL,This bit sets the value on the HOLD SPI Output Port if it is driven. 1=HOLD is driven to 1; 0=HOLD is driven to 0." "0: HOLD is driven to 0,1: HOLD is driven to 1" newline bitfld.long 0xC 1. "WR_PRCT_OUT_EN,1=WRITE PROTECT SPI Output Port is driven 0=WRITE PROTECT SPI Output Port is not driven" "0: WRITE PROTECT SPI Output Port is not driven,1: WRITE PROTECT SPI Output Port is driven" newline bitfld.long 0xC 0. "WR_PRCT_OUT_VAL,This bit sets the value on the WRITE PROTECT SPI Output Port if it is driven. 1=WRITE PROTECT is driven to 1; 0=WRITE PROTECT is driven to 0" "0: WRITE PROTECT is driven to 0,1: WRITE PROTECT is driven to 1" line.long 0x10 "STS,QMSPI Status Register" hexmask.long.byte 0x10 24.--27. 1. "CUR_DESCR_BUF,This field shows the Description Buffer currently active. This field has no meaning if Description Buffers are not enabled." newline bitfld.long 0x10 16. "TRANS_ACTIV,1=A transfer is currently executing 0=No transfer currently in progress." "0: No transfer currently in progress,1: A transfer is currently executing" newline bitfld.long 0x10 15. "RX_BUFF_STALL,1=The SPI interface had been stalled due to a flow issue (an attempt by the interface to write to a full Receive Buffer) 0=No stalls occurred." "0: No stalls occurred,1: The SPI interface had been stalled due to a flow.." newline bitfld.long 0x10 14. "RX_BUFF_REQ,This status is asserted if the Receive Buffer reaches a high water mark established by the RECEIVE_BUFFER_TRIGGER field. 1=RECEIVE_BUFFER_COUNT is greater than or equal to RECEIVE_BUFFER_TRIGGER.." "0: RECEIVE_BUFFER_COUNT is less than..,1: RECEIVE_BUFFER_COUNT is greater than or equal to.." newline bitfld.long 0x10 13. "RX_BUFF_EMP,1=The Receive Buffer is empty 0=The Receive Buffer is not empty." "0: The Receive Buffer is not empty,1: The Receive Buffer is empty" newline bitfld.long 0x10 12. "RX_BUFF_FULL,1=The Receive Buffer is full 0=The Receive Buffer is not full." "0: The Receive Buffer is not full,1: The Receive Buffer is full" newline bitfld.long 0x10 11. "TX_BUFF_STALL,1=The SPI interface had been stalled due to a flow issue (an attempt by the interface to read from an empty Transmit Buffer) 0=No stalls occurred." "0: No stalls occurred,1: The SPI interface had been stalled due to a flow.." newline bitfld.long 0x10 10. "TX_BUFF_REQ,This status is asserted if the Transmit Buffer reaches a high water mark established by the TRANSMIT_BUFFER_TRIGGER field. 1=TRANSMIT_BUFFER_COUNT is less than or equal to TRANSMIT_BUFFER_TRIGGER; 0=TRANSMIT_BUFFER_COUNT is greater than.." "0: TRANSMIT_BUFFER_COUNT is greater than..,1: TRANSMIT_BUFFER_COUNT is less than or equal to.." newline bitfld.long 0x10 9. "TX_BUFF_EMP,1=The Transmit Buffer is empty 0=The Transmit Buffer is not empty." "0: The Transmit Buffer is not empty,1: The Transmit Buffer is empty" newline bitfld.long 0x10 8. "TX_BUFF_FULL,1=The Transmit Buffer is full 0=The Transmit Buffer is not full." "0: The Transmit Buffer is not full,1: The Transmit Buffer is full" newline bitfld.long 0x10 6. "LDMA_TXERR,This bit is set if Local DMA Transmit error is detected. 1=Local DMA TX Error detected; 0=No Local DMA TX detected." "0: No Local DMA TX detected,1: Local DMA TX Error detected" newline bitfld.long 0x10 5. "LDMA_RXERR,This bit is set if Local DMA Receive error is detected. 1=Local DMA RX Error detected; 0=No Local DMA RX detected." "0: No Local DMA RX detected,1: Local DMA RX Error detected" newline bitfld.long 0x10 4. "PRGM_ERR,This bit if a programming error is detected. 1=Programming Error detected; 0=No programming error detected." "0: No programming error detected,1: Programming Error detected" newline bitfld.long 0x10 3. "RX_BUFF_ERR,1=Underflow error occurred (attempt to read from an empty Receive Buffer) 0=No underflow occurred." "0: No underflow occurred,1: Underflow error occurred" newline bitfld.long 0x10 2. "TX_BUFF_ERR,1=Overflow error occurred (attempt to write to a full Transmit Buffer) 0=No overflow occurred." "0: No overflow occurred,1: Overflow error occurred" newline bitfld.long 0x10 1. "DMA_COMPL,This field has no meaning if DMA is not enabled. This bit will be set to 1 when the DMA controller asserts the DONE signal to the SPI controller. This occurs either when the SPI controller has closed the DMA transfer or the DMA channel has.." "0: DMA not completed,1: DMA completed" newline bitfld.long 0x10 0. "TRANS_COMPL,In Manual Mode (neither DMA nor Description Buffers are enabled) this bit will be set to 1 when the transfer matches TRANSFER_LENGTH. If DMA Mode is enabled this bit will be set to 1 when DMA_COMPLETE is set to 1. In.." "0: Transfer not complete,1: Transfer completed" line.long 0x14 "BUF_CNT_STS,QMSPI Buffer Count Status Register" hexmask.long.word 0x14 16.--31. 1. "RX_BUFF_CNT,This is a count of the number of bytes currently valid in the Receive Buffer." newline hexmask.long.word 0x14 0.--15. 1. "TX_BUFF_CNT,This is a count of the number of bytes currently valid in the Transmit Buffer." line.long 0x18 "IEN,QMSPI Interrupt Enable Register" bitfld.long 0x18 14. "RX_BUF_REQ_EN,1=Enable an interrupt if RECEIVE_BUFFER_REQUEST is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if RECEIVE_BUFFER_REQUEST is.." newline bitfld.long 0x18 13. "RX_BUF_EMPTY_EN,1=Enable an interrupt if RECEIVE_BUFFER_EMPTY is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if RECEIVE_BUFFER_EMPTY is.." newline bitfld.long 0x18 12. "RX_BUF_FUL_EN,1=Enable an interrupt if RECEIVE_BUFFER_FULL is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if RECEIVE_BUFFER_FULL is.." newline bitfld.long 0x18 10. "TX_BUF_REQ_EN,1=Enable an interrupt if TRANSMIT_BUFFER_REQUEST is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if TRANSMIT_BUFFER_REQUEST.." newline bitfld.long 0x18 9. "TX_BUF_EMPTY_EN,1=Enable an interrupt if TRANSMIT_BUFFER_EMPTY is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if TRANSMIT_BUFFER_EMPTY is.." newline bitfld.long 0x18 8. "TX_BUF_FULL_EN,1=Enable an interrupt if TRANSMIT_BUFFER_FULL is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if TRANSMIT_BUFFER_FULL is.." newline bitfld.long 0x18 6. "LDMA_TXERRIE,1=Enable an interrupt if Local DMA TX Error is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if Local DMA TX Error is.." newline bitfld.long 0x18 5. "LDMA_RXERRIE,1=Enable an interrupt if Local DMA RX Error is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if Local DMA RX Error is.." newline bitfld.long 0x18 4. "PRGM_ERR_EN,1=Enable an interrupt if PROGRAMMING_ERROR is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if PROGRAMMING_ERROR is.." newline bitfld.long 0x18 3. "RX_BUF_ERR_EN,1=Enable an interrupt if RECEIVE_BUFFER_ERROR is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if RECEIVE_BUFFER_ERROR is.." newline bitfld.long 0x18 2. "TX_BUF_ERR_EN,1=Enable an interrupt if TRANSMIT_BUFFER_ERROR is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if TRANSMIT_BUFFER_ERROR is.." newline bitfld.long 0x18 1. "DMA_COMPL_EN,1=Enable an interrupt if DMA_COMPLETE is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if DMA_COMPLETE is asserted" newline bitfld.long 0x18 0. "TRANS_COMPL_EN,1=Enable an interrupt if TRANSFER_COMPLETE is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if TRANSFER_COMPLETE is.." line.long 0x1C "BUF_CNT_TRIG,QMSPI Buffer Count Trigger Register" hexmask.long.word 0x1C 16.--31. 1. "RX_BUF_TRIG,An interrupt is triggered if the RECEIVE_BUFFER_COUNT field is greater than or equal to this value. A value of 0 disables the interrupt." newline hexmask.long.word 0x1C 0.--15. 1. "TX_BUF_TRIG,An interrupt is triggered if the TRANSMIT_BUFFER_COUNT field is less than or equal to this value. A value of 0 disables the interrupt." line.long 0x20 "TX_FIFO,QMSPI Transmit Buffer Register" hexmask.long 0x20 0.--31. 1. "TX_BUF,Writes to this register store data to be transmitted from the SPI Master to the external SPI Slave. Writes to this block will be written to the Transmit FIFO. A 1 Byte write fills 1 byte of the FIFO. A Word write fills 2 Bytes and a Doubleword.." line.long 0x24 "RX_FIFO,QMSPI Receive Buffer Register" hexmask.long 0x24 0.--31. 1. "RX_BUF,Buffer that stores data from the external SPI Slave device to the SPI Master (this block) which is received over MISO or IO. Reads from this register will empty the Rx FIFO. A 1 Byte read will have valid data on bits [7:0] and a Word read.." line.long 0x28 "CSTM,QMSPI Chip Select Timing Register" hexmask.long.byte 0x28 24.--31. 1. "DLY_OFF_TO_ON,This selects the number of system clock cycles between CS deassertion to CS assertion. This is the minimum pulse width of CS deassertion." newline hexmask.long.byte 0x28 16.--19. 1. "DLY_LAST_DAT_HLD,This selects the number of system clock cycles between CS deassertion to the data ports for WP and HOLD switching from input to output." newline hexmask.long.byte 0x28 8.--11. 1. "DLY_CLK_STOP_CS_OFF,This selects the number of system clock cycles between the last clock edge and the deassertion of CS." newline hexmask.long.byte 0x28 0.--3. 1. "DLY_CS_ON_CLK_STRT,This selects the number of system clock cycles between CS assertion to the start of the SPI Clock." repeat 16. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "DESCR[$1],QMSPI Description Buffer 0 Register" hexmask.long.word 0x0 17.--31. 1. "TX_LEN,The length of the SPI transfer. The count is in bytes or bits depending on the value of TRANSFER_LENGTH_BITS. A value of 0 means an infinite length transfer." newline bitfld.long 0x0 16. "DESCR_BUF_LAST,Last Descriptor. 1=Last Description Buffer in the chain. 0=This is not the last buffer." "0: This is not the last buffer,1: Last Description Buffer in the chain" newline hexmask.long.byte 0x0 12.--15. 1. "DESCR_BUF_NXT_PTR,This defines the next buffer to be used if Description Buffers are enabled and this is not the last buffer. This can point to the current buffer creating an infinite loop." newline bitfld.long 0x0 10.--11. "TRANS_LEN_BITS,3=TRANSFER_LENGTH defined in units of 16-byte segments 2=TRANSFER_LENGTH defined in units of 4-byte segments 1=TRANSFER_LENGTH defined in units of bytes 0=TRANSFER_LENGTH defined in units of bits" "0: TRANSFER_LENGTH defined in units of bits,1: TRANSFER_LENGTH defined in units of bytes,2: TRANSFER_LENGTH defined in units of 4-byte..,3: TRANSFER_LENGTH defined in units of 16-byte.." newline bitfld.long 0x0 9. "CLOSE_TRANS_EN,This selects what action is taken at the end of a transfer. This bit must be set only on the Last Buffer. 1=The transfer is terminated. The Chip Select de-asserts the SPI interface returns to IDLE and the DMA interface completes the.." "0: The transfer is not closed,1: The transfer is terminated" newline bitfld.long 0x0 7.--8. "RX_DMA_EN,This bit enables DMA support for Receive Transfer. If enabled DMA will be requested to empty the FIFO until either the interface reaches TRANSFER_LENGTH or the DMA sends a termination request. The size defined here must match DMA programmed.." "0: DMA is disabled,1: DMA is enabled,2: DMA is enabled and set to 2 Bytes,3: DMA is enabled and set to 4 Bytes" newline bitfld.long 0x0 6. "RX_TRANS_EN,This bit enables the receive function of the SPI interface. 1=Receive is enabled. Data received from the SPI Slave is stored in the Receive Buffer; 0=Receive is disabled." "0: Receive is disabled,1: Receive is enabled" newline bitfld.long 0x0 4.--5. "TX_DMA_EN,This bit enables DMA support for Transmit Transfer. If enabled DMA will be requested to fill the FIFO until either the interface reaches TRANSFER_LENGTH or the DMA sends a termination request. The size defined here must match DMA.." "0: DMA is disabled,1: DMA is enabled,2: DMA is enabled and set to 2 Bytes,3: DMA is enabled and set to 4 Bytes" newline bitfld.long 0x0 2.--3. "TX_TRANS_EN,This field bit selects the transmit function of the SPI interface. 3=Transmit Enabled in 1 Mode. The MOSI or IO Bus will send out only 1's. The Transmit Buffer will not be used 2=Transmit Enabled in 0 Mode. The MOSI or IO Bus will.." "0: Transmit is Disabled,1: Transmit Enabled,2: Transmit Enabled in 0 Mode,3: Transmit Enabled in 1 Mode" newline bitfld.long 0x0 0.--1. "INFACE_MOD,This field sets the transmission mode. If this field is set for Dual Mode or Quad Mode then either TX_TRANSFER_ENABLE or RX_TRANSFER_ENABLE must be 0. 3=Reserved; 2=Quad Mode; 1=Dual Mode; 0=Single/Duplex Mode." "0: Single/Duplex Mode,1: Dual Mode,2: Quad Mode,3: Reserved" repeat.end wgroup.long 0xB0++0x3 line.long 0x0 "ALIAS_CTRL,QMSPI Alias Control Register" hexmask.long.byte 0x0 24.--31. 1. "ALS_TXDBUF_DATA,The Byte of data written into the Tx Buffer if the write is enabled." newline hexmask.long.byte 0x0 16.--23. 1. "ALS_DBUF_XFR_LEN,The value of the data written to the Description Buffers Transfer Length field if the write is enabled." newline hexmask.long.byte 0x0 12.--15. 1. "ALS_DBUF_SEL,Which Description Buffer will be modified by a write if Alias Write Description Buffer Transfer Length is set." newline hexmask.long.byte 0x0 8.--11. 1. "ALS_CTRL_DBUF_PTR,Alias for the QMSPI Control:Description Buffer Pointer field." newline bitfld.long 0x0 6. "ALS_LDMA_INCR_ADD,Alias that overrides the value in all QMSPI Local DMA * [Tx/Rx] Control:Increment Address Enable fields w/ this value." "0,1" newline bitfld.long 0x0 4.--5. "ALS_MOD_CS,Alias for the QMSPI Mode:Chip Select field." "0,1,2,3" newline bitfld.long 0x0 3. "ALS_WRDBUF_XFRLEN,Alias that triggers a write to the Description Buffer pointed to by Alias Description Buffer Select in this register to modify the Transfer Length field with the value of Alias Description Buffer Transfer Length in this register." "0,1" newline bitfld.long 0x0 2. "ALS_WR_TXBUF,Alias that triggers a write to the Tx Buffer of 1 Byte using data from Alias Tx Buffer Data in this register." "0,1" newline bitfld.long 0x0 1. "CLS_ALTMODE_EN,Enable the CS1 Clock Divide to be active if CS1 is the interface in use." "0,1" newline bitfld.long 0x0 0. "ALS_EXEC_STRT,Alias for the QMSPI Execution:Start field." "0,1" group.long 0xC0++0x3 line.long 0x0 "MODE_ALT1,QMSPI Mode Alternate 1 Register" hexmask.long.word 0x0 16.--31. 1. "CS1_ALTCLK_DIV,The SPI clock divide in number of system clocks when CS1 is in use and CS1 Alt Mode Enable is set." newline bitfld.long 0x0 0. "CS1_ALTMOD_EN,Enable the CS1 Clock Divide to be active if CS1 is the interface in use." "0,1" group.long 0xD0++0xB line.long 0x0 "TAPS,QMSPI TAPs Register" hexmask.long.byte 0x0 8.--15. 1. "CTRL_TAP,This will select the tap point for signals that go from the System Domain." newline hexmask.long.byte 0x0 0.--7. 1. "SCK_TAP,This will select the tap point for the feed-back SCK." line.long 0x4 "TAP_ADJ,QMSPI TAP Control Register" hexmask.long.byte 0x4 8.--15. 1. "CTRL_ADJ,This is a signed value that will be added to the Select Control Tap to come up with the final value for the delay." newline hexmask.long.byte 0x4 0.--7. 1. "SCK_ADJ,This is a signed value that will be added to the Select SCK Tap to come up with the final value for the delay." line.long 0x8 "TAP_CTRL,QMSPI TAP Adjustment Register" bitfld.long 0x8 16.--18. "AUTO_MULT,This will multiply the target delay value the Auto-trim H/W will search for." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8. "FW_GO,This will force the auto-trim H/W to run and find a new trim value." "0,1" newline bitfld.long 0x8 2. "CTRL,This is a signed value that will be added to the Select Control Tap to come up with the final value for the delay." "0,1" newline bitfld.long 0x8 0.--1. "AUTO_MOD,This enables the automatic H/W trim of the Tap." "0,1,2,3" group.long 0x104++0x3 line.long 0x0 "DESC_LDMA_TXEN,QMSPI Descriptor Local DMA Tx Enable Register" hexmask.long.word 0x0 0.--15. 1. "DESC_LDMA_TXEN,This enables the Local TX DMA usage (instead of the Central DMA) when the Descriptor Buffer register enables the DMA." group.long 0x100++0x3 line.long 0x0 "DESC_LDMA_RXEN,QMSPI Descriptor Local DMA Rx Enable Register" hexmask.long.word 0x0 0.--15. 1. "DESC_LDMA_RXEN,This enables the Local RX DMA usage (instead of the Central DMA) when the Descriptor Buffer register enables the DMA." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40070110 ad:0x40070120 ad:0x40070130) tree "LDMA_RX[$1]" base $2 group.long ($2)++0xB line.long 0x0 "LDMA_RXCTRL,QMSPI RX Control Register" bitfld.long 0x0 6. "INC_ADDR_EN,When set the DMA Channels Start Address will increment on every access. If not set the address will not increment." "0,1" bitfld.long 0x0 4.--5. "ACS_SZ,Access Size selects the AHB Access Size." "0,1,2,3" bitfld.long 0x0 3. "OVRD_LEN,Override Lenght will override the length field to the QMSPI protocol FSM with the length programmed into the Local DMA." "0,1" bitfld.long 0x0 2. "BUF_ADDR_EN,Address re-enable will automatically re-enables the same address upon completion previous transfer." "0,1" bitfld.long 0x0 1. "RSTRT_EN,This bit automatically re-enables the Local DMA Channel after completion of previous transfer." "0,1" bitfld.long 0x0 0. "CH_EN,This enables the Local RX DMA Channel." "0,1" line.long 0x4 "LDMA_RXSTRT_ADDR,QMSPI Local DMA Rx Start Address Register" hexmask.long 0x4 0.--31. 1. "STRT_ADDR,This is the Starting Address for the DMA access into the memory space (write to this address on Rx). This address is updated by the transfer size based on the Local DMA Access Size after every access." line.long 0x8 "LDMA_RX_LEN,QMSPI Local DMA Rx Length Register" hexmask.long 0x8 0.--31. 1. "RX_LEN,This is the maximum Length of the transfer in Bytes that the DMA Channel will allow access to." rgroup.long ($2+0xC)++0x3 line.long 0x0 "RSVD,Reserved Register" tree.end repeat.end repeat 3. (list 0x0 0x1 0x2)(list ad:0x40070140 ad:0x40070150 ad:0x40070160) tree "LDMA_TX[$1]" base $2 group.long ($2)++0xB line.long 0x0 "LDMA_TXCTRL,QMSPI TX Control Register" bitfld.long 0x0 6. "INC_ADDR_EN,When set the DMA Channels Start Address will increment on every access. If not set the address will not increment." "0,1" bitfld.long 0x0 4.--5. "ACS_SZ,Access Size selects the AHB Access Size." "0,1,2,3" bitfld.long 0x0 3. "OVRD_LEN,Override Lenght will override the length field to the QMSPI protocol FSM with the length programmed into the Local DMA." "0,1" bitfld.long 0x0 2. "BUF_ADDR_EN,Address re-enable will automatically re-enables the same address upon completion previous transfer." "0,1" bitfld.long 0x0 1. "RSTRT_EN,This bit automatically re-enables the Local DMA Channel after completion of previous transfer." "0,1" bitfld.long 0x0 0. "CH_EN,This enables the Local TX DMA Channel." "0,1" line.long 0x4 "LDMA_TXSTRT_ADDR,QMSPI Local DMA Tx Start Address Register" hexmask.long 0x4 0.--31. 1. "STRT_ADDR,This is the Starting Address for the DMA access into the memory space (Read from this address on Tx). This address is updated by the transfer size based on the Local DMA Access Size after every access." line.long 0x8 "LDMA_TX_LEN,QMSPI Local DMA Tx Length Register" hexmask.long 0x8 0.--31. 1. "TX_LEN,This is the maximum Length of the transfer in Bytes that the DMA Channel will allow access to." rgroup.long ($2+0xC)++0x3 line.long 0x0 "RSVD,Reserved Register" tree.end repeat.end tree.end tree "RC_ID (Resistor/Capacitor Identification Detection)" base ad:0x0 tree "RC_ID0" base ad:0x40001400 group.long 0x0++0x7 line.long 0x0 "CONTROL,RC_ID Control Register" bitfld.long 0x0 8.--9. "CLOCK_SET,This field selects the frequency of the Counter circuit clock. This field must retain the same value as long as the ENABLE bit in this register is 1." "0,1,2,3" bitfld.long 0x0 7. "ENABLE,Clearing the bit to 0 causes the RC_ID interface to enter the Reset state gating its clocks clearing the status bits in this register and entering into its lowest power state. Setting this bit to 1 causes the RC_ID interface to enter the.." "0,1" bitfld.long 0x0 6. "START,Setting this bit to 1 initiates the Discharged phase of an RC_ID measurement." "0,1" bitfld.long 0x0 2. "CY_ER,This bit is 1 if an RC_ID measurement encountered an error and the reading in the RC_ID Data Register is invalid. This bit is cleared to 0 when the RC_ID interface is in the Reset phase." "0,1" bitfld.long 0x0 1. "TC,This bit is cleared to 0 when the RC_ID interface is in the Reset phase and set to 1 when the interface completes the Discharged phase of an RC_ID measurement." "0,1" bitfld.long 0x0 0. "DONE,This bit is cleared to 0 when the RC_ID interface is in the Reset phase and set to 1 when the interface completes an RC_ID measurement." "0,1" line.long 0x4 "DATA,Reads of this register provide the result of an RC_ID measurement." hexmask.long.word 0x4 0.--15. 1. "RCID_DATA,Reads of this register provide the result of an RC_ID measurement." tree.end tree "RC_ID1" base ad:0x40001480 group.long 0x0++0x7 line.long 0x0 "CONTROL,RC_ID Control Register" bitfld.long 0x0 8.--9. "CLOCK_SET,This field selects the frequency of the Counter circuit clock. This field must retain the same value as long as the ENABLE bit in this register is 1." "0,1,2,3" bitfld.long 0x0 7. "ENABLE,Clearing the bit to 0 causes the RC_ID interface to enter the Reset state gating its clocks clearing the status bits in this register and entering into its lowest power state. Setting this bit to 1 causes the RC_ID interface to enter the.." "0,1" bitfld.long 0x0 6. "START,Setting this bit to 1 initiates the Discharged phase of an RC_ID measurement." "0,1" bitfld.long 0x0 2. "CY_ER,This bit is 1 if an RC_ID measurement encountered an error and the reading in the RC_ID Data Register is invalid. This bit is cleared to 0 when the RC_ID interface is in the Reset phase." "0,1" bitfld.long 0x0 1. "TC,This bit is cleared to 0 when the RC_ID interface is in the Reset phase and set to 1 when the interface completes the Discharged phase of an RC_ID measurement." "0,1" bitfld.long 0x0 0. "DONE,This bit is cleared to 0 when the RC_ID interface is in the Reset phase and set to 1 when the interface completes an RC_ID measurement." "0,1" line.long 0x4 "DATA,Reads of this register provide the result of an RC_ID measurement." hexmask.long.word 0x4 0.--15. 1. "RCID_DATA,Reads of this register provide the result of an RC_ID measurement." tree.end tree "RC_ID2" base ad:0x40001500 group.long 0x0++0x7 line.long 0x0 "CONTROL,RC_ID Control Register" bitfld.long 0x0 8.--9. "CLOCK_SET,This field selects the frequency of the Counter circuit clock. This field must retain the same value as long as the ENABLE bit in this register is 1." "0,1,2,3" bitfld.long 0x0 7. "ENABLE,Clearing the bit to 0 causes the RC_ID interface to enter the Reset state gating its clocks clearing the status bits in this register and entering into its lowest power state. Setting this bit to 1 causes the RC_ID interface to enter the.." "0,1" bitfld.long 0x0 6. "START,Setting this bit to 1 initiates the Discharged phase of an RC_ID measurement." "0,1" bitfld.long 0x0 2. "CY_ER,This bit is 1 if an RC_ID measurement encountered an error and the reading in the RC_ID Data Register is invalid. This bit is cleared to 0 when the RC_ID interface is in the Reset phase." "0,1" bitfld.long 0x0 1. "TC,This bit is cleared to 0 when the RC_ID interface is in the Reset phase and set to 1 when the interface completes the Discharged phase of an RC_ID measurement." "0,1" bitfld.long 0x0 0. "DONE,This bit is cleared to 0 when the RC_ID interface is in the Reset phase and set to 1 when the interface completes an RC_ID measurement." "0,1" line.long 0x4 "DATA,Reads of this register provide the result of an RC_ID measurement." hexmask.long.word 0x4 0.--15. 1. "RCID_DATA,Reads of this register provide the result of an RC_ID measurement." tree.end tree.end tree "RTC (Real Time Clock)" base ad:0x400F5000 group.byte 0x0++0xD line.byte 0x0 "SEC,Seconds Register" line.byte 0x1 "SEC_ALARM,Seconds Alarm Register" line.byte 0x2 "MIN,Minutes Register" line.byte 0x3 "MIN_ALARM,Minutes Alarm Register" line.byte 0x4 "HR,Hours Register" line.byte 0x5 "HR_ALARM,Hours Alarm Register" line.byte 0x6 "DAY_OF_WK,Day of Week Register" line.byte 0x7 "DAY_OF_MON,Day of Month Register" line.byte 0x8 "MONTH,Month Register" line.byte 0x9 "YEAR,Year Register" line.byte 0xA "REGA,Register A" line.byte 0xB "REGB,Register B" line.byte 0xC "REGC,Register C" line.byte 0xD "REGD,Register D" group.long 0x10++0xF line.long 0x0 "CTRL,RTC Control Register" bitfld.long 0x0 3. "ALM_EN,ALARM_ENABLE 1=Enables the Alarm features 0=Disables the Alarm features" "0: Disables the Alarm features,1: Enables the Alarm features" bitfld.long 0x0 2. "VCI_EN,VCI Enable 1= RTC Alarm to VCI Circuitry 0= No RTC alarm to VCI circuitry" "0: No RTC alarm to VCI circuitry,1: RTC Alarm to VCI Circuitry" bitfld.long 0x0 1. "SOFT_RST,SOFT_RESET A 1 written to this bit position will trigger the RTC_RST reset resetting the block and all registers except this one and the Test Register. This bit is self-clearing at the end of the reset one cycle of Host Bus Clock later .." "0,1" bitfld.long 0x0 0. "BLK_EN,BLOCK_ENABLE This bit must be 1 in order for the block to function internally. Registers may be initialized first before setting this bit to '1' to start operation." "0,1" line.long 0x4 "WK_ALARM,Week Alarm Register[7:0] - ALARM_DAY_OF_WEEK This register. if written to a value in the range 1- -7. will inhibit the Alarm interrupt unless this field matches the contents of the Day of Week Register also." line.long 0x8 "DAYLT_SAVF,Daylight Savings Forward Register" bitfld.long 0x8 31. "DST_AM_PM,This bit selects AM vs. PM to match bit[7] of the Hours Register if 12-Hour mode is selected in Register B at the time of writing." "0,1" hexmask.long.byte 0x8 24.--30. 1. "DST_HR,This field holds the matching value for bits[6:0] of the Hours register. The written value will be interpreted according to the 24/12 Hour mode and DM mode settings at the time of writing." bitfld.long 0x8 16.--18. "DST_WK,5=Last week of month 4 =Fourth week of month 3=Third week of month 2=Second week of month 1=First week of month" "?,1: First week of month,2: Second week of month,3: Third week of month,4: Fourth week of month,5: Last week of month,?,?" bitfld.long 0x8 8.--10. "DST_DAY_OF_WK,This field matches the Day of Week Register bits[2:0]." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--7. 1. "DST_MON,This field matches the Month Register." line.long 0xC "DAYLT_SAVB,Daylight Savings Backward Register" bitfld.long 0xC 31. "DST_AM_PM,This bit selects AM vs. PM to match bit[7] of the Hours Register if 12-Hour mode is selected in Register B at the time of writing." "0,1" hexmask.long.byte 0xC 24.--30. 1. "DST_HR,This field holds the matching value for bits[6:0] of the Hours register. The written value will be interpreted according to the 24/12 Hour mode and DM mode settings at the time of writing." bitfld.long 0xC 16.--18. "DST_WK,5=Last week of month 4 =Fourth week of month 3=Third week of month 2=Second week of month 1=First week of month" "?,1: First week of month,2: Second week of month,3: Third week of month,4: Fourth week of month,5: Last week of month,?,?" bitfld.long 0xC 8.--10. "DST_DAY_OF_WK,This field matches the Day of Week Register bits[2:0]." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 0.--7. 1. "DST_MON,This field matches the Month Register." tree.end tree "RTOS (RTOS Timer)" base ad:0x40007400 group.long 0x0++0xB line.long 0x0 "CNT,RTOS Timer Count Register." hexmask.long 0x0 0.--31. 1. "CNTR,This register contains the current value of the RTOS Timer counter. This register should be read as a DWORD. There is no latching mechanism of the upper bytes implemented if the register is accessed as a byte or word. Reading the register.." line.long 0x4 "PRLD,RTOS Timer Preload Register" hexmask.long 0x4 0.--31. 1. "PRELOAD,The this register is loaded into the RTOS Timer counter either when the TIMER_START bit is written with a 1 or when the timer counter counts down to 0 and the AUTO_RELOAD bit is 1. This register must be programmed with a new count value.." line.long 0x8 "CTRL,RTOS Timer Control Register" bitfld.long 0x8 4. "FW_TMR_HALT,1=The timer counter is halted. If the counter was running clearing this bit will restart the counter from the value at which it halted 0=The timer counter if enabled will continue to run" "0: The timer counter,1: The timer counter is halted" bitfld.long 0x8 3. "EXT_HW_HALT_EN,1=The timer counter is halted when the external HALT signal is asserted. Counting is always enabled if HALT is de-asserted. 0=The HALT signal does not affect the RTOS Timer" "0: The HALT signal does not affect the RTOS Timer,1: The timer counter is halted when the external.." newline bitfld.long 0x8 2. "TMR_STRT,Writing a 1 to this bit will load the timer counter with the RTOS Timer Preload Register and start counting. If the Preload Register is 0 counting will not start and this bit will be cleared to 0. Writing a 0 to this bit will halt the.." "0,1" bitfld.long 0x8 1. "AU_RELOAD,1=The the RTOS Timer Preload Register is loaded into the timer counter and the counter is restarted when the counter transitions from 1 to 0 0=The timer counter halts when it transitions from 1 to 0 and will not restart." "0: The timer counter halts when it transitions from..,1: The the RTOS Timer Preload Register is loaded.." newline bitfld.long 0x8 0. "BLK_EN,1=RTOS timer counter is enabled 0=RTOS timer disabled. All register bits are reset to their default state" "0: RTOS timer disabled,1: RTOS timer counter is enabled" wgroup.long 0xC++0x3 line.long 0x0 "SOFTIRQ,Soft Interrupt Register" bitfld.long 0x0 3. "SWI3,Software Interrupt. A write of a '1' to this bit will generate an SWI interrupt to the EC. Writes of a '0' have no effect. Reads return '0'." "0,1" bitfld.long 0x0 2. "SWI2,Software Interrupt. A write of a '1' to this bit will generate an SWI interrupt to the EC. Writes of a '0' have no effect. Reads return '0'." "0,1" newline bitfld.long 0x0 1. "SWI1,Software Interrupt. A write of a '1' to this bit will generate an SWI interrupt to the EC. Writes of a '0' have no effect. Reads return '0'." "0,1" bitfld.long 0x0 0. "SWI0,Software Interrupt. A write of a '1' to this bit will generate an SWI interrupt to the EC. Writes of a '0' have no effect. Reads return '0'." "0,1" tree.end tree "SAFBC (SAF Bridge Component)" base ad:0x0 tree "SAFBC_CACHE" base ad:0x4000F000 group.long 0x18++0x17 line.long 0x0 "EC_LEN_TAG_CMD,This register defines the command type and length of transfers requested by EC firmware" hexmask.long.byte 0x0 24.--31. 1. "EC_LENGTH,This field contains the Length field for all requests. Read or Write: The length in bytes of the data transfer to or from the SRAM buffer. Must be in the range 1 -- 64 (01h -- 40h)." hexmask.long.byte 0x0 8.--15. 1. "EC_CTYPE_CMD,This field encodes the operation requested: 00h = Read 01h = Write (Page Program) 02h = Erase Other encodings are undefined" hexmask.long.byte 0x0 0.--7. 1. "EC_PUT_CMD,This field must contain the value 0Ah; that is the eSPI command PUT_FLASH_NP." line.long 0x4 "EC_FLASH_ADD,This register hold the Flash Space address to be accessed by the current command from EC firmware." hexmask.long 0x4 0.--31. 1. "FLASH_ADDR,FLASH_ADDR: This field holds the Flash address to be accessed." line.long 0x8 "EC_START,This register contains the Start control for a Flash access requested in the rest of the EC Portal registers. It triggers the requested transfer." bitfld.long 0x8 0. "START,This bit is written with '1' to start a new request but always appears 0 when being read." "0,1" line.long 0xC "EC_AHB_ADD,This register holds a location in the EC's own address space that is to be used as the SRAM buffer for an EC Flash access." hexmask.long 0xC 2.--31. 1. "BUF_ADDR,This field holds bits [31:2] of the SRAM buffer address. Bits[1:0] of the address are fixed at 00." bitfld.long 0xC 0. "ADDR_INC,This bit controls whether the saf bridge increases the address in saf2_ahb_address." "0,1" line.long 0x10 "EC_DONE_STATUS,This register holds the DONE status bit." bitfld.long 0x10 9. "RPMC_OP2LEN,This bit indicates that a lenght greater that 49 is set for RPMC OP2 command. This is R/WC." "0,1" bitfld.long 0x10 8. "BAD_REQUEST,This bit indicates that an invalid Request code has been specified in the Portal Command Register at the time the START bit was set to trigger it. This is R/WC." "0,1" bitfld.long 0x10 7. "START_OVERFLOW,This bit indicates that an access was already in progress when a new access was requested by writing '1' to the START bit. This is R/WC." "0,1" bitfld.long 0x10 6. "ERASE_SIZ_ERR,This bit indicates that an invalid Erase Block Size has been specified in an Erase request. This is R/WC." "0,1" bitfld.long 0x10 5. "BOUNDARY_4K,This bit indicates that a Read request from the EC has been rejected because it has attempted to cross a 4K Flash address boundary. This bit is cleared by writing '1' to its position. This is R/WC." "0,1" newline bitfld.long 0x10 4. "ACCESS_VIOLATION,This bit indicates that a request from the EC has been rejected because it violates the Protection Register settings. This bit is cleared by writing '1' to its position. This is R/WC." "0,1" bitfld.long 0x10 3. "OUTOFRNG,This bit indicates that a request has been rejected because it is beyond the physical limits of the attached Flash devices. This bit is cleared by writing '1' to its position. This is R/WC." "0,1" bitfld.long 0x10 2. "TIMEOUT,This bit indicates that an Erase or Write request from the EC has failed because the Flash has timed out. This is R/WC." "0,1" bitfld.long 0x10 1. "SAF2_AK_NKN,This bit will always return 1 for f/w. This field is auto cleared by hardware. This is R/WC." "0,1" bitfld.long 0x10 0. "SAF2_RDY_NXT,When this bit is set the f/w initiated transaction is complete. This field is auto cleared by hardware. This is R/WC." "0,1" line.long 0x14 "EC_EN,This register contains the one bit DONE_EN in bit position[0]. This bit enables the DONE bit in the status register to trigger an interrupt." bitfld.long 0x14 9. "RPMC_OP2LEN_EN,This controls whether an interrupt is fired when RPMC OP2 Lenght is asserted." "0,1" bitfld.long 0x14 8. "BAD_REQUEST_EN,This controls whether an interrupt is fired when Bad Request is asserted." "0,1" bitfld.long 0x14 7. "START_OVERFLOW_EN,This controls whether an interrupt is fired when Start Overflow is asserted." "0,1" bitfld.long 0x14 6. "ERASE_SIZ_ERR_EN,This controls whether an interrupt is fired when Erase Size Error is asserted." "0,1" bitfld.long 0x14 5. "BOUNDARY_4K_EN,This controls whether an interrupt is fired when 4K Boundary is asserted." "0,1" newline bitfld.long 0x14 4. "ACCESS_VIOLATION_EN,This controls whether an interrupt is fired when Access Violation is asserted." "0,1" bitfld.long 0x14 3. "OUTOFRNG_EN,This controls whether an interrupt is fired when Out Of Range is asserted." "0,1" bitfld.long 0x14 2. "TIMEOUT_EN,This controls whether an interrupt is fired when Timeout is asserted." "0,1" bitfld.long 0x14 0. "RDY_NXT_EN,This bit controls whether an interrupt is fired when Ready_Next is asserted." "0,1" tree.end tree "SAFBC_EC" base ad:0x40008000 group.long 0x18++0x2F line.long 0x0 "ECP_CMD,This register defines the command type and length of transfers requested by EC firmware" hexmask.long.byte 0x0 24.--31. 1. "EC_LEN,This field contains the Length field for all requests. Read or Write or RPMC OP1 or OP2: The length in bytes of the data transfer to or from the SRAM buffer. Must be in the range 1 -- 64 (01h -- 40h)." newline hexmask.long.byte 0x0 8.--15. 1. "EC_CTYPE_CMD,This field encodes the operation requested: 00h = Read 01h = Write (Page Program) 02h = Erase 03h = RPMC OP1 directed to Flash CS0# 04h = RPMC OP2 directed to.." newline hexmask.long.byte 0x0 0.--7. 1. "EC_PUT_CMD,This field must contain the value 0Ah; that is the eSPI command PUT_FLASH_NP." line.long 0x4 "ECP_FLASH_ADDR,This register hold the Flash Space address to be accessed by the current command from EC firmware." hexmask.long 0x4 0.--31. 1. "ADDR,FLASH_ADDR: This field holds the Flash address to be accessed." line.long 0x8 "ECP_START,This register contains the Start control for a Flash access requested in the rest of the EC Portal registers. It triggers the requested transfer." bitfld.long 0x8 0. "START,This bit is written with '1' to start a new request but always appears '0' when being read. Writing '1' to this bit immediately sets the EC_BUSY bit to '1' as an acknowledgement that the request is being.." "0,1" line.long 0xC "ECP_BUF_ADDR,This register holds a location in the EC's own address space that is to be used as the SRAM buffer for an EC Flash access." hexmask.long 0xC 2.--31. 1. "ADR,This field holds bits [31:2] of the SRAM buffer address. Bits[1:0] of the address are fixed at 00." line.long 0x10 "ECP_STS,This register holds the DONE status bit." bitfld.long 0x10 9. "RPMC_OP2LEN,This bit indicates that a lenght greater that 49 is set for RPMC OP2 command. This is R/WC." "0,1" newline bitfld.long 0x10 8. "BAD_REQ,This bit indicates that an invalid Request code has been specified in the Portal Command Register at the time the START bit was set to trigger it. This bit is cleared by writing '1' to its position. This is R/WC." "0,1" newline bitfld.long 0x10 7. "STRT_OVRFLW,This bit indicates that an access was already in progress when a new access was requested by writing '1' to the START bit. Such a request is ignored except to set this bit. This bit is cleared by writing '1' to its position." "0,1" newline bitfld.long 0x10 6. "ERASE_SIZE,This bit indicates that an invalid Erase Block Size has been specified in an Erase request from the EC. This error is detected by seeing 00h in the specific Erase Size opcode field. This bit is cleared by writing '1' to its.." "0,1" newline bitfld.long 0x10 5. "BOUND_4K,This bit indicates that a Read request from the EC has been rejected because it has attempted to cross a 4K Flash address boundary. This bit is cleared by writing '1' to its position. This is R/WC." "0,1" newline bitfld.long 0x10 4. "ACCESS_VIOLAT,This bit indicates that a request from the EC has been rejected because it violates the Protection Register settings. This bit is cleared by writing '1' to its position. This is R/WC." "0,1" newline bitfld.long 0x10 3. "OUT_OF_RANGE,This bit indicates that a request from the EC has been rejected because it is beyond the physical limits of the attached Flash devices as declared in the Size Limit and Threshold Registers. This bit is cleared by writing '1'.." "0,1" newline bitfld.long 0x10 2. "TIMEOUT,This bit indicates that an Erase or Write or RPMC OP1 request from the EC has failed because the Flash has timed out. This bit is cleared by writing '1' to its position. This is R/WC." "0,1" newline bitfld.long 0x10 1. "DONE_TST,This bit is set to '1' by hardware during a requested access by the EC. It has no usage except for possible diagnostic purposes but should be cleared (with the rest of this register) by writing '1' before starting any new access." "0,1" newline bitfld.long 0x10 0. "DONE,This bit is set to '1' by hardware to indicate the end of a requested access by the EC. It can be enabled to trigger an interrupt when '1'. Writing a '1' clears this bit and the interrupt source. This is R/WC." "0,1" line.long 0x14 "ECP_IEN,This register contains the one bit DONE_EN in bit position[0]. This bit enables the DONE bit in the status register to trigger an interrupt." bitfld.long 0x14 9. "RPMC_OP2LEN_EN,This controls whether an interrupt is fired when RPMC OP2 Lenght is asserted." "0,1" newline bitfld.long 0x14 8. "BAD_REQ_EN,This controls whether an interrupt is fired when Bad Request is asserted." "0,1" newline bitfld.long 0x14 7. "STRT_OVRFL_EN,This controls whether an interrupt is fired when Start Overflow is asserted." "0,1" newline bitfld.long 0x14 6. "ERASE_SIZ_EN,This controls whether an interrupt is fired when Erase Size Error is asserted." "0,1" newline bitfld.long 0x14 5. "BOUND_4K_EN,This controls whether an interrupt is fired when 4K Boundary is asserted." "0,1" newline bitfld.long 0x14 4. "ACCESS_VIOLAT_EN,This controls whether an interrupt is fired when Access Violation is asserted." "0,1" newline bitfld.long 0x14 3. "OUTOFRNG_EN,This controls whether an interrupt is fired when Out Of Range is asserted." "0,1" newline bitfld.long 0x14 2. "TIMEOUT_EN,This controls whether an interrupt is fired when Timeout is asserted." "0,1" newline bitfld.long 0x14 0. "DONE_EN,This bit enables interrupts from the DONE bit in the Status register. 1 = Enabled 0 = Disabled" "0: Disabled,1: Enabled" line.long 0x18 "FLASH_SIZE_LIM,This register declares the address of the final byte of the Flash space implemented in the physically present Flash device or devices." hexmask.long 0x18 0.--31. 1. "LIMIT,This register declares the address of the final byte of the Flash space implemented in the physically present Flash device or devices." line.long 0x1C "FLASH_THR,This register declares whether there are two Flash devices. and if so. where the boundary is between the devices." hexmask.long 0x1C 0.--31. 1. "THRES,The address placed in this register is the address of the first byte of the second Flash device. If there is only one Flash device then this register must contain a value greater than the Size Limit register above." line.long 0x20 "FLASH_MISC_CFG,Bits[7:6] (PREFIX) declare the need for some Flash devices (notably Micron) to be given an explicit command to enter Continuous Mode. as opposed to requiring only Mode bits in the first Read access." bitfld.long 0x20 24. "F_RPMC_SCSS,Force RPMC Success. 1=Forces all RPMC OP1 operations to be reported as successful." "?,1: Forces all RPMC OP1 operations to be reported as.." newline bitfld.long 0x20 22. "RLD_ACTV_CNT_EC1_EN,Enables the activity counter to reload on EC1 Activity" "0,1" newline bitfld.long 0x20 21. "RLD_ACTV_CNT_EC0_EN,Enables the activity counter to reload on EC0 Activity Counter Reload" "0,1" newline bitfld.long 0x20 20. "RLD_ACTV_CNT_ESPI_EN,Enables the Activity Counter to Reload On SPI Enable" "0,1" newline bitfld.long 0x20 18. "FACTV_CNT_EN,Enables the saf block to sleep on the Activity Counter reaching zero." "0,1" newline bitfld.long 0x20 17. "FPWRDN_HVY_SLPEN,Enables the SAF block to sleep the flash on Heavy Sleep Enable" "0,1" newline bitfld.long 0x20 16. "FPWRDN_LGHT_SLPEN,Enables the SAF block to sleep the flash on Light Sleep Enable" "0,1" newline bitfld.long 0x20 13. "SAF_MODE_LOCK,0=The SAF Bridge register sets are unlocked and available R/W to EC firmware. 1=The SAF Bridge register sets Device Configuration and Device Timing including this register are locked read-only to EC firmware." "0: The SAF Bridge register sets are unlocked and..,1: The SAF Bridge register sets Device.." newline bitfld.long 0x20 12. "SAF_MODE_EN,0=SAFS Mode operation is globally disabled. 1=SAFS Mode operation is globally enabled. The Captive QMSPI Block register set and the SAF Communication register set also become inaccessible to EC firmware." "0: SAFS Mode operation is globally disabled,1: SAFS Mode operation is globally enabled" newline bitfld.long 0x20 7. "CS1_CONT_PREFIX_EN,Declares whether the Flash device on CS1# (if any) requires a prefix command to enter Continuous Mode. 0=No prefix command is required by the Flash device on CS1#. 1=A Prefix command will be issued from the CS1 fields.." "0: No prefix command is required by the Flash..,1: A Prefix command will be issued from the CS1.." newline bitfld.long 0x20 6. "CS0_CONT_PREFIX_EN,Declares whether the Flash device on CS0# requires a prefix command to enter Continuous Mode. 0=No prefix command is required by the Flash device on CS0#. 1=A Prefix command will be issued from the CS0 fields of the SAF.." "0: No prefix command is required by the Flash..,1: A Prefix command will be issued from the CS0.." newline bitfld.long 0x20 5. "CS1_4BYTE_ADDR_MODE,Declares whether the Flash device on CS1# uses a 32-bit address. Set this bit to '1' if the Flash device is 32Mbytes (256MBits) or greater. This bit does not cause the Flash device itself to be placed into 4-byte.." "0: Issue 3-byte addresses to the CS1# Flash device,1: Issue 4-byte addresses to the CS1# Flash device" newline bitfld.long 0x20 4. "CS0_4BYTE_ADDR_MODE,Declares whether the Flash device on CS0# uses a 32-bit address. Set this bit to '1' if the Flash device is 32Mbytes (256MBits) or greater. This bit does not cause the Flash device itself to be placed into 4-byte.." "0: Issue 3-byte addresses to the CS0# Flash device,1: Issue 4-byte addresses to the CS0# Flash device" newline bitfld.long 0x20 0.--1. "PREFETCH_OPT_EN,Selects optimized data prefetching from the Flash devices to the eSPI Master. This field has no effect unless the PREFETCH_EN bit is also '1' 00= Prefetched data from Flash is delivered using canonical eSPI methods." "0: Prefetched data from Flash is delivered using..,?,?,?" line.long 0x24 "ESPI_ERRINTR_STAT,These bits may be individually enabled to trigger interrupts using the corresponding Interrupt Enable register." bitfld.long 0x24 4. "ERASE_SIZE,This bit indicates that an invalid Erase Block Size has been specified in an Erase request from the Host Chipset. This bit is cleared by writing '1' to its position. This is R/WC." "0,1" newline bitfld.long 0x24 3. "BOUND_4K,This bit indicates that a Read request from the Host Chipset has been rejected because it has attempted to cross a 4K Flash address boundary. This bit is cleared by writing '1' to its position. This is R/WC." "0,1" newline bitfld.long 0x24 2. "ACCESS_VIOLAT,This bit indicates that a request from the Host Chipset has been rejected because it violates the Protection Register settings. This bit is cleared by writing '1' to its position. This is R/WC." "0,1" newline bitfld.long 0x24 1. "OUT_OF_RANGE,This bit indicates that a request from the Host Chipset has been rejected because it is beyond the physical limits of the attached Flash devices. This bit is cleared by writing '1' to its position. This is R/WC." "0,1" newline bitfld.long 0x24 0. "TIMEOUT,This bit indicates that an Erase or Write request from the Host Chipset has failed because the Flash has timed out. This bit is cleared by writing '1' to its position. This is R/WC." "0,1" line.long 0x28 "ESPI_ERR_IEN,This is the eSPI Error interrupt Enable Register." bitfld.long 0x28 5. "RPMC_OP2LEN_EN,This bit enables the RPMC OP2 Length Error status bit as an interrupt." "0,1" newline bitfld.long 0x28 4. "ERASE_SIZE_EN,This bit enables the ERASE_SIZE status bit as an interrupt." "0,1" newline bitfld.long 0x28 3. "BOUND_4K_EN,This bit enables the 4K_BOUNDARY status bit as an interrupt." "0,1" newline bitfld.long 0x28 2. "ACCESS_VIOLAT_EN,This bit enables the ACCESS_VIOLATION status bit as an interrupt." "0,1" newline bitfld.long 0x28 1. "OUT_OF_RANGE_EN,This bit enables the OUT_OF_RANGE status bit as an interrupt." "0,1" newline bitfld.long 0x28 0. "TIMEOUT_EN,This bit enables the TIMEOUT status bit as an interrupt." "0,1" line.long 0x2C "EC_BUSY,This register holds the EC_BUSY status bit. which indicates when the EC Portal is busy performing an access." bitfld.long 0x2C 0. "EC_BUSY,This Read-Only bit is set to '1' by hardware when the START bit is written with '1' to start a new request. It is cleared to '0' when request completes and its falling edge sets the DONE bit. While this bit is '1' the EC Portal.." "0,1" group.long 0x4C++0x37 line.long 0x0 "CS0_OPA,There are two Opcode A registers. one associated with each of the Flashes. If the CS1 Flash does not exist. its register can be left in its default state. The four fields in each register represent the 8-bit Flash opcodes for Write.." hexmask.long.byte 0x0 24.--31. 1. "OP_POLL1,This field contains the 8-bit Opcode for Read Status Register in the respective Flash device." newline hexmask.long.byte 0x0 16.--23. 1. "OP_RSM,This field contains the 8-bit Opcode for Resume in the respective Flash device." newline hexmask.long.byte 0x0 8.--15. 1. "OP_SUS,This field contains the 8-bit Opcode for Suspend in the respective Flash device." newline hexmask.long.byte 0x0 0.--7. 1. "OP_WE,This field contains the 8-bit Opcode for Write Enable in the respective Flash device." line.long 0x4 "CS0_OPB,There are two Opcode B registers. one associated with each of the Flashes. If the CS1 Flash does not exist. its register can be left in its default state. The OP_PROGRAM field is mandatory. and must hold the Page Program opcode for the.." hexmask.long.byte 0x4 24.--31. 1. "OP_PRG,This field contains the 8-bit Opcode for Page Program in the respective Flash device." newline hexmask.long.byte 0x4 16.--23. 1. "OP_ERASE2,This field contains the 8-bit Opcode for 64K Erase in the respective Flash device. If there are two Flash devices present and 64K Erase is not supported by both Flash devices then this field must be left as 00h in both the CS0.." newline hexmask.long.byte 0x4 8.--15. 1. "OP_ERASE1,This field contains the 8-bit Opcode for 32K Erase in the respective Flash device. If there are two Flash devices present and 32K Erase is not supported by both Flash devices then this field must be left as 00h in both the CS0.." newline hexmask.long.byte 0x4 0.--7. 1. "OP_ERASE0,This field contains the 8-bit Opcode for 4K Erase in the respective Flash device. This Erase size is mandatory." line.long 0x8 "CS0_OPC,There are two Opcode C registers. one associated with each of the Flashes. If the CS1 Flash does not exist. its register can be left in its default state. Two fields (OP) define opcodes. and two fields (MODE) represent the Mode code.." hexmask.long.byte 0x8 24.--31. 1. "OP_POLL2,This field contains the 8-bit Opcode used to confirm Suspended status in the Flash device. It is issued using a designated Timing Descriptor chain Poll which is used to read a 16-bit value. This value is evaluated using the Mask.." newline hexmask.long.byte 0x8 16.--23. 1. "MODE_CONT,This field contains the 8-bit Mode code used to place (or keep) the Flash device in Continuous Read mode. It is strongly recommended that this value be set to A5h as a universally-acceptable value among Flash devices." newline hexmask.long.byte 0x8 8.--15. 1. "MODE_NONC,This field is currently a placeholder and is not used. The recommended value for this field for future compatibility is FFh." newline hexmask.long.byte 0x8 0.--7. 1. "OP_READ,This field must contain the 8-bit Opcode for Fast Read Quad or Fast Read Dual in the respective Flash device. This code is used in entering Continuous Read mode and does not appear afterward." line.long 0xC "CS0_PFD,There are two Per-Flash Descriptors registers. one associated with each of the Flash devices." hexmask.long.byte 0xC 12.--15. 1. "SIZE_CONT,This field points to the Descriptor element within the READ_CONT chain that contains the Length field for data." newline hexmask.long.byte 0xC 8.--11. 1. "READ_CONT,This field points to the first Descriptor element of the Continuous Read chain." newline hexmask.long.byte 0xC 0.--3. 1. "ENTER_CONT,This field points to the first Descriptor element of the Enter Continuous Mode chain." line.long 0x10 "CS1_OPA,This is the CS1 Opcode A register. If the CS1 Flash does not exist. its register can be left in its default state. The four fields in each register represent the 8-bit Flash opcodes for Write Enable. Suspend. Resume and Read Status Register." hexmask.long.byte 0x10 24.--31. 1. "OP_POLL1,This field contains the 8-bit Opcode for Read Status Register in the respective Flash device." newline hexmask.long.byte 0x10 16.--23. 1. "OP_RSM,This field contains the 8-bit Opcode for Resume in the respective Flash device." newline hexmask.long.byte 0x10 8.--15. 1. "OP_SUS,This field contains the 8-bit Opcode for Suspend in the respective Flash device." newline hexmask.long.byte 0x10 0.--7. 1. "OP_WE,This field contains the 8-bit Opcode for Write Enable in the respective Flash device." line.long 0x14 "CS1_OPB,This is the CS1 Flash Opcode B register. If the CS1 Flash does not exist. its register can be left in its default state. The OP_PROGRAM field is mandatory. and must hold the Page Program opcode for the respective Flash. The Erase size of.." hexmask.long.byte 0x14 24.--31. 1. "OP_PROGRAM,This field contains the 8-bit Opcode for Page Program in the respective Flash device." newline hexmask.long.byte 0x14 16.--23. 1. "OP_ERASE2,This field contains the 8-bit Opcode for 64K Erase in the respective Flash device. If there are two Flash devices present and 64K Erase is not supported by both Flash devices then this field must be left as 00h in both the CS0.." newline hexmask.long.byte 0x14 8.--15. 1. "OP_ERASE1,This field contains the 8-bit Opcode for 32K Erase in the respective Flash device. If there are two Flash devices present and 32K Erase is not supported by both Flash devices then this field must be left as 00h in both the CS0.." newline hexmask.long.byte 0x14 0.--7. 1. "OP_ERASE0,This field contains the 8-bit Opcode for 4K Erase in the respective Flash device. This Erase size is mandatory." line.long 0x18 "CS1_OPC,This is the CS1 Flash device Opcode C register. If the CS1 Flash does not exist. its register can be left in its default state. Two fields (OP) define opcodes. and two fields (MODE) represent the Mode code values. Mode codes are provided.." hexmask.long.byte 0x18 24.--31. 1. "OP_POLL2,This field contains the 8-bit Opcode used to confirm Suspended status in the Flash device. It is issued using a designated Timing Descriptor chain Poll which is used to read a 16-bit value. This value is evaluated using the Mask.." newline hexmask.long.byte 0x18 16.--23. 1. "MODE_CONT,This field contains the 8-bit Mode code used to place (or keep) the Flash device in Continuous Read mode. It is strongly recommended that this value be set to A5h as a universally-acceptable value among Flash devices." newline hexmask.long.byte 0x18 8.--15. 1. "MODE_NONC,This field is currently a placeholder and is not used. The recommended value for this field for future compatibility is FFh." newline hexmask.long.byte 0x18 0.--7. 1. "OP_READ,This field must contain the 8-bit Opcode for Fast Read Quad or Fast Read Dual in the respective Flash device. This code is used in entering Continuous Read mode and does not appear afterward." line.long 0x1C "CS1_PFD,This is the Per-Flash Descriptors register for CS1 Flash." hexmask.long.byte 0x1C 12.--15. 1. "SIZE_CONT,This field points to the Descriptor element within the READ_CONT chain that contains the Length field for data." newline hexmask.long.byte 0x1C 8.--11. 1. "READ_CONT,This field points to the first Descriptor element of the Continuous Read chain." newline hexmask.long.byte 0x1C 0.--3. 1. "ENTER_CONT,This field points to the first Descriptor element of the Enter Continuous Mode chain." line.long 0x20 "GEND,This is a single register. which accompanies the two Per-Flash Descriptors registers. and provides Descriptor pointers that are shared by both CS0 and CS1 devices uniformly. Each 4-bit field is a pointer which identifies a Timing Descriptor.." hexmask.long.byte 0x20 12.--15. 1. "POLL2,This field points to the first Descriptor element of the Poll chain used when polling for Suspended status." newline hexmask.long.byte 0x20 8.--11. 1. "POLL1,This field points to the first Descriptor element of the Poll chain used when polling for Busy status." newline hexmask.long.byte 0x20 0.--3. 1. "EXIT_CONT,This field points to the first Descriptor element of the Exit Continuous Mode chain." line.long 0x24 "PRLOCK,There is a bit in this register for each of the 17 Protection Region Register sets. Writing '1' to a bit locks the associated 4-Register set to Read-Only access. and also locks this bit itself to a Read-Only '1'." bitfld.long 0x24 16. "SAF_16,In its initial 0 state this bit allows Read and Write access to the corresponding Region Register set RR = 16: Start Limit Write and Read. When written to 1 this bit locks those four registers as read-only and also locks this.." "0,1" newline bitfld.long 0x24 15. "SAF_15,In its initial 0 state this bit allows Read and Write access to the corresponding Region Register set RR = 15: Start Limit Write and Read. When written to 1 this bit locks those four registers as read-only and also locks this.." "0,1" newline bitfld.long 0x24 14. "SAF_14,In its initial 0 state this bit allows Read and Write access to the corresponding Region Register set RR = 14: Start Limit Write and Read. When written to 1 this bit locks those four registers as read-only and also locks this.." "0,1" newline bitfld.long 0x24 13. "SAF_13,In its initial 0 state this bit allows Read and Write access to the corresponding Region Register set RR = 13: Start Limit Write and Read. When written to 1 this bit locks those four registers as read-only and also locks this.." "0,1" newline bitfld.long 0x24 12. "SAF_12,In its initial 0 state this bit allows Read and Write access to the corresponding Region Register set RR = 12: Start Limit Write and Read. When written to 1 this bit locks those four registers as read-only and also locks this.." "0,1" newline bitfld.long 0x24 11. "SAF_11,In its initial 0 state this bit allows Read and Write access to the corresponding Region Register set RR = 11: Start Limit Write and Read. When written to 1 this bit locks those four registers as read-only and also locks this.." "0,1" newline bitfld.long 0x24 10. "SAF_10,In its initial 0 state this bit allows Read and Write access to the corresponding Region Register set RR = 10: Start Limit Write and Read. When written to 1 this bit locks those four registers as read-only and also locks this.." "0,1" newline bitfld.long 0x24 9. "SAF_9,In its initial 0 state this bit allows Read and Write access to the corresponding Region Register set RR = 9: Start Limit Write and Read. When written to 1 this bit locks those four registers as read-only and also locks this.." "0,1" newline bitfld.long 0x24 8. "SAF_8,In its initial 0 state this bit allows Read and Write access to the corresponding Region Register set RR = 8: Start Limit Write and Read. When written to 1 this bit locks those four registers as read-only and also locks this.." "0,1" newline bitfld.long 0x24 7. "SAF_7,In its initial 0 state this bit allows Read and Write access to the corresponding Region Register set RR = 7: Start Limit Write and Read. When written to 1 this bit locks those four registers as read-only and also locks this.." "0,1" newline bitfld.long 0x24 6. "SAF_6,In its initial 0 state this bit allows Read and Write access to the corresponding Region Register set RR = 6: Start Limit Write and Read. When written to 1 this bit locks those four registers as read-only and also locks this.." "0,1" newline bitfld.long 0x24 5. "SAF_5,In its initial 0 state this bit allows Read and Write access to the corresponding Region Register set RR = 5: Start Limit Write and Read. When written to 1 this bit locks those four registers as read-only and also locks this.." "0,1" newline bitfld.long 0x24 4. "SAF_4,In its initial 0 state this bit allows Read and Write access to the corresponding Region Register set RR = 4: Start Limit Write and Read. When written to 1 this bit locks those four registers as read-only and also locks this.." "0,1" newline bitfld.long 0x24 3. "SAF_3,In its initial 0 state this bit allows Read and Write access to the corresponding Region Register set RR = 3: Start Limit Write and Read. When written to 1 this bit locks those four registers as read-only and also locks this.." "0,1" newline bitfld.long 0x24 2. "SAF_2,In its initial 0 state this bit allows Read and Write access to the corresponding Region Register set RR = 2: Start Limit Write and Read. When written to 1 this bit locks those four registers as read-only and also locks this.." "?,?" newline bitfld.long 0x24 1. "SAF_1,In its initial 0 state this bit allows Read and Write access to the corresponding Region Register set RR = 1: Start Limit Write and Read. When written to 1 this bit locks those four registers as read-only and also locks this.." "?,1: Start" newline bitfld.long 0x24 0. "SAF_0,In its initial 0 state this bit allows Read and Write access to the corresponding Region Register set RR = 0: Start Limit Write and Read. When written to 1 this bit locks those four registers as read-only and also locks this.." "0: Start,?" line.long 0x28 "PRDIRTY,There is a bit in this register for each of the 12 Flash Regions that can be allocated from the Region Table in the Intel Descriptor structure. Register sets 12 through 16 do not represent allocated Flash regions. and so they do not have.." bitfld.long 0x28 11. "SAF_11,Indicates whether contents of Region 11 have been changed. 0=There has been no Write or Erase performed in this region since this bit was last cleared. 1=A Write or Erase has been performed in this region since this bit was last.." "0: There has been no Write or Erase performed in..,1: A Write or Erase has been performed in this.." newline bitfld.long 0x28 10. "SAF_10,Indicates whether contents of Region 10 have been changed. 0=There has been no Write or Erase performed in this region since this bit was last cleared. 1=A Write or Erase has been performed in this region since this bit was last.." "0: There has been no Write or Erase performed in..,1: A Write or Erase has been performed in this.." newline bitfld.long 0x28 9. "SAF_9,Indicates whether contents of Region 9 have been changed. 0=There has been no Write or Erase performed in this region since this bit was last cleared. 1=A Write or Erase has been performed in this region since this bit was last.." "0: There has been no Write or Erase performed in..,1: A Write or Erase has been performed in this.." newline bitfld.long 0x28 8. "SAF_8,Indicates whether contents of Region 8 have been changed. 0=There has been no Write or Erase performed in this region since this bit was last cleared. 1=A Write or Erase has been performed in this region since this bit was last.." "0: There has been no Write or Erase performed in..,1: A Write or Erase has been performed in this.." newline bitfld.long 0x28 7. "SAF_7,Indicates whether contents of Region 7 have been changed. 0=There has been no Write or Erase performed in this region since this bit was last cleared. 1=A Write or Erase has been performed in this region since this bit was last.." "0: There has been no Write or Erase performed in..,1: A Write or Erase has been performed in this.." newline bitfld.long 0x28 6. "SAF_6,Indicates whether contents of Region 6 have been changed. 0=There has been no Write or Erase performed in this region since this bit was last cleared. 1=A Write or Erase has been performed in this region since this bit was last.." "0: There has been no Write or Erase performed in..,1: A Write or Erase has been performed in this.." newline bitfld.long 0x28 5. "SAF_5,Indicates whether contents of Region 5 have been changed. 0=There has been no Write or Erase performed in this region since this bit was last cleared. 1=A Write or Erase has been performed in this region since this bit was last.." "0: There has been no Write or Erase performed in..,1: A Write or Erase has been performed in this.." newline bitfld.long 0x28 4. "SAF_4,Indicates whether contents of Region 4 have been changed. 0=There has been no Write or Erase performed in this region since this bit was last cleared. 1=A Write or Erase has been performed in this region since this bit was last.." "0: There has been no Write or Erase performed in..,1: A Write or Erase has been performed in this.." newline bitfld.long 0x28 3. "SAF_3,Indicates whether contents of Region 3 have been changed. 0=There has been no Write or Erase performed in this region since this bit was last cleared. 1=A Write or Erase has been performed in this region since this bit was last.." "0: There has been no Write or Erase performed in..,1: A Write or Erase has been performed in this.." newline bitfld.long 0x28 2. "SAF_2,Indicates whether contents of Region 2 have been changed. 0=There has been no Write or Erase performed in this region since this bit was last cleared. 1=A Write or Erase has been performed in this region since this bit was last.." "0: There has been no Write or Erase performed in..,1: A Write or Erase has been performed in this.." newline bitfld.long 0x28 1. "SAF_1,Indicates whether contents of Region 1 have been changed. 0=There has been no Write or Erase performed in this region since this bit was last cleared. 1=A Write or Erase has been performed in this region since this bit was last.." "0: There has been no Write or Erase performed in..,1: A Write or Erase has been performed in this.." newline bitfld.long 0x28 0. "SAF_0,Indicates whether contents of Region 0 have been changed. 0=There has been no Write or Erase performed in this region since this bit was last cleared. 1=A Write or Erase has been performed in this region since this bit was last.." "0: There has been no Write or Erase performed in..,1: A Write or Erase has been performed in this.." line.long 0x2C "TAG_MAP0,The default values in this register match hard-wired assignments made in the Chipset for eSPI Tag values 0h through 7h. A default value of 7 indicates a non-existent map entry. for a Tag value which should never happen." bitfld.long 0x2C 28.--30. "STM_7,This bit contains the mapping of the 4-bit eSPI Tag value 7h to its 3-bit Protection Master number." "0,1,2,3,4,5,6,7" newline bitfld.long 0x2C 24.--26. "STM_6,This bit contains the mapping of the 4-bit eSPI Tag value 6h to its 3-bit Protection Master number." "0,1,2,3,4,5,6,7" newline bitfld.long 0x2C 20.--22. "STM_5,This bit contains the mapping of the 4-bit eSPI Tag value 5h to its 3-bit Protection Master number." "0,1,2,3,4,5,6,7" newline bitfld.long 0x2C 16.--18. "STM_4,This bit contains the mapping of the 4-bit eSPI Tag value 4h to its 3-bit Protection Master number." "0,1,2,3,4,5,6,7" newline bitfld.long 0x2C 12.--14. "STM_3,This bit contains the mapping of the 4-bit eSPI Tag value 3h to its 3-bit Protection Master number." "0,1,2,3,4,5,6,7" newline bitfld.long 0x2C 8.--10. "STM_2,This bit contains the mapping of the 4-bit eSPI Tag value 2h to its 3-bit Protection Master number." "0,1,2,3,4,5,6,7" newline bitfld.long 0x2C 4.--6. "STM_1,This bit contains the mapping of the 4-bit eSPI Tag value 1h to its 3-bit Protection Master number." "0,1,2,3,4,5,6,7" newline bitfld.long 0x2C 0.--2. "STM_0,This bit contains the mapping of the 4-bit eSPI Tag value 0h to its 3-bit Protection Master number." "0,1,2,3,4,5,6,7" line.long 0x30 "TAG_MAP1,The default values in this register match hard-wired assignments made in the Chipset for eSPI Tag values 8h through Fh. A default value of 7 indicates a non-existent map entry. for a Tag value which should never happen." bitfld.long 0x30 28.--30. "STM_F,This bit contains the mapping of the 4-bit eSPI Tag value Fh to its 3-bit Protection Master number." "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 24.--26. "STM_E,This bit contains the mapping of the 4-bit eSPI Tag value Eh to its 3-bit Protection Master number." "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 20.--22. "STM_D,This bit contains the mapping of the 4-bit eSPI Tag value Dh to its 3-bit Protection Master number." "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 16.--18. "STM_C,This bit contains the mapping of the 4-bit eSPI Tag value Ch to its 3-bit Protection Master number." "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 12.--14. "STM_B,This bit contains the mapping of the 4-bit eSPI Tag value Bh to its 3-bit Protection Master number." "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 8.--10. "STM_A,This bit contains the mapping of the 4-bit eSPI Tag value Ah to its 3-bit Protection Master number." "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 4.--6. "STM_9,This bit contains the mapping of the 4-bit eSPI Tag value 9h to its 3-bit Protection Master number." "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 0.--2. "STM_8,This bit contains the mapping of the 4-bit eSPI Tag value 8h to its 3-bit Protection Master number." "0,1,2,3,4,5,6,7" line.long 0x34 "TAG_MAP2,The default value in bits [2:0] of this register matches the hard-wired assignment made in the Chipset for accesses made by an EC. After ensuring that all three Tag Map Registers [2:0] contain valid mappings. the STM_LK bit should be set.." bitfld.long 0x34 31. "STM_LK,1 Locks all bits in the Tag Map Registers including this bit. 0 (Default) keeps all Tag Map Register fields R/W." "0,1" newline bitfld.long 0x34 0.--2. "SM_EC,This bit maps the 3-bit Protection Master number assigned to EC Firmware accesses." "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40008084 ad:0x40008094 ad:0x400080A4 ad:0x400080B4 ad:0x400080C4 ad:0x400080D4 ad:0x400080E4 ad:0x400080F4 ad:0x40008104 ad:0x40008114 ad:0x40008124 ad:0x40008134 ad:0x40008144 ad:0x40008154 ad:0x40008164 ad:0x40008174) tree "SAF_PROT[$1]" base $2 group.long ($2)++0xF line.long 0x0 "START,This is Start00 register. Unless the Start register is less than or equal to the Limit register. the associated register set [RR] is Disabled. and has no effect on permissions. The default state of these registers. in all of the register.." hexmask.long.tbyte 0x0 0.--19. 1. "SAF_PROT,This field contains the start address of this Region in units of 4K bytes." line.long 0x4 "LIMIT,This is Limit00 register. Unless the Start register is less than or equal to the Limit register. the associated register set [RR] is Disabled. and has no effect on permissions. The default state of these registers. in all of the register.." hexmask.long.tbyte 0x4 0.--19. 1. "SAF_PROT,This field contains the limit address of this Region in units of 4K bytes. The entire 4K block identified is within the Region: that is the final byte address is determined by appending FFFh to this field." line.long 0x8 "WRITE,This is Write00 register. It applies to the region defined by the associated [RR] Start and Limit registers. Bits at positions [0]--[7] grant Write/Erase permission to Permission Masters numbered 0--7 respectively." bitfld.long 0x8 7. "SAF_PROT_WR7,This bit contains the permission for Write or Erase access by Protection Master 7 to this Region. 0=Protection Master 7 may not Write or Erase in this region. 1=Protection Master 7 may Write and Erase in this region." "0: Protection Master 7 may not Write or Erase in..,1: Protection Master 7 may Write and Erase in this.." bitfld.long 0x8 6. "SAF_PROT_WR6,This bit contains the permission for Write or Erase access by Protection Master 6 to this Region. 0=Protection Master 6 may not Write or Erase in this region. 1=Protection Master 6 may Write and Erase in this region." "0: Protection Master 6 may not Write or Erase in..,1: Protection Master 6 may Write and Erase in this.." newline bitfld.long 0x8 5. "SAF_PROT_WR5,This bit contains the permission for Write or Erase access by Protection Master 5 to this Region. 0=Protection Master 5 may not Write or Erase in this region. 1=Protection Master 5 may Write and Erase in this region." "0: Protection Master 5 may not Write or Erase in..,1: Protection Master 5 may Write and Erase in this.." bitfld.long 0x8 4. "SAF_PROT_WR4,This bit contains the permission for Write or Erase access by Protection Master 4 to this Region. 0=Protection Master 4 may not Write or Erase in this region. 1=Protection Master 4 may Write and Erase in this region." "0: Protection Master 4 may not Write or Erase in..,1: Protection Master 4 may Write and Erase in this.." newline bitfld.long 0x8 3. "SAF_PROT_WR3,This bit contains the permission for Write or Erase access by Protection Master 3 to this Region. 0=Protection Master 3 may not Write or Erase in this region. 1=Protection Master 3 may Write and Erase in this region." "0: Protection Master 3 may not Write or Erase in..,1: Protection Master 3 may Write and Erase in this.." bitfld.long 0x8 2. "SAF_PROT_WR2,This bit contains the permission for Write or Erase access by Protection Master 2 to this Region. 0=Protection Master 2 may not Write or Erase in this region. 1=Protection Master 2 may Write and Erase in this region." "0: Protection Master 2 may not Write or Erase in..,1: Protection Master 2 may Write and Erase in this.." newline bitfld.long 0x8 1. "SAF_PROT_WR1,This bit contains the permission for Write or Erase access by Protection Master 1 to this Region. 0=Protection Master 1 may not Write or Erase in this region. 1=Protection Master 1 may Write and Erase in this region." "0: Protection Master 1 may not Write or Erase in..,1: Protection Master 1 may Write and Erase in this.." bitfld.long 0x8 0. "SAF_PROT_WR0,This bit contains the permission for Write or Erase access by Protection Master 0 to this Region. It is a read-only '1' placeholder because Protection Master 0 has full access to all Flash locations. 1=Protection.." "?,1: Protection Master 0 may always Write and Erase.." line.long 0xC "READ,This is Read00 register. Bits at positions [0]--[7] grant Read permission to Permission Masters numbered 0--7 respectively." bitfld.long 0xC 7. "SAF_PROT_RD7,This bit contains the permission for Read access by Protection Master 7 to this Region. 0=Protection Master 7 may not Read in this region. 1=Protection Master 7 may Read in this region." "0: Protection Master 7 may not Read in this region,1: Protection Master 7 may Read in this region" bitfld.long 0xC 6. "SAF_PROT_RD6,This bit contains the permission for Read access by Protection Master 6 to this Region. 0=Protection Master 6 may not Read in this region. 1=Protection Master 6 may Read in this region." "0: Protection Master 6 may not Read in this region,1: Protection Master 6 may Read in this region" newline bitfld.long 0xC 5. "SAF_PROT_RD5,This bit contains the permission for Read access by Protection Master 5 to this Region. 0=Protection Master 5 may not Read in this region. 1=Protection Master 5 may Read in this region." "0: Protection Master 5 may not Read in this region,1: Protection Master 5 may Read in this region" bitfld.long 0xC 4. "SAF_PROT_RD4,This bit contains the permission for Read access by Protection Master 4 to this Region. 0=Protection Master 4 may not Read in this region. 1=Protection Master 4 may Read in this region." "0: Protection Master 4 may not Read in this region,1: Protection Master 4 may Read in this region" newline bitfld.long 0xC 3. "SAF_PROT_RD3,This bit contains the permission for Read access by Protection Master 3 to this Region. 0=Protection Master 3 may not Read in this region. 1=Protection Master 3 may Read in this region." "0: Protection Master 3 may not Read in this region,1: Protection Master 3 may Read in this region" bitfld.long 0xC 2. "SAF_PROT_RD2,This bit contains the permission for Read access by Protection Master 2 to this Region. 0=Protection Master 2 may not Read in this region. 1=Protection Master 2 may Read in this region." "0: Protection Master 2 may not Read in this region,1: Protection Master 2 may Read in this region" newline bitfld.long 0xC 1. "SAF_PROT_RD1,This bit contains the permission for Read access by Protection Master 1 to this Region. 0=Protection Master 1 may not Read in this region. 1=Protection Master 1 may Read in this region." "0: Protection Master 1 may not Read in this region,1: Protection Master 1 may Read in this region" bitfld.long 0xC 0. "SAF_PROT_RD0,This bit contains the permission for Read access by Protection Master 0 to this Region. It is a read-only placeholder because Protection Master 0 has full access to all Flash locations. 1=Protection Master 0 may always Read.." "?,1: Protection Master 0 may always Read in this region" tree.end repeat.end base ad:0x40008000 tree "SAF_PROT[16]" base ad:0x40008184 group.long 0x0++0xF line.long 0x0 "START,This is Start00 register. Unless the Start register is less than or equal to the Limit register. the associated register set [RR] is Disabled. and has no effect on permissions. The default state of these registers. in all of the register.." hexmask.long.tbyte 0x0 0.--19. 1. "SAF_PROT,This field contains the start address of this Region in units of 4K bytes." line.long 0x4 "LIMIT,This is Limit00 register. Unless the Start register is less than or equal to the Limit register. the associated register set [RR] is Disabled. and has no effect on permissions. The default state of these registers. in all of the register.." hexmask.long.tbyte 0x4 0.--19. 1. "SAF_PROT,This field contains the limit address of this Region in units of 4K bytes. The entire 4K block identified is within the Region: that is the final byte address is determined by appending FFFh to this field." line.long 0x8 "WRITE,This is Write00 register. It applies to the region defined by the associated [RR] Start and Limit registers. Bits at positions [0]--[7] grant Write/Erase permission to Permission Masters numbered 0--7 respectively." bitfld.long 0x8 7. "SAF_PROT_WR7,This bit contains the permission for Write or Erase access by Protection Master 7 to this Region. 0=Protection Master 7 may not Write or Erase in this region. 1=Protection Master 7 may Write and Erase in this region." "0: Protection Master 7 may not Write or Erase in..,1: Protection Master 7 may Write and Erase in this.." bitfld.long 0x8 6. "SAF_PROT_WR6,This bit contains the permission for Write or Erase access by Protection Master 6 to this Region. 0=Protection Master 6 may not Write or Erase in this region. 1=Protection Master 6 may Write and Erase in this region." "0: Protection Master 6 may not Write or Erase in..,1: Protection Master 6 may Write and Erase in this.." newline bitfld.long 0x8 5. "SAF_PROT_WR5,This bit contains the permission for Write or Erase access by Protection Master 5 to this Region. 0=Protection Master 5 may not Write or Erase in this region. 1=Protection Master 5 may Write and Erase in this region." "0: Protection Master 5 may not Write or Erase in..,1: Protection Master 5 may Write and Erase in this.." bitfld.long 0x8 4. "SAF_PROT_WR4,This bit contains the permission for Write or Erase access by Protection Master 4 to this Region. 0=Protection Master 4 may not Write or Erase in this region. 1=Protection Master 4 may Write and Erase in this region." "0: Protection Master 4 may not Write or Erase in..,1: Protection Master 4 may Write and Erase in this.." newline bitfld.long 0x8 3. "SAF_PROT_WR3,This bit contains the permission for Write or Erase access by Protection Master 3 to this Region. 0=Protection Master 3 may not Write or Erase in this region. 1=Protection Master 3 may Write and Erase in this region." "0: Protection Master 3 may not Write or Erase in..,1: Protection Master 3 may Write and Erase in this.." bitfld.long 0x8 2. "SAF_PROT_WR2,This bit contains the permission for Write or Erase access by Protection Master 2 to this Region. 0=Protection Master 2 may not Write or Erase in this region. 1=Protection Master 2 may Write and Erase in this region." "0: Protection Master 2 may not Write or Erase in..,1: Protection Master 2 may Write and Erase in this.." newline bitfld.long 0x8 1. "SAF_PROT_WR1,This bit contains the permission for Write or Erase access by Protection Master 1 to this Region. 0=Protection Master 1 may not Write or Erase in this region. 1=Protection Master 1 may Write and Erase in this region." "0: Protection Master 1 may not Write or Erase in..,1: Protection Master 1 may Write and Erase in this.." bitfld.long 0x8 0. "SAF_PROT_WR0,This bit contains the permission for Write or Erase access by Protection Master 0 to this Region. It is a read-only '1' placeholder because Protection Master 0 has full access to all Flash locations. 1=Protection.." "?,1: Protection Master 0 may always Write and Erase.." line.long 0xC "READ,This is Read00 register. Bits at positions [0]--[7] grant Read permission to Permission Masters numbered 0--7 respectively." bitfld.long 0xC 7. "SAF_PROT_RD7,This bit contains the permission for Read access by Protection Master 7 to this Region. 0=Protection Master 7 may not Read in this region. 1=Protection Master 7 may Read in this region." "0: Protection Master 7 may not Read in this region,1: Protection Master 7 may Read in this region" bitfld.long 0xC 6. "SAF_PROT_RD6,This bit contains the permission for Read access by Protection Master 6 to this Region. 0=Protection Master 6 may not Read in this region. 1=Protection Master 6 may Read in this region." "0: Protection Master 6 may not Read in this region,1: Protection Master 6 may Read in this region" newline bitfld.long 0xC 5. "SAF_PROT_RD5,This bit contains the permission for Read access by Protection Master 5 to this Region. 0=Protection Master 5 may not Read in this region. 1=Protection Master 5 may Read in this region." "0: Protection Master 5 may not Read in this region,1: Protection Master 5 may Read in this region" bitfld.long 0xC 4. "SAF_PROT_RD4,This bit contains the permission for Read access by Protection Master 4 to this Region. 0=Protection Master 4 may not Read in this region. 1=Protection Master 4 may Read in this region." "0: Protection Master 4 may not Read in this region,1: Protection Master 4 may Read in this region" newline bitfld.long 0xC 3. "SAF_PROT_RD3,This bit contains the permission for Read access by Protection Master 3 to this Region. 0=Protection Master 3 may not Read in this region. 1=Protection Master 3 may Read in this region." "0: Protection Master 3 may not Read in this region,1: Protection Master 3 may Read in this region" bitfld.long 0xC 2. "SAF_PROT_RD2,This bit contains the permission for Read access by Protection Master 2 to this Region. 0=Protection Master 2 may not Read in this region. 1=Protection Master 2 may Read in this region." "0: Protection Master 2 may not Read in this region,1: Protection Master 2 may Read in this region" newline bitfld.long 0xC 1. "SAF_PROT_RD1,This bit contains the permission for Read access by Protection Master 1 to this Region. 0=Protection Master 1 may not Read in this region. 1=Protection Master 1 may Read in this region." "0: Protection Master 1 may not Read in this region,1: Protection Master 1 may Read in this region" bitfld.long 0xC 0. "SAF_PROT_RD0,This bit contains the permission for Read access by Protection Master 0 to this Region. It is a read-only placeholder because Protection Master 0 has full access to all Flash locations. 1=Protection Master 0 may always Read.." "?,1: Protection Master 0 may always Read in this region" tree.end base ad:0x40008000 newline group.long 0x194++0x23 newline line.long 0x0 "POLL_TMOUT,This is an error timeout value imposed on any consecutive series of Poll-1 commands to a Flash. The timeout counter starts whenever any new Poll-1 sequence starts. and stops when a Poll-1 detects Not-BUSY status from the Flash." hexmask.long.tbyte 0x0 0.--17. 1. "TOUT,This field provides a polling timeout value in units of the 32KHz clock. Recommended value is 5 seconds expressed as 28000h (163 840 decimal) in this field." line.long 0x4 "POLL_INTRVL,This register should be kept zero except for diagnostic purposes. Where needed. it can be set to provide spacing between consecutive Poll-1 operations to limit the amount of traffic." hexmask.long.word 0x4 0.--15. 1. "INTRVL,This field provides an interval in units of the EC internal clock MCLK." line.long 0x8 "SUSP_RES_INTRVL,The value placed in this register provides necessary programmable support to a Flash that is performing an Erase or a Program operation. When an Erase or Program is started or Resumed. a Suspend is held off until this time.." hexmask.long.word 0x8 0.--15. 1. "INTRVL,This field provides an interval value in units of the 32KHz RTC clock. Its value should be taken from the Flash datasheet parameter that specifies minimum time for an Erase or Program step to make progress." line.long 0xC "CONSEC_RD_TMOUT,This register is used to detect when a series of Read transfers has finished. When this time expires without any new Read request. any suspended Erase or Program operation is given the Resume command to continue." hexmask.long.tbyte 0xC 0.--19. 1. "RD_TOUT,This field provides a timeout value in units of the EC internal clock MCLK. This value is tunable for system performance but a value at or below 20us is suggested." line.long 0x10 "FC_POLL2_MASK,Upon issuing a Suspend command. a Poll-1 operation is repeated until the Flash is no longer BUSY. then a Poll-2 operation to determine whether the Flash device is in a Suspended state." hexmask.long.word 0x10 16.--31. 1. "CS1_POLL2,A '1' in this field masks out (ignores) the corresponding bit returned in Poll-2 status for the CS1 Flash." newline hexmask.long.word 0x10 0.--15. 1. "CS0_POLL2,A '1' in this field masks out (ignores) the corresponding bit returned in Poll-2 status for the CS0 Flash." line.long 0x14 "FC_SPEC_MODE,This register provides special mode control." bitfld.long 0x14 0. "DIS_SUSPEND,A '1' in this field enters DISABLE_SUSPEND mode which prevents suspending an Erase or Write in progress. In this mode Read operations will be held waiting until the Erase or Write finishes." "0,1" line.long 0x18 "SUSP_CHECK_DLY,This register provides a time delay for support of some Flash devices. It holds off the first Poll-1 check after a Suspend command has been given to the Flash." hexmask.long.tbyte 0x18 0.--19. 1. "DLY,This field provides a delay value in units of the EC internal clock MCLK. This value should be set to 20us." line.long 0x1C "FC_SPEC_MODE2,Micron requires a prefix consisting of two command frames (in separate CS# assertions) to be sent before Mode information will be recognized to enter Continuous Read mode. This technique is called (Micron XIP) in their datasheets." hexmask.long.byte 0x1C 24.--31. 1. "CS1_PRE_DAT,This field is the data sent with the CS1_PREFIX_OP command." newline hexmask.long.byte 0x1C 16.--23. 1. "CS1_PRE_OP,This field is the Prefix Opcode for Micron XIP mode on CS1. It should be set to 81h for Micron parts." newline hexmask.long.byte 0x1C 8.--15. 1. "CS0_PRE_DAT,This field is the data sent with the CS0_PREFIX_OP command." newline hexmask.long.byte 0x1C 0.--7. 1. "CS0_PRE_OP,This field is the Prefix Opcode for Micron XIP mode on CS0. It should be set to 81h for Micron parts." line.long 0x20 "DNX_PRO_BYPAS,DnX DnX Protection Bypass Register." bitfld.long 0x20 28. "DNX_LK,Lock bit for this register: 0= All Read/Write bits in this register are unlocked and writable. 1= All Read/Write bits in this register are locked to Read-Only (including this bit)." "0: All Read/Write bits in this register are..,1: All Read/Write bits in this register are locked.." group.word 0x1B8++0x1 line.word 0x0 "ACTV_CNT,Timeout Activity Counter." hexmask.word 0x0 0.--15. 1. "FT_ACTV_CNT,This is the Flash Avtivity Timeout Counter." group.byte 0x1BC++0x0 line.byte 0x0 "FLP_CTRL,SAF Low Power Control Register." bitfld.byte 0x0 3. "CS1WAKON_PROCESSOR_ACTI_EN,Enable wake SPI Flash CS1 when processor wakes." "0,1" newline bitfld.byte 0x0 2. "CS0WAKON_PROCESSOR_ACTI_EN,Enable wake SPI Flash CS0 when processor wakes." "0,1" newline bitfld.byte 0x0 1. "CS1LP_EN,CS1 Low Power Enable." "0,1" newline bitfld.byte 0x0 0. "CS0LP_EN,CS0 Low Power Enable." "0,1" group.byte 0x1C0++0x0 line.byte 0x0 "FLP_STAT,SAF Low Power Status Register." bitfld.byte 0x0 1. "CS1LP_STAT,CS1 Low Power Enable." "0,1" newline bitfld.byte 0x0 0. "CS0LP_STAT,CS0 Low Power Status." "0,1" group.long 0x1C4++0x7 line.long 0x0 "FLP_CS0_OPCD,SAF Low Power CS0 OPCODE Register." hexmask.long.byte 0x0 16.--23. 1. "CS0_RPMC_OP2,CS0 Opcode for rpmc op2." newline hexmask.long.byte 0x0 8.--15. 1. "CS0OPCD_XIT,CS0 Low Power Opcode for low power exit." newline hexmask.long.byte 0x0 0.--7. 1. "CS0OPCD_NTRY,CS0 Low Power Opcode for low power entry." line.long 0x4 "FLP_CS1_OPCD,SAF Low Power CS0 OPCODE Register." hexmask.long.byte 0x4 16.--23. 1. "CS1_RPMC_OP2,CS1 Opcode for rpmc op2." newline hexmask.long.byte 0x4 8.--15. 1. "CS1OPCD_XIT,CS1 Low Power Opcode for low power exit." newline hexmask.long.byte 0x4 0.--7. 1. "CS1OPCD_NTRY,CS1 Low Power Opcode for low power entry." group.word 0x1CC++0x1 line.word 0x0 "FPD_TOUT_PDUP,Flash Timeout Power Down Up." hexmask.word 0x0 0.--15. 1. "FPD_TOUT_CNT,This is the Flash Timeout Power Down Up." group.long 0x200++0x13 line.long 0x0 "CS0CLKDIV,Clock Divider for CS0." hexmask.long.word 0x0 16.--31. 1. "CS0RESTCLKDIV,Read clock divider for CS0." newline hexmask.long.word 0x0 0.--15. 1. "CS0RDCLKDIV,Read clock divider for CS0." line.long 0x4 "CS1CLKDIV,Clock Divider for CS1." hexmask.long.word 0x4 16.--31. 1. "CS1RESTCLKDIV,Read clock divider for CS1." newline hexmask.long.word 0x4 0.--15. 1. "CS1RDCLKDIV,Read clock divider for CS1." line.long 0x8 "ESPIRPMCOP2_RESADD,eSPI RPMC OP2 Result Address." hexmask.long 0x8 0.--31. 1. "EC0RPMCOP2_RESADD,eSPI RPMC OP2 Result Address for EC0." line.long 0xC "EC0RPMCOP2_RESADD,EC0 RPMC OP2 Result Address." hexmask.long 0xC 0.--31. 1. "EC0RPMCOP2_RESADD,eSPI RPMC OP2 Result Address for EC0." line.long 0x10 "EC1RPMCOP2_RESADD,EC1 RPMC OP2 Result Address." hexmask.long 0x10 0.--31. 1. "EC1RPMCOP2_RESADD,eSPI RPMC OP2 Result Address for EC1." tree.end tree.end tree "SAFCOMM" base ad:0x40071000 group.long 0x2B8++0x3 line.long 0x0 "SAF_MODE,This register contains one bit PREFETCH_EN that should be set to '1' during initialization. to enable Prefetch Mode operation in SAFS Mode." bitfld.long 0x0 0. "PREFETCH_EN,1= Allow Prefetching from Flash devices and use the bits CS0_PREFETCH_OPT_EN and CS1_PREFETCH_OPT_EN to select any additional optimization. 0= Do not perform Prefetches from Flash devices" "0: Do not perform Prefetches from Flash devices,1: Allow Prefetching from Flash devices" tree.end tree "SCR (System Control Registers)" base ad:0xE000E000 rgroup.long 0x4++0x3 line.long 0x0 "ICTR,Interrupt Controller Type Register" hexmask.long.byte 0x0 0.--3. 1. "INTLINESNUM" group.long 0x8++0x3 line.long 0x0 "ACTLR,Auxiliary Control Register" bitfld.long 0x0 9. "DISOOFP,Disable out-of-order FP instructions" "0,1" bitfld.long 0x0 8. "DISFPCA,Disable automatic update of CONTROL.FPCA" "0,1" newline bitfld.long 0x0 2. "DISFOLD,Disable IT folding" "0,1" bitfld.long 0x0 1. "DISDEFWBUF,Disable wruite buffer use during default memory map accesses" "0,1" newline bitfld.long 0x0 0. "DISMCYCINT,Disable interruption of LDM/STM instructions" "0,1" rgroup.long 0xD00++0x3 line.long 0x0 "CPUID,CPUID Base Register" hexmask.long.byte 0x0 24.--31. 1. "IMPLEMENTER,Implementer code 0x41=ARM" hexmask.long.byte 0x0 20.--23. 1. "VARIANT,Variant number" newline hexmask.long.byte 0x0 16.--19. 1. "CONSTANT,Constant" hexmask.long.word 0x0 4.--15. 1. "PARTNO,Process Part Number 0xC24=Cortex-M4" newline hexmask.long.byte 0x0 0.--3. 1. "REVISION,Processor revision number" group.long 0xD04++0x3 line.long 0x0 "ICSR,Interrupt Control and State Register" bitfld.long 0x0 31. "NMIPENDSET,NMI set-pending bit" "0: Write: no effect; read: NMI exception is not..,1: Write: changes NMI exception state to pending;.." bitfld.long 0x0 28. "PENDSVSET,PendSV set-pending bit" "0: Write: no effect; read: PendSV exception is not..,1: Write: changes PendSV exception state to.." newline bitfld.long 0x0 27. "PENDSVCLR,PendSV clear-pending bit" "0: No effect,1: Removes the pending state from the PendSV.." bitfld.long 0x0 26. "PENDSTSET,SysTick set-pending bit" "0: Write: no effect; read: SysTick exception is not..,1: Write: changes SysTick exception state to.." newline bitfld.long 0x0 25. "PENDSTCLR,SysTick clear-pending bit" "0: No effect,1: Removes the pending state from the SysTick.." bitfld.long 0x0 23. "ISRPREEMPT,Debug only" "0,1" newline bitfld.long 0x0 22. "ISRPENDING,Interrupt pending flag" "0,1" hexmask.long.byte 0x0 12.--17. 1. "VECTPENDING,Exception number of the highest priority pending enabled exception" newline bitfld.long 0x0 11. "RETTOBASE,No preempted active exceptions to execute" "0,1" hexmask.long.word 0x0 0.--8. 1. "VECTACTIVE,Active exception number" group.long 0xD0C++0x33 line.long 0x0 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x0 16.--31. 1. "VECTKEY,Register key" bitfld.long 0x0 15. "ENDIANNESS,Data endianness 0=little 1=big" "0: little,1: big" newline bitfld.long 0x0 8.--10. "PRIGROUP,Interrupt priority grouping" "0,1,2,3,4,5,6,7" bitfld.long 0x0 2. "SYSRESETREQ,System Reset Request" "0: No system reset request,1: Asserts a signal to the outer system that.." newline bitfld.long 0x0 1. "VECTCLRACTIVE,Must write 0" "0,1" bitfld.long 0x0 0. "VECTRESET,Must write 0" "0,1" line.long 0x4 "SCR,System Control Register" bitfld.long 0x4 4. "SEVONPEND,Send Event on Pending bit" "0: Only enabled interrupts or events can wakeup the..,1: Enabled events and all interrupts including.." bitfld.long 0x4 2. "SLEEPDEEP,Deep Sleep used as low power mode" "0: Sleep,1: Deep sleep" newline bitfld.long 0x4 1. "SLEEPONEXIT,Sleep-on-exit on handler return" "0: Do not sleep when returning to Thread mode,1: Enter sleep or deep sleep on return from an ISR" line.long 0x8 "CCR,Configuration and Control Register" bitfld.long 0x8 9. "STKALIGN,Indicates stack alignment on exception entry" "0: 4-byte aligned,1: 8-byte aligned" bitfld.long 0x8 8. "BFHFNMIGN,Ignore LDM/STM BusFault for -1/-2 priority handlers" "0,1" newline bitfld.long 0x8 4. "DIV_0_TRP,Enables divide by 0 trap" "0,1" bitfld.long 0x8 3. "UNALIGN_TRP,Enables unaligned access traps" "0: Do not trap unaligned halfword and word accesses,1: Trap unaligned halfword and word accesses" newline bitfld.long 0x8 1. "USERSETMPEND,Enables unprivileged software access to STIR register" "0,1" bitfld.long 0x8 0. "NONBASETHRDENA,Indicates how processor enters Thread mode" "0,1" line.long 0xC "SHPR1,System Handler Priority Register 1" hexmask.long.byte 0xC 16.--23. 1. "PRI_6,Priority of system handler 6 UsageFault" hexmask.long.byte 0xC 8.--15. 1. "PRI_5,Priority of system handler 5 BusFault" newline hexmask.long.byte 0xC 0.--7. 1. "PRI_4,Priority of system handler 4 MemManage" line.long 0x10 "SHPR2,System Handler Priority Register 2" hexmask.long.byte 0x10 24.--31. 1. "PRI_11,Priority of system handler 11 SVCall" line.long 0x14 "SHPR3,System Handler Priority Register 3" hexmask.long.byte 0x14 24.--31. 1. "PRI_15,Priority of system handler 15 SysTick exception" hexmask.long.byte 0x14 16.--23. 1. "PRI_14,Priority of system handler 14 PendSV" line.long 0x18 "SHCSR,System Handler Control and State Register" bitfld.long 0x18 18. "USGFAULTENA,UsageFault enable bit" "0,1" bitfld.long 0x18 17. "BUSFAULTENA,BusFault enable bit" "0,1" newline bitfld.long 0x18 16. "MEMFAULTENA,MemManage enable bit" "0,1" bitfld.long 0x18 15. "SVCALLPENDED,SVCall pending bit" "0,1" newline bitfld.long 0x18 14. "BUSFAULTPENDED,BusFault exception pending bit" "0,1" bitfld.long 0x18 13. "MEMFAULTPENDED,MemManage exception pending bit" "0,1" newline bitfld.long 0x18 12. "USGFAULTPENDED,UsageFault exception pending bit" "0,1" bitfld.long 0x18 11. "SYSTICKACT,SysTick exception active bit" "0,1" newline bitfld.long 0x18 10. "PENDSVACT,PendSV exception active bit" "0,1" bitfld.long 0x18 8. "MONITORACT,DebugMonitor exception active bit" "0,1" newline bitfld.long 0x18 7. "SVCALLACT,SVCall active bit" "0,1" bitfld.long 0x18 3. "USGFAULTACT,UsageFault exception active bit" "0,1" newline bitfld.long 0x18 1. "BUSFAULTACT,BusFault exception active bit" "0,1" bitfld.long 0x18 0. "MEMFAULTACT,MemManage exception active bit" "0,1" line.long 0x1C "CFSR,Configurable Fault Status Register" bitfld.long 0x1C 25. "DIVBYZERO,Divide by zero UsageFault" "0,1" bitfld.long 0x1C 24. "UNALIGNED,Unaligned access UsageFault" "0,1" newline bitfld.long 0x1C 19. "NOCP,No coprocessor UsageFault" "0,1" bitfld.long 0x1C 18. "INVPC,Invalid PC load UsageFault" "0,1" newline bitfld.long 0x1C 17. "INVSTATE,Invalid state UsageFault" "0,1" bitfld.long 0x1C 16. "UNDEFINSTR,Undefined instruction UsageFault" "0,1" newline bitfld.long 0x1C 15. "BFARVALID,BusFault Address Register valid" "0,1" bitfld.long 0x1C 13. "LSPERR,BusFault occured during FP lazy state preservation" "0,1" newline bitfld.long 0x1C 12. "STKERR,BusFault on stacking for exception entry" "0,1" bitfld.long 0x1C 11. "UNSTKERR,BusFault on unstacking for exception return" "0,1" newline bitfld.long 0x1C 10. "IMPRECISERR,Imprecise data bus error" "0,1" bitfld.long 0x1C 9. "PRECISERR,Precise data bus error" "0,1" newline bitfld.long 0x1C 8. "IBUSERR,Instruction bus error" "0,1" bitfld.long 0x1C 7. "MMARVALID,MemManage Fault Address Register valid" "0,1" newline bitfld.long 0x1C 5. "MLSPERR,MemManager Fault occured during FP lazy state preservation" "0,1" bitfld.long 0x1C 4. "MSTKERR,MemManage Fault on stacking for exception entry" "0,1" newline bitfld.long 0x1C 3. "MUNSTKERR,MemManage Fault on unstacking for exception return" "0,1" bitfld.long 0x1C 1. "DACCVIOL,Data access violation" "0,1" newline bitfld.long 0x1C 0. "IACCVIOL,Instruction access violation" "0,1" line.long 0x20 "HFSR,HardFault Status Register" bitfld.long 0x20 31. "DEBUGEVT,Debug: always write 0" "0,1" bitfld.long 0x20 30. "FORCED,Forced Hard Fault" "0,1" newline bitfld.long 0x20 1. "VECTTBL,BusFault on a Vector Table read during exception processing" "0,1" line.long 0x24 "DFSR,Debug Fault Status Register" bitfld.long 0x24 4. "EXTERNAL" "0,1" bitfld.long 0x24 3. "VCATCH" "0,1" newline bitfld.long 0x24 2. "DWTTRAP" "0,1" bitfld.long 0x24 1. "BKPT" "0,1" newline bitfld.long 0x24 0. "HALTED" "0,1" line.long 0x28 "MMFAR,MemManage Fault Address Register" hexmask.long 0x28 0.--31. 1. "ADDRESS,Address that generated the MemManage fault" line.long 0x2C "BFAR,BusFault Address Register" hexmask.long 0x2C 0.--31. 1. "ADDRESS,Address that generated the BusFault" line.long 0x30 "AFSR,Auxiliary Fault Status Register" hexmask.long 0x30 0.--31. 1. "IMPDEF,AUXFAULT input signals" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xD40)++0x3 line.long 0x0 "PFR[$1],Processor Feature Register" repeat.end rgroup.long 0xD48++0x7 line.long 0x0 "DFR,Debug Feature Register" line.long 0x4 "ADR,Auxiliary Feature Register" repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0xD50)++0x3 line.long 0x0 "MMFR[$1],Memory Model Feature Register" repeat.end repeat 5. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0xD60)++0x3 line.long 0x0 "ISAR[$1],Instruction Set Attributes Register" repeat.end group.long 0xD88++0x3 line.long 0x0 "CPACR,Coprocessor Access Control Register" bitfld.long 0x0 22.--23. "CP11,Access privileges for coprocessor 11" "0: Access denied,1: Privileged access only,?,3: Full access" bitfld.long 0x0 20.--21. "CP10,Access privileges for coprocessor 10" "0: Access denied,1: Privileged access only,?,3: Full access" tree.end tree "SMB (SMB Controller)" base ad:0x0 tree "SMB0" base ad:0x40004000 wgroup.long 0x0++0x3 line.long 0x0 "WCTRL,Control Register" bitfld.long 0x0 7. "PIN,The Pending Interrupt Not (PIN) bit serves as a software reset function. Writing the PIN bit to a logic '1' de-asserts all status bits except for the nBB bit which is not affected by the PIN bit. The PIN bit is a self-clearing bit. Writing this bit.." "0,1" bitfld.long 0x0 6. "ESO,The Enable Serial Output bit (ESO) enables and disables the SMB Controller Core serial data output (SDAT)" "0,1" newline bitfld.long 0x0 3. "ENI,Enable Interrupt bit (ENI) controls the Interrupt Interface" "0,1" bitfld.long 0x0 2. "STA,The STA and STO bits control the generation of the I2C Start condition and the transmission of the Slave Address and R/nW bit (from the Data Register) generation of repeated Start condition and generation of the Stop condition" "0,1" newline bitfld.long 0x0 1. "STO,See STA description" "0,1" bitfld.long 0x0 0. "ACK,The Acknowledge bit (ACK) must normally be asserted ('1'). This causes the controller to send an acknowledge automatically after each byte (this occurs during the 9th clock pulse). The ACK bit must not be asserted ('0') when the controller is.." "0,1" rgroup.long 0x0++0x3 line.long 0x0 "RSTS,Status Register" bitfld.long 0x0 7. "PIN,Pending Interrupt bit" "0,1" bitfld.long 0x0 6. "SAD,SMBus Address Decoded (SAD)" "0,1" newline bitfld.long 0x0 5. "STS,When in slave receiver mode STS is asserted ('1') when an externally generated STOP condition is detected. Note that STS is used only in slave receiver mode." "0,1" bitfld.long 0x0 4. "BER,When Bus Error (BER) is asserted a misplaced START or STOP condition or Bus Time-Outs have been detected." "0,1" newline bitfld.long 0x0 3. "LRB_AD0,The Last Received Bit or Address 0 (general call) bit (LRB/AD0) serves a dual function and is valid only while the PIN bit is asserted ('0'). When the AAS bit is not asserted ('0') (i.e. not addressed as a slave) the LRB/AD0.." "0,1" bitfld.long 0x0 2. "AAS,The Addressed As Slave bit (AAS) is valid only when PIN is asserted ('0'). When acting as slave AAS is set when an incoming address over the bus matches the value in the Own Address Register or if the 'general call' address (00h) has been received" "0,1" newline bitfld.long 0x0 1. "LAB,The Lost Arbitration Bit (LAB) is set when in multi-master operation arbitration is lost to another master on the bus" "0,1" bitfld.long 0x0 0. "NBB,The Bus Busy bit (NBB) is a read-only flag indicating when the bus is in use. A zero indicates that the bus is busy and access is not possible." "0,1" group.long 0x4++0x3 line.long 0x0 "OWN_ADDR,Own Address Register Note that the Data Register and Own Address fields are offset by one bit. so that programming Own Address 1 with a value of 55h will result in the value AAh being recognized as the SMB Controller Core slave address." hexmask.long.byte 0x0 8.--14. 1. "ADDR2,The Own Address 2 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." hexmask.long.byte 0x0 0.--6. 1. "ADDR1,The Own Address 1 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." group.byte 0x8++0x0 line.byte 0x0 "I2CDATA,This register holds the data that are either shifted out to or shifted in from the I2C port." repeat 3. (increment 0x0 0x1)(increment 0x0 0x1) rgroup.byte ($2+0x9)++0x0 line.byte 0x0 "RSVD1[$1],Reserved" repeat.end group.long 0xC++0xF line.long 0x0 "MCMD,SMBus Master Command Register" hexmask.long.byte 0x0 24.--31. 1. "RD_CNT,This field is a count of the number of bytes to read in from the SMBus to the SMBus Master Receive Buffer Register and must be greater than 0 in order for the Master State Machine to initiate a read phase. It is decremented by 1 for each byte read.." hexmask.long.byte 0x0 16.--23. 1. "WR_CNT,This field is a count of the number of bytes to transmit to the SMBus from the SMBus Master Transmit Buffer Register It is decremented by 1 for each byte written to the SMBus from the SMBus Master Transmit Buffer Register." newline bitfld.long 0x0 13. "RD_PEC,If this bit is 0 reading from the SMBus stops when ReadCount reaches 0. If this bit is 1 reading continues when ReadCount is 0 for one more byte." "0,1" bitfld.long 0x0 12. "READM,If this bit is 1 then the ReadCount field is replaced by the byte that is read from the SMBus when ReadCount[7:0] is 1. After ReadCount[7:0] is updated this bit is cleared to 0." "0,1" newline bitfld.long 0x0 11. "PEC_TERM,If this bit is 1 a copy of the PEC register is transmitted when WriteCount is 0. After the PEC register is read both the PEC register and this bit are cleared to 0." "0,1" bitfld.long 0x0 10. "STOP,If this bit is 1 send a Stop bit after the transaction completes." "0,1" newline bitfld.long 0x0 9. "STARTN,If this bit is 1 send a Start bit just before the last byte of the WriteCount is sent to the SMBus transmitter." "0,1" bitfld.long 0x0 8. "START0,If this bit is 1 send a Start bit on the SMBus before the first byte of the WriteCount is sent to the SMBus transmitter." "0,1" newline bitfld.long 0x0 1. "MPROCEED,When this bit is 0 the Master State Machine does not transition out of the IDLE or PAUSE states. When this bit is 1 the Master State Machine immediately transitions to the WAIT-BUSBUSY and MRUN-RECEIVE states respectively." "0,1" bitfld.long 0x0 0. "MRUN,While this bit is 1 transfer bytes over SMBus. As long as WriteCount is non-zero a byte from the Master Transmit Buffer is transmitted to the slave device and WriteCount is decremented." "0,1" line.long 0x4 "SCMD,SMBus Slave Command Register" hexmask.long.byte 0x4 16.--23. 1. "RD_CNT,This field is decremented each time a byte is copied from DATA to the SMBus Slave Receive Buffer Register." hexmask.long.byte 0x4 8.--15. 1. "WR_CNT,This field is set to the number of bytes software expects to send to the Master." newline bitfld.long 0x4 2. "PEC,If Slave_WriteCount is 0 and Slave_PEC is 1 when the Master requests data the PEC Register is copied to the DATA register. After the PEC Register is copied to the SMBus the PEC Register is cleared and Slave_PEC is set to 0." "0,1" bitfld.long 0x4 1. "SPROCEED,When this bit is 0 the Slave State Machine does not transition out of the IDLE REPEAT_START_WRITE or REPEAT_START_READ states. When this bit is 1 the Slave State Machine immediately transitions to the START_WAIT RECEIVE and TRANSMIT states .." "0,1" newline bitfld.long 0x4 0. "SRUN,Setting this bit to 1 enables the Slave State Machine to operate." "0,1" line.long 0x8 "PEC,Packet Error Check (PEC) Register" hexmask.long.byte 0x8 0.--7. 1. "PEC,The SMBus Packet Error Check (PEC) byte." line.long 0xC "RSHTM,Repeated Start Hold Time Register" hexmask.long.byte 0xC 0.--7. 1. "RSHTM,This is the value of the timing requirement tHd:Sta in the I2C specification for a repeated START bit. This is used to hold the clock until the Hold Time for the repeated Start Bit has been satisfied." rgroup.long 0x1C++0x3 line.long 0x0 "EXTND_LEN,Extended Length Register" hexmask.long.byte 0x0 0.--7. 1. "EXTND_LEN,Extended Length Register adds 8 MSB bits to the SMBUS Master/Slave Tx/Rx Length fields." group.long 0x20++0xF line.long 0x0 "COMPL,Completion Register" bitfld.long 0x0 31. "SDONE,If this bit is 1 Slave State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect.(R/WC)" "0,1" bitfld.long 0x0 30. "MDONE,If this bit is 1 Master State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect. (R/WC)" "0,1" newline bitfld.long 0x0 29. "IDLE,This bit is set when the I2C bus becomes idle (on the rising edge of nBB). (R/WC)" "0,1" bitfld.long 0x0 25. "MTR,0: Master has just finished the receive phase of a transaction. 1: Master has just finished the transmit phase of a transaction." "0: Master has just finished the receive phase of a..,1: Master has just finished the transmit phase of a.." newline bitfld.long 0x0 24. "MNAKX,If this bit is 1 the Master state machine received a NACK from the receiving Slave while the Master was transmitting data over the SMBus interface. (R/WC)" "0,1" bitfld.long 0x0 21. "REP_WR,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 0 indicating that the Master requested a Write operation." "0,1" newline bitfld.long 0x0 20. "REP_RD,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 1 indicating that the Master requested a Read operation." "0,1" bitfld.long 0x0 19. "SPROT,If this bit is 1 the WriteCount[7:0] counter in the Slave state machine either counted down to 0 before the Master sent a NACK signal or the Slave received a NACK signal before the counter reached 0." "0,1" newline bitfld.long 0x0 17. "STR,0: Slave has just finished the receive phase of a transaction. 1: Slave has just finished the transmit phase of a transaction." "0: Slave has just finished the receive phase of a..,1: Slave has just finished the transmit phase of a.." bitfld.long 0x0 16. "SNAKR,If this bit is 1 the Slave state machine sent a NACK to the transmitting Master while the Slave was receiving data from the SMBus interface." "0,1" newline bitfld.long 0x0 14. "LAB,If this bit is 1 the LAB bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" bitfld.long 0x0 13. "BER,If this bit is 1 the BER bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" newline bitfld.long 0x0 12. "CHDH,CHDH is the bus idle time-out detect bit(R/WC)" "0,1" bitfld.long 0x0 11. "CHDL,CHDL is the clock high time-out detect bit(R/WC)" "0,1" newline bitfld.long 0x0 10. "SCTO,SCTO is the Slave Cumulative Time-out bit(R/WC)" "0,1" bitfld.long 0x0 9. "MCTO,MCTO is the Master Cumulative Time-out bit. (R/WC)" "0,1" newline bitfld.long 0x0 8. "DTO,DTO is the Device Time-out bit. (R/WC)" "0,1" bitfld.long 0x0 6. "TIMERR,The Time-out Error Detected bit (TIMERR) is asserted ('1') whenever any of the enabled time-out error detect status bits (CHDH CHDL SCTO MCTO and DTO) are asserted." "0,1" newline bitfld.long 0x0 5. "BIDEN,When BIDEN is asserted ('1') Bus Idle Detect Time-Out checking is enabled. When BIDEN is not asserted ('0') Bus Idle Detect Time-Out checking is disabled." "0,1" bitfld.long 0x0 4. "SCEN,When SCEN is asserted ('1') Slave Cumulative Time-Out checking is enabled. When SCEN is not asserted ('0') Slave Cumulative Time-Out checking is disabled." "0,1" newline bitfld.long 0x0 3. "MCEN,When MCEN is asserted ('1') Master Cumulative Time-Out checking is enabled. When MCEN is not asserted ('0') Master Cumulative Time-Out checking is disabled." "0,1" bitfld.long 0x0 2. "DTEN,When DTEN is asserted ('1') Device Time-out checking is enabled. When DTEN is not asserted ('0') Device Time-out checking is disabled." "0,1" line.long 0x4 "IDLSC,Idle Scaling Register" hexmask.long.word 0x4 16.--27. 1. "FAIR_IDL_DLY,This field defines the number of ticks of the baud clock required to program the delay. The default value for this field sets the delay period to 32us which is the appropriate value for a 100 KHz bus" hexmask.long.word 0x4 0.--11. 1. "FAIR_BUS_IDL_MIN,This field defines the number of ticks of the baud clock required to satisfy the fairness protocol. The default value for this field sets the idle window to 31us which is the appropriate value for a 100 KHz bus" line.long 0x8 "CFG,Configuration Register" bitfld.long 0x8 31. "ENSI,If this bit is 1 the Slave Done interrupt is enabled. If this bit is 0 the Slave Done interrupt is disabled" "0,1" bitfld.long 0x8 30. "ENMI,If this bit is 1 the Master Done interrupt is enabled. If this bit is 0 the Master Done interrupt is disabled." "0,1" newline bitfld.long 0x8 29. "ENIDI,If this bit is 1 the Idle interrupt is enabled. If this bit is 0 the Idle interrupt is disabled." "0,1" bitfld.long 0x8 28. "EN_AAS,0: Disable the AAS 1: Enable the AAS Interrupt" "0: Disable the AAS,1: Enable the AAS Interrupt" newline bitfld.long 0x8 19. "FLUSH_MRBUF,A write of a 1 to this bit forces the SMBus Master Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 18. "FLUSH_MXBUF,A write of a 1 to this bit forces the SMBus Master Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 17. "FLUSH_SRBUF,A write of a 1 to this bit forces the SMBus Slave Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 16. "FLUSH_SXBUF,A write of a 1 to this bit forces the SMBus Slave Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 15. "CFG_PROMIS,This bit define the Mode of SM Bus Controler Mode of operation. 0= Normal Operation. 1= Promiscuous Mode Enable." "0: Normal Operation,1: Promiscuous Mode Enable" bitfld.long 0x8 14. "GC_DIS,This is the General Call Disable bit. 0: the response to the General Call address as a slave is enabled 1: the response to the General Call address as a slave is disabled." "0: the response to the General Call address as a..,1: the response to the General Call address as a.." newline bitfld.long 0x8 13. "TEST0,Must be always written with 0." "0,1" bitfld.long 0x8 12. "FAIR,If this bit is 1 the MCTP Fairness protocol is in effect." "0,1" newline bitfld.long 0x8 11. "DSA,0: Slave Address I2C Compatibility Mode (default). 1: SMBus Address Decode Mode" "0: Slave Address I2C Compatibility Mode,1: SMBus Address Decode Mode" bitfld.long 0x8 10. "EN,When ENAB (Enable) is not asserted ('0') (default) the SMB Controller Core is disabled and in the lowest power consumption state (Disabled State). The ENAB bit must be asserted ('1') for normal operation." "0,1" newline bitfld.long 0x8 9. "RST,When RESET is asserted ('1') all logic and registers except for the RESET bit itself are initialized to the power-on default state." "0,1" bitfld.long 0x8 8. "FEN,Input filtering enable. Input filtering is required by the I2C specification if external filtering is not available. 1=Input filtering is enabled; 0=Input filtering is disabled." "0: Input filtering is disabled,1: Input filtering is enabled" newline bitfld.long 0x8 7. "PECEN,When the PEC Enable bit (PECEN) is asserted ('1') Hardware PEC Support is enabled" "0,1" bitfld.long 0x8 6. "TEST,Must be always written with 0." "0,1" newline bitfld.long 0x8 5. "SLOW_CLK,When this bit is 1 the base period for the Bus Clock Register is multiplied by 4 and thus the frequency is divided by 4." "0,1" bitfld.long 0x8 4. "TCEN,When the Timing Check Enable bit (TCEN) is asserted ('1') Bus Time-Outs are enabled" "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "PORT_SEL,The PORT SEL [3:0] bits determine which one of 16 possible bus ports apply to the active 2-wire SDAT and SCLK bus pair." line.long 0xC "BUSCLK,Bus Clock Register" hexmask.long.byte 0xC 8.--15. 1. "HIGH_PER,This field defines the number of I2C Baud Clock periods that make up the high phase of the I2C/SMBus bus clock." hexmask.long.byte 0xC 0.--7. 1. "LOW_PER,This field defines the number of I2C Baud Clock periods that make up the low phase of the I2C/SMBus bus clock." rgroup.byte 0x30++0x0 line.byte 0x0 "BLKID,Block ID Register" hexmask.byte 0x0 0.--7. 1. "ID,Block ID." rgroup.byte 0x34++0x0 line.byte 0x0 "BLKREV,Revision Register" hexmask.byte 0x0 0.--7. 1. "REV,Block Revision Number" group.long 0x38++0x3 line.long 0x0 "BBCTRL,Bit-Bang Control Register" bitfld.long 0x0 6. "BBDATI,Bit-Bang Data In. The BBDATI bit always returns the state of SDAT" "0,1" bitfld.long 0x0 5. "BBCLKI,Bit-Bang Clock In. The BBCLKI bit always returns the state of SCLK." "0,1" newline bitfld.long 0x0 4. "BBDAT,Bit-Bang Data. The BBDAT bit controls the state of SDAT when BBEN = and DADIR = '1'" "0,1" bitfld.long 0x0 3. "BBCLK,Bit-Bang Clock. The BBCLK bit controls the state of SCLK when BBEN = and CLDIR = '1'" "0,1" newline bitfld.long 0x0 2. "DADIR,Bit-Bang Data Direction. The DADIR bit controls the direction of SDAT. 0 - Input. 1 - Output" "0,1" bitfld.long 0x0 1. "CLDIR,Bit-Bang Clock Direction. The CLDIR bit controls the direction of SCLK. 0 - Input 1 - Output" "0,1" newline bitfld.long 0x0 0. "BBEN,Bit-Bang Mode Enable. 0 - Bit Bang Mode Disabled. 1 - Bit Bang Mode Enabled" "0,1" rgroup.byte 0x3C++0x0 line.byte 0x0 "TEST,Test" hexmask.byte 0x0 0.--7. 1. "TEST,This register must not be written or undesirable results may occur." group.long 0x40++0x17 line.long 0x0 "DATATM,Data Timing Register" hexmask.long.byte 0x0 24.--31. 1. "FIRST_START_HOLD,This field determines the SCL hold time following SDA driven low during the first START bit in a transfer. It is the parameter THD:STA in the I2C Specification for an initial START bit. Repeated START hold time is determined by the.." hexmask.long.byte 0x0 16.--23. 1. "STOP_SETUP,The Stop Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a STOP condition." newline hexmask.long.byte 0x0 8.--15. 1. "RESTART_SETUP,The Restart Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a repeated START condition." hexmask.long.byte 0x0 0.--7. 1. "DATA_HOLD,The Data Hold [7:0] timer determines the SDAT hold time following SCLK driven low." line.long 0x4 "TMOUTSC,Time-Out Scaling Register" hexmask.long.byte 0x4 24.--31. 1. "BUS_IDLE_MIN,Bus Idle Minimum time = Bus Idle Min [7:0] x Baud_Clock_Period" hexmask.long.byte 0x4 16.--23. 1. "MAST_CUM_TIM_OUT,Master Cumulative Time-Out duration = Master Cum Time-Out [7:0] x Baud_Clock_Period x 512" newline hexmask.long.byte 0x4 8.--15. 1. "SLV_CUM_TIM_OUT,Slave Cumulative Time-Out duration = Slave Cum Time-Out [7:0] x Baud_Clock_Period x 1024" hexmask.long.byte 0x4 0.--7. 1. "CLK_HIGH_TIM_OUT,Clock High time out period = Clock High Time-Out [7:0] x Baud_Clock_Period x 2" line.long 0x8 "SLV_TXB,SMBus Slave Transmit Buffer Register" hexmask.long.byte 0x8 0.--7. 1. "STXB,SLAVE_TRANSMIT_BUFFER" line.long 0xC "SLV_RXB,SMBus Slave Receive Buffer Register" hexmask.long.byte 0xC 0.--7. 1. "SRXB,SLAVE_RECEIVE_BUFFER" line.long 0x10 "MTR_TXB,SMBus Master Transmit Buffer Register" hexmask.long.byte 0x10 0.--7. 1. "MTXB,MASTER_TRANSMIT_BUFFER" line.long 0x14 "MTR_RXB,SMBus Master Receive Buffer Register" hexmask.long.byte 0x14 0.--7. 1. "MRXB,MASTER_RECEIVE_BUFFER" group.long 0x60++0x7 line.long 0x0 "WAKE_STS,WAKE STATUS Register" bitfld.long 0x0 0. "START_BIT_DET,This bit is set to '1' when a START bit is detected while the controller is enabled. This bit is cleared to '0' when written with a '1'. Writes of '0' have no effect. (R/WC)" "0,1" line.long 0x4 "WAKE_EN,WAKE ENABLE Register" bitfld.long 0x4 0. "START_DET_INT_EN,Enable Start Bit Detection Interrupt. The Start Bit Detection Interrupt is wake-capable. 1=Start Bit Detection Interrupt enabled; 0=Start Bit Detection Interrupt disabled" "0: Start Bit Detection Interrupt disabled,1: Start Bit Detection Interrupt enabled" group.byte 0x6C++0x0 line.byte 0x0 "SLV_ADDR,This is the Slave Address Register" hexmask.byte 0x0 0.--7. 1. "SADDR,This register stores value of address + LSB direction after the 8th clock of the Address Byte." group.byte 0x70++0x0 line.byte 0x0 "PRM_STS,This is the Promiscuous Interrupt Register" bitfld.byte 0x0 0. "ADDR_INTR,This is the Promiscuous Address Status interrupt and is set on the 8th clock of the I2C Address. This bit will hold the Clock line low till this register bit is cleared. This is Write 1 to clear. R/W1C." "0,1" group.byte 0x74++0x0 line.byte 0x0 "PRM_IEN,This is the Promiscuous Interrupt Enable Register" bitfld.byte 0x0 0. "ADDR,This is the Promiscuous interrupt enable register. 1= Interrupt Enable. 0= Interrupt Disabled." "0: Interrupt Disabled,1: Interrupt Enable" group.byte 0x78++0x0 line.byte 0x0 "PRM_CTRL,This is the Promiscuous Control Register" bitfld.byte 0x0 0. "ACK_NAK,This is the Promiscuous ACK / NAK response register. 1= ACK. 0= NAK." "0: NAK,1: ACK" group.byte 0x7C++0x0 line.byte 0x0 "SHDW_DATA,This is the I2C Shadow Data Register" hexmask.byte 0x0 0.--7. 1. "SHDW_DATA,This is the I2C Shadow Data Register" tree.end tree "SMB1" base ad:0x40004400 wgroup.long 0x0++0x3 line.long 0x0 "WCTRL,Control Register" bitfld.long 0x0 7. "PIN,The Pending Interrupt Not (PIN) bit serves as a software reset function. Writing the PIN bit to a logic '1' de-asserts all status bits except for the nBB bit which is not affected by the PIN bit. The PIN bit is a self-clearing bit. Writing this bit.." "0,1" bitfld.long 0x0 6. "ESO,The Enable Serial Output bit (ESO) enables and disables the SMB Controller Core serial data output (SDAT)" "0,1" newline bitfld.long 0x0 3. "ENI,Enable Interrupt bit (ENI) controls the Interrupt Interface" "0,1" bitfld.long 0x0 2. "STA,The STA and STO bits control the generation of the I2C Start condition and the transmission of the Slave Address and R/nW bit (from the Data Register) generation of repeated Start condition and generation of the Stop condition" "0,1" newline bitfld.long 0x0 1. "STO,See STA description" "0,1" bitfld.long 0x0 0. "ACK,The Acknowledge bit (ACK) must normally be asserted ('1'). This causes the controller to send an acknowledge automatically after each byte (this occurs during the 9th clock pulse). The ACK bit must not be asserted ('0') when the controller is.." "0,1" rgroup.long 0x0++0x3 line.long 0x0 "RSTS,Status Register" bitfld.long 0x0 7. "PIN,Pending Interrupt bit" "0,1" bitfld.long 0x0 6. "SAD,SMBus Address Decoded (SAD)" "0,1" newline bitfld.long 0x0 5. "STS,When in slave receiver mode STS is asserted ('1') when an externally generated STOP condition is detected. Note that STS is used only in slave receiver mode." "0,1" bitfld.long 0x0 4. "BER,When Bus Error (BER) is asserted a misplaced START or STOP condition or Bus Time-Outs have been detected." "0,1" newline bitfld.long 0x0 3. "LRB_AD0,The Last Received Bit or Address 0 (general call) bit (LRB/AD0) serves a dual function and is valid only while the PIN bit is asserted ('0'). When the AAS bit is not asserted ('0') (i.e. not addressed as a slave) the LRB/AD0.." "0,1" bitfld.long 0x0 2. "AAS,The Addressed As Slave bit (AAS) is valid only when PIN is asserted ('0'). When acting as slave AAS is set when an incoming address over the bus matches the value in the Own Address Register or if the 'general call' address (00h) has been received" "0,1" newline bitfld.long 0x0 1. "LAB,The Lost Arbitration Bit (LAB) is set when in multi-master operation arbitration is lost to another master on the bus" "0,1" bitfld.long 0x0 0. "NBB,The Bus Busy bit (NBB) is a read-only flag indicating when the bus is in use. A zero indicates that the bus is busy and access is not possible." "0,1" group.long 0x4++0x3 line.long 0x0 "OWN_ADDR,Own Address Register Note that the Data Register and Own Address fields are offset by one bit. so that programming Own Address 1 with a value of 55h will result in the value AAh being recognized as the SMB Controller Core slave address." hexmask.long.byte 0x0 8.--14. 1. "ADDR2,The Own Address 2 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." hexmask.long.byte 0x0 0.--6. 1. "ADDR1,The Own Address 1 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." group.byte 0x8++0x0 line.byte 0x0 "I2CDATA,This register holds the data that are either shifted out to or shifted in from the I2C port." repeat 3. (increment 0x0 0x1)(increment 0x0 0x1) rgroup.byte ($2+0x9)++0x0 line.byte 0x0 "RSVD1[$1],Reserved" repeat.end group.long 0xC++0xF line.long 0x0 "MCMD,SMBus Master Command Register" hexmask.long.byte 0x0 24.--31. 1. "RD_CNT,This field is a count of the number of bytes to read in from the SMBus to the SMBus Master Receive Buffer Register and must be greater than 0 in order for the Master State Machine to initiate a read phase. It is decremented by 1 for each byte read.." hexmask.long.byte 0x0 16.--23. 1. "WR_CNT,This field is a count of the number of bytes to transmit to the SMBus from the SMBus Master Transmit Buffer Register It is decremented by 1 for each byte written to the SMBus from the SMBus Master Transmit Buffer Register." newline bitfld.long 0x0 13. "RD_PEC,If this bit is 0 reading from the SMBus stops when ReadCount reaches 0. If this bit is 1 reading continues when ReadCount is 0 for one more byte." "0,1" bitfld.long 0x0 12. "READM,If this bit is 1 then the ReadCount field is replaced by the byte that is read from the SMBus when ReadCount[7:0] is 1. After ReadCount[7:0] is updated this bit is cleared to 0." "0,1" newline bitfld.long 0x0 11. "PEC_TERM,If this bit is 1 a copy of the PEC register is transmitted when WriteCount is 0. After the PEC register is read both the PEC register and this bit are cleared to 0." "0,1" bitfld.long 0x0 10. "STOP,If this bit is 1 send a Stop bit after the transaction completes." "0,1" newline bitfld.long 0x0 9. "STARTN,If this bit is 1 send a Start bit just before the last byte of the WriteCount is sent to the SMBus transmitter." "0,1" bitfld.long 0x0 8. "START0,If this bit is 1 send a Start bit on the SMBus before the first byte of the WriteCount is sent to the SMBus transmitter." "0,1" newline bitfld.long 0x0 1. "MPROCEED,When this bit is 0 the Master State Machine does not transition out of the IDLE or PAUSE states. When this bit is 1 the Master State Machine immediately transitions to the WAIT-BUSBUSY and MRUN-RECEIVE states respectively." "0,1" bitfld.long 0x0 0. "MRUN,While this bit is 1 transfer bytes over SMBus. As long as WriteCount is non-zero a byte from the Master Transmit Buffer is transmitted to the slave device and WriteCount is decremented." "0,1" line.long 0x4 "SCMD,SMBus Slave Command Register" hexmask.long.byte 0x4 16.--23. 1. "RD_CNT,This field is decremented each time a byte is copied from DATA to the SMBus Slave Receive Buffer Register." hexmask.long.byte 0x4 8.--15. 1. "WR_CNT,This field is set to the number of bytes software expects to send to the Master." newline bitfld.long 0x4 2. "PEC,If Slave_WriteCount is 0 and Slave_PEC is 1 when the Master requests data the PEC Register is copied to the DATA register. After the PEC Register is copied to the SMBus the PEC Register is cleared and Slave_PEC is set to 0." "0,1" bitfld.long 0x4 1. "SPROCEED,When this bit is 0 the Slave State Machine does not transition out of the IDLE REPEAT_START_WRITE or REPEAT_START_READ states. When this bit is 1 the Slave State Machine immediately transitions to the START_WAIT RECEIVE and TRANSMIT states .." "0,1" newline bitfld.long 0x4 0. "SRUN,Setting this bit to 1 enables the Slave State Machine to operate." "0,1" line.long 0x8 "PEC,Packet Error Check (PEC) Register" hexmask.long.byte 0x8 0.--7. 1. "PEC,The SMBus Packet Error Check (PEC) byte." line.long 0xC "RSHTM,Repeated Start Hold Time Register" hexmask.long.byte 0xC 0.--7. 1. "RSHTM,This is the value of the timing requirement tHd:Sta in the I2C specification for a repeated START bit. This is used to hold the clock until the Hold Time for the repeated Start Bit has been satisfied." rgroup.long 0x1C++0x3 line.long 0x0 "EXTND_LEN,Extended Length Register" hexmask.long.byte 0x0 0.--7. 1. "EXTND_LEN,Extended Length Register adds 8 MSB bits to the SMBUS Master/Slave Tx/Rx Length fields." group.long 0x20++0xF line.long 0x0 "COMPL,Completion Register" bitfld.long 0x0 31. "SDONE,If this bit is 1 Slave State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect.(R/WC)" "0,1" bitfld.long 0x0 30. "MDONE,If this bit is 1 Master State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect. (R/WC)" "0,1" newline bitfld.long 0x0 29. "IDLE,This bit is set when the I2C bus becomes idle (on the rising edge of nBB). (R/WC)" "0,1" bitfld.long 0x0 25. "MTR,0: Master has just finished the receive phase of a transaction. 1: Master has just finished the transmit phase of a transaction." "0: Master has just finished the receive phase of a..,1: Master has just finished the transmit phase of a.." newline bitfld.long 0x0 24. "MNAKX,If this bit is 1 the Master state machine received a NACK from the receiving Slave while the Master was transmitting data over the SMBus interface. (R/WC)" "0,1" bitfld.long 0x0 21. "REP_WR,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 0 indicating that the Master requested a Write operation." "0,1" newline bitfld.long 0x0 20. "REP_RD,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 1 indicating that the Master requested a Read operation." "0,1" bitfld.long 0x0 19. "SPROT,If this bit is 1 the WriteCount[7:0] counter in the Slave state machine either counted down to 0 before the Master sent a NACK signal or the Slave received a NACK signal before the counter reached 0." "0,1" newline bitfld.long 0x0 17. "STR,0: Slave has just finished the receive phase of a transaction. 1: Slave has just finished the transmit phase of a transaction." "0: Slave has just finished the receive phase of a..,1: Slave has just finished the transmit phase of a.." bitfld.long 0x0 16. "SNAKR,If this bit is 1 the Slave state machine sent a NACK to the transmitting Master while the Slave was receiving data from the SMBus interface." "0,1" newline bitfld.long 0x0 14. "LAB,If this bit is 1 the LAB bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" bitfld.long 0x0 13. "BER,If this bit is 1 the BER bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" newline bitfld.long 0x0 12. "CHDH,CHDH is the bus idle time-out detect bit(R/WC)" "0,1" bitfld.long 0x0 11. "CHDL,CHDL is the clock high time-out detect bit(R/WC)" "0,1" newline bitfld.long 0x0 10. "SCTO,SCTO is the Slave Cumulative Time-out bit(R/WC)" "0,1" bitfld.long 0x0 9. "MCTO,MCTO is the Master Cumulative Time-out bit. (R/WC)" "0,1" newline bitfld.long 0x0 8. "DTO,DTO is the Device Time-out bit. (R/WC)" "0,1" bitfld.long 0x0 6. "TIMERR,The Time-out Error Detected bit (TIMERR) is asserted ('1') whenever any of the enabled time-out error detect status bits (CHDH CHDL SCTO MCTO and DTO) are asserted." "0,1" newline bitfld.long 0x0 5. "BIDEN,When BIDEN is asserted ('1') Bus Idle Detect Time-Out checking is enabled. When BIDEN is not asserted ('0') Bus Idle Detect Time-Out checking is disabled." "0,1" bitfld.long 0x0 4. "SCEN,When SCEN is asserted ('1') Slave Cumulative Time-Out checking is enabled. When SCEN is not asserted ('0') Slave Cumulative Time-Out checking is disabled." "0,1" newline bitfld.long 0x0 3. "MCEN,When MCEN is asserted ('1') Master Cumulative Time-Out checking is enabled. When MCEN is not asserted ('0') Master Cumulative Time-Out checking is disabled." "0,1" bitfld.long 0x0 2. "DTEN,When DTEN is asserted ('1') Device Time-out checking is enabled. When DTEN is not asserted ('0') Device Time-out checking is disabled." "0,1" line.long 0x4 "IDLSC,Idle Scaling Register" hexmask.long.word 0x4 16.--27. 1. "FAIR_IDL_DLY,This field defines the number of ticks of the baud clock required to program the delay. The default value for this field sets the delay period to 32us which is the appropriate value for a 100 KHz bus" hexmask.long.word 0x4 0.--11. 1. "FAIR_BUS_IDL_MIN,This field defines the number of ticks of the baud clock required to satisfy the fairness protocol. The default value for this field sets the idle window to 31us which is the appropriate value for a 100 KHz bus" line.long 0x8 "CFG,Configuration Register" bitfld.long 0x8 31. "ENSI,If this bit is 1 the Slave Done interrupt is enabled. If this bit is 0 the Slave Done interrupt is disabled" "0,1" bitfld.long 0x8 30. "ENMI,If this bit is 1 the Master Done interrupt is enabled. If this bit is 0 the Master Done interrupt is disabled." "0,1" newline bitfld.long 0x8 29. "ENIDI,If this bit is 1 the Idle interrupt is enabled. If this bit is 0 the Idle interrupt is disabled." "0,1" bitfld.long 0x8 28. "EN_AAS,0: Disable the AAS 1: Enable the AAS Interrupt" "0: Disable the AAS,1: Enable the AAS Interrupt" newline bitfld.long 0x8 19. "FLUSH_MRBUF,A write of a 1 to this bit forces the SMBus Master Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 18. "FLUSH_MXBUF,A write of a 1 to this bit forces the SMBus Master Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 17. "FLUSH_SRBUF,A write of a 1 to this bit forces the SMBus Slave Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 16. "FLUSH_SXBUF,A write of a 1 to this bit forces the SMBus Slave Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 15. "CFG_PROMIS,This bit define the Mode of SM Bus Controler Mode of operation. 0= Normal Operation. 1= Promiscuous Mode Enable." "0: Normal Operation,1: Promiscuous Mode Enable" bitfld.long 0x8 14. "GC_DIS,This is the General Call Disable bit. 0: the response to the General Call address as a slave is enabled 1: the response to the General Call address as a slave is disabled." "0: the response to the General Call address as a..,1: the response to the General Call address as a.." newline bitfld.long 0x8 13. "TEST0,Must be always written with 0." "0,1" bitfld.long 0x8 12. "FAIR,If this bit is 1 the MCTP Fairness protocol is in effect." "0,1" newline bitfld.long 0x8 11. "DSA,0: Slave Address I2C Compatibility Mode (default). 1: SMBus Address Decode Mode" "0: Slave Address I2C Compatibility Mode,1: SMBus Address Decode Mode" bitfld.long 0x8 10. "EN,When ENAB (Enable) is not asserted ('0') (default) the SMB Controller Core is disabled and in the lowest power consumption state (Disabled State). The ENAB bit must be asserted ('1') for normal operation." "0,1" newline bitfld.long 0x8 9. "RST,When RESET is asserted ('1') all logic and registers except for the RESET bit itself are initialized to the power-on default state." "0,1" bitfld.long 0x8 8. "FEN,Input filtering enable. Input filtering is required by the I2C specification if external filtering is not available. 1=Input filtering is enabled; 0=Input filtering is disabled." "0: Input filtering is disabled,1: Input filtering is enabled" newline bitfld.long 0x8 7. "PECEN,When the PEC Enable bit (PECEN) is asserted ('1') Hardware PEC Support is enabled" "0,1" bitfld.long 0x8 6. "TEST,Must be always written with 0." "0,1" newline bitfld.long 0x8 5. "SLOW_CLK,When this bit is 1 the base period for the Bus Clock Register is multiplied by 4 and thus the frequency is divided by 4." "0,1" bitfld.long 0x8 4. "TCEN,When the Timing Check Enable bit (TCEN) is asserted ('1') Bus Time-Outs are enabled" "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "PORT_SEL,The PORT SEL [3:0] bits determine which one of 16 possible bus ports apply to the active 2-wire SDAT and SCLK bus pair." line.long 0xC "BUSCLK,Bus Clock Register" hexmask.long.byte 0xC 8.--15. 1. "HIGH_PER,This field defines the number of I2C Baud Clock periods that make up the high phase of the I2C/SMBus bus clock." hexmask.long.byte 0xC 0.--7. 1. "LOW_PER,This field defines the number of I2C Baud Clock periods that make up the low phase of the I2C/SMBus bus clock." rgroup.byte 0x30++0x0 line.byte 0x0 "BLKID,Block ID Register" hexmask.byte 0x0 0.--7. 1. "ID,Block ID." rgroup.byte 0x34++0x0 line.byte 0x0 "BLKREV,Revision Register" hexmask.byte 0x0 0.--7. 1. "REV,Block Revision Number" group.long 0x38++0x3 line.long 0x0 "BBCTRL,Bit-Bang Control Register" bitfld.long 0x0 6. "BBDATI,Bit-Bang Data In. The BBDATI bit always returns the state of SDAT" "0,1" bitfld.long 0x0 5. "BBCLKI,Bit-Bang Clock In. The BBCLKI bit always returns the state of SCLK." "0,1" newline bitfld.long 0x0 4. "BBDAT,Bit-Bang Data. The BBDAT bit controls the state of SDAT when BBEN = and DADIR = '1'" "0,1" bitfld.long 0x0 3. "BBCLK,Bit-Bang Clock. The BBCLK bit controls the state of SCLK when BBEN = and CLDIR = '1'" "0,1" newline bitfld.long 0x0 2. "DADIR,Bit-Bang Data Direction. The DADIR bit controls the direction of SDAT. 0 - Input. 1 - Output" "0,1" bitfld.long 0x0 1. "CLDIR,Bit-Bang Clock Direction. The CLDIR bit controls the direction of SCLK. 0 - Input 1 - Output" "0,1" newline bitfld.long 0x0 0. "BBEN,Bit-Bang Mode Enable. 0 - Bit Bang Mode Disabled. 1 - Bit Bang Mode Enabled" "0,1" rgroup.byte 0x3C++0x0 line.byte 0x0 "TEST,Test" hexmask.byte 0x0 0.--7. 1. "TEST,This register must not be written or undesirable results may occur." group.long 0x40++0x17 line.long 0x0 "DATATM,Data Timing Register" hexmask.long.byte 0x0 24.--31. 1. "FIRST_START_HOLD,This field determines the SCL hold time following SDA driven low during the first START bit in a transfer. It is the parameter THD:STA in the I2C Specification for an initial START bit. Repeated START hold time is determined by the.." hexmask.long.byte 0x0 16.--23. 1. "STOP_SETUP,The Stop Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a STOP condition." newline hexmask.long.byte 0x0 8.--15. 1. "RESTART_SETUP,The Restart Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a repeated START condition." hexmask.long.byte 0x0 0.--7. 1. "DATA_HOLD,The Data Hold [7:0] timer determines the SDAT hold time following SCLK driven low." line.long 0x4 "TMOUTSC,Time-Out Scaling Register" hexmask.long.byte 0x4 24.--31. 1. "BUS_IDLE_MIN,Bus Idle Minimum time = Bus Idle Min [7:0] x Baud_Clock_Period" hexmask.long.byte 0x4 16.--23. 1. "MAST_CUM_TIM_OUT,Master Cumulative Time-Out duration = Master Cum Time-Out [7:0] x Baud_Clock_Period x 512" newline hexmask.long.byte 0x4 8.--15. 1. "SLV_CUM_TIM_OUT,Slave Cumulative Time-Out duration = Slave Cum Time-Out [7:0] x Baud_Clock_Period x 1024" hexmask.long.byte 0x4 0.--7. 1. "CLK_HIGH_TIM_OUT,Clock High time out period = Clock High Time-Out [7:0] x Baud_Clock_Period x 2" line.long 0x8 "SLV_TXB,SMBus Slave Transmit Buffer Register" hexmask.long.byte 0x8 0.--7. 1. "STXB,SLAVE_TRANSMIT_BUFFER" line.long 0xC "SLV_RXB,SMBus Slave Receive Buffer Register" hexmask.long.byte 0xC 0.--7. 1. "SRXB,SLAVE_RECEIVE_BUFFER" line.long 0x10 "MTR_TXB,SMBus Master Transmit Buffer Register" hexmask.long.byte 0x10 0.--7. 1. "MTXB,MASTER_TRANSMIT_BUFFER" line.long 0x14 "MTR_RXB,SMBus Master Receive Buffer Register" hexmask.long.byte 0x14 0.--7. 1. "MRXB,MASTER_RECEIVE_BUFFER" group.long 0x60++0x7 line.long 0x0 "WAKE_STS,WAKE STATUS Register" bitfld.long 0x0 0. "START_BIT_DET,This bit is set to '1' when a START bit is detected while the controller is enabled. This bit is cleared to '0' when written with a '1'. Writes of '0' have no effect. (R/WC)" "0,1" line.long 0x4 "WAKE_EN,WAKE ENABLE Register" bitfld.long 0x4 0. "START_DET_INT_EN,Enable Start Bit Detection Interrupt. The Start Bit Detection Interrupt is wake-capable. 1=Start Bit Detection Interrupt enabled; 0=Start Bit Detection Interrupt disabled" "0: Start Bit Detection Interrupt disabled,1: Start Bit Detection Interrupt enabled" group.byte 0x6C++0x0 line.byte 0x0 "SLV_ADDR,This is the Slave Address Register" hexmask.byte 0x0 0.--7. 1. "SADDR,This register stores value of address + LSB direction after the 8th clock of the Address Byte." group.byte 0x70++0x0 line.byte 0x0 "PRM_STS,This is the Promiscuous Interrupt Register" bitfld.byte 0x0 0. "ADDR_INTR,This is the Promiscuous Address Status interrupt and is set on the 8th clock of the I2C Address. This bit will hold the Clock line low till this register bit is cleared. This is Write 1 to clear. R/W1C." "0,1" group.byte 0x74++0x0 line.byte 0x0 "PRM_IEN,This is the Promiscuous Interrupt Enable Register" bitfld.byte 0x0 0. "ADDR,This is the Promiscuous interrupt enable register. 1= Interrupt Enable. 0= Interrupt Disabled." "0: Interrupt Disabled,1: Interrupt Enable" group.byte 0x78++0x0 line.byte 0x0 "PRM_CTRL,This is the Promiscuous Control Register" bitfld.byte 0x0 0. "ACK_NAK,This is the Promiscuous ACK / NAK response register. 1= ACK. 0= NAK." "0: NAK,1: ACK" group.byte 0x7C++0x0 line.byte 0x0 "SHDW_DATA,This is the I2C Shadow Data Register" hexmask.byte 0x0 0.--7. 1. "SHDW_DATA,This is the I2C Shadow Data Register" tree.end tree "SMB2" base ad:0x40004800 wgroup.long 0x0++0x3 line.long 0x0 "WCTRL,Control Register" bitfld.long 0x0 7. "PIN,The Pending Interrupt Not (PIN) bit serves as a software reset function. Writing the PIN bit to a logic '1' de-asserts all status bits except for the nBB bit which is not affected by the PIN bit. The PIN bit is a self-clearing bit. Writing this bit.." "0,1" bitfld.long 0x0 6. "ESO,The Enable Serial Output bit (ESO) enables and disables the SMB Controller Core serial data output (SDAT)" "0,1" newline bitfld.long 0x0 3. "ENI,Enable Interrupt bit (ENI) controls the Interrupt Interface" "0,1" bitfld.long 0x0 2. "STA,The STA and STO bits control the generation of the I2C Start condition and the transmission of the Slave Address and R/nW bit (from the Data Register) generation of repeated Start condition and generation of the Stop condition" "0,1" newline bitfld.long 0x0 1. "STO,See STA description" "0,1" bitfld.long 0x0 0. "ACK,The Acknowledge bit (ACK) must normally be asserted ('1'). This causes the controller to send an acknowledge automatically after each byte (this occurs during the 9th clock pulse). The ACK bit must not be asserted ('0') when the controller is.." "0,1" rgroup.long 0x0++0x3 line.long 0x0 "RSTS,Status Register" bitfld.long 0x0 7. "PIN,Pending Interrupt bit" "0,1" bitfld.long 0x0 6. "SAD,SMBus Address Decoded (SAD)" "0,1" newline bitfld.long 0x0 5. "STS,When in slave receiver mode STS is asserted ('1') when an externally generated STOP condition is detected. Note that STS is used only in slave receiver mode." "0,1" bitfld.long 0x0 4. "BER,When Bus Error (BER) is asserted a misplaced START or STOP condition or Bus Time-Outs have been detected." "0,1" newline bitfld.long 0x0 3. "LRB_AD0,The Last Received Bit or Address 0 (general call) bit (LRB/AD0) serves a dual function and is valid only while the PIN bit is asserted ('0'). When the AAS bit is not asserted ('0') (i.e. not addressed as a slave) the LRB/AD0.." "0,1" bitfld.long 0x0 2. "AAS,The Addressed As Slave bit (AAS) is valid only when PIN is asserted ('0'). When acting as slave AAS is set when an incoming address over the bus matches the value in the Own Address Register or if the 'general call' address (00h) has been received" "0,1" newline bitfld.long 0x0 1. "LAB,The Lost Arbitration Bit (LAB) is set when in multi-master operation arbitration is lost to another master on the bus" "0,1" bitfld.long 0x0 0. "NBB,The Bus Busy bit (NBB) is a read-only flag indicating when the bus is in use. A zero indicates that the bus is busy and access is not possible." "0,1" group.long 0x4++0x3 line.long 0x0 "OWN_ADDR,Own Address Register Note that the Data Register and Own Address fields are offset by one bit. so that programming Own Address 1 with a value of 55h will result in the value AAh being recognized as the SMB Controller Core slave address." hexmask.long.byte 0x0 8.--14. 1. "ADDR2,The Own Address 2 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." hexmask.long.byte 0x0 0.--6. 1. "ADDR1,The Own Address 1 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." group.byte 0x8++0x0 line.byte 0x0 "I2CDATA,This register holds the data that are either shifted out to or shifted in from the I2C port." repeat 3. (increment 0x0 0x1)(increment 0x0 0x1) rgroup.byte ($2+0x9)++0x0 line.byte 0x0 "RSVD1[$1],Reserved" repeat.end group.long 0xC++0xF line.long 0x0 "MCMD,SMBus Master Command Register" hexmask.long.byte 0x0 24.--31. 1. "RD_CNT,This field is a count of the number of bytes to read in from the SMBus to the SMBus Master Receive Buffer Register and must be greater than 0 in order for the Master State Machine to initiate a read phase. It is decremented by 1 for each byte read.." hexmask.long.byte 0x0 16.--23. 1. "WR_CNT,This field is a count of the number of bytes to transmit to the SMBus from the SMBus Master Transmit Buffer Register It is decremented by 1 for each byte written to the SMBus from the SMBus Master Transmit Buffer Register." newline bitfld.long 0x0 13. "RD_PEC,If this bit is 0 reading from the SMBus stops when ReadCount reaches 0. If this bit is 1 reading continues when ReadCount is 0 for one more byte." "0,1" bitfld.long 0x0 12. "READM,If this bit is 1 then the ReadCount field is replaced by the byte that is read from the SMBus when ReadCount[7:0] is 1. After ReadCount[7:0] is updated this bit is cleared to 0." "0,1" newline bitfld.long 0x0 11. "PEC_TERM,If this bit is 1 a copy of the PEC register is transmitted when WriteCount is 0. After the PEC register is read both the PEC register and this bit are cleared to 0." "0,1" bitfld.long 0x0 10. "STOP,If this bit is 1 send a Stop bit after the transaction completes." "0,1" newline bitfld.long 0x0 9. "STARTN,If this bit is 1 send a Start bit just before the last byte of the WriteCount is sent to the SMBus transmitter." "0,1" bitfld.long 0x0 8. "START0,If this bit is 1 send a Start bit on the SMBus before the first byte of the WriteCount is sent to the SMBus transmitter." "0,1" newline bitfld.long 0x0 1. "MPROCEED,When this bit is 0 the Master State Machine does not transition out of the IDLE or PAUSE states. When this bit is 1 the Master State Machine immediately transitions to the WAIT-BUSBUSY and MRUN-RECEIVE states respectively." "0,1" bitfld.long 0x0 0. "MRUN,While this bit is 1 transfer bytes over SMBus. As long as WriteCount is non-zero a byte from the Master Transmit Buffer is transmitted to the slave device and WriteCount is decremented." "0,1" line.long 0x4 "SCMD,SMBus Slave Command Register" hexmask.long.byte 0x4 16.--23. 1. "RD_CNT,This field is decremented each time a byte is copied from DATA to the SMBus Slave Receive Buffer Register." hexmask.long.byte 0x4 8.--15. 1. "WR_CNT,This field is set to the number of bytes software expects to send to the Master." newline bitfld.long 0x4 2. "PEC,If Slave_WriteCount is 0 and Slave_PEC is 1 when the Master requests data the PEC Register is copied to the DATA register. After the PEC Register is copied to the SMBus the PEC Register is cleared and Slave_PEC is set to 0." "0,1" bitfld.long 0x4 1. "SPROCEED,When this bit is 0 the Slave State Machine does not transition out of the IDLE REPEAT_START_WRITE or REPEAT_START_READ states. When this bit is 1 the Slave State Machine immediately transitions to the START_WAIT RECEIVE and TRANSMIT states .." "0,1" newline bitfld.long 0x4 0. "SRUN,Setting this bit to 1 enables the Slave State Machine to operate." "0,1" line.long 0x8 "PEC,Packet Error Check (PEC) Register" hexmask.long.byte 0x8 0.--7. 1. "PEC,The SMBus Packet Error Check (PEC) byte." line.long 0xC "RSHTM,Repeated Start Hold Time Register" hexmask.long.byte 0xC 0.--7. 1. "RSHTM,This is the value of the timing requirement tHd:Sta in the I2C specification for a repeated START bit. This is used to hold the clock until the Hold Time for the repeated Start Bit has been satisfied." rgroup.long 0x1C++0x3 line.long 0x0 "EXTND_LEN,Extended Length Register" hexmask.long.byte 0x0 0.--7. 1. "EXTND_LEN,Extended Length Register adds 8 MSB bits to the SMBUS Master/Slave Tx/Rx Length fields." group.long 0x20++0xF line.long 0x0 "COMPL,Completion Register" bitfld.long 0x0 31. "SDONE,If this bit is 1 Slave State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect.(R/WC)" "0,1" bitfld.long 0x0 30. "MDONE,If this bit is 1 Master State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect. (R/WC)" "0,1" newline bitfld.long 0x0 29. "IDLE,This bit is set when the I2C bus becomes idle (on the rising edge of nBB). (R/WC)" "0,1" bitfld.long 0x0 25. "MTR,0: Master has just finished the receive phase of a transaction. 1: Master has just finished the transmit phase of a transaction." "0: Master has just finished the receive phase of a..,1: Master has just finished the transmit phase of a.." newline bitfld.long 0x0 24. "MNAKX,If this bit is 1 the Master state machine received a NACK from the receiving Slave while the Master was transmitting data over the SMBus interface. (R/WC)" "0,1" bitfld.long 0x0 21. "REP_WR,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 0 indicating that the Master requested a Write operation." "0,1" newline bitfld.long 0x0 20. "REP_RD,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 1 indicating that the Master requested a Read operation." "0,1" bitfld.long 0x0 19. "SPROT,If this bit is 1 the WriteCount[7:0] counter in the Slave state machine either counted down to 0 before the Master sent a NACK signal or the Slave received a NACK signal before the counter reached 0." "0,1" newline bitfld.long 0x0 17. "STR,0: Slave has just finished the receive phase of a transaction. 1: Slave has just finished the transmit phase of a transaction." "0: Slave has just finished the receive phase of a..,1: Slave has just finished the transmit phase of a.." bitfld.long 0x0 16. "SNAKR,If this bit is 1 the Slave state machine sent a NACK to the transmitting Master while the Slave was receiving data from the SMBus interface." "0,1" newline bitfld.long 0x0 14. "LAB,If this bit is 1 the LAB bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" bitfld.long 0x0 13. "BER,If this bit is 1 the BER bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" newline bitfld.long 0x0 12. "CHDH,CHDH is the bus idle time-out detect bit(R/WC)" "0,1" bitfld.long 0x0 11. "CHDL,CHDL is the clock high time-out detect bit(R/WC)" "0,1" newline bitfld.long 0x0 10. "SCTO,SCTO is the Slave Cumulative Time-out bit(R/WC)" "0,1" bitfld.long 0x0 9. "MCTO,MCTO is the Master Cumulative Time-out bit. (R/WC)" "0,1" newline bitfld.long 0x0 8. "DTO,DTO is the Device Time-out bit. (R/WC)" "0,1" bitfld.long 0x0 6. "TIMERR,The Time-out Error Detected bit (TIMERR) is asserted ('1') whenever any of the enabled time-out error detect status bits (CHDH CHDL SCTO MCTO and DTO) are asserted." "0,1" newline bitfld.long 0x0 5. "BIDEN,When BIDEN is asserted ('1') Bus Idle Detect Time-Out checking is enabled. When BIDEN is not asserted ('0') Bus Idle Detect Time-Out checking is disabled." "0,1" bitfld.long 0x0 4. "SCEN,When SCEN is asserted ('1') Slave Cumulative Time-Out checking is enabled. When SCEN is not asserted ('0') Slave Cumulative Time-Out checking is disabled." "0,1" newline bitfld.long 0x0 3. "MCEN,When MCEN is asserted ('1') Master Cumulative Time-Out checking is enabled. When MCEN is not asserted ('0') Master Cumulative Time-Out checking is disabled." "0,1" bitfld.long 0x0 2. "DTEN,When DTEN is asserted ('1') Device Time-out checking is enabled. When DTEN is not asserted ('0') Device Time-out checking is disabled." "0,1" line.long 0x4 "IDLSC,Idle Scaling Register" hexmask.long.word 0x4 16.--27. 1. "FAIR_IDL_DLY,This field defines the number of ticks of the baud clock required to program the delay. The default value for this field sets the delay period to 32us which is the appropriate value for a 100 KHz bus" hexmask.long.word 0x4 0.--11. 1. "FAIR_BUS_IDL_MIN,This field defines the number of ticks of the baud clock required to satisfy the fairness protocol. The default value for this field sets the idle window to 31us which is the appropriate value for a 100 KHz bus" line.long 0x8 "CFG,Configuration Register" bitfld.long 0x8 31. "ENSI,If this bit is 1 the Slave Done interrupt is enabled. If this bit is 0 the Slave Done interrupt is disabled" "0,1" bitfld.long 0x8 30. "ENMI,If this bit is 1 the Master Done interrupt is enabled. If this bit is 0 the Master Done interrupt is disabled." "0,1" newline bitfld.long 0x8 29. "ENIDI,If this bit is 1 the Idle interrupt is enabled. If this bit is 0 the Idle interrupt is disabled." "0,1" bitfld.long 0x8 28. "EN_AAS,0: Disable the AAS 1: Enable the AAS Interrupt" "0: Disable the AAS,1: Enable the AAS Interrupt" newline bitfld.long 0x8 19. "FLUSH_MRBUF,A write of a 1 to this bit forces the SMBus Master Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 18. "FLUSH_MXBUF,A write of a 1 to this bit forces the SMBus Master Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 17. "FLUSH_SRBUF,A write of a 1 to this bit forces the SMBus Slave Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 16. "FLUSH_SXBUF,A write of a 1 to this bit forces the SMBus Slave Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 15. "CFG_PROMIS,This bit define the Mode of SM Bus Controler Mode of operation. 0= Normal Operation. 1= Promiscuous Mode Enable." "0: Normal Operation,1: Promiscuous Mode Enable" bitfld.long 0x8 14. "GC_DIS,This is the General Call Disable bit. 0: the response to the General Call address as a slave is enabled 1: the response to the General Call address as a slave is disabled." "0: the response to the General Call address as a..,1: the response to the General Call address as a.." newline bitfld.long 0x8 13. "TEST0,Must be always written with 0." "0,1" bitfld.long 0x8 12. "FAIR,If this bit is 1 the MCTP Fairness protocol is in effect." "0,1" newline bitfld.long 0x8 11. "DSA,0: Slave Address I2C Compatibility Mode (default). 1: SMBus Address Decode Mode" "0: Slave Address I2C Compatibility Mode,1: SMBus Address Decode Mode" bitfld.long 0x8 10. "EN,When ENAB (Enable) is not asserted ('0') (default) the SMB Controller Core is disabled and in the lowest power consumption state (Disabled State). The ENAB bit must be asserted ('1') for normal operation." "0,1" newline bitfld.long 0x8 9. "RST,When RESET is asserted ('1') all logic and registers except for the RESET bit itself are initialized to the power-on default state." "0,1" bitfld.long 0x8 8. "FEN,Input filtering enable. Input filtering is required by the I2C specification if external filtering is not available. 1=Input filtering is enabled; 0=Input filtering is disabled." "0: Input filtering is disabled,1: Input filtering is enabled" newline bitfld.long 0x8 7. "PECEN,When the PEC Enable bit (PECEN) is asserted ('1') Hardware PEC Support is enabled" "0,1" bitfld.long 0x8 6. "TEST,Must be always written with 0." "0,1" newline bitfld.long 0x8 5. "SLOW_CLK,When this bit is 1 the base period for the Bus Clock Register is multiplied by 4 and thus the frequency is divided by 4." "0,1" bitfld.long 0x8 4. "TCEN,When the Timing Check Enable bit (TCEN) is asserted ('1') Bus Time-Outs are enabled" "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "PORT_SEL,The PORT SEL [3:0] bits determine which one of 16 possible bus ports apply to the active 2-wire SDAT and SCLK bus pair." line.long 0xC "BUSCLK,Bus Clock Register" hexmask.long.byte 0xC 8.--15. 1. "HIGH_PER,This field defines the number of I2C Baud Clock periods that make up the high phase of the I2C/SMBus bus clock." hexmask.long.byte 0xC 0.--7. 1. "LOW_PER,This field defines the number of I2C Baud Clock periods that make up the low phase of the I2C/SMBus bus clock." rgroup.byte 0x30++0x0 line.byte 0x0 "BLKID,Block ID Register" hexmask.byte 0x0 0.--7. 1. "ID,Block ID." rgroup.byte 0x34++0x0 line.byte 0x0 "BLKREV,Revision Register" hexmask.byte 0x0 0.--7. 1. "REV,Block Revision Number" group.long 0x38++0x3 line.long 0x0 "BBCTRL,Bit-Bang Control Register" bitfld.long 0x0 6. "BBDATI,Bit-Bang Data In. The BBDATI bit always returns the state of SDAT" "0,1" bitfld.long 0x0 5. "BBCLKI,Bit-Bang Clock In. The BBCLKI bit always returns the state of SCLK." "0,1" newline bitfld.long 0x0 4. "BBDAT,Bit-Bang Data. The BBDAT bit controls the state of SDAT when BBEN = and DADIR = '1'" "0,1" bitfld.long 0x0 3. "BBCLK,Bit-Bang Clock. The BBCLK bit controls the state of SCLK when BBEN = and CLDIR = '1'" "0,1" newline bitfld.long 0x0 2. "DADIR,Bit-Bang Data Direction. The DADIR bit controls the direction of SDAT. 0 - Input. 1 - Output" "0,1" bitfld.long 0x0 1. "CLDIR,Bit-Bang Clock Direction. The CLDIR bit controls the direction of SCLK. 0 - Input 1 - Output" "0,1" newline bitfld.long 0x0 0. "BBEN,Bit-Bang Mode Enable. 0 - Bit Bang Mode Disabled. 1 - Bit Bang Mode Enabled" "0,1" rgroup.byte 0x3C++0x0 line.byte 0x0 "TEST,Test" hexmask.byte 0x0 0.--7. 1. "TEST,This register must not be written or undesirable results may occur." group.long 0x40++0x17 line.long 0x0 "DATATM,Data Timing Register" hexmask.long.byte 0x0 24.--31. 1. "FIRST_START_HOLD,This field determines the SCL hold time following SDA driven low during the first START bit in a transfer. It is the parameter THD:STA in the I2C Specification for an initial START bit. Repeated START hold time is determined by the.." hexmask.long.byte 0x0 16.--23. 1. "STOP_SETUP,The Stop Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a STOP condition." newline hexmask.long.byte 0x0 8.--15. 1. "RESTART_SETUP,The Restart Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a repeated START condition." hexmask.long.byte 0x0 0.--7. 1. "DATA_HOLD,The Data Hold [7:0] timer determines the SDAT hold time following SCLK driven low." line.long 0x4 "TMOUTSC,Time-Out Scaling Register" hexmask.long.byte 0x4 24.--31. 1. "BUS_IDLE_MIN,Bus Idle Minimum time = Bus Idle Min [7:0] x Baud_Clock_Period" hexmask.long.byte 0x4 16.--23. 1. "MAST_CUM_TIM_OUT,Master Cumulative Time-Out duration = Master Cum Time-Out [7:0] x Baud_Clock_Period x 512" newline hexmask.long.byte 0x4 8.--15. 1. "SLV_CUM_TIM_OUT,Slave Cumulative Time-Out duration = Slave Cum Time-Out [7:0] x Baud_Clock_Period x 1024" hexmask.long.byte 0x4 0.--7. 1. "CLK_HIGH_TIM_OUT,Clock High time out period = Clock High Time-Out [7:0] x Baud_Clock_Period x 2" line.long 0x8 "SLV_TXB,SMBus Slave Transmit Buffer Register" hexmask.long.byte 0x8 0.--7. 1. "STXB,SLAVE_TRANSMIT_BUFFER" line.long 0xC "SLV_RXB,SMBus Slave Receive Buffer Register" hexmask.long.byte 0xC 0.--7. 1. "SRXB,SLAVE_RECEIVE_BUFFER" line.long 0x10 "MTR_TXB,SMBus Master Transmit Buffer Register" hexmask.long.byte 0x10 0.--7. 1. "MTXB,MASTER_TRANSMIT_BUFFER" line.long 0x14 "MTR_RXB,SMBus Master Receive Buffer Register" hexmask.long.byte 0x14 0.--7. 1. "MRXB,MASTER_RECEIVE_BUFFER" group.long 0x60++0x7 line.long 0x0 "WAKE_STS,WAKE STATUS Register" bitfld.long 0x0 0. "START_BIT_DET,This bit is set to '1' when a START bit is detected while the controller is enabled. This bit is cleared to '0' when written with a '1'. Writes of '0' have no effect. (R/WC)" "0,1" line.long 0x4 "WAKE_EN,WAKE ENABLE Register" bitfld.long 0x4 0. "START_DET_INT_EN,Enable Start Bit Detection Interrupt. The Start Bit Detection Interrupt is wake-capable. 1=Start Bit Detection Interrupt enabled; 0=Start Bit Detection Interrupt disabled" "0: Start Bit Detection Interrupt disabled,1: Start Bit Detection Interrupt enabled" group.byte 0x6C++0x0 line.byte 0x0 "SLV_ADDR,This is the Slave Address Register" hexmask.byte 0x0 0.--7. 1. "SADDR,This register stores value of address + LSB direction after the 8th clock of the Address Byte." group.byte 0x70++0x0 line.byte 0x0 "PRM_STS,This is the Promiscuous Interrupt Register" bitfld.byte 0x0 0. "ADDR_INTR,This is the Promiscuous Address Status interrupt and is set on the 8th clock of the I2C Address. This bit will hold the Clock line low till this register bit is cleared. This is Write 1 to clear. R/W1C." "0,1" group.byte 0x74++0x0 line.byte 0x0 "PRM_IEN,This is the Promiscuous Interrupt Enable Register" bitfld.byte 0x0 0. "ADDR,This is the Promiscuous interrupt enable register. 1= Interrupt Enable. 0= Interrupt Disabled." "0: Interrupt Disabled,1: Interrupt Enable" group.byte 0x78++0x0 line.byte 0x0 "PRM_CTRL,This is the Promiscuous Control Register" bitfld.byte 0x0 0. "ACK_NAK,This is the Promiscuous ACK / NAK response register. 1= ACK. 0= NAK." "0: NAK,1: ACK" group.byte 0x7C++0x0 line.byte 0x0 "SHDW_DATA,This is the I2C Shadow Data Register" hexmask.byte 0x0 0.--7. 1. "SHDW_DATA,This is the I2C Shadow Data Register" tree.end tree "SMB3" base ad:0x40004C00 wgroup.long 0x0++0x3 line.long 0x0 "WCTRL,Control Register" bitfld.long 0x0 7. "PIN,The Pending Interrupt Not (PIN) bit serves as a software reset function. Writing the PIN bit to a logic '1' de-asserts all status bits except for the nBB bit which is not affected by the PIN bit. The PIN bit is a self-clearing bit. Writing this bit.." "0,1" bitfld.long 0x0 6. "ESO,The Enable Serial Output bit (ESO) enables and disables the SMB Controller Core serial data output (SDAT)" "0,1" newline bitfld.long 0x0 3. "ENI,Enable Interrupt bit (ENI) controls the Interrupt Interface" "0,1" bitfld.long 0x0 2. "STA,The STA and STO bits control the generation of the I2C Start condition and the transmission of the Slave Address and R/nW bit (from the Data Register) generation of repeated Start condition and generation of the Stop condition" "0,1" newline bitfld.long 0x0 1. "STO,See STA description" "0,1" bitfld.long 0x0 0. "ACK,The Acknowledge bit (ACK) must normally be asserted ('1'). This causes the controller to send an acknowledge automatically after each byte (this occurs during the 9th clock pulse). The ACK bit must not be asserted ('0') when the controller is.." "0,1" rgroup.long 0x0++0x3 line.long 0x0 "RSTS,Status Register" bitfld.long 0x0 7. "PIN,Pending Interrupt bit" "0,1" bitfld.long 0x0 6. "SAD,SMBus Address Decoded (SAD)" "0,1" newline bitfld.long 0x0 5. "STS,When in slave receiver mode STS is asserted ('1') when an externally generated STOP condition is detected. Note that STS is used only in slave receiver mode." "0,1" bitfld.long 0x0 4. "BER,When Bus Error (BER) is asserted a misplaced START or STOP condition or Bus Time-Outs have been detected." "0,1" newline bitfld.long 0x0 3. "LRB_AD0,The Last Received Bit or Address 0 (general call) bit (LRB/AD0) serves a dual function and is valid only while the PIN bit is asserted ('0'). When the AAS bit is not asserted ('0') (i.e. not addressed as a slave) the LRB/AD0.." "0,1" bitfld.long 0x0 2. "AAS,The Addressed As Slave bit (AAS) is valid only when PIN is asserted ('0'). When acting as slave AAS is set when an incoming address over the bus matches the value in the Own Address Register or if the 'general call' address (00h) has been received" "0,1" newline bitfld.long 0x0 1. "LAB,The Lost Arbitration Bit (LAB) is set when in multi-master operation arbitration is lost to another master on the bus" "0,1" bitfld.long 0x0 0. "NBB,The Bus Busy bit (NBB) is a read-only flag indicating when the bus is in use. A zero indicates that the bus is busy and access is not possible." "0,1" group.long 0x4++0x3 line.long 0x0 "OWN_ADDR,Own Address Register Note that the Data Register and Own Address fields are offset by one bit. so that programming Own Address 1 with a value of 55h will result in the value AAh being recognized as the SMB Controller Core slave address." hexmask.long.byte 0x0 8.--14. 1. "ADDR2,The Own Address 2 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." hexmask.long.byte 0x0 0.--6. 1. "ADDR1,The Own Address 1 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." group.byte 0x8++0x0 line.byte 0x0 "I2CDATA,This register holds the data that are either shifted out to or shifted in from the I2C port." repeat 3. (increment 0x0 0x1)(increment 0x0 0x1) rgroup.byte ($2+0x9)++0x0 line.byte 0x0 "RSVD1[$1],Reserved" repeat.end group.long 0xC++0xF line.long 0x0 "MCMD,SMBus Master Command Register" hexmask.long.byte 0x0 24.--31. 1. "RD_CNT,This field is a count of the number of bytes to read in from the SMBus to the SMBus Master Receive Buffer Register and must be greater than 0 in order for the Master State Machine to initiate a read phase. It is decremented by 1 for each byte read.." hexmask.long.byte 0x0 16.--23. 1. "WR_CNT,This field is a count of the number of bytes to transmit to the SMBus from the SMBus Master Transmit Buffer Register It is decremented by 1 for each byte written to the SMBus from the SMBus Master Transmit Buffer Register." newline bitfld.long 0x0 13. "RD_PEC,If this bit is 0 reading from the SMBus stops when ReadCount reaches 0. If this bit is 1 reading continues when ReadCount is 0 for one more byte." "0,1" bitfld.long 0x0 12. "READM,If this bit is 1 then the ReadCount field is replaced by the byte that is read from the SMBus when ReadCount[7:0] is 1. After ReadCount[7:0] is updated this bit is cleared to 0." "0,1" newline bitfld.long 0x0 11. "PEC_TERM,If this bit is 1 a copy of the PEC register is transmitted when WriteCount is 0. After the PEC register is read both the PEC register and this bit are cleared to 0." "0,1" bitfld.long 0x0 10. "STOP,If this bit is 1 send a Stop bit after the transaction completes." "0,1" newline bitfld.long 0x0 9. "STARTN,If this bit is 1 send a Start bit just before the last byte of the WriteCount is sent to the SMBus transmitter." "0,1" bitfld.long 0x0 8. "START0,If this bit is 1 send a Start bit on the SMBus before the first byte of the WriteCount is sent to the SMBus transmitter." "0,1" newline bitfld.long 0x0 1. "MPROCEED,When this bit is 0 the Master State Machine does not transition out of the IDLE or PAUSE states. When this bit is 1 the Master State Machine immediately transitions to the WAIT-BUSBUSY and MRUN-RECEIVE states respectively." "0,1" bitfld.long 0x0 0. "MRUN,While this bit is 1 transfer bytes over SMBus. As long as WriteCount is non-zero a byte from the Master Transmit Buffer is transmitted to the slave device and WriteCount is decremented." "0,1" line.long 0x4 "SCMD,SMBus Slave Command Register" hexmask.long.byte 0x4 16.--23. 1. "RD_CNT,This field is decremented each time a byte is copied from DATA to the SMBus Slave Receive Buffer Register." hexmask.long.byte 0x4 8.--15. 1. "WR_CNT,This field is set to the number of bytes software expects to send to the Master." newline bitfld.long 0x4 2. "PEC,If Slave_WriteCount is 0 and Slave_PEC is 1 when the Master requests data the PEC Register is copied to the DATA register. After the PEC Register is copied to the SMBus the PEC Register is cleared and Slave_PEC is set to 0." "0,1" bitfld.long 0x4 1. "SPROCEED,When this bit is 0 the Slave State Machine does not transition out of the IDLE REPEAT_START_WRITE or REPEAT_START_READ states. When this bit is 1 the Slave State Machine immediately transitions to the START_WAIT RECEIVE and TRANSMIT states .." "0,1" newline bitfld.long 0x4 0. "SRUN,Setting this bit to 1 enables the Slave State Machine to operate." "0,1" line.long 0x8 "PEC,Packet Error Check (PEC) Register" hexmask.long.byte 0x8 0.--7. 1. "PEC,The SMBus Packet Error Check (PEC) byte." line.long 0xC "RSHTM,Repeated Start Hold Time Register" hexmask.long.byte 0xC 0.--7. 1. "RSHTM,This is the value of the timing requirement tHd:Sta in the I2C specification for a repeated START bit. This is used to hold the clock until the Hold Time for the repeated Start Bit has been satisfied." rgroup.long 0x1C++0x3 line.long 0x0 "EXTND_LEN,Extended Length Register" hexmask.long.byte 0x0 0.--7. 1. "EXTND_LEN,Extended Length Register adds 8 MSB bits to the SMBUS Master/Slave Tx/Rx Length fields." group.long 0x20++0xF line.long 0x0 "COMPL,Completion Register" bitfld.long 0x0 31. "SDONE,If this bit is 1 Slave State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect.(R/WC)" "0,1" bitfld.long 0x0 30. "MDONE,If this bit is 1 Master State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect. (R/WC)" "0,1" newline bitfld.long 0x0 29. "IDLE,This bit is set when the I2C bus becomes idle (on the rising edge of nBB). (R/WC)" "0,1" bitfld.long 0x0 25. "MTR,0: Master has just finished the receive phase of a transaction. 1: Master has just finished the transmit phase of a transaction." "0: Master has just finished the receive phase of a..,1: Master has just finished the transmit phase of a.." newline bitfld.long 0x0 24. "MNAKX,If this bit is 1 the Master state machine received a NACK from the receiving Slave while the Master was transmitting data over the SMBus interface. (R/WC)" "0,1" bitfld.long 0x0 21. "REP_WR,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 0 indicating that the Master requested a Write operation." "0,1" newline bitfld.long 0x0 20. "REP_RD,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 1 indicating that the Master requested a Read operation." "0,1" bitfld.long 0x0 19. "SPROT,If this bit is 1 the WriteCount[7:0] counter in the Slave state machine either counted down to 0 before the Master sent a NACK signal or the Slave received a NACK signal before the counter reached 0." "0,1" newline bitfld.long 0x0 17. "STR,0: Slave has just finished the receive phase of a transaction. 1: Slave has just finished the transmit phase of a transaction." "0: Slave has just finished the receive phase of a..,1: Slave has just finished the transmit phase of a.." bitfld.long 0x0 16. "SNAKR,If this bit is 1 the Slave state machine sent a NACK to the transmitting Master while the Slave was receiving data from the SMBus interface." "0,1" newline bitfld.long 0x0 14. "LAB,If this bit is 1 the LAB bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" bitfld.long 0x0 13. "BER,If this bit is 1 the BER bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" newline bitfld.long 0x0 12. "CHDH,CHDH is the bus idle time-out detect bit(R/WC)" "0,1" bitfld.long 0x0 11. "CHDL,CHDL is the clock high time-out detect bit(R/WC)" "0,1" newline bitfld.long 0x0 10. "SCTO,SCTO is the Slave Cumulative Time-out bit(R/WC)" "0,1" bitfld.long 0x0 9. "MCTO,MCTO is the Master Cumulative Time-out bit. (R/WC)" "0,1" newline bitfld.long 0x0 8. "DTO,DTO is the Device Time-out bit. (R/WC)" "0,1" bitfld.long 0x0 6. "TIMERR,The Time-out Error Detected bit (TIMERR) is asserted ('1') whenever any of the enabled time-out error detect status bits (CHDH CHDL SCTO MCTO and DTO) are asserted." "0,1" newline bitfld.long 0x0 5. "BIDEN,When BIDEN is asserted ('1') Bus Idle Detect Time-Out checking is enabled. When BIDEN is not asserted ('0') Bus Idle Detect Time-Out checking is disabled." "0,1" bitfld.long 0x0 4. "SCEN,When SCEN is asserted ('1') Slave Cumulative Time-Out checking is enabled. When SCEN is not asserted ('0') Slave Cumulative Time-Out checking is disabled." "0,1" newline bitfld.long 0x0 3. "MCEN,When MCEN is asserted ('1') Master Cumulative Time-Out checking is enabled. When MCEN is not asserted ('0') Master Cumulative Time-Out checking is disabled." "0,1" bitfld.long 0x0 2. "DTEN,When DTEN is asserted ('1') Device Time-out checking is enabled. When DTEN is not asserted ('0') Device Time-out checking is disabled." "0,1" line.long 0x4 "IDLSC,Idle Scaling Register" hexmask.long.word 0x4 16.--27. 1. "FAIR_IDL_DLY,This field defines the number of ticks of the baud clock required to program the delay. The default value for this field sets the delay period to 32us which is the appropriate value for a 100 KHz bus" hexmask.long.word 0x4 0.--11. 1. "FAIR_BUS_IDL_MIN,This field defines the number of ticks of the baud clock required to satisfy the fairness protocol. The default value for this field sets the idle window to 31us which is the appropriate value for a 100 KHz bus" line.long 0x8 "CFG,Configuration Register" bitfld.long 0x8 31. "ENSI,If this bit is 1 the Slave Done interrupt is enabled. If this bit is 0 the Slave Done interrupt is disabled" "0,1" bitfld.long 0x8 30. "ENMI,If this bit is 1 the Master Done interrupt is enabled. If this bit is 0 the Master Done interrupt is disabled." "0,1" newline bitfld.long 0x8 29. "ENIDI,If this bit is 1 the Idle interrupt is enabled. If this bit is 0 the Idle interrupt is disabled." "0,1" bitfld.long 0x8 28. "EN_AAS,0: Disable the AAS 1: Enable the AAS Interrupt" "0: Disable the AAS,1: Enable the AAS Interrupt" newline bitfld.long 0x8 19. "FLUSH_MRBUF,A write of a 1 to this bit forces the SMBus Master Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 18. "FLUSH_MXBUF,A write of a 1 to this bit forces the SMBus Master Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 17. "FLUSH_SRBUF,A write of a 1 to this bit forces the SMBus Slave Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 16. "FLUSH_SXBUF,A write of a 1 to this bit forces the SMBus Slave Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 15. "CFG_PROMIS,This bit define the Mode of SM Bus Controler Mode of operation. 0= Normal Operation. 1= Promiscuous Mode Enable." "0: Normal Operation,1: Promiscuous Mode Enable" bitfld.long 0x8 14. "GC_DIS,This is the General Call Disable bit. 0: the response to the General Call address as a slave is enabled 1: the response to the General Call address as a slave is disabled." "0: the response to the General Call address as a..,1: the response to the General Call address as a.." newline bitfld.long 0x8 13. "TEST0,Must be always written with 0." "0,1" bitfld.long 0x8 12. "FAIR,If this bit is 1 the MCTP Fairness protocol is in effect." "0,1" newline bitfld.long 0x8 11. "DSA,0: Slave Address I2C Compatibility Mode (default). 1: SMBus Address Decode Mode" "0: Slave Address I2C Compatibility Mode,1: SMBus Address Decode Mode" bitfld.long 0x8 10. "EN,When ENAB (Enable) is not asserted ('0') (default) the SMB Controller Core is disabled and in the lowest power consumption state (Disabled State). The ENAB bit must be asserted ('1') for normal operation." "0,1" newline bitfld.long 0x8 9. "RST,When RESET is asserted ('1') all logic and registers except for the RESET bit itself are initialized to the power-on default state." "0,1" bitfld.long 0x8 8. "FEN,Input filtering enable. Input filtering is required by the I2C specification if external filtering is not available. 1=Input filtering is enabled; 0=Input filtering is disabled." "0: Input filtering is disabled,1: Input filtering is enabled" newline bitfld.long 0x8 7. "PECEN,When the PEC Enable bit (PECEN) is asserted ('1') Hardware PEC Support is enabled" "0,1" bitfld.long 0x8 6. "TEST,Must be always written with 0." "0,1" newline bitfld.long 0x8 5. "SLOW_CLK,When this bit is 1 the base period for the Bus Clock Register is multiplied by 4 and thus the frequency is divided by 4." "0,1" bitfld.long 0x8 4. "TCEN,When the Timing Check Enable bit (TCEN) is asserted ('1') Bus Time-Outs are enabled" "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "PORT_SEL,The PORT SEL [3:0] bits determine which one of 16 possible bus ports apply to the active 2-wire SDAT and SCLK bus pair." line.long 0xC "BUSCLK,Bus Clock Register" hexmask.long.byte 0xC 8.--15. 1. "HIGH_PER,This field defines the number of I2C Baud Clock periods that make up the high phase of the I2C/SMBus bus clock." hexmask.long.byte 0xC 0.--7. 1. "LOW_PER,This field defines the number of I2C Baud Clock periods that make up the low phase of the I2C/SMBus bus clock." rgroup.byte 0x30++0x0 line.byte 0x0 "BLKID,Block ID Register" hexmask.byte 0x0 0.--7. 1. "ID,Block ID." rgroup.byte 0x34++0x0 line.byte 0x0 "BLKREV,Revision Register" hexmask.byte 0x0 0.--7. 1. "REV,Block Revision Number" group.long 0x38++0x3 line.long 0x0 "BBCTRL,Bit-Bang Control Register" bitfld.long 0x0 6. "BBDATI,Bit-Bang Data In. The BBDATI bit always returns the state of SDAT" "0,1" bitfld.long 0x0 5. "BBCLKI,Bit-Bang Clock In. The BBCLKI bit always returns the state of SCLK." "0,1" newline bitfld.long 0x0 4. "BBDAT,Bit-Bang Data. The BBDAT bit controls the state of SDAT when BBEN = and DADIR = '1'" "0,1" bitfld.long 0x0 3. "BBCLK,Bit-Bang Clock. The BBCLK bit controls the state of SCLK when BBEN = and CLDIR = '1'" "0,1" newline bitfld.long 0x0 2. "DADIR,Bit-Bang Data Direction. The DADIR bit controls the direction of SDAT. 0 - Input. 1 - Output" "0,1" bitfld.long 0x0 1. "CLDIR,Bit-Bang Clock Direction. The CLDIR bit controls the direction of SCLK. 0 - Input 1 - Output" "0,1" newline bitfld.long 0x0 0. "BBEN,Bit-Bang Mode Enable. 0 - Bit Bang Mode Disabled. 1 - Bit Bang Mode Enabled" "0,1" rgroup.byte 0x3C++0x0 line.byte 0x0 "TEST,Test" hexmask.byte 0x0 0.--7. 1. "TEST,This register must not be written or undesirable results may occur." group.long 0x40++0x17 line.long 0x0 "DATATM,Data Timing Register" hexmask.long.byte 0x0 24.--31. 1. "FIRST_START_HOLD,This field determines the SCL hold time following SDA driven low during the first START bit in a transfer. It is the parameter THD:STA in the I2C Specification for an initial START bit. Repeated START hold time is determined by the.." hexmask.long.byte 0x0 16.--23. 1. "STOP_SETUP,The Stop Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a STOP condition." newline hexmask.long.byte 0x0 8.--15. 1. "RESTART_SETUP,The Restart Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a repeated START condition." hexmask.long.byte 0x0 0.--7. 1. "DATA_HOLD,The Data Hold [7:0] timer determines the SDAT hold time following SCLK driven low." line.long 0x4 "TMOUTSC,Time-Out Scaling Register" hexmask.long.byte 0x4 24.--31. 1. "BUS_IDLE_MIN,Bus Idle Minimum time = Bus Idle Min [7:0] x Baud_Clock_Period" hexmask.long.byte 0x4 16.--23. 1. "MAST_CUM_TIM_OUT,Master Cumulative Time-Out duration = Master Cum Time-Out [7:0] x Baud_Clock_Period x 512" newline hexmask.long.byte 0x4 8.--15. 1. "SLV_CUM_TIM_OUT,Slave Cumulative Time-Out duration = Slave Cum Time-Out [7:0] x Baud_Clock_Period x 1024" hexmask.long.byte 0x4 0.--7. 1. "CLK_HIGH_TIM_OUT,Clock High time out period = Clock High Time-Out [7:0] x Baud_Clock_Period x 2" line.long 0x8 "SLV_TXB,SMBus Slave Transmit Buffer Register" hexmask.long.byte 0x8 0.--7. 1. "STXB,SLAVE_TRANSMIT_BUFFER" line.long 0xC "SLV_RXB,SMBus Slave Receive Buffer Register" hexmask.long.byte 0xC 0.--7. 1. "SRXB,SLAVE_RECEIVE_BUFFER" line.long 0x10 "MTR_TXB,SMBus Master Transmit Buffer Register" hexmask.long.byte 0x10 0.--7. 1. "MTXB,MASTER_TRANSMIT_BUFFER" line.long 0x14 "MTR_RXB,SMBus Master Receive Buffer Register" hexmask.long.byte 0x14 0.--7. 1. "MRXB,MASTER_RECEIVE_BUFFER" group.long 0x60++0x7 line.long 0x0 "WAKE_STS,WAKE STATUS Register" bitfld.long 0x0 0. "START_BIT_DET,This bit is set to '1' when a START bit is detected while the controller is enabled. This bit is cleared to '0' when written with a '1'. Writes of '0' have no effect. (R/WC)" "0,1" line.long 0x4 "WAKE_EN,WAKE ENABLE Register" bitfld.long 0x4 0. "START_DET_INT_EN,Enable Start Bit Detection Interrupt. The Start Bit Detection Interrupt is wake-capable. 1=Start Bit Detection Interrupt enabled; 0=Start Bit Detection Interrupt disabled" "0: Start Bit Detection Interrupt disabled,1: Start Bit Detection Interrupt enabled" group.byte 0x6C++0x0 line.byte 0x0 "SLV_ADDR,This is the Slave Address Register" hexmask.byte 0x0 0.--7. 1. "SADDR,This register stores value of address + LSB direction after the 8th clock of the Address Byte." group.byte 0x70++0x0 line.byte 0x0 "PRM_STS,This is the Promiscuous Interrupt Register" bitfld.byte 0x0 0. "ADDR_INTR,This is the Promiscuous Address Status interrupt and is set on the 8th clock of the I2C Address. This bit will hold the Clock line low till this register bit is cleared. This is Write 1 to clear. R/W1C." "0,1" group.byte 0x74++0x0 line.byte 0x0 "PRM_IEN,This is the Promiscuous Interrupt Enable Register" bitfld.byte 0x0 0. "ADDR,This is the Promiscuous interrupt enable register. 1= Interrupt Enable. 0= Interrupt Disabled." "0: Interrupt Disabled,1: Interrupt Enable" group.byte 0x78++0x0 line.byte 0x0 "PRM_CTRL,This is the Promiscuous Control Register" bitfld.byte 0x0 0. "ACK_NAK,This is the Promiscuous ACK / NAK response register. 1= ACK. 0= NAK." "0: NAK,1: ACK" group.byte 0x7C++0x0 line.byte 0x0 "SHDW_DATA,This is the I2C Shadow Data Register" hexmask.byte 0x0 0.--7. 1. "SHDW_DATA,This is the I2C Shadow Data Register" tree.end tree "SMB4" base ad:0x40005000 wgroup.long 0x0++0x3 line.long 0x0 "WCTRL,Control Register" bitfld.long 0x0 7. "PIN,The Pending Interrupt Not (PIN) bit serves as a software reset function. Writing the PIN bit to a logic '1' de-asserts all status bits except for the nBB bit which is not affected by the PIN bit. The PIN bit is a self-clearing bit. Writing this bit.." "0,1" bitfld.long 0x0 6. "ESO,The Enable Serial Output bit (ESO) enables and disables the SMB Controller Core serial data output (SDAT)" "0,1" newline bitfld.long 0x0 3. "ENI,Enable Interrupt bit (ENI) controls the Interrupt Interface" "0,1" bitfld.long 0x0 2. "STA,The STA and STO bits control the generation of the I2C Start condition and the transmission of the Slave Address and R/nW bit (from the Data Register) generation of repeated Start condition and generation of the Stop condition" "0,1" newline bitfld.long 0x0 1. "STO,See STA description" "0,1" bitfld.long 0x0 0. "ACK,The Acknowledge bit (ACK) must normally be asserted ('1'). This causes the controller to send an acknowledge automatically after each byte (this occurs during the 9th clock pulse). The ACK bit must not be asserted ('0') when the controller is.." "0,1" rgroup.long 0x0++0x3 line.long 0x0 "RSTS,Status Register" bitfld.long 0x0 7. "PIN,Pending Interrupt bit" "0,1" bitfld.long 0x0 6. "SAD,SMBus Address Decoded (SAD)" "0,1" newline bitfld.long 0x0 5. "STS,When in slave receiver mode STS is asserted ('1') when an externally generated STOP condition is detected. Note that STS is used only in slave receiver mode." "0,1" bitfld.long 0x0 4. "BER,When Bus Error (BER) is asserted a misplaced START or STOP condition or Bus Time-Outs have been detected." "0,1" newline bitfld.long 0x0 3. "LRB_AD0,The Last Received Bit or Address 0 (general call) bit (LRB/AD0) serves a dual function and is valid only while the PIN bit is asserted ('0'). When the AAS bit is not asserted ('0') (i.e. not addressed as a slave) the LRB/AD0.." "0,1" bitfld.long 0x0 2. "AAS,The Addressed As Slave bit (AAS) is valid only when PIN is asserted ('0'). When acting as slave AAS is set when an incoming address over the bus matches the value in the Own Address Register or if the 'general call' address (00h) has been received" "0,1" newline bitfld.long 0x0 1. "LAB,The Lost Arbitration Bit (LAB) is set when in multi-master operation arbitration is lost to another master on the bus" "0,1" bitfld.long 0x0 0. "NBB,The Bus Busy bit (NBB) is a read-only flag indicating when the bus is in use. A zero indicates that the bus is busy and access is not possible." "0,1" group.long 0x4++0x3 line.long 0x0 "OWN_ADDR,Own Address Register Note that the Data Register and Own Address fields are offset by one bit. so that programming Own Address 1 with a value of 55h will result in the value AAh being recognized as the SMB Controller Core slave address." hexmask.long.byte 0x0 8.--14. 1. "ADDR2,The Own Address 2 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." hexmask.long.byte 0x0 0.--6. 1. "ADDR1,The Own Address 1 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." group.byte 0x8++0x0 line.byte 0x0 "I2CDATA,This register holds the data that are either shifted out to or shifted in from the I2C port." repeat 3. (increment 0x0 0x1)(increment 0x0 0x1) rgroup.byte ($2+0x9)++0x0 line.byte 0x0 "RSVD1[$1],Reserved" repeat.end group.long 0xC++0xF line.long 0x0 "MCMD,SMBus Master Command Register" hexmask.long.byte 0x0 24.--31. 1. "RD_CNT,This field is a count of the number of bytes to read in from the SMBus to the SMBus Master Receive Buffer Register and must be greater than 0 in order for the Master State Machine to initiate a read phase. It is decremented by 1 for each byte read.." hexmask.long.byte 0x0 16.--23. 1. "WR_CNT,This field is a count of the number of bytes to transmit to the SMBus from the SMBus Master Transmit Buffer Register It is decremented by 1 for each byte written to the SMBus from the SMBus Master Transmit Buffer Register." newline bitfld.long 0x0 13. "RD_PEC,If this bit is 0 reading from the SMBus stops when ReadCount reaches 0. If this bit is 1 reading continues when ReadCount is 0 for one more byte." "0,1" bitfld.long 0x0 12. "READM,If this bit is 1 then the ReadCount field is replaced by the byte that is read from the SMBus when ReadCount[7:0] is 1. After ReadCount[7:0] is updated this bit is cleared to 0." "0,1" newline bitfld.long 0x0 11. "PEC_TERM,If this bit is 1 a copy of the PEC register is transmitted when WriteCount is 0. After the PEC register is read both the PEC register and this bit are cleared to 0." "0,1" bitfld.long 0x0 10. "STOP,If this bit is 1 send a Stop bit after the transaction completes." "0,1" newline bitfld.long 0x0 9. "STARTN,If this bit is 1 send a Start bit just before the last byte of the WriteCount is sent to the SMBus transmitter." "0,1" bitfld.long 0x0 8. "START0,If this bit is 1 send a Start bit on the SMBus before the first byte of the WriteCount is sent to the SMBus transmitter." "0,1" newline bitfld.long 0x0 1. "MPROCEED,When this bit is 0 the Master State Machine does not transition out of the IDLE or PAUSE states. When this bit is 1 the Master State Machine immediately transitions to the WAIT-BUSBUSY and MRUN-RECEIVE states respectively." "0,1" bitfld.long 0x0 0. "MRUN,While this bit is 1 transfer bytes over SMBus. As long as WriteCount is non-zero a byte from the Master Transmit Buffer is transmitted to the slave device and WriteCount is decremented." "0,1" line.long 0x4 "SCMD,SMBus Slave Command Register" hexmask.long.byte 0x4 16.--23. 1. "RD_CNT,This field is decremented each time a byte is copied from DATA to the SMBus Slave Receive Buffer Register." hexmask.long.byte 0x4 8.--15. 1. "WR_CNT,This field is set to the number of bytes software expects to send to the Master." newline bitfld.long 0x4 2. "PEC,If Slave_WriteCount is 0 and Slave_PEC is 1 when the Master requests data the PEC Register is copied to the DATA register. After the PEC Register is copied to the SMBus the PEC Register is cleared and Slave_PEC is set to 0." "0,1" bitfld.long 0x4 1. "SPROCEED,When this bit is 0 the Slave State Machine does not transition out of the IDLE REPEAT_START_WRITE or REPEAT_START_READ states. When this bit is 1 the Slave State Machine immediately transitions to the START_WAIT RECEIVE and TRANSMIT states .." "0,1" newline bitfld.long 0x4 0. "SRUN,Setting this bit to 1 enables the Slave State Machine to operate." "0,1" line.long 0x8 "PEC,Packet Error Check (PEC) Register" hexmask.long.byte 0x8 0.--7. 1. "PEC,The SMBus Packet Error Check (PEC) byte." line.long 0xC "RSHTM,Repeated Start Hold Time Register" hexmask.long.byte 0xC 0.--7. 1. "RSHTM,This is the value of the timing requirement tHd:Sta in the I2C specification for a repeated START bit. This is used to hold the clock until the Hold Time for the repeated Start Bit has been satisfied." rgroup.long 0x1C++0x3 line.long 0x0 "EXTND_LEN,Extended Length Register" hexmask.long.byte 0x0 0.--7. 1. "EXTND_LEN,Extended Length Register adds 8 MSB bits to the SMBUS Master/Slave Tx/Rx Length fields." group.long 0x20++0xF line.long 0x0 "COMPL,Completion Register" bitfld.long 0x0 31. "SDONE,If this bit is 1 Slave State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect.(R/WC)" "0,1" bitfld.long 0x0 30. "MDONE,If this bit is 1 Master State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect. (R/WC)" "0,1" newline bitfld.long 0x0 29. "IDLE,This bit is set when the I2C bus becomes idle (on the rising edge of nBB). (R/WC)" "0,1" bitfld.long 0x0 25. "MTR,0: Master has just finished the receive phase of a transaction. 1: Master has just finished the transmit phase of a transaction." "0: Master has just finished the receive phase of a..,1: Master has just finished the transmit phase of a.." newline bitfld.long 0x0 24. "MNAKX,If this bit is 1 the Master state machine received a NACK from the receiving Slave while the Master was transmitting data over the SMBus interface. (R/WC)" "0,1" bitfld.long 0x0 21. "REP_WR,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 0 indicating that the Master requested a Write operation." "0,1" newline bitfld.long 0x0 20. "REP_RD,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 1 indicating that the Master requested a Read operation." "0,1" bitfld.long 0x0 19. "SPROT,If this bit is 1 the WriteCount[7:0] counter in the Slave state machine either counted down to 0 before the Master sent a NACK signal or the Slave received a NACK signal before the counter reached 0." "0,1" newline bitfld.long 0x0 17. "STR,0: Slave has just finished the receive phase of a transaction. 1: Slave has just finished the transmit phase of a transaction." "0: Slave has just finished the receive phase of a..,1: Slave has just finished the transmit phase of a.." bitfld.long 0x0 16. "SNAKR,If this bit is 1 the Slave state machine sent a NACK to the transmitting Master while the Slave was receiving data from the SMBus interface." "0,1" newline bitfld.long 0x0 14. "LAB,If this bit is 1 the LAB bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" bitfld.long 0x0 13. "BER,If this bit is 1 the BER bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" newline bitfld.long 0x0 12. "CHDH,CHDH is the bus idle time-out detect bit(R/WC)" "0,1" bitfld.long 0x0 11. "CHDL,CHDL is the clock high time-out detect bit(R/WC)" "0,1" newline bitfld.long 0x0 10. "SCTO,SCTO is the Slave Cumulative Time-out bit(R/WC)" "0,1" bitfld.long 0x0 9. "MCTO,MCTO is the Master Cumulative Time-out bit. (R/WC)" "0,1" newline bitfld.long 0x0 8. "DTO,DTO is the Device Time-out bit. (R/WC)" "0,1" bitfld.long 0x0 6. "TIMERR,The Time-out Error Detected bit (TIMERR) is asserted ('1') whenever any of the enabled time-out error detect status bits (CHDH CHDL SCTO MCTO and DTO) are asserted." "0,1" newline bitfld.long 0x0 5. "BIDEN,When BIDEN is asserted ('1') Bus Idle Detect Time-Out checking is enabled. When BIDEN is not asserted ('0') Bus Idle Detect Time-Out checking is disabled." "0,1" bitfld.long 0x0 4. "SCEN,When SCEN is asserted ('1') Slave Cumulative Time-Out checking is enabled. When SCEN is not asserted ('0') Slave Cumulative Time-Out checking is disabled." "0,1" newline bitfld.long 0x0 3. "MCEN,When MCEN is asserted ('1') Master Cumulative Time-Out checking is enabled. When MCEN is not asserted ('0') Master Cumulative Time-Out checking is disabled." "0,1" bitfld.long 0x0 2. "DTEN,When DTEN is asserted ('1') Device Time-out checking is enabled. When DTEN is not asserted ('0') Device Time-out checking is disabled." "0,1" line.long 0x4 "IDLSC,Idle Scaling Register" hexmask.long.word 0x4 16.--27. 1. "FAIR_IDL_DLY,This field defines the number of ticks of the baud clock required to program the delay. The default value for this field sets the delay period to 32us which is the appropriate value for a 100 KHz bus" hexmask.long.word 0x4 0.--11. 1. "FAIR_BUS_IDL_MIN,This field defines the number of ticks of the baud clock required to satisfy the fairness protocol. The default value for this field sets the idle window to 31us which is the appropriate value for a 100 KHz bus" line.long 0x8 "CFG,Configuration Register" bitfld.long 0x8 31. "ENSI,If this bit is 1 the Slave Done interrupt is enabled. If this bit is 0 the Slave Done interrupt is disabled" "0,1" bitfld.long 0x8 30. "ENMI,If this bit is 1 the Master Done interrupt is enabled. If this bit is 0 the Master Done interrupt is disabled." "0,1" newline bitfld.long 0x8 29. "ENIDI,If this bit is 1 the Idle interrupt is enabled. If this bit is 0 the Idle interrupt is disabled." "0,1" bitfld.long 0x8 28. "EN_AAS,0: Disable the AAS 1: Enable the AAS Interrupt" "0: Disable the AAS,1: Enable the AAS Interrupt" newline bitfld.long 0x8 19. "FLUSH_MRBUF,A write of a 1 to this bit forces the SMBus Master Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 18. "FLUSH_MXBUF,A write of a 1 to this bit forces the SMBus Master Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 17. "FLUSH_SRBUF,A write of a 1 to this bit forces the SMBus Slave Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 16. "FLUSH_SXBUF,A write of a 1 to this bit forces the SMBus Slave Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 15. "CFG_PROMIS,This bit define the Mode of SM Bus Controler Mode of operation. 0= Normal Operation. 1= Promiscuous Mode Enable." "0: Normal Operation,1: Promiscuous Mode Enable" bitfld.long 0x8 14. "GC_DIS,This is the General Call Disable bit. 0: the response to the General Call address as a slave is enabled 1: the response to the General Call address as a slave is disabled." "0: the response to the General Call address as a..,1: the response to the General Call address as a.." newline bitfld.long 0x8 13. "TEST0,Must be always written with 0." "0,1" bitfld.long 0x8 12. "FAIR,If this bit is 1 the MCTP Fairness protocol is in effect." "0,1" newline bitfld.long 0x8 11. "DSA,0: Slave Address I2C Compatibility Mode (default). 1: SMBus Address Decode Mode" "0: Slave Address I2C Compatibility Mode,1: SMBus Address Decode Mode" bitfld.long 0x8 10. "EN,When ENAB (Enable) is not asserted ('0') (default) the SMB Controller Core is disabled and in the lowest power consumption state (Disabled State). The ENAB bit must be asserted ('1') for normal operation." "0,1" newline bitfld.long 0x8 9. "RST,When RESET is asserted ('1') all logic and registers except for the RESET bit itself are initialized to the power-on default state." "0,1" bitfld.long 0x8 8. "FEN,Input filtering enable. Input filtering is required by the I2C specification if external filtering is not available. 1=Input filtering is enabled; 0=Input filtering is disabled." "0: Input filtering is disabled,1: Input filtering is enabled" newline bitfld.long 0x8 7. "PECEN,When the PEC Enable bit (PECEN) is asserted ('1') Hardware PEC Support is enabled" "0,1" bitfld.long 0x8 6. "TEST,Must be always written with 0." "0,1" newline bitfld.long 0x8 5. "SLOW_CLK,When this bit is 1 the base period for the Bus Clock Register is multiplied by 4 and thus the frequency is divided by 4." "0,1" bitfld.long 0x8 4. "TCEN,When the Timing Check Enable bit (TCEN) is asserted ('1') Bus Time-Outs are enabled" "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "PORT_SEL,The PORT SEL [3:0] bits determine which one of 16 possible bus ports apply to the active 2-wire SDAT and SCLK bus pair." line.long 0xC "BUSCLK,Bus Clock Register" hexmask.long.byte 0xC 8.--15. 1. "HIGH_PER,This field defines the number of I2C Baud Clock periods that make up the high phase of the I2C/SMBus bus clock." hexmask.long.byte 0xC 0.--7. 1. "LOW_PER,This field defines the number of I2C Baud Clock periods that make up the low phase of the I2C/SMBus bus clock." rgroup.byte 0x30++0x0 line.byte 0x0 "BLKID,Block ID Register" hexmask.byte 0x0 0.--7. 1. "ID,Block ID." rgroup.byte 0x34++0x0 line.byte 0x0 "BLKREV,Revision Register" hexmask.byte 0x0 0.--7. 1. "REV,Block Revision Number" group.long 0x38++0x3 line.long 0x0 "BBCTRL,Bit-Bang Control Register" bitfld.long 0x0 6. "BBDATI,Bit-Bang Data In. The BBDATI bit always returns the state of SDAT" "0,1" bitfld.long 0x0 5. "BBCLKI,Bit-Bang Clock In. The BBCLKI bit always returns the state of SCLK." "0,1" newline bitfld.long 0x0 4. "BBDAT,Bit-Bang Data. The BBDAT bit controls the state of SDAT when BBEN = and DADIR = '1'" "0,1" bitfld.long 0x0 3. "BBCLK,Bit-Bang Clock. The BBCLK bit controls the state of SCLK when BBEN = and CLDIR = '1'" "0,1" newline bitfld.long 0x0 2. "DADIR,Bit-Bang Data Direction. The DADIR bit controls the direction of SDAT. 0 - Input. 1 - Output" "0,1" bitfld.long 0x0 1. "CLDIR,Bit-Bang Clock Direction. The CLDIR bit controls the direction of SCLK. 0 - Input 1 - Output" "0,1" newline bitfld.long 0x0 0. "BBEN,Bit-Bang Mode Enable. 0 - Bit Bang Mode Disabled. 1 - Bit Bang Mode Enabled" "0,1" rgroup.byte 0x3C++0x0 line.byte 0x0 "TEST,Test" hexmask.byte 0x0 0.--7. 1. "TEST,This register must not be written or undesirable results may occur." group.long 0x40++0x17 line.long 0x0 "DATATM,Data Timing Register" hexmask.long.byte 0x0 24.--31. 1. "FIRST_START_HOLD,This field determines the SCL hold time following SDA driven low during the first START bit in a transfer. It is the parameter THD:STA in the I2C Specification for an initial START bit. Repeated START hold time is determined by the.." hexmask.long.byte 0x0 16.--23. 1. "STOP_SETUP,The Stop Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a STOP condition." newline hexmask.long.byte 0x0 8.--15. 1. "RESTART_SETUP,The Restart Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a repeated START condition." hexmask.long.byte 0x0 0.--7. 1. "DATA_HOLD,The Data Hold [7:0] timer determines the SDAT hold time following SCLK driven low." line.long 0x4 "TMOUTSC,Time-Out Scaling Register" hexmask.long.byte 0x4 24.--31. 1. "BUS_IDLE_MIN,Bus Idle Minimum time = Bus Idle Min [7:0] x Baud_Clock_Period" hexmask.long.byte 0x4 16.--23. 1. "MAST_CUM_TIM_OUT,Master Cumulative Time-Out duration = Master Cum Time-Out [7:0] x Baud_Clock_Period x 512" newline hexmask.long.byte 0x4 8.--15. 1. "SLV_CUM_TIM_OUT,Slave Cumulative Time-Out duration = Slave Cum Time-Out [7:0] x Baud_Clock_Period x 1024" hexmask.long.byte 0x4 0.--7. 1. "CLK_HIGH_TIM_OUT,Clock High time out period = Clock High Time-Out [7:0] x Baud_Clock_Period x 2" line.long 0x8 "SLV_TXB,SMBus Slave Transmit Buffer Register" hexmask.long.byte 0x8 0.--7. 1. "STXB,SLAVE_TRANSMIT_BUFFER" line.long 0xC "SLV_RXB,SMBus Slave Receive Buffer Register" hexmask.long.byte 0xC 0.--7. 1. "SRXB,SLAVE_RECEIVE_BUFFER" line.long 0x10 "MTR_TXB,SMBus Master Transmit Buffer Register" hexmask.long.byte 0x10 0.--7. 1. "MTXB,MASTER_TRANSMIT_BUFFER" line.long 0x14 "MTR_RXB,SMBus Master Receive Buffer Register" hexmask.long.byte 0x14 0.--7. 1. "MRXB,MASTER_RECEIVE_BUFFER" group.long 0x60++0x7 line.long 0x0 "WAKE_STS,WAKE STATUS Register" bitfld.long 0x0 0. "START_BIT_DET,This bit is set to '1' when a START bit is detected while the controller is enabled. This bit is cleared to '0' when written with a '1'. Writes of '0' have no effect. (R/WC)" "0,1" line.long 0x4 "WAKE_EN,WAKE ENABLE Register" bitfld.long 0x4 0. "START_DET_INT_EN,Enable Start Bit Detection Interrupt. The Start Bit Detection Interrupt is wake-capable. 1=Start Bit Detection Interrupt enabled; 0=Start Bit Detection Interrupt disabled" "0: Start Bit Detection Interrupt disabled,1: Start Bit Detection Interrupt enabled" group.byte 0x6C++0x0 line.byte 0x0 "SLV_ADDR,This is the Slave Address Register" hexmask.byte 0x0 0.--7. 1. "SADDR,This register stores value of address + LSB direction after the 8th clock of the Address Byte." group.byte 0x70++0x0 line.byte 0x0 "PRM_STS,This is the Promiscuous Interrupt Register" bitfld.byte 0x0 0. "ADDR_INTR,This is the Promiscuous Address Status interrupt and is set on the 8th clock of the I2C Address. This bit will hold the Clock line low till this register bit is cleared. This is Write 1 to clear. R/W1C." "0,1" group.byte 0x74++0x0 line.byte 0x0 "PRM_IEN,This is the Promiscuous Interrupt Enable Register" bitfld.byte 0x0 0. "ADDR,This is the Promiscuous interrupt enable register. 1= Interrupt Enable. 0= Interrupt Disabled." "0: Interrupt Disabled,1: Interrupt Enable" group.byte 0x78++0x0 line.byte 0x0 "PRM_CTRL,This is the Promiscuous Control Register" bitfld.byte 0x0 0. "ACK_NAK,This is the Promiscuous ACK / NAK response register. 1= ACK. 0= NAK." "0: NAK,1: ACK" group.byte 0x7C++0x0 line.byte 0x0 "SHDW_DATA,This is the I2C Shadow Data Register" hexmask.byte 0x0 0.--7. 1. "SHDW_DATA,This is the I2C Shadow Data Register" tree.end tree.end tree "SPI_SLAVE (SPI Slave Controller)" base ad:0x40007000 group.long 0x0++0x2F line.long 0x0 "SPI_CFG,SPI Slave Communication Configuration Register." hexmask.long.byte 0x0 16.--23. 1. "WAIT_TIME,These bits set the amount of wait time in cycles before transmitting data back to master. During this wait time status bits will be transmitted" bitfld.long 0x0 8.--10. "TAR_TIM_SEL,Turn Around Time select for Quad wire mode. 0h = 1 cycle. 1h = 2 cycles. 2h = 4 cycles. 3h = 8 cycles. Other values are reserved." "0,1,2,3,4,5,6,7" bitfld.long 0x0 0. "SNG_QUD_SEL,This field defines the Single / Quad Wire mode of operation for SPI Slave block. 0 = Single Wire Slave SPI block operation. 1 = Quad Wire Slave SPI block operation." "0: Single Wire Slave SPI block operation,1: Quad Wire Slave SPI block operation" line.long 0x4 "SPI_STS,SPI Slave Status Register." bitfld.long 0x4 28. "RXF_OVRFLW,If SPI Master writes more than the space in the FIFO the FIFO will flag an overflow error and data will not be stored." "0,1" bitfld.long 0x4 27. "RXF_UNFLW,If the SPI Slave reads RX FIFO when it is empty RX FIFO Underflow flag will be set. This condition will never happen under normal situation." "0,1" bitfld.long 0x4 26. "TXF_OVRFLW,If Master doesn't read all of the data it requested from the posted read block cycle than data will still be left in the FIFO. This will cause misalignment with the following transactions and a new read cycle can cause overflow." "0,1" newline bitfld.long 0x4 25. "TXF_UNFLW,If Master reads more than what is in FIFO FIFO will flag an underflow error and the data returned will just be the last valid pointer value." "0,1" bitfld.long 0x4 24. "RXF_SIZE_ERR,If size requested is more than what Master provided and the Master terminates early error flag shut down request signal to ARM Bus. Size requested is less than what Master provided -- ignored and continue transaction may be.." "0,1" bitfld.long 0x4 23. "DV_BUSY,If the Master requested a transaction whose destination is busy the request is ignored. Should use the poll or wait for interrupts." "0,1" newline bitfld.long 0x4 22. "UNDEF_CMD_ERR,Undefined Command Error: The command received from the master isn't defined." "0,1" bitfld.long 0x4 21. "ARMBUS_ERR,ARM Bus Error returned for the curren data transfer." "0,1" bitfld.long 0x4 20. "OOL1_ERR,This flag is set with the transfer address requested by the master is out of Limit 1 range or when the BAR is disabled." "0,1" newline bitfld.long 0x4 19. "OOL0_ERR,This flag is set with the transfer address requested by the master is out of Limit 0 range or when the BAR is disabled." "0,1" bitfld.long 0x4 18. "TXF_RST_DN,Set after the SPI Master initiates a TX FIFO reset and the reset has been processed. FIFO is cleared." "0,1" bitfld.long 0x4 17. "RXF_RST_DN,Set after the SPI Master initiates a RX FIFO reset and the reset has been processed. FIFO is cleared." "0,1" newline bitfld.long 0x4 16. "SPIM_RST_REQ,Set when the SPI Master Requested a Configuration Reset." "0,1" bitfld.long 0x4 15. "OBF_FLG,Set when the EC writes to the Output Buffer signaling there is data for the Host to read." "0,1" bitfld.long 0x4 14. "IBF_FLG,Set when the Host writes to the Input Buffer signaling there is data for the EC to read." "0,1" newline bitfld.long 0x4 13. "TMCLK_CNT_ERR,This bit is set when the SPI Clock Count Test Mode is set and there is an uneven amount of clocks." "0,1" bitfld.long 0x4 11. "TXF_FUL,The TX FIFO is full of data that was read from Memory." "0,1" bitfld.long 0x4 10. "TXF_EMP,Signifies SPI Master has read the data requested from Memory. Can be used to show there is data the SPI Master has requested and not been read yet. New read transactions will be aligned." "0,1" newline bitfld.long 0x4 9. "RXF_FUL,The RX FIFO is full of data to be written to Memory." "0,1" bitfld.long 0x4 8. "RXF_EMP,Signifies all Memory write transactions for the SPI Masters requested size have been performed. New transactions are allowed." "0,1" bitfld.long 0x4 6. "POLL_HIGH,If this bit is set then something in the high 16-bit of status register is set and needs to be checked. SPI Master should take action to clear this." "0,1" newline bitfld.long 0x4 5. "SREG_TRANS,When an SREG transaction is currently being processed." "0,1" bitfld.long 0x4 4. "MEM_RD_BUSY,When an Memory Read transaction is currently being processed." "0,1" bitfld.long 0x4 3. "MEM_WR_BUSY,When an Memory Write transaction is currently being processed." "0,1" newline bitfld.long 0x4 1. "MEM_RD_DONE,When the ARM BUS side has fully finished writing the last written DWord to the FIFO for a set of data read from Memory for Posted Reads. - cleared with new Read request." "0,1" bitfld.long 0x4 0. "MEM_WR_DONE,When the ARM BUS side has fully finished the last transaction from the FIFO to write the data to Memory for Posted Writes . Clear with new Write request." "0,1" line.long 0x8 "SPI_EC_STS,SPI Slave EC Status Register." bitfld.long 0x8 28. "RXF_OVRFLW,If SPI Master writes more than the space in the FIFO the FIFO will flag an overflow error and data will not be stored." "0,1" bitfld.long 0x8 27. "RXF_UNFLW,If the SPI Slave reads RX FIFO when it is empty RX FIFO Underflow flag will be set. This condition will never happen under normal situation." "0,1" bitfld.long 0x8 26. "TXF_OVRFLW,If Master doesn't read all of the data it requested from the posted read block cycle than data will still be left in the FIFO. This will cause misalignment with the following transactions and a new read cycle can cause overflow." "0,1" newline bitfld.long 0x8 25. "TXF_UNFLW,If Master reads more than what is in FIFO FIFO will flag an underflow error and the data returned will just be the last valid pointer value." "0,1" bitfld.long 0x8 24. "RXF_SIZE_ERR,If size requested is more than what Master provided and the Master terminates early error flag shut down request signal to ARM Bus. Size requested is less than what Master provided -- ignored and continue transaction may be.." "0,1" bitfld.long 0x8 23. "DV_BUSY,If the Master requested a transaction whose destination is busy the request is ignored. Should use the poll or wait for interrupts." "0,1" newline bitfld.long 0x8 22. "UNDEF_CMD_ERR,Undefined Command Error: The command received from the master isn't defined." "0,1" bitfld.long 0x8 21. "ARMBUS_ERR,ARM Bus Error returned for the curren data transfer." "0,1" bitfld.long 0x8 20. "OOL1_ERR,This flag is set with the transfer address requested by the master is out of Limit 1 range or when the BAR is disabled." "0,1" newline bitfld.long 0x8 19. "OOL0_ERR,This flag is set with the transfer address requested by the master is out of Limit 0 range or when the BAR is disabled." "0,1" bitfld.long 0x8 18. "TXF_RST_DN,Set after the SPI Master initiates a TX FIFO reset and the reset has been processed. FIFO is cleared." "0,1" bitfld.long 0x8 17. "RXF_RST_DN,Set after the SPI Master initiates a RX FIFO reset and the reset has been processed. FIFO is cleared." "0,1" newline bitfld.long 0x8 16. "SPIM_RST_REQ,Set when the SPI Master Requested a Configuration Reset." "0,1" bitfld.long 0x8 15. "OBF_FLG,Set when the EC writes to the Output Buffer signaling there is data for the Host to read." "0,1" bitfld.long 0x8 14. "IBF_FLG,Set when the Host writes to the Input Buffer signaling there is data for the EC to read." "0,1" newline bitfld.long 0x8 13. "TMCLK_CNT_ERR,This bit is set when the SPI Clock Count Test Mode is set and there is an uneven amount of clocks." "0,1" bitfld.long 0x8 11. "TXF_FUL,The TX FIFO is full of data that was read from Memory." "0,1" bitfld.long 0x8 10. "TXF_EMP,Signifies SPI Master has read the data requested from Memory. Can be used to show there is data the SPI Master has requested and not been read yet. New read transactions will be aligned." "0,1" newline bitfld.long 0x8 9. "RXF_FUL,The RX FIFO is full of data to be written to Memory." "0,1" bitfld.long 0x8 8. "RXF_EMP,Signifies all Memory write transactions for the SPI Masters requested size have been performed. New transactions are allowed." "0,1" bitfld.long 0x8 6. "POLL_HI,If this bit is set then something in the high 16-bit of status register is set and needs to be checked. SPI Master should take action to clear this." "0,1" newline bitfld.long 0x8 5. "SREG_TRANS,When an SREG transaction is currently being processed." "0,1" bitfld.long 0x8 4. "MEM_RD_BUSY,When an Memory Read transaction is currently being processed." "0,1" bitfld.long 0x8 3. "MEM_WR_BUSY,When an Memory Write transaction is currently being processed." "0,1" newline bitfld.long 0x8 1. "MEM_RD_DONE,When the ARM BUS side has fully finished writing the last written DWord to the FIFO for a set of data read from Memory for Posted Reads. - cleared with new Read request." "0,1" bitfld.long 0x8 0. "MEM_WR_DONE,When the ARM BUS side has fully finished the last transaction from the FIFO to write the data to Memory for Posted Writes .- clear with new Write request." "0,1" line.long 0xC "SPI_IEN,SPI Slave Interrupt Enable Register." bitfld.long 0xC 28. "RXF_OVRFLW,Enable RX FIFO Overflow Interrupt to SPI Master." "0,1" bitfld.long 0xC 27. "RXF_UNFLW,Enable RX FIFO Underflow Interrupt to SPI Master." "0,1" bitfld.long 0xC 26. "TXF_OVRFLOW,Enable TX FIFO Overflow Interrupt to SPI Master." "0,1" newline bitfld.long 0xC 25. "TXF_UNFLW,Enable TX FIFO Underflow Interrupt to SPI Master." "0,1" bitfld.long 0xC 24. "RXF_SIZE_ERR,Enable RX FIFO SIZE Error Interrupt to SPI Master." "0,1" bitfld.long 0xC 23. "DV_BUSY,Enable Device Busy Interrupt to SPI Master." "0,1" newline bitfld.long 0xC 22. "UNDEF_CMD_ERR,Enable Undefined Command Error Interrupt to SPI Master." "0,1" bitfld.long 0xC 21. "ARMBUS_ERR,Enable AHB BUS Error Interrupt to SPI Master." "0,1" bitfld.long 0xC 20. "OOL1_ERR,Enable Out Of Limit 1 Error Interrupt to SPI Master." "0,1" newline bitfld.long 0xC 19. "OOL0_ERR,Enable Out Of Limit 0 Error Interrupt to SPI Master." "0,1" bitfld.long 0xC 18. "TXF_RST_DN,Enable TX FIFO Reset Done Interrupt to SPI Master." "0,1" bitfld.long 0xC 17. "RXF_RST_DN,Enable RX FIFO Reset Done Interrupt to SPI Master." "0,1" newline bitfld.long 0xC 16. "SPIM_RST_REQ,Enable SPI Master Request Reset Interrupt to SPI Master." "0,1" bitfld.long 0xC 15. "OBF_FLG,Enable Output Buffer signaling Interrupt to SPI Master." "0,1" bitfld.long 0xC 14. "IBF_FLG,Enable Input Buffer Signaling Interrupt to SPI Master." "0,1" newline bitfld.long 0xC 13. "TMCLK_CNT_ERR,Enable Test Mode SPI Clock Count Error Interrupt to SPI Master." "0,1" bitfld.long 0xC 11. "TXF_FUL,Enable TX FIFI FULL Interrupt to SPI Master." "0,1" bitfld.long 0xC 10. "TXF_EMP,Enable TX FIFO Empty Interrupt to SPI Master." "0,1" newline bitfld.long 0xC 9. "RXF_FUL,Enable RX FIFO Full Interrupt to SPI Master." "0,1" bitfld.long 0xC 8. "RXF_EMP,Enable SREG RX FIFO Empty Interrupt to SPI Master." "0,1" bitfld.long 0xC 6. "POLL_HI,Enable Poll High Request Interrupt to SPI Master." "0,1" newline bitfld.long 0xC 5. "SREG_TRANS,Enable SREG Trans Busy Interrupt to SPI Master." "0,1" bitfld.long 0xC 4. "MEM_RD_BUSY,Enable Memory Read Busy Interrupt to SPI Master." "0,1" bitfld.long 0xC 3. "MEM_WR_BUSY,Enable Memory Write Busy Interrupt to SPI Master." "0,1" newline bitfld.long 0xC 1. "MEM_RD_DONE,Enable Memory Read Done Interrupt to SPI Master." "0,1" bitfld.long 0xC 0. "MEM_WR_DONE,Enable Memory Write Done Interrupt to SPI Master." "0,1" line.long 0x10 "EC_IEN,SPI Slave EC Interrupt Enable Register." bitfld.long 0x10 28. "RXF_OVRFLW,Enable RX FIFO Overflow Interrupt to EC." "0,1" bitfld.long 0x10 27. "RXF_UNFLW,Enable RX FIFO Underflow Interrupt to EC." "0,1" bitfld.long 0x10 26. "TXF_OVRFLW,Enable TX FIFO Overflow Interrupt to EC." "0,1" newline bitfld.long 0x10 25. "TXF_UNFLW,Enable TX FIFO Underflow Interrupt to EC." "0,1" bitfld.long 0x10 24. "RXF_SIZE_ERR,Enable RX FIFO SIZE Error Interrupt to EC." "0,1" bitfld.long 0x10 23. "DV_BUSY,Enable Device Busy Interrupt to EC." "0,1" newline bitfld.long 0x10 22. "UNDEF_CMD_ERR,Enable Undefined Command Error Interrupt to EC." "0,1" bitfld.long 0x10 21. "ARMBUS_ERR,Enable AHB BUS Error Interrupt to EC." "0,1" bitfld.long 0x10 20. "OOL1_ERR,Enable Out Of Limit 1 Error Interrupt to EC." "0,1" newline bitfld.long 0x10 19. "OOL0_ERR,Enable Out Of Limit 0 Error Interrupt to EC." "0,1" bitfld.long 0x10 18. "TXF_RST_DN,Enable TX FIFO Reset Done Interrupt to EC." "0,1" bitfld.long 0x10 17. "RXF_RST_DN,Enable RX FIFO Reset Done Interrupt to EC." "0,1" newline bitfld.long 0x10 16. "SPIM_RST_REQ,Enable SPI Master Request Reset Interrupt to EC." "0,1" bitfld.long 0x10 15. "OBF_FLG,Enable Output Buffer signaling Interrupt to EC." "0,1" bitfld.long 0x10 14. "IBF_FLG,Enable Input Buffer Signaling Interrupt to EC." "0,1" newline bitfld.long 0x10 13. "TMCLK_CNT_ERR,Enable Test Mode SPI Clock Count Error Interrupt to EC." "0,1" bitfld.long 0x10 11. "TXF_FUL,Enable TX FIFI FULL Interrupt to EC." "0,1" bitfld.long 0x10 10. "TXF_EMP,Enable TX FIFO Empty Interrupt to EC." "0,1" newline bitfld.long 0x10 9. "RXF_FUL,Enable RX FIFO Full Interrupt to EC." "0,1" bitfld.long 0x10 8. "RXF_EMP,Enable SREG RX FIFO Empty Interrupt to EC." "0,1" bitfld.long 0x10 6. "POLL_HI,Enable Poll High Request Interrupt to EC." "0,1" newline bitfld.long 0x10 5. "SREG_TRANS,Enable SREG Trans Busy Interrupt to EC." "0,1" bitfld.long 0x10 4. "MEM_RD_BUSY,Enable Memory Read Busy Interrupt to EC." "0,1" bitfld.long 0x10 3. "MEM_WR_BUSY,Enable Memory Write Busy Interrupt to EC." "0,1" newline bitfld.long 0x10 1. "MEM_RD_DONE,Enable Memory Read Done Interrupt to EC." "0,1" bitfld.long 0x10 0. "MEM_WR_DONE,Enable Memory Write Done Interrupt to EC." "0,1" line.long 0x14 "MEM_CFG,SPI Slave Memory Configuration Register." bitfld.long 0x14 1. "BAR_EN1_SEL,Enables Region 1 operation. 0 = Disable Region 1. 1 = Enable Region 1." "0: Disable Region 1,1: Enable Region 1" bitfld.long 0x14 0. "BAR_EN0_SEL,Enables Region 0 operation. 0 = Disable Region 0. 1 = Enable Region 0." "0: Disable Region 0,1: Enable Region 0" line.long 0x18 "MEM_BAR0,SPI Slave Memory Base Address0 Register." hexmask.long 0x18 0.--31. 1. "BAS_ADD0,Base Address for Region 0." line.long 0x1C "MEM_WR_LIM0,SPI Slave Memory Write LIMIT 0 Register." hexmask.long.word 0x1C 0.--14. 1. "LMT0,Write Limit for Region 0." line.long 0x20 "MEM_RD_LIM0,SPI Slave Memory Read LIMIT 0 Register." hexmask.long.word 0x20 0.--14. 1. "LMT0,Read Limit for Region 0." line.long 0x24 "MEM_BAR1,SPI Slave Memory Base Address1 Register." hexmask.long 0x24 0.--31. 1. "ADD1,Base Address for Region 1." line.long 0x28 "MEM_WR_LIM1,SPI Slave Memory Write LIMIT 1 Register." hexmask.long.word 0x28 0.--14. 1. "LMT1,Write Limit for Region 1." line.long 0x2C "MEM_RD_LIM1,SPI Slave Memory Read LIMIT 1 Register." hexmask.long.word 0x2C 0.--14. 1. "LMT1,Read Limit for Region 1." rgroup.long 0x30++0xF line.long 0x0 "RXF_HOST_BAR,SPI Slave RX FIFO Host Bar Register." hexmask.long.word 0x0 0.--15. 1. "BAR,RX FIFO Host Bar Register." line.long 0x4 "RXF_BYTE_CNT,SPI Slave RX FIFO Byte Counter Register." hexmask.long.word 0x4 0.--14. 1. "BCNT,RX FIFO Byte Count Register." line.long 0x8 "TXF_HOST_BAR,SPI Slave TX FIFO Host Bar Register." hexmask.long.word 0x8 0.--15. 1. "BAR,TX FIFO Host Bar Register." line.long 0xC "TXF_BYTE_CNT,SPI Slave TX FIFO Byte Counter Register." hexmask.long.word 0xC 0.--14. 1. "BCNT,TX FIFO Byte Count Register." group.long 0x40++0xB line.long 0x0 "SYS_CFG,SPI Slave System Configuration Register." bitfld.long 0x0 19. "ECDATL,Notification to TX FIFO Engine that data is available for AHB Transfer. This register but is cleared by Hardware at the end of the transaction with SPI_CS_N de-assertion. (R/WC)." "0,1" bitfld.long 0x0 18. "SIM_EN,Enable SPI Slave Simple Mode operation." "0,1" bitfld.long 0x0 17. "MAS_ECREG,Mask EC register 'fld_mask_ec_register' from SPI Master. All the register are neither readable now writable from SPI Master." "0,1" newline bitfld.long 0x0 16. "SPI_SLV_EN,Enable / Disable SPI Slave Block. 0 = Disable SPI Slave module. 1 = Enable SPI Slave module." "0: Disable SPI Slave module,1: Enable SPI Slave module" bitfld.long 0x0 10. "LOCK_TEST_MODE,Lock TEST Mode register write access from SPI Master." "0,1" bitfld.long 0x0 7. "LOCK_MEM_BAR1,Lock Memory Bar 1 register write access from SPI Master." "0,1" newline bitfld.long 0x0 6. "LOCK_MEM_BAR0,Lock Memory Bar 0 register write access from SPI Master." "0,1" bitfld.long 0x0 5. "LOCK_SPIINT_EN,Lock SPI Interrupt Enable register write access from SPI Master." "0,1" bitfld.long 0x0 4. "LOCK_MEM_CFG,Lock Memory Configuration register write access from SPI Master." "0,1" newline bitfld.long 0x0 3. "LOCK_WAIT_CYCL,Lock Wait Cycle bits write access from SPI Master." "0,1" bitfld.long 0x0 2. "LOCK_TAR_TIME,Lock Tar Time bit write access from SPI Master." "0,1" bitfld.long 0x0 1. "LOCK_QUAD_SNGL_WRMOD,Lock Quad / Single Write Mode bit write access from SPI Master." "0,1" newline bitfld.long 0x0 0. "SOFT_RST,Soft reset for entire SPI Slave Block. This bit is self clearing." "0,1" line.long 0x4 "SPIM2EC_MBX,SPI Slave Master to EC Mailbox Register." hexmask.long 0x4 0.--31. 1. "M2EC,Write only register for the Host. When data is written to this register the IBF Flag is set. EC can read the data and writes of 0xFFFF will clear this register. Any form of read will clear the flag for this register." line.long 0x8 "EC2SPIM_MBX,SPI Slave Master to EC Mailbox Register." hexmask.long 0x8 0.--31. 1. "EC2M,Read only register for the Host. When data is written to this register the OBF Flag is set. Host can read the data and writes of 0xFFFF_FFFF will clear this register also clearing the flag. Any form of read will clear the flag for.." tree.end tree "SYSTICK (System Timer)" base ad:0xE000E010 group.long 0x0++0xB line.long 0x0 "CSR,SysTick Control and Status Register" bitfld.long 0x0 16. "COUNTFLAG,Timer counted to 0 since last read of register" "0,1" bitfld.long 0x0 2. "CLKSOURCE,Clock Source 0=external 1=processor" "0: external,1: processor" newline bitfld.long 0x0 1. "TICKINT,SysTick Exception Request Enable" "0: Counting down to 0 does not assert the SysTick..,1: Counting down to 0 asserts the SysTick exception.." bitfld.long 0x0 0. "ENABLE,SysTick Counter Enable" "0: Counter disabled,1: Counter enabled" line.long 0x4 "RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x4 0.--23. 1. "RELOAD,Value to load into the SysTick Current Value Register when the counter reaches 0" line.long 0x8 "CVR,SysTick Current Value Register" hexmask.long.tbyte 0x8 0.--23. 1. "CURRENT,Current value at the time the register is accessed" rgroup.long 0xC++0x3 line.long 0x0 "CALIB,SysTick Calibration Value Register" bitfld.long 0x0 31. "NOREF,No Separate Reference Clock" "0: The reference clock is provided,1: The reference clock is not provided" bitfld.long 0x0 30. "SKEW,TENMS is rounded from non-integer ratio" "0: 10ms calibration value is exact,1: 10ms calibration value is inexact because of the.." newline hexmask.long.tbyte 0x0 0.--23. 1. "TENMS,Reload value to use for 10ms timing" tree.end tree "TACH (Tachometers)" base ad:0x0 tree "TACH0" base ad:0x40006000 group.long 0x0++0xF line.long 0x0 "CTRL,TACHx Control Register" hexmask.long.word 0x0 16.--31. 1. "CNTR,This 16-bit field contains the latched value of the internal Tach pulse counter which may be configured by the Tach Reading Mode Select field to operate as a free-running counter or to be gated by the Tach input signal." bitfld.long 0x0 15. "IN_INT_EN,TACH_INPUT_INT_EN 1=Enable Tach Input toggle interrupt from Tach block 0=Disable Tach Input toggle interrupt from Tach block" "0: Disable Tach Input toggle interrupt from Tach..,1: Enable Tach Input toggle interrupt from Tach block" newline bitfld.long 0x0 14. "CNT_RDY_INT_EN,COUNT_READY_INT_EN 1=Enable Count Ready interrupt from Tach block 0=Disable Count Ready interrupt from Tach block" "0: Disable Count Ready interrupt from Tach block,1: Enable Count Ready interrupt from Tach block" bitfld.long 0x0 11.--12. "EDGES,TACH_EDGES A Tach signal is a square wave with a 50 percent duty cycle. Typically two Tach periods represents one revolution of the fan. A Tach period consists of three Tach edges. This programmed value represents the number of Tach edges that.." "0,1,2,3" newline bitfld.long 0x0 10. "RD_MOD_SEL,TACH_READING_MODE_SELECT 1=Counter is incremented on the rising edge of the 100kHz_Clk input. The counter is latched into the TACHX_COUNTER field and reset when the programmed number of edges is detected." "0: Counter is incremented when Tach Input..,1: Counter is incremented on the rising edge of the.." bitfld.long 0x0 8. "FILT_EN,FILTER_ENABLE This filter is used to remove high frequency glitches from Tach Input. When this filter is enabled Tach input pulses less than two 100kHz_- Clk periods wide get filtered. 1= Filter enabled 0=.." "0: Filter disabled,1: Filter enabled" newline bitfld.long 0x0 1. "EN,TACH_ENABLE 1= TACH Monitoring enabled clocks enabled. 0= TACH Idle clocks gated" "0: TACH Idle,1: TACH Monitoring enabled" bitfld.long 0x0 0. "OUTOF_LIM_EN,TACH_OUT_OF_LIMIT_ENABLE This bit is used to enable the TACH_OUT_OF_LIMIT_STATUS bit in the TACHx Status Register to generate an interrupt event. 1=Enable interrupt output from Tach block 0=Disable.." "0: Disable interrupt output from Tach block,1: Enable interrupt output from Tach block" line.long 0x4 "STS,TACHx Status Register" bitfld.long 0x4 3. "CNT_RDY_STS,COUNT_READY_STATUS 1=Reading ready 0=Reading not ready" "0: Reading not ready,1: Reading ready" bitfld.long 0x4 2. "TOG_STS,TOGGLE_STATUS 1=Tach Input changed state (this bit is set on a low-to-high or high-tolow transition) 0=Tach stable (R/WC)" "0: Tach stable,1: Tach Input changed state" newline bitfld.long 0x4 1. "PIN_STS,TACH_PIN_STATUS 1= Tach Input is high 0= Tach Input is low" "0: Tach Input is low,1: Tach Input is high" bitfld.long 0x4 0. "OUTOF_LIM_STS,TACH_OUT_OF_LIMIT_STATUS 1=Tach is outside of limits 0=Tach is within limits (R/WC)" "0: Tach is within limits,1: Tach is outside of limits" line.long 0x8 "LIM_HI,TACH HIGH LIMIT Register" hexmask.long.word 0x8 0.--15. 1. "T_HIGH,This value is compared with the value in the TACHX_COUNTER field. If the value in the counter is greater than the value programmed in this register the TACH_OUT_OF_LIMIT_STATUS bit will be set. The TACH_OUT_OF_LIMIT_STATUS status event may be.." line.long 0xC "LIM_LO,TACHx Low Limit Register" hexmask.long.word 0xC 0.--15. 1. "T_LOW,This value is compared with the value in the TACHX_COUNTER field of the TACHx Control Register. If the value in the counter is less than the value programmed in this register the TACH_OUT_OF_LIMIT_STATUS bit will be set. The.." tree.end tree "TACH1" base ad:0x40006010 group.long 0x0++0xF line.long 0x0 "CTRL,TACHx Control Register" hexmask.long.word 0x0 16.--31. 1. "CNTR,This 16-bit field contains the latched value of the internal Tach pulse counter which may be configured by the Tach Reading Mode Select field to operate as a free-running counter or to be gated by the Tach input signal." bitfld.long 0x0 15. "IN_INT_EN,TACH_INPUT_INT_EN 1=Enable Tach Input toggle interrupt from Tach block 0=Disable Tach Input toggle interrupt from Tach block" "0: Disable Tach Input toggle interrupt from Tach..,1: Enable Tach Input toggle interrupt from Tach block" newline bitfld.long 0x0 14. "CNT_RDY_INT_EN,COUNT_READY_INT_EN 1=Enable Count Ready interrupt from Tach block 0=Disable Count Ready interrupt from Tach block" "0: Disable Count Ready interrupt from Tach block,1: Enable Count Ready interrupt from Tach block" bitfld.long 0x0 11.--12. "EDGES,TACH_EDGES A Tach signal is a square wave with a 50 percent duty cycle. Typically two Tach periods represents one revolution of the fan. A Tach period consists of three Tach edges. This programmed value represents the number of Tach edges that.." "0,1,2,3" newline bitfld.long 0x0 10. "RD_MOD_SEL,TACH_READING_MODE_SELECT 1=Counter is incremented on the rising edge of the 100kHz_Clk input. The counter is latched into the TACHX_COUNTER field and reset when the programmed number of edges is detected." "0: Counter is incremented when Tach Input..,1: Counter is incremented on the rising edge of the.." bitfld.long 0x0 8. "FILT_EN,FILTER_ENABLE This filter is used to remove high frequency glitches from Tach Input. When this filter is enabled Tach input pulses less than two 100kHz_- Clk periods wide get filtered. 1= Filter enabled 0=.." "0: Filter disabled,1: Filter enabled" newline bitfld.long 0x0 1. "EN,TACH_ENABLE 1= TACH Monitoring enabled clocks enabled. 0= TACH Idle clocks gated" "0: TACH Idle,1: TACH Monitoring enabled" bitfld.long 0x0 0. "OUTOF_LIM_EN,TACH_OUT_OF_LIMIT_ENABLE This bit is used to enable the TACH_OUT_OF_LIMIT_STATUS bit in the TACHx Status Register to generate an interrupt event. 1=Enable interrupt output from Tach block 0=Disable.." "0: Disable interrupt output from Tach block,1: Enable interrupt output from Tach block" line.long 0x4 "STS,TACHx Status Register" bitfld.long 0x4 3. "CNT_RDY_STS,COUNT_READY_STATUS 1=Reading ready 0=Reading not ready" "0: Reading not ready,1: Reading ready" bitfld.long 0x4 2. "TOG_STS,TOGGLE_STATUS 1=Tach Input changed state (this bit is set on a low-to-high or high-tolow transition) 0=Tach stable (R/WC)" "0: Tach stable,1: Tach Input changed state" newline bitfld.long 0x4 1. "PIN_STS,TACH_PIN_STATUS 1= Tach Input is high 0= Tach Input is low" "0: Tach Input is low,1: Tach Input is high" bitfld.long 0x4 0. "OUTOF_LIM_STS,TACH_OUT_OF_LIMIT_STATUS 1=Tach is outside of limits 0=Tach is within limits (R/WC)" "0: Tach is within limits,1: Tach is outside of limits" line.long 0x8 "LIM_HI,TACH HIGH LIMIT Register" hexmask.long.word 0x8 0.--15. 1. "T_HIGH,This value is compared with the value in the TACHX_COUNTER field. If the value in the counter is greater than the value programmed in this register the TACH_OUT_OF_LIMIT_STATUS bit will be set. The TACH_OUT_OF_LIMIT_STATUS status event may be.." line.long 0xC "LIM_LO,TACHx Low Limit Register" hexmask.long.word 0xC 0.--15. 1. "T_LOW,This value is compared with the value in the TACHX_COUNTER field of the TACHx Control Register. If the value in the counter is less than the value programmed in this register the TACH_OUT_OF_LIMIT_STATUS bit will be set. The.." tree.end tree "TACH2" base ad:0x40006020 group.long 0x0++0xF line.long 0x0 "CTRL,TACHx Control Register" hexmask.long.word 0x0 16.--31. 1. "CNTR,This 16-bit field contains the latched value of the internal Tach pulse counter which may be configured by the Tach Reading Mode Select field to operate as a free-running counter or to be gated by the Tach input signal." bitfld.long 0x0 15. "IN_INT_EN,TACH_INPUT_INT_EN 1=Enable Tach Input toggle interrupt from Tach block 0=Disable Tach Input toggle interrupt from Tach block" "0: Disable Tach Input toggle interrupt from Tach..,1: Enable Tach Input toggle interrupt from Tach block" newline bitfld.long 0x0 14. "CNT_RDY_INT_EN,COUNT_READY_INT_EN 1=Enable Count Ready interrupt from Tach block 0=Disable Count Ready interrupt from Tach block" "0: Disable Count Ready interrupt from Tach block,1: Enable Count Ready interrupt from Tach block" bitfld.long 0x0 11.--12. "EDGES,TACH_EDGES A Tach signal is a square wave with a 50 percent duty cycle. Typically two Tach periods represents one revolution of the fan. A Tach period consists of three Tach edges. This programmed value represents the number of Tach edges that.." "0,1,2,3" newline bitfld.long 0x0 10. "RD_MOD_SEL,TACH_READING_MODE_SELECT 1=Counter is incremented on the rising edge of the 100kHz_Clk input. The counter is latched into the TACHX_COUNTER field and reset when the programmed number of edges is detected." "0: Counter is incremented when Tach Input..,1: Counter is incremented on the rising edge of the.." bitfld.long 0x0 8. "FILT_EN,FILTER_ENABLE This filter is used to remove high frequency glitches from Tach Input. When this filter is enabled Tach input pulses less than two 100kHz_- Clk periods wide get filtered. 1= Filter enabled 0=.." "0: Filter disabled,1: Filter enabled" newline bitfld.long 0x0 1. "EN,TACH_ENABLE 1= TACH Monitoring enabled clocks enabled. 0= TACH Idle clocks gated" "0: TACH Idle,1: TACH Monitoring enabled" bitfld.long 0x0 0. "OUTOF_LIM_EN,TACH_OUT_OF_LIMIT_ENABLE This bit is used to enable the TACH_OUT_OF_LIMIT_STATUS bit in the TACHx Status Register to generate an interrupt event. 1=Enable interrupt output from Tach block 0=Disable.." "0: Disable interrupt output from Tach block,1: Enable interrupt output from Tach block" line.long 0x4 "STS,TACHx Status Register" bitfld.long 0x4 3. "CNT_RDY_STS,COUNT_READY_STATUS 1=Reading ready 0=Reading not ready" "0: Reading not ready,1: Reading ready" bitfld.long 0x4 2. "TOG_STS,TOGGLE_STATUS 1=Tach Input changed state (this bit is set on a low-to-high or high-tolow transition) 0=Tach stable (R/WC)" "0: Tach stable,1: Tach Input changed state" newline bitfld.long 0x4 1. "PIN_STS,TACH_PIN_STATUS 1= Tach Input is high 0= Tach Input is low" "0: Tach Input is low,1: Tach Input is high" bitfld.long 0x4 0. "OUTOF_LIM_STS,TACH_OUT_OF_LIMIT_STATUS 1=Tach is outside of limits 0=Tach is within limits (R/WC)" "0: Tach is within limits,1: Tach is outside of limits" line.long 0x8 "LIM_HI,TACH HIGH LIMIT Register" hexmask.long.word 0x8 0.--15. 1. "T_HIGH,This value is compared with the value in the TACHX_COUNTER field. If the value in the counter is greater than the value programmed in this register the TACH_OUT_OF_LIMIT_STATUS bit will be set. The TACH_OUT_OF_LIMIT_STATUS status event may be.." line.long 0xC "LIM_LO,TACHx Low Limit Register" hexmask.long.word 0xC 0.--15. 1. "T_LOW,This value is compared with the value in the TACHX_COUNTER field of the TACHx Control Register. If the value in the counter is less than the value programmed in this register the TACH_OUT_OF_LIMIT_STATUS bit will be set. The.." tree.end tree "TACH3" base ad:0x40006030 group.long 0x0++0xF line.long 0x0 "CTRL,TACHx Control Register" hexmask.long.word 0x0 16.--31. 1. "CNTR,This 16-bit field contains the latched value of the internal Tach pulse counter which may be configured by the Tach Reading Mode Select field to operate as a free-running counter or to be gated by the Tach input signal." bitfld.long 0x0 15. "IN_INT_EN,TACH_INPUT_INT_EN 1=Enable Tach Input toggle interrupt from Tach block 0=Disable Tach Input toggle interrupt from Tach block" "0: Disable Tach Input toggle interrupt from Tach..,1: Enable Tach Input toggle interrupt from Tach block" newline bitfld.long 0x0 14. "CNT_RDY_INT_EN,COUNT_READY_INT_EN 1=Enable Count Ready interrupt from Tach block 0=Disable Count Ready interrupt from Tach block" "0: Disable Count Ready interrupt from Tach block,1: Enable Count Ready interrupt from Tach block" bitfld.long 0x0 11.--12. "EDGES,TACH_EDGES A Tach signal is a square wave with a 50 percent duty cycle. Typically two Tach periods represents one revolution of the fan. A Tach period consists of three Tach edges. This programmed value represents the number of Tach edges that.." "0,1,2,3" newline bitfld.long 0x0 10. "RD_MOD_SEL,TACH_READING_MODE_SELECT 1=Counter is incremented on the rising edge of the 100kHz_Clk input. The counter is latched into the TACHX_COUNTER field and reset when the programmed number of edges is detected." "0: Counter is incremented when Tach Input..,1: Counter is incremented on the rising edge of the.." bitfld.long 0x0 8. "FILT_EN,FILTER_ENABLE This filter is used to remove high frequency glitches from Tach Input. When this filter is enabled Tach input pulses less than two 100kHz_- Clk periods wide get filtered. 1= Filter enabled 0=.." "0: Filter disabled,1: Filter enabled" newline bitfld.long 0x0 1. "EN,TACH_ENABLE 1= TACH Monitoring enabled clocks enabled. 0= TACH Idle clocks gated" "0: TACH Idle,1: TACH Monitoring enabled" bitfld.long 0x0 0. "OUTOF_LIM_EN,TACH_OUT_OF_LIMIT_ENABLE This bit is used to enable the TACH_OUT_OF_LIMIT_STATUS bit in the TACHx Status Register to generate an interrupt event. 1=Enable interrupt output from Tach block 0=Disable.." "0: Disable interrupt output from Tach block,1: Enable interrupt output from Tach block" line.long 0x4 "STS,TACHx Status Register" bitfld.long 0x4 3. "CNT_RDY_STS,COUNT_READY_STATUS 1=Reading ready 0=Reading not ready" "0: Reading not ready,1: Reading ready" bitfld.long 0x4 2. "TOG_STS,TOGGLE_STATUS 1=Tach Input changed state (this bit is set on a low-to-high or high-tolow transition) 0=Tach stable (R/WC)" "0: Tach stable,1: Tach Input changed state" newline bitfld.long 0x4 1. "PIN_STS,TACH_PIN_STATUS 1= Tach Input is high 0= Tach Input is low" "0: Tach Input is low,1: Tach Input is high" bitfld.long 0x4 0. "OUTOF_LIM_STS,TACH_OUT_OF_LIMIT_STATUS 1=Tach is outside of limits 0=Tach is within limits (R/WC)" "0: Tach is within limits,1: Tach is outside of limits" line.long 0x8 "LIM_HI,TACH HIGH LIMIT Register" hexmask.long.word 0x8 0.--15. 1. "T_HIGH,This value is compared with the value in the TACHX_COUNTER field. If the value in the counter is greater than the value programmed in this register the TACH_OUT_OF_LIMIT_STATUS bit will be set. The TACH_OUT_OF_LIMIT_STATUS status event may be.." line.long 0xC "LIM_LO,TACHx Low Limit Register" hexmask.long.word 0xC 0.--15. 1. "T_LOW,This value is compared with the value in the TACHX_COUNTER field of the TACHx Control Register. If the value in the counter is less than the value programmed in this register the TACH_OUT_OF_LIMIT_STATUS bit will be set. The.." tree.end tree.end tree "TFDP (Trace FIFO Debug Port)" base ad:0x40008C00 group.byte 0x0++0x0 line.byte 0x0 "MSDATA,Debug data to be shifted out on the TFDP Debug port. While data is being shifted out. the Host Interface will 'hold-off' additional writes to the data register until the transfer is complete." group.byte 0x4++0x0 line.byte 0x0 "CTRL,Debug Control Register" bitfld.byte 0x0 4.--6. "IP_DLY,Inter-packet Delay. The delay is in terms of TFDP Debug output clocks." "0,1,2,3,4,5,6,7" bitfld.byte 0x0 2.--3. "DIVSEL,Clock Divider Select." "0,1,2,3" bitfld.byte 0x0 1. "EDGE_SEL,1= Data is shifted out on the falling edge of the debug clock 0= Data is shifted out on the rising edge of the debug clock (Default)" "0: Data is shifted out on the rising edge of the..,1: Data is shifted out on the falling edge of the.." bitfld.byte 0x0 0. "EN,Enable. 1=Clock enabled 0=Clock is disabled (Default)" "0: Clock is disabled,1: Clock enabled" tree.end tree "TIMER16 (16-bit Timers)" base ad:0x0 tree "TIMER16_0" base ad:0x40000C00 group.long 0x0++0x13 line.long 0x0 "CNT,This is the value of the Timer counter." line.long 0x4 "PRLD,This is Timer pre-load for the counter." line.long 0x8 "STS,This is the interrupt status that fires when the timer reaches its limit" bitfld.long 0x8 0. "EVT_INT,This may be level or a self clearing signal cycle pulse based on the AUTO_RESTART bit in the Timer Control Register." "0,1" line.long 0xC "IEN,This is the WDT Interrupt Enable Register" bitfld.long 0xC 0. "EN,This is the interrupt enable for the status EVENT_INTERRUPT bit in the Timer Status Register." "0,1" line.long 0x10 "CTRL,Timer Control Register" hexmask.long.word 0x10 16.--31. 1. "PRESCALE,This is used to divide down the system clock through clock enables to lower the power consumption of the block and allow slow timers. Updating this value during operation may result in erroneous clock enable pulses until the clock divider.." bitfld.long 0x10 7. "HLT,This is a halt bit. This will halt the timer as long as it is active. Once the halt is inactive the timer will start from where it left off. 1=Timer is halted. It stops counting. The clock divider will also be reset. 0=Timer runs normally." "0: Timer runs normally,1: Timer is halted" newline bitfld.long 0x10 6. "RLD,This bit reloads the counter without interrupting it operation. This will not function if the timer has already completed (when the START bit in this register is '0'). This is used to periodically prevent the timer from firing when an event.." "0,1" bitfld.long 0x10 5. "STRT,This bit triggers the timer counter. The counter will operate until it hits its terminating condition. This will clear this bit. It should be noted that when operating in restart mode there is no terminating condition for the counter so.." "0,1" newline bitfld.long 0x10 4. "SFT_RST,This is a soft reset. This is self clearing 1 cycle after it is written. Firmware does not need to wait before reconfiguring the Basic Timer following soft reset." "0,1" bitfld.long 0x10 3. "AU_RESTRT,This will select the action taken upon completing a count. 1=The counter will automatically restart the count using the contents of the Timer Preload Register to load the Timer Count Register. The interrupt will be set in edge mode.." "0: The counter will simply enter a done state and..,1: The counter will automatically restart the count" newline bitfld.long 0x10 2. "CNT_UP,This selects the counter direction. When the counter in incrementing the counter will saturate and trigger the event when it reaches all F's. When the counter is decrementing the counter will saturate when it reaches 0h. 1=The counter will.." "0: The counter will decrement,1: The counter will increment" bitfld.long 0x10 0. "EN,This enables the block for operation. 1=This block will function normally; 0=This block will gate its clock and go into its lowest power state" "0: This block will gate its clock and go into its..,1: This block will function normally" tree.end tree "TIMER16_1" base ad:0x40000C20 group.long 0x0++0x13 line.long 0x0 "CNT,This is the value of the Timer counter." line.long 0x4 "PRLD,This is Timer pre-load for the counter." line.long 0x8 "STS,This is the interrupt status that fires when the timer reaches its limit" bitfld.long 0x8 0. "EVT_INT,This may be level or a self clearing signal cycle pulse based on the AUTO_RESTART bit in the Timer Control Register." "0,1" line.long 0xC "IEN,This is the WDT Interrupt Enable Register" bitfld.long 0xC 0. "EN,This is the interrupt enable for the status EVENT_INTERRUPT bit in the Timer Status Register." "0,1" line.long 0x10 "CTRL,Timer Control Register" hexmask.long.word 0x10 16.--31. 1. "PRESCALE,This is used to divide down the system clock through clock enables to lower the power consumption of the block and allow slow timers. Updating this value during operation may result in erroneous clock enable pulses until the clock divider.." bitfld.long 0x10 7. "HLT,This is a halt bit. This will halt the timer as long as it is active. Once the halt is inactive the timer will start from where it left off. 1=Timer is halted. It stops counting. The clock divider will also be reset. 0=Timer runs normally." "0: Timer runs normally,1: Timer is halted" newline bitfld.long 0x10 6. "RLD,This bit reloads the counter without interrupting it operation. This will not function if the timer has already completed (when the START bit in this register is '0'). This is used to periodically prevent the timer from firing when an event.." "0,1" bitfld.long 0x10 5. "STRT,This bit triggers the timer counter. The counter will operate until it hits its terminating condition. This will clear this bit. It should be noted that when operating in restart mode there is no terminating condition for the counter so.." "0,1" newline bitfld.long 0x10 4. "SFT_RST,This is a soft reset. This is self clearing 1 cycle after it is written. Firmware does not need to wait before reconfiguring the Basic Timer following soft reset." "0,1" bitfld.long 0x10 3. "AU_RESTRT,This will select the action taken upon completing a count. 1=The counter will automatically restart the count using the contents of the Timer Preload Register to load the Timer Count Register. The interrupt will be set in edge mode.." "0: The counter will simply enter a done state and..,1: The counter will automatically restart the count" newline bitfld.long 0x10 2. "CNT_UP,This selects the counter direction. When the counter in incrementing the counter will saturate and trigger the event when it reaches all F's. When the counter is decrementing the counter will saturate when it reaches 0h. 1=The counter will.." "0: The counter will decrement,1: The counter will increment" bitfld.long 0x10 0. "EN,This enables the block for operation. 1=This block will function normally; 0=This block will gate its clock and go into its lowest power state" "0: This block will gate its clock and go into its..,1: This block will function normally" tree.end tree "TIMER16_2" base ad:0x40000C40 group.long 0x0++0x13 line.long 0x0 "CNT,This is the value of the Timer counter." line.long 0x4 "PRLD,This is Timer pre-load for the counter." line.long 0x8 "STS,This is the interrupt status that fires when the timer reaches its limit" bitfld.long 0x8 0. "EVT_INT,This may be level or a self clearing signal cycle pulse based on the AUTO_RESTART bit in the Timer Control Register." "0,1" line.long 0xC "IEN,This is the WDT Interrupt Enable Register" bitfld.long 0xC 0. "EN,This is the interrupt enable for the status EVENT_INTERRUPT bit in the Timer Status Register." "0,1" line.long 0x10 "CTRL,Timer Control Register" hexmask.long.word 0x10 16.--31. 1. "PRESCALE,This is used to divide down the system clock through clock enables to lower the power consumption of the block and allow slow timers. Updating this value during operation may result in erroneous clock enable pulses until the clock divider.." bitfld.long 0x10 7. "HLT,This is a halt bit. This will halt the timer as long as it is active. Once the halt is inactive the timer will start from where it left off. 1=Timer is halted. It stops counting. The clock divider will also be reset. 0=Timer runs normally." "0: Timer runs normally,1: Timer is halted" newline bitfld.long 0x10 6. "RLD,This bit reloads the counter without interrupting it operation. This will not function if the timer has already completed (when the START bit in this register is '0'). This is used to periodically prevent the timer from firing when an event.." "0,1" bitfld.long 0x10 5. "STRT,This bit triggers the timer counter. The counter will operate until it hits its terminating condition. This will clear this bit. It should be noted that when operating in restart mode there is no terminating condition for the counter so.." "0,1" newline bitfld.long 0x10 4. "SFT_RST,This is a soft reset. This is self clearing 1 cycle after it is written. Firmware does not need to wait before reconfiguring the Basic Timer following soft reset." "0,1" bitfld.long 0x10 3. "AU_RESTRT,This will select the action taken upon completing a count. 1=The counter will automatically restart the count using the contents of the Timer Preload Register to load the Timer Count Register. The interrupt will be set in edge mode.." "0: The counter will simply enter a done state and..,1: The counter will automatically restart the count" newline bitfld.long 0x10 2. "CNT_UP,This selects the counter direction. When the counter in incrementing the counter will saturate and trigger the event when it reaches all F's. When the counter is decrementing the counter will saturate when it reaches 0h. 1=The counter will.." "0: The counter will decrement,1: The counter will increment" bitfld.long 0x10 0. "EN,This enables the block for operation. 1=This block will function normally; 0=This block will gate its clock and go into its lowest power state" "0: This block will gate its clock and go into its..,1: This block will function normally" tree.end tree "TIMER16_3" base ad:0x40000C60 group.long 0x0++0x13 line.long 0x0 "CNT,This is the value of the Timer counter." line.long 0x4 "PRLD,This is Timer pre-load for the counter." line.long 0x8 "STS,This is the interrupt status that fires when the timer reaches its limit" bitfld.long 0x8 0. "EVT_INT,This may be level or a self clearing signal cycle pulse based on the AUTO_RESTART bit in the Timer Control Register." "0,1" line.long 0xC "IEN,This is the WDT Interrupt Enable Register" bitfld.long 0xC 0. "EN,This is the interrupt enable for the status EVENT_INTERRUPT bit in the Timer Status Register." "0,1" line.long 0x10 "CTRL,Timer Control Register" hexmask.long.word 0x10 16.--31. 1. "PRESCALE,This is used to divide down the system clock through clock enables to lower the power consumption of the block and allow slow timers. Updating this value during operation may result in erroneous clock enable pulses until the clock divider.." bitfld.long 0x10 7. "HLT,This is a halt bit. This will halt the timer as long as it is active. Once the halt is inactive the timer will start from where it left off. 1=Timer is halted. It stops counting. The clock divider will also be reset. 0=Timer runs normally." "0: Timer runs normally,1: Timer is halted" newline bitfld.long 0x10 6. "RLD,This bit reloads the counter without interrupting it operation. This will not function if the timer has already completed (when the START bit in this register is '0'). This is used to periodically prevent the timer from firing when an event.." "0,1" bitfld.long 0x10 5. "STRT,This bit triggers the timer counter. The counter will operate until it hits its terminating condition. This will clear this bit. It should be noted that when operating in restart mode there is no terminating condition for the counter so.." "0,1" newline bitfld.long 0x10 4. "SFT_RST,This is a soft reset. This is self clearing 1 cycle after it is written. Firmware does not need to wait before reconfiguring the Basic Timer following soft reset." "0,1" bitfld.long 0x10 3. "AU_RESTRT,This will select the action taken upon completing a count. 1=The counter will automatically restart the count using the contents of the Timer Preload Register to load the Timer Count Register. The interrupt will be set in edge mode.." "0: The counter will simply enter a done state and..,1: The counter will automatically restart the count" newline bitfld.long 0x10 2. "CNT_UP,This selects the counter direction. When the counter in incrementing the counter will saturate and trigger the event when it reaches all F's. When the counter is decrementing the counter will saturate when it reaches 0h. 1=The counter will.." "0: The counter will decrement,1: The counter will increment" bitfld.long 0x10 0. "EN,This enables the block for operation. 1=This block will function normally; 0=This block will gate its clock and go into its lowest power state" "0: This block will gate its clock and go into its..,1: This block will function normally" tree.end tree.end tree "TIMER32 (32-bit Timers)" base ad:0x0 tree "TIMER32_0" base ad:0x40000C80 group.long 0x0++0x13 line.long 0x0 "CNT,This is the value of the Timer counter. This is updated by Hardware but may be set by Firmware." line.long 0x4 "PRLD,This is the value of the Timer pre-load for the counter. This is used by H/W when the counter is to be restarted automatically; this will become the new value of the counter upon restart." line.long 0x8 "STS,This is the interrupt status that fires when the timer reaches its limit" bitfld.long 0x8 0. "EVT_INT,This is the interrupt status that fires when the timer reaches its limit. This is the interrupt status that fires when the timer reaches its limit. This may be level or a self clearing signal cycle pulse based on the AUTO_RESTART bit in.." "0,1" line.long 0xC "IEN,This is the interrupt enable for the status EVENT_INTERRUPT bit in the Timer Status Register" bitfld.long 0xC 0. "EN,This is the interrupt enable for the status EVENT_INTERRUPT bit in the Timer Status Register." "0,1" line.long 0x10 "CTRL,Timer Control Register" hexmask.long.word 0x10 16.--31. 1. "PRESCALE,This is used to divide down the system clock through clock enables to lower the power consumption of the block and allow slow timers. Updating this value during operation may result in erroneous clock enable pulses until the clock divider.." bitfld.long 0x10 7. "HLT,This is a halt bit. This will halt the timer as long as it is active. Once the halt is inactive the timer will start from where it left off. 1=Timer is halted. It stops counting. The clock divider will also be reset. 0=Timer runs normally." "0: Timer runs normally,1: Timer is halted" newline bitfld.long 0x10 6. "RLD,This bit reloads the counter without interrupting it operation. This will not function if the timer has already completed (when the START bit in this register is '0'). This is used to periodically prevent the timer from firing when an event.." "0,1" bitfld.long 0x10 5. "STRT,This bit triggers the timer counter. The counter will operate until it hits its terminating condition. This will clear this bit. It should be noted that when operating in restart mode there is no terminating condition for the counter so.." "0,1" newline bitfld.long 0x10 4. "SFT_RST,This is a soft reset. This is self clearing 1 cycle after it is written. Firmware does not need to wait before reconfiguring the Basic Timer following soft reset." "0,1" bitfld.long 0x10 3. "AU_RESTRT,This will select the action taken upon completing a count. 1=The counter will automatically restart the count using the contents of the Timer Preload Register to load the Timer Count Register. The interrupt will be set in edge mode.." "0: The counter will simply enter a done state and..,1: The counter will automatically restart the count" newline bitfld.long 0x10 2. "CNT_UP,This selects the counter direction. When the counter in incrementing the counter will saturate and trigger the event when it reaches all F's. When the counter is decrementing the counter will saturate when it reaches 0h. 1=The counter will.." "0: The counter will decrement,1: The counter will increment" bitfld.long 0x10 0. "EN,This enables the block for operation. 1=This block will function normally; 0=This block will gate its clock and go into its lowest power state" "0: This block will gate its clock and go into its..,1: This block will function normally" tree.end tree "TIMER32_1" base ad:0x40000CA0 group.long 0x0++0x13 line.long 0x0 "CNT,This is the value of the Timer counter. This is updated by Hardware but may be set by Firmware." line.long 0x4 "PRLD,This is the value of the Timer pre-load for the counter. This is used by H/W when the counter is to be restarted automatically; this will become the new value of the counter upon restart." line.long 0x8 "STS,This is the interrupt status that fires when the timer reaches its limit" bitfld.long 0x8 0. "EVT_INT,This is the interrupt status that fires when the timer reaches its limit. This is the interrupt status that fires when the timer reaches its limit. This may be level or a self clearing signal cycle pulse based on the AUTO_RESTART bit in.." "0,1" line.long 0xC "IEN,This is the interrupt enable for the status EVENT_INTERRUPT bit in the Timer Status Register" bitfld.long 0xC 0. "EN,This is the interrupt enable for the status EVENT_INTERRUPT bit in the Timer Status Register." "0,1" line.long 0x10 "CTRL,Timer Control Register" hexmask.long.word 0x10 16.--31. 1. "PRESCALE,This is used to divide down the system clock through clock enables to lower the power consumption of the block and allow slow timers. Updating this value during operation may result in erroneous clock enable pulses until the clock divider.." bitfld.long 0x10 7. "HLT,This is a halt bit. This will halt the timer as long as it is active. Once the halt is inactive the timer will start from where it left off. 1=Timer is halted. It stops counting. The clock divider will also be reset. 0=Timer runs normally." "0: Timer runs normally,1: Timer is halted" newline bitfld.long 0x10 6. "RLD,This bit reloads the counter without interrupting it operation. This will not function if the timer has already completed (when the START bit in this register is '0'). This is used to periodically prevent the timer from firing when an event.." "0,1" bitfld.long 0x10 5. "STRT,This bit triggers the timer counter. The counter will operate until it hits its terminating condition. This will clear this bit. It should be noted that when operating in restart mode there is no terminating condition for the counter so.." "0,1" newline bitfld.long 0x10 4. "SFT_RST,This is a soft reset. This is self clearing 1 cycle after it is written. Firmware does not need to wait before reconfiguring the Basic Timer following soft reset." "0,1" bitfld.long 0x10 3. "AU_RESTRT,This will select the action taken upon completing a count. 1=The counter will automatically restart the count using the contents of the Timer Preload Register to load the Timer Count Register. The interrupt will be set in edge mode.." "0: The counter will simply enter a done state and..,1: The counter will automatically restart the count" newline bitfld.long 0x10 2. "CNT_UP,This selects the counter direction. When the counter in incrementing the counter will saturate and trigger the event when it reaches all F's. When the counter is decrementing the counter will saturate when it reaches 0h. 1=The counter will.." "0: The counter will decrement,1: The counter will increment" bitfld.long 0x10 0. "EN,This enables the block for operation. 1=This block will function normally; 0=This block will gate its clock and go into its lowest power state" "0: This block will gate its clock and go into its..,1: This block will function normally" tree.end tree.end tree "UART (Universal Asynchronous Receiver/Transmitter)" base ad:0x0 tree "UART0" base ad:0x400F2400 tree "DATA (UART when DLAB=0)" rgroup.byte 0x0++0x0 line.byte 0x0 "RX_DAT,UART Receive (Read) Buffer Register (DLAB=0)" wgroup.byte 0x0++0x0 line.byte 0x0 "TX_DAT,UART Transmit (Write) Buffer Register (DLAB=0)" group.byte 0x1++0x0 line.byte 0x0 "IEN,UART Interrupt Enable Register (DLAB=0)" bitfld.byte 0x0 3. "EMSI,EMSI This bit enables the MODEM Status Interrupt when set to logic '1'." "0,1" bitfld.byte 0x0 2. "ELSI,ELSI This bit enables the Received Line Status Interrupt when set to logic '1'." "0,1" newline bitfld.byte 0x0 1. "ETHREI,ETHREI This bit enables the Transmitter Holding Register Empty Interrupt when set to logic '1'." "0,1" bitfld.byte 0x0 0. "ERDAI,ERDAI This bit enables the Received Data Available Interrupt (and timeout interrupts in the FIFO mode) when set to logic '1'." "0,1" wgroup.byte 0x2++0x0 line.byte 0x0 "FIFO_CR,UART FIFO Control Register" bitfld.byte 0x0 6.--7. "RECV_FIFO_TRIG_LVL,RECV_FIFO_TRIGGER_LEVEL These bits are used to set the trigger level for the RCVR FIFO interrupt." "0,1,2,3" bitfld.byte 0x0 3. "DMA_MODE_SEL,DMA_MODE_SELECT Writing to this bit has no effect on the operation of the UART. The RXRDY and TXRDY pins are not available on this chip." "0,1" newline bitfld.byte 0x0 2. "CLR_XMIT_FIFO,CLEAR_XMIT_FIFO Setting this bit to a logic '1' clears all bytes in the XMIT FIFO and resets its counter logic to '0' . The shift register is not cleared. This bit is self-clearing." "0,1" bitfld.byte 0x0 1. "CLR_RECV_FIFO,CLEAR_RECV_FIFO Setting this bit to a logic '1' clears all bytes in the RCVR FIFO and resets its counter logic to '0'." "0,1" newline bitfld.byte 0x0 0. "EXRF,EXRF Enable XMIT and RECV FIFO." "0,1" rgroup.byte 0x2++0x0 line.byte 0x0 "INT_ID,UART Interrupt Identification Register" bitfld.byte 0x0 6.--7. "FIFO_EN,These two bits are set when the FIFO CONTROL Register bit 0 equals 1." "0,1,2,3" bitfld.byte 0x0 1.--3. "INTID,INTID These bits identify the highest priority interrupt pending" "0,1,2,3,4,5,6,7" newline bitfld.byte 0x0 0. "IPEND,IPEND This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending." "0,1" group.byte 0x3++0x1 line.byte 0x0 "LCR,UART Line Control Register" bitfld.byte 0x0 7. "DLAB,DLAB Divisor Latch Access Bit (DLAB)." "0,1" bitfld.byte 0x0 6. "BRK_CTRL,BREAK_CONTROL Set Break Control bit" "0,1" newline bitfld.byte 0x0 5. "STICK_PAR,STICK_PARITY Stick Parity bit." "0,1" bitfld.byte 0x0 4. "PAR_SEL,PARITY_SELECT Even Parity Select bit." "0,1" newline bitfld.byte 0x0 3. "EN_PAR,ENABLE_PARITY Parity Enable bit." "0,1" bitfld.byte 0x0 2. "STOP_BITS,STOP_BITS This bit specifies the number of stop bits in each transmitted or received serial character." "0,1" newline bitfld.byte 0x0 0.--1. "WORD_LEN,WORD_LENGTH These two bits specify the number of bits in each transmitted or received serial character." "0,1,2,3" line.byte 0x1 "MCR,UART Modem Control Register" bitfld.byte 0x1 4. "LOOPBACK,LOOPBACK This bit provides the loopback feature for diagnostic testing of the Serial Port." "0,1" bitfld.byte 0x1 3. "OUT2,OUT2 This bit is used to enable an UART interrupt." "0,1" newline bitfld.byte 0x1 2. "OUT1,OUT1 This bit controls the Output 1 (OUT1) bit." "0,1" bitfld.byte 0x1 1. "RTS,RTS This bit controls the Request To Send (nRTS) output." "0,1" newline bitfld.byte 0x1 0. "DTR,DTR This bit controls the Data Terminal Ready (nDTR) output." "0,1" rgroup.byte 0x5++0x1 line.byte 0x0 "LSR,UART Line Status Register" bitfld.byte 0x0 7. "FIFO_ERR,FIFO_ERROR" "0,1" bitfld.byte 0x0 6. "TRANS_ERR,Transmitter Empty. Bit 6 is set to a logic '1' whenever the Transmitter Holding Register (THR) and Transmitter Shift Register (TSR) are both empty." "0,1" newline bitfld.byte 0x0 5. "TRANS_EMPTY,TRANSMIT_EMPTY Transmitter Holding Register Empty Bit 5 indicates that the Serial Port is ready to accept a new character for transmission." "0,1" bitfld.byte 0x0 4. "BRK_INTR,BREAK_INTERRUPT Break Interrupt." "0,1" newline bitfld.byte 0x0 3. "FRAME_ERR,FRAME_ERROR Framing Error." "0,1" bitfld.byte 0x0 2. "PE,PARITY ERROR Parity Error." "0,1" newline bitfld.byte 0x0 1. "OVERRUN,OVERRUN Overrun Error." "0,1" bitfld.byte 0x0 0. "DATA_READY,DATA_READY Data Ready. It is set to a logic '1' whenever a complete incoming character has been received and transferred into the Receiver Buffer Register or the FIFO" "0,1" line.byte 0x1 "MSR,UART Modem Status Register" bitfld.byte 0x1 7. "nDCD,nDCD This bit is the complement of the Data Carrier Detect (nDCD) input." "0,1" bitfld.byte 0x1 6. "nRI,nRI This bit is the complement of the Ring Indicator (nRI) input." "0,1" newline bitfld.byte 0x1 5. "nDSR,This bit is the complement of the Data Set Ready (nDSR) input." "0,1" bitfld.byte 0x1 4. "nCTS,nCTS This bit is the complement of the Clear To Send (nCTS) input." "0,1" newline bitfld.byte 0x1 3. "DCD,DCD Delta Data Carrier Detect (DDCD)." "0,1" bitfld.byte 0x1 2. "RI,RI Trailing Edge of Ring Indicator (TERI)." "0,1" newline bitfld.byte 0x1 1. "DSR,DSR Delta Data Set Ready (DDSR)." "0,1" bitfld.byte 0x1 0. "CTS,CTS Delta Clear To Send (DCTS)." "0,1" group.byte 0x7++0x0 line.byte 0x0 "SCR,UART Scratchpad Register This 8 bit read/write register has no effect on the operation of the Serial Port. It is intended as a scratchpad register to be used by the programmer to hold data temporarily." group.byte 0x330++0x0 line.byte 0x0 "ACTIVATE,UART Activate Register. [0:0] ACTIVATE When this bit is 1. the UART logical device is powered and functional. When this bit is 0. the UART logical device is powered down and inactive." group.byte 0x3F0++0x0 line.byte 0x0 "CFG_SEL,UART Config Select Register" bitfld.byte 0x0 2. "POLAR,POLARITY 1=The UART_TX and UART_RX pins functions are inverted 0=The UART_TX and UART_RX pins functions are not inverted" "0: The UART_TX and UART_RX pins functions are not..,1: The UART_TX and UART_RX pins functions are.." bitfld.byte 0x0 1. "PWR,POWER 1=The RESET reset signal is derived from nSIO_RESET 0=The RESET reset signal is derived from VCC1_RESET" "0: The RESET reset signal is derived from VCC1_RESET,1: The RESET reset signal is derived from nSIO_RESET" newline bitfld.byte 0x0 0. "CLK_SRC,CLK_SRC 1=The UART Baud Clock is derived from an external clock source 0=The UART Baud Clock is derived from one of the two internal clock sources" "0: The UART Baud Clock is derived from one of the..,1: The UART Baud Clock is derived from an external.." tree.end tree "DLAB (UART when DLAB=1)" group.byte 0x0++0x1 line.byte 0x0 "BAUDRT_LSB,UART Programmable BAUD Rate Generator (LSB) Register (DLAB=1)" line.byte 0x1 "BAUDRT_MSB,UART Programmable BAUD Rate Generator (MSB) Register (DLAB=1). [6:0] BAUD_RATE_DIVISOR_MSB. [7:7] BAUD_CLK_SEL 1=If CLK_SRC is '0'. the baud clock is derived from the 1.8432MHz_Clk. If CLK_SRC is '1'. this bit has no effect.." wgroup.byte 0x2++0x0 line.byte 0x0 "FIFO_CR,UART FIFO Control Register" bitfld.byte 0x0 6.--7. "RECV_FIFO_TRIG_LVL,RECV_FIFO_TRIGGER_LEVEL These bits are used to set the trigger level for the RCVR FIFO interrupt." "0,1,2,3" bitfld.byte 0x0 3. "DMA_MODE_SEL,DMA_MODE_SELECT Writing to this bit has no effect on the operation of the UART. The RXRDY and TXRDY pins are not available on this chip." "0,1" newline bitfld.byte 0x0 2. "CLR_XMIT_FIFO,CLEAR_XMIT_FIFO Setting this bit to a logic '1' clears all bytes in the XMIT FIFO and resets its counter logic to '0' . The shift register is not cleared. This bit is self-clearing." "0,1" bitfld.byte 0x0 1. "CLR_RECV_FIFO,CLEAR_RECV_FIFO Setting this bit to a logic '1' clears all bytes in the RCVR FIFO and resets its counter logic to '0'." "0,1" newline bitfld.byte 0x0 0. "EXRF,EXRF Enable XMIT and RECV FIFO." "0,1" rgroup.byte 0x2++0x0 line.byte 0x0 "INT_ID,UART Interrupt Identification Register" bitfld.byte 0x0 6.--7. "FIFO_EN,These two bits are set when the FIFO CONTROL Register bit 0 equals 1." "0,1,2,3" bitfld.byte 0x0 1.--3. "INTID,INTID These bits identify the highest priority interrupt pending" "0,1,2,3,4,5,6,7" newline bitfld.byte 0x0 0. "IPEND,IPEND This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending." "0,1" group.byte 0x3++0x1 line.byte 0x0 "LCR,UART Line Control Register" bitfld.byte 0x0 7. "DLAB,DLAB Divisor Latch Access Bit (DLAB)." "0,1" bitfld.byte 0x0 6. "BRK_CTRL,BREAK_CONTROL Set Break Control bit" "0,1" newline bitfld.byte 0x0 5. "STICK_PAR,STICK_PARITY Stick Parity bit." "0,1" bitfld.byte 0x0 4. "PAR_SEL,PARITY_SELECT Even Parity Select bit." "0,1" newline bitfld.byte 0x0 3. "EN_PAR,ENABLE_PARITY Parity Enable bit." "0,1" bitfld.byte 0x0 2. "STOP_BITS,STOP_BITS This bit specifies the number of stop bits in each transmitted or received serial character." "0,1" newline bitfld.byte 0x0 0.--1. "WORD_LEN,WORD_LENGTH These two bits specify the number of bits in each transmitted or received serial character." "0,1,2,3" line.byte 0x1 "MCR,UART Modem Control Register" bitfld.byte 0x1 4. "LOOPBACK,LOOPBACK This bit provides the loopback feature for diagnostic testing of the Serial Port." "0,1" bitfld.byte 0x1 3. "OUT2,OUT2 This bit is used to enable an UART interrupt." "0,1" newline bitfld.byte 0x1 2. "OUT1,OUT1 This bit controls the Output 1 (OUT1) bit." "0,1" bitfld.byte 0x1 1. "RTS,RTS This bit controls the Request To Send (nRTS) output." "0,1" newline bitfld.byte 0x1 0. "DTR,DTR This bit controls the Data Terminal Ready (nDTR) output." "0,1" rgroup.byte 0x5++0x1 line.byte 0x0 "LSR,UART Line Status Register" bitfld.byte 0x0 7. "FIFO_ERR,FIFO_ERROR" "0,1" bitfld.byte 0x0 6. "TRANS_ERR,Transmitter Empty. Bit 6 is set to a logic '1' whenever the Transmitter Holding Register (THR) and Transmitter Shift Register (TSR) are both empty." "0,1" newline bitfld.byte 0x0 5. "TRANS_EMPTY,TRANSMIT_EMPTY Transmitter Holding Register Empty Bit 5 indicates that the Serial Port is ready to accept a new character for transmission." "0,1" bitfld.byte 0x0 4. "BRK_INTR,BREAK_INTERRUPT Break Interrupt." "0,1" newline bitfld.byte 0x0 3. "FRAME_ERR,FRAME_ERROR Framing Error." "0,1" bitfld.byte 0x0 2. "PE,PARITY ERROR Parity Error." "0,1" newline bitfld.byte 0x0 1. "OVERRUN,OVERRUN Overrun Error." "0,1" bitfld.byte 0x0 0. "DATA_READY,DATA_READY Data Ready. It is set to a logic '1' whenever a complete incoming character has been received and transferred into the Receiver Buffer Register or the FIFO" "0,1" line.byte 0x1 "MSR,UART Modem Status Register" bitfld.byte 0x1 7. "nDCD,nDCD This bit is the complement of the Data Carrier Detect (nDCD) input." "0,1" bitfld.byte 0x1 6. "nRI,nRI This bit is the complement of the Ring Indicator (nRI) input." "0,1" newline bitfld.byte 0x1 5. "nDSR,This bit is the complement of the Data Set Ready (nDSR) input." "0,1" bitfld.byte 0x1 4. "nCTS,nCTS This bit is the complement of the Clear To Send (nCTS) input." "0,1" newline bitfld.byte 0x1 3. "DCD,DCD Delta Data Carrier Detect (DDCD)." "0,1" bitfld.byte 0x1 2. "RI,RI Trailing Edge of Ring Indicator (TERI)." "0,1" newline bitfld.byte 0x1 1. "DSR,DSR Delta Data Set Ready (DDSR)." "0,1" bitfld.byte 0x1 0. "CTS,CTS Delta Clear To Send (DCTS)." "0,1" group.byte 0x7++0x0 line.byte 0x0 "SCR,UART Scratchpad Register This 8 bit read/write register has no effect on the operation of the Serial Port. It is intended as a scratchpad register to be used by the programmer to hold data temporarily." group.byte 0x330++0x0 line.byte 0x0 "ACTIVATE,UART Activate Register. [0:0] ACTIVATE When this bit is 1. the UART logical device is powered and functional. When this bit is 0. the UART logical device is powered down and inactive." group.byte 0x3F0++0x0 line.byte 0x0 "CFG_SEL,UART Config Select Register" bitfld.byte 0x0 2. "POLAR,POLARITY 1=The UART_TX and UART_RX pins functions are inverted 0=The UART_TX and UART_RX pins functions are not inverted" "0: The UART_TX and UART_RX pins functions are not..,1: The UART_TX and UART_RX pins functions are.." bitfld.byte 0x0 1. "PWR,POWER 1=The RESET reset signal is derived from nSIO_RESET 0=The RESET reset signal is derived from VCC1_RESET" "0: The RESET reset signal is derived from VCC1_RESET,1: The RESET reset signal is derived from nSIO_RESET" newline bitfld.byte 0x0 0. "CLK_SRC,CLK_SRC 1=The UART Baud Clock is derived from an external clock source 0=The UART Baud Clock is derived from one of the two internal clock sources" "0: The UART Baud Clock is derived from one of the..,1: The UART Baud Clock is derived from an external.." tree.end tree.end tree "UART1" base ad:0x400F2800 tree "DATA (UART when DLAB=0)" rgroup.byte 0x0++0x0 line.byte 0x0 "RX_DAT,UART Receive (Read) Buffer Register (DLAB=0)" wgroup.byte 0x0++0x0 line.byte 0x0 "TX_DAT,UART Transmit (Write) Buffer Register (DLAB=0)" group.byte 0x1++0x0 line.byte 0x0 "IEN,UART Interrupt Enable Register (DLAB=0)" bitfld.byte 0x0 3. "EMSI,EMSI This bit enables the MODEM Status Interrupt when set to logic '1'." "0,1" bitfld.byte 0x0 2. "ELSI,ELSI This bit enables the Received Line Status Interrupt when set to logic '1'." "0,1" newline bitfld.byte 0x0 1. "ETHREI,ETHREI This bit enables the Transmitter Holding Register Empty Interrupt when set to logic '1'." "0,1" bitfld.byte 0x0 0. "ERDAI,ERDAI This bit enables the Received Data Available Interrupt (and timeout interrupts in the FIFO mode) when set to logic '1'." "0,1" wgroup.byte 0x2++0x0 line.byte 0x0 "FIFO_CR,UART FIFO Control Register" bitfld.byte 0x0 6.--7. "RECV_FIFO_TRIG_LVL,RECV_FIFO_TRIGGER_LEVEL These bits are used to set the trigger level for the RCVR FIFO interrupt." "0,1,2,3" bitfld.byte 0x0 3. "DMA_MODE_SEL,DMA_MODE_SELECT Writing to this bit has no effect on the operation of the UART. The RXRDY and TXRDY pins are not available on this chip." "0,1" newline bitfld.byte 0x0 2. "CLR_XMIT_FIFO,CLEAR_XMIT_FIFO Setting this bit to a logic '1' clears all bytes in the XMIT FIFO and resets its counter logic to '0' . The shift register is not cleared. This bit is self-clearing." "0,1" bitfld.byte 0x0 1. "CLR_RECV_FIFO,CLEAR_RECV_FIFO Setting this bit to a logic '1' clears all bytes in the RCVR FIFO and resets its counter logic to '0'." "0,1" newline bitfld.byte 0x0 0. "EXRF,EXRF Enable XMIT and RECV FIFO." "0,1" rgroup.byte 0x2++0x0 line.byte 0x0 "INT_ID,UART Interrupt Identification Register" bitfld.byte 0x0 6.--7. "FIFO_EN,These two bits are set when the FIFO CONTROL Register bit 0 equals 1." "0,1,2,3" bitfld.byte 0x0 1.--3. "INTID,INTID These bits identify the highest priority interrupt pending" "0,1,2,3,4,5,6,7" newline bitfld.byte 0x0 0. "IPEND,IPEND This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending." "0,1" group.byte 0x3++0x1 line.byte 0x0 "LCR,UART Line Control Register" bitfld.byte 0x0 7. "DLAB,DLAB Divisor Latch Access Bit (DLAB)." "0,1" bitfld.byte 0x0 6. "BRK_CTRL,BREAK_CONTROL Set Break Control bit" "0,1" newline bitfld.byte 0x0 5. "STICK_PAR,STICK_PARITY Stick Parity bit." "0,1" bitfld.byte 0x0 4. "PAR_SEL,PARITY_SELECT Even Parity Select bit." "0,1" newline bitfld.byte 0x0 3. "EN_PAR,ENABLE_PARITY Parity Enable bit." "0,1" bitfld.byte 0x0 2. "STOP_BITS,STOP_BITS This bit specifies the number of stop bits in each transmitted or received serial character." "0,1" newline bitfld.byte 0x0 0.--1. "WORD_LEN,WORD_LENGTH These two bits specify the number of bits in each transmitted or received serial character." "0,1,2,3" line.byte 0x1 "MCR,UART Modem Control Register" bitfld.byte 0x1 4. "LOOPBACK,LOOPBACK This bit provides the loopback feature for diagnostic testing of the Serial Port." "0,1" bitfld.byte 0x1 3. "OUT2,OUT2 This bit is used to enable an UART interrupt." "0,1" newline bitfld.byte 0x1 2. "OUT1,OUT1 This bit controls the Output 1 (OUT1) bit." "0,1" bitfld.byte 0x1 1. "RTS,RTS This bit controls the Request To Send (nRTS) output." "0,1" newline bitfld.byte 0x1 0. "DTR,DTR This bit controls the Data Terminal Ready (nDTR) output." "0,1" rgroup.byte 0x5++0x1 line.byte 0x0 "LSR,UART Line Status Register" bitfld.byte 0x0 7. "FIFO_ERR,FIFO_ERROR" "0,1" bitfld.byte 0x0 6. "TRANS_ERR,Transmitter Empty. Bit 6 is set to a logic '1' whenever the Transmitter Holding Register (THR) and Transmitter Shift Register (TSR) are both empty." "0,1" newline bitfld.byte 0x0 5. "TRANS_EMPTY,TRANSMIT_EMPTY Transmitter Holding Register Empty Bit 5 indicates that the Serial Port is ready to accept a new character for transmission." "0,1" bitfld.byte 0x0 4. "BRK_INTR,BREAK_INTERRUPT Break Interrupt." "0,1" newline bitfld.byte 0x0 3. "FRAME_ERR,FRAME_ERROR Framing Error." "0,1" bitfld.byte 0x0 2. "PE,PARITY ERROR Parity Error." "0,1" newline bitfld.byte 0x0 1. "OVERRUN,OVERRUN Overrun Error." "0,1" bitfld.byte 0x0 0. "DATA_READY,DATA_READY Data Ready. It is set to a logic '1' whenever a complete incoming character has been received and transferred into the Receiver Buffer Register or the FIFO" "0,1" line.byte 0x1 "MSR,UART Modem Status Register" bitfld.byte 0x1 7. "nDCD,nDCD This bit is the complement of the Data Carrier Detect (nDCD) input." "0,1" bitfld.byte 0x1 6. "nRI,nRI This bit is the complement of the Ring Indicator (nRI) input." "0,1" newline bitfld.byte 0x1 5. "nDSR,This bit is the complement of the Data Set Ready (nDSR) input." "0,1" bitfld.byte 0x1 4. "nCTS,nCTS This bit is the complement of the Clear To Send (nCTS) input." "0,1" newline bitfld.byte 0x1 3. "DCD,DCD Delta Data Carrier Detect (DDCD)." "0,1" bitfld.byte 0x1 2. "RI,RI Trailing Edge of Ring Indicator (TERI)." "0,1" newline bitfld.byte 0x1 1. "DSR,DSR Delta Data Set Ready (DDSR)." "0,1" bitfld.byte 0x1 0. "CTS,CTS Delta Clear To Send (DCTS)." "0,1" group.byte 0x7++0x0 line.byte 0x0 "SCR,UART Scratchpad Register This 8 bit read/write register has no effect on the operation of the Serial Port. It is intended as a scratchpad register to be used by the programmer to hold data temporarily." group.byte 0x330++0x0 line.byte 0x0 "ACTIVATE,UART Activate Register. [0:0] ACTIVATE When this bit is 1. the UART logical device is powered and functional. When this bit is 0. the UART logical device is powered down and inactive." group.byte 0x3F0++0x0 line.byte 0x0 "CFG_SEL,UART Config Select Register" bitfld.byte 0x0 2. "POLAR,POLARITY 1=The UART_TX and UART_RX pins functions are inverted 0=The UART_TX and UART_RX pins functions are not inverted" "0: The UART_TX and UART_RX pins functions are not..,1: The UART_TX and UART_RX pins functions are.." bitfld.byte 0x0 1. "PWR,POWER 1=The RESET reset signal is derived from nSIO_RESET 0=The RESET reset signal is derived from VCC1_RESET" "0: The RESET reset signal is derived from VCC1_RESET,1: The RESET reset signal is derived from nSIO_RESET" newline bitfld.byte 0x0 0. "CLK_SRC,CLK_SRC 1=The UART Baud Clock is derived from an external clock source 0=The UART Baud Clock is derived from one of the two internal clock sources" "0: The UART Baud Clock is derived from one of the..,1: The UART Baud Clock is derived from an external.." tree.end tree "DLAB (UART when DLAB=1)" group.byte 0x0++0x1 line.byte 0x0 "BAUDRT_LSB,UART Programmable BAUD Rate Generator (LSB) Register (DLAB=1)" line.byte 0x1 "BAUDRT_MSB,UART Programmable BAUD Rate Generator (MSB) Register (DLAB=1). [6:0] BAUD_RATE_DIVISOR_MSB. [7:7] BAUD_CLK_SEL 1=If CLK_SRC is '0'. the baud clock is derived from the 1.8432MHz_Clk. If CLK_SRC is '1'. this bit has no effect.." wgroup.byte 0x2++0x0 line.byte 0x0 "FIFO_CR,UART FIFO Control Register" bitfld.byte 0x0 6.--7. "RECV_FIFO_TRIG_LVL,RECV_FIFO_TRIGGER_LEVEL These bits are used to set the trigger level for the RCVR FIFO interrupt." "0,1,2,3" bitfld.byte 0x0 3. "DMA_MODE_SEL,DMA_MODE_SELECT Writing to this bit has no effect on the operation of the UART. The RXRDY and TXRDY pins are not available on this chip." "0,1" newline bitfld.byte 0x0 2. "CLR_XMIT_FIFO,CLEAR_XMIT_FIFO Setting this bit to a logic '1' clears all bytes in the XMIT FIFO and resets its counter logic to '0' . The shift register is not cleared. This bit is self-clearing." "0,1" bitfld.byte 0x0 1. "CLR_RECV_FIFO,CLEAR_RECV_FIFO Setting this bit to a logic '1' clears all bytes in the RCVR FIFO and resets its counter logic to '0'." "0,1" newline bitfld.byte 0x0 0. "EXRF,EXRF Enable XMIT and RECV FIFO." "0,1" rgroup.byte 0x2++0x0 line.byte 0x0 "INT_ID,UART Interrupt Identification Register" bitfld.byte 0x0 6.--7. "FIFO_EN,These two bits are set when the FIFO CONTROL Register bit 0 equals 1." "0,1,2,3" bitfld.byte 0x0 1.--3. "INTID,INTID These bits identify the highest priority interrupt pending" "0,1,2,3,4,5,6,7" newline bitfld.byte 0x0 0. "IPEND,IPEND This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending." "0,1" group.byte 0x3++0x1 line.byte 0x0 "LCR,UART Line Control Register" bitfld.byte 0x0 7. "DLAB,DLAB Divisor Latch Access Bit (DLAB)." "0,1" bitfld.byte 0x0 6. "BRK_CTRL,BREAK_CONTROL Set Break Control bit" "0,1" newline bitfld.byte 0x0 5. "STICK_PAR,STICK_PARITY Stick Parity bit." "0,1" bitfld.byte 0x0 4. "PAR_SEL,PARITY_SELECT Even Parity Select bit." "0,1" newline bitfld.byte 0x0 3. "EN_PAR,ENABLE_PARITY Parity Enable bit." "0,1" bitfld.byte 0x0 2. "STOP_BITS,STOP_BITS This bit specifies the number of stop bits in each transmitted or received serial character." "0,1" newline bitfld.byte 0x0 0.--1. "WORD_LEN,WORD_LENGTH These two bits specify the number of bits in each transmitted or received serial character." "0,1,2,3" line.byte 0x1 "MCR,UART Modem Control Register" bitfld.byte 0x1 4. "LOOPBACK,LOOPBACK This bit provides the loopback feature for diagnostic testing of the Serial Port." "0,1" bitfld.byte 0x1 3. "OUT2,OUT2 This bit is used to enable an UART interrupt." "0,1" newline bitfld.byte 0x1 2. "OUT1,OUT1 This bit controls the Output 1 (OUT1) bit." "0,1" bitfld.byte 0x1 1. "RTS,RTS This bit controls the Request To Send (nRTS) output." "0,1" newline bitfld.byte 0x1 0. "DTR,DTR This bit controls the Data Terminal Ready (nDTR) output." "0,1" rgroup.byte 0x5++0x1 line.byte 0x0 "LSR,UART Line Status Register" bitfld.byte 0x0 7. "FIFO_ERR,FIFO_ERROR" "0,1" bitfld.byte 0x0 6. "TRANS_ERR,Transmitter Empty. Bit 6 is set to a logic '1' whenever the Transmitter Holding Register (THR) and Transmitter Shift Register (TSR) are both empty." "0,1" newline bitfld.byte 0x0 5. "TRANS_EMPTY,TRANSMIT_EMPTY Transmitter Holding Register Empty Bit 5 indicates that the Serial Port is ready to accept a new character for transmission." "0,1" bitfld.byte 0x0 4. "BRK_INTR,BREAK_INTERRUPT Break Interrupt." "0,1" newline bitfld.byte 0x0 3. "FRAME_ERR,FRAME_ERROR Framing Error." "0,1" bitfld.byte 0x0 2. "PE,PARITY ERROR Parity Error." "0,1" newline bitfld.byte 0x0 1. "OVERRUN,OVERRUN Overrun Error." "0,1" bitfld.byte 0x0 0. "DATA_READY,DATA_READY Data Ready. It is set to a logic '1' whenever a complete incoming character has been received and transferred into the Receiver Buffer Register or the FIFO" "0,1" line.byte 0x1 "MSR,UART Modem Status Register" bitfld.byte 0x1 7. "nDCD,nDCD This bit is the complement of the Data Carrier Detect (nDCD) input." "0,1" bitfld.byte 0x1 6. "nRI,nRI This bit is the complement of the Ring Indicator (nRI) input." "0,1" newline bitfld.byte 0x1 5. "nDSR,This bit is the complement of the Data Set Ready (nDSR) input." "0,1" bitfld.byte 0x1 4. "nCTS,nCTS This bit is the complement of the Clear To Send (nCTS) input." "0,1" newline bitfld.byte 0x1 3. "DCD,DCD Delta Data Carrier Detect (DDCD)." "0,1" bitfld.byte 0x1 2. "RI,RI Trailing Edge of Ring Indicator (TERI)." "0,1" newline bitfld.byte 0x1 1. "DSR,DSR Delta Data Set Ready (DDSR)." "0,1" bitfld.byte 0x1 0. "CTS,CTS Delta Clear To Send (DCTS)." "0,1" group.byte 0x7++0x0 line.byte 0x0 "SCR,UART Scratchpad Register This 8 bit read/write register has no effect on the operation of the Serial Port. It is intended as a scratchpad register to be used by the programmer to hold data temporarily." group.byte 0x330++0x0 line.byte 0x0 "ACTIVATE,UART Activate Register. [0:0] ACTIVATE When this bit is 1. the UART logical device is powered and functional. When this bit is 0. the UART logical device is powered down and inactive." group.byte 0x3F0++0x0 line.byte 0x0 "CFG_SEL,UART Config Select Register" bitfld.byte 0x0 2. "POLAR,POLARITY 1=The UART_TX and UART_RX pins functions are inverted 0=The UART_TX and UART_RX pins functions are not inverted" "0: The UART_TX and UART_RX pins functions are not..,1: The UART_TX and UART_RX pins functions are.." bitfld.byte 0x0 1. "PWR,POWER 1=The RESET reset signal is derived from nSIO_RESET 0=The RESET reset signal is derived from VCC1_RESET" "0: The RESET reset signal is derived from VCC1_RESET,1: The RESET reset signal is derived from nSIO_RESET" newline bitfld.byte 0x0 0. "CLK_SRC,CLK_SRC 1=The UART Baud Clock is derived from an external clock source 0=The UART Baud Clock is derived from one of the two internal clock sources" "0: The UART Baud Clock is derived from one of the..,1: The UART Baud Clock is derived from an external.." tree.end tree.end tree.end tree "VBAT (VBAT Register Bank)" base ad:0x4000A400 group.byte 0x0++0x0 line.byte 0x0 "PFRS,The Power-Fail and Reset Status Register collects and retains the VBAT RST and WDT event status when VCC1 is unpowered." bitfld.byte 0x0 7. "VBAT_RST,The VBAT RST bit is set to '1' by hardware when a RESET_VBAT is detected. This is the register default value. To clear VBAT RST EC firmware must write a '1' to this bit; writing a '0' to VBAT RST has no affect.(R/WC)" "0,1" bitfld.byte 0x0 6. "SYS_RSTREQ,This bit is set to '1b' if a RESET_SYS was triggered by an ARM SYSRESETREQ event. This bit is cleared to '0b' when written with a '1b'; writes of a '0b' have no effect. (R/WC)" "0,1" bitfld.byte 0x0 5. "WDT_EVT,This bit is set to '1b' if a RESET_SYS was triggered by a Watchdog Timer event. This bit is cleared to '0b' when written with a '1b'; writes of a '0b' have no effect. (R/WC)" "0,1" newline bitfld.byte 0x0 4. "RSTI,This bit is set to '1b' if a RESET_SYS was triggered by a low signal on the RESETI# input pin. This bit is cleared to '0b' when written with a '1b'; writes of a '0b' have no effect. (R/WC)" "0,1" bitfld.byte 0x0 3. "TEST,Test" "0,1" bitfld.byte 0x0 2. "SOFT,This bit is set to '1b' if a was triggered by an assertion of the SOFT_SYS_RESET bit in the System Reset Register. This bit is cleared to '0b' when written with a '1b'; writes of a '0b' have no effect. (R/WC)" "0,1" group.long 0x8++0x3 line.long 0x0 "CLK_EN,32KHz Clock Enable Register" bitfld.long 0x0 18. "ICLK_SPRS,When enabled the Internal 32kHz VBAT clock source is suppressed (disabled) when VTR goes down." "0,1" bitfld.long 0x0 16.--17. "PRPHL_32KHZ_CLK,MUX Select for the source of the 32kHz Peripheral Clock." "0,1,2,3" bitfld.long 0x0 11.--12. "XTAL_CTRL,XTAL Gain Control 0 = Original Gain. 1 or 2=Gain reduced. 3= Gain is smallest." "0: Original Gain,?,2: Gain reduced,3: Gain is smallest" newline bitfld.long 0x0 10. "XSTRTP_DIS,XTAL Startup Disable When enabled the XTAL in Dual-Ended Mode will enter a low power mode." "0,1" bitfld.long 0x0 9. "XOSEL,This bit selects between a single-ended clock source for the crystal oscillator or an external parallel crystal. 1= the Crystal Oscillator is driven by a single-ended 32KHz clock source connected to the XTAL2 pin. 0=.." "0: the Crystal Oscillator requires a 32KHz parallel..,1: the Crystal Oscillator is driven by a.." bitfld.long 0x0 8. "XTAL_EN,XTAL Enable Enables/Starts the XTAL clock operation." "0,1" newline bitfld.long 0x0 0. "TEST,This is a test bit and must not be modified." "0,1" group.long 0x20++0x7 line.long 0x0 "MCNT_LO,MONOTONIC COUNTER" hexmask.long 0x0 0.--31. 1. "CNTR,Read-only register that increments by 1 every time it is read. It is reset to 0 on a VBAT Power On Reset." line.long 0x4 "MCNT_HI,COUNTER HIWORD" hexmask.long 0x4 0.--31. 1. "CNTR,Thirty-two bit read/write register. If software sets this register to an incrementing value based on an external non-volatile store this register may be combined with the Monotonic Counter Register to form a 64-bit monotonic counter." group.long 0x34++0x3 line.long 0x0 "EMDRST_DBNC_EN,Embedded Reset Debouce Enable." bitfld.long 0x0 0. "DBNC_EN,Embedded Reset Debouce Enable. 0 = Disable 1 = Enable" "0: Disable,1: Enable" tree.end tree "VBAT_RAM (VBAT Powered RAM)" base ad:0x4000A800 repeat 32. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "MEM[$1],32-bits of VBAT powered RAM." repeat.end tree.end tree "VCI (VBAT-Powered Control Interface)" base ad:0x4000AE00 group.long 0x0++0x23 line.long 0x0 "CTRL_STS,VCI Register" bitfld.long 0x0 18. "SYSPWR_PRES,This is the System power present select bit. 1= VCI_IN3 is used as System power present. 0= VCI_IN3 is used as VCI_IN3." "0: VCI_IN3 is used as VCI_IN3,1: VCI_IN3 is used as System power present" bitfld.long 0x0 17. "RTC_ALRM,If enabled by RTC_ALRM_LE this bit is set to 1 if the RTC Alarm signal is asserted. It is reset by writes to RTC_ALRM_LS." "0,1" newline bitfld.long 0x0 16. "WK_ALRM,If enabled by WEEK_ALRM_LE this bit is set to 1 if the Week Alarm signal is asserted. It is reset by writes to WEEK_ALRM_LS." "0,1" bitfld.long 0x0 12. "FLTRS_BYPASS,The Filters Bypass bit is used to enable and disable the input filters on the VCI_IN# pins. 1=Filters disabled; 0=Filters enabled (default)." "0: Filters enabled,1: Filters disabled" newline bitfld.long 0x0 11. "FW_EXT,This bit controls selecting between the external VBAT-Powered Control Interface inputs or the VCI_FW_CNTRL bit output to control the VCI_OUT pin. 1=VCI_OUT is determined by the VCI_FW_CNTRL field when VTR is active 0=VCI_OUT is.." "0: VCI_OUT is determined by the external inputs,1: VCI_OUT is determined by the VCI_FW_CNTRL field" bitfld.long 0x0 10. "VCI_FW_CTRL,This bit can allow EC firmware to control the state of the VCI_OUT pin. For example when VTR_PWRGD is asserted and the FW_EXT bit is 1 clearing the VCI_FW_CNTRL bit de-asserts the active high VCI_OUT pin. BIOS must set this bit to 1.." "0,1" newline bitfld.long 0x0 9. "VCI_OUT,This bit provides the current status of the VCI_OUT pin." "0,1" bitfld.long 0x0 8. "VCI_OVRD_IN,This bit provides the current status of the VCI_OVRD_IN pin. Note: The VCI_OVRD_IN bit defaults to the state of the respective input pin." "0,1" newline bitfld.long 0x0 7. "VCI_OUT_GPIO_SEL,This bit selects the power source for GPIO outputs. 1= GPIO will be powered by VBAT power well (VCI_OUT functionality). 0= GPIO will be powered by VTR power well." "0: GPIO will be powered by VTR power well,1: GPIO will be powered by VBAT power well" hexmask.long.byte 0x0 0.--3. 1. "VCI_IN,These bits provide the latched state of the associated VCI_IN# pin if latching is enabled or the current state of the pin if latching is not enabled. In both cases the value is determined after the action of the VCI Polarity Register." line.long 0x4 "LATCH_EN,Latch Enable Register" bitfld.long 0x4 17. "RTC_ALRM_LE,Latch enable for the RTC Power-Up signal. 1=Enabled. Assertions of the RTC Alarm are held until the latch is reset by writing the corresponding LS bit 0=Not Enabled. The RTC Alarm signal is not latched but passed directly to the.." "0: Not Enabled,1: Enabled" bitfld.long 0x4 16. "WK_ALRM_LE,Latch enable for the Week Alarm Power-Up signal. 1=Enabled. Assertions of the Week Alarm are held until the latch is reset by writing the corresponding LS bit 0=Not Enabled. The Week Alarm signal is not latched but passed directly to.." "0: Not Enabled,1: Enabled" newline hexmask.long.byte 0x4 0.--3. 1. "LE,Latching Enables. Latching occurs after the Polarity configuration so a VCI_INi# pin is asserted when it is '0' if VCI_IN_POL is '0' and asserted when it is '1' if VCI_IN_POL is '1'. For each bit in the field: 1=Enabled. Assertions of the.." line.long 0x8 "LATCH_RST,Latch Resets Register" bitfld.long 0x8 17. "RTC_ALRM_LS,RTC Alarm Latch Reset. When this bit is written with a '1' the RTC Alarm Event latch is reset. The RTC Alarm input to the latch has priority over the Reset input Reads of this register are undefined." "0,1" bitfld.long 0x8 16. "WK_ALRM_LS,Week Alarm Latch Reset. When this bit is written with a '1' the Week Alarm Event latch is reset. The Week Alarm input to the latch has priority over the Reset input Reads of this register are undefined." "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "LS,Latch Resets. When a Latch Resets bit is written with a '1' the corresponding VCI_INi# latch is de-asserted ('1'). The VCI_INi# input to the latch has priority over the Latch Reset input so firmware cannot reset the latch while the VCI_INi# pin.." line.long 0xC "INPUT_EN,VCI Input Enable Register" hexmask.long.byte 0xC 0.--3. 1. "IE,Input Enables for VCI_IN# signals. After changing the input enable for a VCI input firmware should reset the input latch and clear any potential interrupt that may have been triggered by the input as changing the enable may cause the internal.." line.long 0x10 "HLDOFF_CNT,Holdoff Count Register" hexmask.long.byte 0x10 0.--7. 1. "TIME,These bits determine the period of time the VCI_OUT logic is inhibited from re-asserting VCI_OUT after a SYS_SHDN# event. FFh-01h=The Power On Inhibit Holdoff Time is set to a period between 125ms and 31.875 seconds. 0=The Power On Inhibit.." line.long 0x14 "POLARITY,VCI Polarity Register" hexmask.long.byte 0x14 0.--3. 1. "VCI_IN,These bits determine the polarity of the VCI_IN input signals: For each bit in the field: 1=Active High. The value on the pins is inverted before use 0=Active Low (default)." line.long 0x18 "PEDGE_DET,VCI Posedge Detect Register" hexmask.long.byte 0x18 0.--3. 1. "VCI_IN,These bits record a low to high transition on the VCI_IN# pins. A 1 indicates a transition occurred. For each bit in the field: 1=Positive Edge Detected; 0=No edge detected." line.long 0x1C "NEDGE_DET,VCI Negedge Detect Register" hexmask.long.byte 0x1C 0.--3. 1. "VCI_IN,These bits record a high to low transition on the VCI_IN# pins. A 1 indicates a transition occurred. For each bit in the field: 1=Negative Edge Detected; 0=No edge detected." line.long 0x20 "BUFFER_EN,VCI Buffer Enable Register" hexmask.long.byte 0x20 0.--3. 1. "V_BUF,Input Buffer enable. After changing the buffer enable for a VCI input firmware should reset the input latch and clear any potential interrupt that may have been triggered by the input as changing the buffer may cause the internal status to.." tree.end tree "WDT (Watchdog Timer)" base ad:0x40000400 group.word 0x0++0x1 line.word 0x0 "LOAD,Writing this field reloads the Watch Dog Timer counter." group.word 0x4++0x1 line.word 0x0 "CTRL,WDT Control Register" bitfld.word 0x0 9. "WDT_RST,If the WDT_RESET bit is set and the watch dog timer expires the Watch dog module will generate interrupt and clear the WDT_RESET to 0b." "0,1" bitfld.word 0x0 4. "JTAG_STL,This bit enables the WDT Stall function if JTAG or SWD debug functions are active 1=The WDT is stalled while either JTAG or SWD is active 0=The WDT is not affected by the JTAG debug interface." "0: The WDT is not affected by the JTAG debug..,1: The WDT is stalled while either JTAG or SWD is.." newline bitfld.word 0x0 3. "WK_TMR_STL,This bit enables the WDT Stall function if the Week Timer is active. 1=The WDT is stalled while the Week Timer is active 0=The WDT is not affected by the Week Timer." "0: The WDT is not affected by the Week Timer,1: The WDT is stalled while the Week Timer is active" bitfld.word 0x0 2. "HIB_TMR0_STL,This bit enables the WDT Stall function if the Hibernation Timer 0 is active. 1=The WDT is stalled while the Hibernation Timer 0 is active 0=The WDT is not affected by Hibernation Timer 0." "0: The WDT is not affected by Hibernation Timer 0,1: The WDT is stalled while the Hibernation Timer 0.." newline bitfld.word 0x0 1. "WDT_STS,WDT_STATUS is set by hardware if the last reset of the device was caused by an underflow of the WDT. This bit must be cleared by the EC firmware writing a '1' to this bit. Writing a '0' to this bit has no effect." "0,1" bitfld.word 0x0 0. "WDT_EN,WDT Block enabled" "0,1" wgroup.byte 0x8++0x0 line.byte 0x0 "KICK,The WDT Kick Register is a strobe. Reads of this register return 0. Writes to this register cause the WDT to reload the WDT Load Register value and start decrementing when the WDT_ENABLE bit in the WDT Control Register is set to '1'. When the.." rgroup.word 0xC++0x1 line.word 0x0 "CNT,This read-only register provides the current WDT count." group.byte 0x10++0x0 line.byte 0x0 "STS,This register provides the current WDT count." bitfld.byte 0x0 0. "WDT_EV_IRQ,WDT_EVENT_IRQ : This bit indicates the status of interrupt from Watch dog module." "0,1" group.byte 0x14++0x0 line.byte 0x0 "IEN,Watch Dog Interrupt Enable Register." bitfld.byte 0x0 0. "WDT_INTEN,WDT_Int_Enable: This is the interrupt enables bit for WDT_INT interrupt. 1= WDT_INT Interrupt Enable 0= WDT_INT Interrupt Disabled" "0: WDT_INT Interrupt Disabled,1: WDT_INT Interrupt Enable" tree.end tree "WEEK (Week Alarm Interface)" base ad:0x4000AC80 group.long 0x0++0x27 line.long 0x0 "CTRL,Control Register" bitfld.long 0x0 6. "PWRUP_EN,This bit controls the state of the Power-Up Event Output and enables Week POWER-UP Event decoding in the VBAT-Powered Control Interface. 1=Power-Up Event Output Enabled 0=Power-Up Event Output Disabled and Reset" "0: Power-Up Event Output Disabled and Reset,1: Power-Up Event Output Enabled" bitfld.long 0x0 0. "WT_EN,The WT_ENABLE bit is used to start and stop the Week Alarm Counter Register and the Clock Divider Register. The value in the Counter Register is held when the WT_ENABLE bit is not asserted (0) and the count is resumed from the last value when.." "0,1" line.long 0x4 "ALARM_CNT,Week Alarm Counter Register" hexmask.long 0x4 0.--27. 1. "WK_CNTR,While the WT_ENABLE bit is 1 this register is incremented at a 1 Hz rate. Writes of this register may require one second to take effect. Reads return the current state of the register. Reads and writes complete independently of the state of.." line.long 0x8 "TMR_COMP,Week Timer Compare Register" hexmask.long 0x8 0.--27. 1. "WK_COMP,A Week Alarm Interrupt and a Week Alarm Power-Up Event are asserted when the Week Alarm Counter Register is greater than or equal to the contents of this register. Reads and writes complete independently of the state of WT_ENABLE." line.long 0xC "CLKDIV,Clock Divider Register" hexmask.long.word 0xC 0.--14. 1. "DIV,Reads of this register return the current state of the Week Timer 15- bit clock divider." line.long 0x10 "SS_INTR_SEL,Sub-Second Programmable Interrupt Select Register" hexmask.long.byte 0x10 0.--3. 1. "SPISR,This field determines the rate at which Sub-Second interrupt events are generated." line.long 0x14 "SWK_CTRL,Sub-Week Control Register" bitfld.long 0x14 7.--9. "SWK_TICK,This field selects the clock source for the Sub-Week Counter." "0,1,2,3,4,5,6,7" bitfld.long 0x14 6. "AU_RLD,1= No reload occurs when the Sub-Week Counter expires 0= Reloads the SUBWEEK_COUNTER_LOAD field into the Sub- Week Counter when the counter expires." "0: Reloads the SUBWEEK_COUNTER_LOAD field into the..,1: No reload occurs when the Sub-Week Counter expires" bitfld.long 0x14 5. "TEST0,Test" "0,1" newline bitfld.long 0x14 4. "TEST,Test" "0,1" bitfld.long 0x14 1. "WKTMR_PWRUP_EVT_STS,This bit is set to 1 when the Week Alarm Counter Register is greater than or equal the contents of the Week Timer Compare Register and the POWERUP_EN is 1. Writes of 1 clear this bit. Writes of 0 have no effect. Note: This bit.." "0,1" bitfld.long 0x14 0. "SWKTMR_PWRUP_EVT_STS,This bit is set to 1 when the Sub-Week Alarm Counter Register decrements from 1 to 0 and the POWERUP_EN is 1. Writes of 1 clear this bit. Writes of 0 have no effect. Note: This bit MUST be cleared to remove a Sub-Week Timer.." "0,1" line.long 0x18 "SWK_ALARM,Sub-Week Alarm Counter Register" hexmask.long.word 0x18 16.--24. 1. "CNTR_STS,Reads of this register return the current state of the 9-bit Sub-Week Alarm counter." hexmask.long.word 0x18 0.--8. 1. "CNTR_LOAD,Writes with a non-zero value to this field reload the 9-bit Sub-Week Alarm counter. Writes of 0 disable the counter. If the Sub-Week Alarm counter decrements to 0 and the AUTO_RELOAD bit is set the value in this field is automatically.." line.long 0x1C "BGPO_DATA,BGPO Data Register" bitfld.long 0x1C 0.--2. "DAT,Battery powered General Purpose Output. Each output pin may be individually configured to be either a VBAT-power BGPO or a VTR powered GPIO based on the corresponding settings in the BGPO Power Register. Additionally each output pin may be.." "0: BGPO[i] output is low,1: BGPO[i] output is high,?,?,?,?,?,?" line.long 0x20 "BGPO_PWR,BGPO Power Register" bitfld.long 0x20 0.--2. "PWR,Battery powered General Purpose Output power source. For each bit [i] in the field: 1=BGPO[i] is powered by VBAT. The BGPO[i] pin is always determined by the corresponding bit in the BGPO Data Register. The GPIO Input register for the GPIO.." "0: The pin for BGPO[i] functions as a GPIO,1: BGPO[i] is powered by VBAT,?,?,?,?,?,?" line.long 0x24 "BGPO_RST,BGPO Reset Register" bitfld.long 0x24 0.--2. "RST,Battery powered General Purpose Output reset event. For each bit [i] in the field: 1=BGPO[i] is reset to 0 on RESET_VTR; 0=BGPO[i] is reset to 0 on RESET_SYS." "0: BGPO[i] is reset to 0 on RESET_SYS,1: BGPO[i] is reset to 0 on RESET_VTR,?,?,?,?,?,?" tree.end newline AUTOINDENT.OFF